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git01.mediatek.com / filogic / uboot / 04e97e091c6d5b6fc80fd8469326849f7aca5bb3 / . / board / rattler / rattler.c
blob: ad75c215612e57332ad0e63615d67b7121741e3d [file] [log] [blame]
wdenkbc3202a2005-04-03 23:11:38 +0000[diff] [blame]1/*
2 * Copyright (C) 2004 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
4 *
5 * Support for Analogue&Micro Rattler boards family.
6 * Tested on Rattler8248.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <mpc8260.h>
29#include <ioports.h>
30
31/*
32 * I/O Port configuration table
33 *
34 * if conf is 1, then that port pin will be configured at boot time
35 * according to the five values podr/pdir/ppar/psor/pdat for that entry
36 */
37
38#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
39#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
40
41const iop_conf_t iop_conf_tab[4][32] = {
42
43 /* Port A */
44 { /* conf ppar psor pdir podr pdat */
45 /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
46 /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
47 /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
48 /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
49 /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
50 /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
51 /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
52 /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
53 /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
54 /* PA22 */ { 1, 0, 0, 1, 0, 1 }, /* Eth PHYs reset */
55 /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
56 /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
57 /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
58 /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
59 /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
60 /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
61 /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
62 /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
63 /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
64 /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
65 /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
66 /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
67 /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
68 /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
69 /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
70 /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
71 /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
72 /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
73 /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
74 /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
75 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
76 /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
77 },
78
79 /* Port B */
80 { /* conf ppar psor pdir podr pdat */
81 /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
82 /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
83 /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
84 /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
85 /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
86 /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
87 /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
88 /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
89 /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
90 /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
91 /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
92 /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
93 /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
94 /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
95 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
96 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
97 /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
98 /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
99 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
100 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
101 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
102 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
103 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
104 /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
105 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
106 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
107 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
108 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
109 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
110 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
111 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
112 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
113 },
114
115 /* Port C */
116 { /* conf ppar psor pdir podr pdat */
117 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
118 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
119 /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
120 /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
121 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
122 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
123 /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
124 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
125 /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
126 /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK10) */
127 /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK11) */
128 /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
129 /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
130 /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */
131 /* PC17 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK15) */
132 /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
133 /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
134 /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
135 /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
136 /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
137 /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
138 /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
139 /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */
140 /* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */
141 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
142 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
143 /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */
144 /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */
145 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
146 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
147 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
148 /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
149 },
150
151 /* Port D */
152 { /* conf ppar psor pdir podr pdat */
153 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */
154 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */
155 /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
156 /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
157 /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
158 /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
159 /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
160 /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
161 /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
162 /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
163 /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
164 /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
165 /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
166 /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
167 /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
168 /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
169 /* PD15 */ { 0, 0, 0, 0, 0, 0 }, /* PD15 */
170 /* PD14 */ { 0, 0, 0, 0, 0, 0 }, /* PD14 */
171 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
172 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
173 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
174 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
175 /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
176 /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
177 /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
178 /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
179 /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
180 /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
181 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
182 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
183 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
184 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
185 }
186};
187
Becky Brucebd99ae72008-06-09 16:03:40 -0500[diff] [blame]188phys_size_t initdram(int board_type)
wdenkbc3202a2005-04-03 23:11:38 +0000[diff] [blame]189{
190 long int msize = CFG_SDRAM_SIZE;
191
192#ifndef CFG_RAMBOOT
193 volatile immap_t *immap = (immap_t *)CFG_IMMR;
194 volatile memctl8260_t *memctl = &immap->im_memctl;
195 vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE;
196 uchar c = 0xFF;
197 uint psdmr = CFG_PSDMR;
198 int i;
199
200 immap->im_siu_conf.sc_ppc_acr = 0x02;
201 immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
202 immap->im_siu_conf.sc_tescr1 = 0x00004000;
203
204 memctl->memc_mptpr = CFG_MPTPR;
205
206 /* Initialise 60x bus SDRAM */
207 memctl->memc_psrt = CFG_PSRT;
208 memctl->memc_or1 = CFG_SDRAM_OR;
209 memctl->memc_br1 = CFG_SDRAM_BR;
210 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
211 *ramaddr = c;
212 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
213 for (i = 0; i < 8; i++)
214 *ramaddr = c;
215 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
216 *ramaddr = c;
217 memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
218 *ramaddr = c;
219#endif /* !CFG_RAMBOOT */
220
221 /* Return total 60x bus SDRAM size */
222 return msize * 1024 * 1024;
223}
224
225int checkboard(void)
226{
227 vu_char *bcsr = (vu_char *)CFG_BCSR;
228
229 printf("Board: Rattler Rev. %c\n", bcsr[0x20] + 0x40);
230 return 0;
231}