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git01.mediatek.com / filogic / uboot / 0440d864ca9909836f85eac188a958678a8759a4 / . / board / freescale / mx23evk / spl_boot.c
blob: 14e9b4a8634f3bfdef25c9ee7f542ee6fdec6d69 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Otavio Salvador50e60902013-01-23 10:30:34 +0000[diff] [blame]2/*
3 * Freescale MX23EVK Boot setup
4 *
5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * on behalf of DENX Software Engineering GmbH
Otavio Salvador50e60902013-01-23 10:30:34 +0000[diff] [blame]7 */
8
9#include <common.h>
10#include <config.h>
11#include <asm/io.h>
12#include <asm/arch/iomux-mx23.h>
13#include <asm/arch/imx-regs.h>
14#include <asm/arch/sys_proto.h>
15
Fabio Estevam78d7a172013-05-05 15:52:55 +0000[diff] [blame]16#define MUX_CONFIG_SSP1 (MXS_PAD_8MA | MXS_PAD_PULLUP)
Fabio Estevam2e2ee512013-05-03 04:37:08 +0000[diff] [blame]17#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
Fabio Estevame6fa5dc2013-05-10 09:14:10 +0000[diff] [blame]18#define MUX_CONFIG_LCD (MXS_PAD_4MA | MXS_PAD_NOPULL)
Otavio Salvador50e60902013-01-23 10:30:34 +0000[diff] [blame]19
20const iomux_cfg_t iomux_setup[] = {
21 /* DUART */
22 MX23_PAD_PWM0__DUART_RX,
23 MX23_PAD_PWM1__DUART_TX,
24
25 /* EMI */
26 MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI,
27 MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI,
28 MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI,
29 MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI,
30 MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI,
31 MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI,
32 MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI,
33 MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI,
34 MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI,
35 MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI,
36 MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI,
37 MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI,
38 MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI,
39 MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI,
40 MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI,
41 MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI,
42 MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
43 MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
44 MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
45 MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
46 MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
47 MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI,
48
49 MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI,
50 MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI,
51 MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI,
52 MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI,
53 MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI,
54 MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI,
55 MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI,
56 MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI,
57 MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI,
58 MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI,
59 MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI,
60 MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI,
61 MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI,
62 MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
63 MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
64
65 MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
66 MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
67 MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
68 MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
69 MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
70 MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
71
72 /* MMC 0 */
73 MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP1,
74 MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP1,
75 MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP1,
76 MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP1,
77 MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP1,
78 MX23_PAD_SSP1_DETECT__SSP1_DETECT | MUX_CONFIG_SSP1,
79 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
80 MX23_PAD_SSP1_SCK__SSP1_SCK |
81 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
82 /* Write Protect Pin */
83 MX23_PAD_PWM4__GPIO_1_30 |
84 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
85 /* Slot Power Enable */
86 MX23_PAD_PWM3__GPIO_1_29 |
87 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
Fabio Estevame6fa5dc2013-05-10 09:14:10 +0000[diff] [blame]88 /* LCD */
89 MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD,
90 MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD,
91 MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD,
92 MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD,
93 MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD,
94 MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD,
95 MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD,
96 MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD,
97 MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD,
98 MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD,
99 MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
100 MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
101 MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
102 MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
103 MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
104 MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
105 MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
106 MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
107 MX23_PAD_GPMI_D08__LCD_D18 | MUX_CONFIG_LCD,
108 MX23_PAD_GPMI_D09__LCD_D19 | MUX_CONFIG_LCD,
109 MX23_PAD_GPMI_D10__LCD_D20 | MUX_CONFIG_LCD,
110 MX23_PAD_GPMI_D11__LCD_D21 | MUX_CONFIG_LCD,
111 MX23_PAD_GPMI_D12__LCD_D22 | MUX_CONFIG_LCD,
112 MX23_PAD_GPMI_D13__LCD_D23 | MUX_CONFIG_LCD,
113 MX23_PAD_LCD_DOTCK__LCD_DOTCK | MUX_CONFIG_LCD,
114 MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
115 MX23_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
116 MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
117 MX23_PAD_LCD_RESET__GPIO_1_18 | MUX_CONFIG_LCD, /* LCD power */
118 MX23_PAD_PWM2__GPIO_1_28 | MUX_CONFIG_LCD, /* LCD contrast */
Otavio Salvador50e60902013-01-23 10:30:34 +0000[diff] [blame]119};
120
Otavio Salvador39dffa62013-02-23 02:43:06 +0000[diff] [blame]121#define HW_DRAM_CTL14 (0x38 >> 2)
122#define CS_MAP 0x3
123#define INTAREF 0x2
124#define HW_DRAM_CTL14_CONFIG (INTAREF << 8 | CS_MAP)
125
126void mxs_adjust_memory_params(uint32_t *dram_vals)
127{
128 dram_vals[HW_DRAM_CTL14] = HW_DRAM_CTL14_CONFIG;
129}
130
Marek Vasut0dc62ba2013-08-31 15:53:44 +0200[diff] [blame]131void board_init_ll(const uint32_t arg, const uint32_t *resptr)
Otavio Salvador50e60902013-01-23 10:30:34 +0000[diff] [blame]132{
Marek Vasut0dc62ba2013-08-31 15:53:44 +0200[diff] [blame]133 mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
Otavio Salvador50e60902013-01-23 10:30:34 +0000[diff] [blame]134}