blob: 068163b73a65986dbd3ac48fc325be1370c2748e [file] [log] [blame]
Albert ARIBAUD6277b192013-02-25 00:58:58 +00001/*
2 * Copyright (c) 2004-2008 Texas Instruments
3 *
4 * (C) Copyright 2002
5 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Albert ARIBAUD6277b192013-02-25 00:58:58 +00008 */
9
10OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
11OUTPUT_ARCH(arm)
12ENTRY(_start)
13SECTIONS
14{
15 . = 0x00000000;
16
17 . = ALIGN(4);
18 .text :
19 {
20 __image_copy_start = .;
Albert ARIBAUD9852cc62014-04-15 16:13:51 +020021 *(.vectors)
Albert ARIBAUD6277b192013-02-25 00:58:58 +000022 CPUDIR/start.o (.text*)
23 *(.text*)
24 }
25
26 . = ALIGN(4);
27 .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
28
29 . = ALIGN(4);
30 .data : {
31 *(.data*)
32 }
33
34 . = ALIGN(4);
Simon Glass06f1c742015-06-23 15:38:30 -060035 .u_boot_list : {
Tom Rini0ed608e2016-03-15 17:56:29 -040036 KEEP(*(SORT(.u_boot_list*)));
Simon Glass06f1c742015-06-23 15:38:30 -060037 }
38
Simon Glass3df10c02014-11-10 17:16:52 -070039 . = ALIGN(4);
Albert ARIBAUD6277b192013-02-25 00:58:58 +000040
41 __image_copy_end = .;
42
43 .rel.dyn : {
44 __rel_dyn_start = .;
45 *(.rel*)
46 __rel_dyn_end = .;
47 }
48
Albert ARIBAUD9d25fa42014-02-22 17:53:42 +010049 .end :
50 {
51 *(.__end)
52 }
53
54 _image_binary_end = .;
Albert ARIBAUD6277b192013-02-25 00:58:58 +000055
Albert ARIBAUD6277b192013-02-25 00:58:58 +000056 .bss __rel_dyn_start (OVERLAY) : {
57 __bss_start = .;
58 *(.bss*)
59 . = ALIGN(4);
Tom Rini19aac972013-03-18 12:31:00 -040060 __bss_end = .;
Albert ARIBAUD6277b192013-02-25 00:58:58 +000061 }
Simon Glass89caf332015-06-23 15:38:29 -060062 __bss_size = __bss_end - __bss_start;
Albert ARIBAUD9d25fa42014-02-22 17:53:42 +010063 .dynsym _image_binary_end : { *(.dynsym) }
Albert ARIBAUD95fc6d62013-11-07 14:21:46 +010064 .dynbss : { *(.dynbss) }
65 .dynstr : { *(.dynstr*) }
66 .dynamic : { *(.dynamic*) }
67 .hash : { *(.hash*) }
68 .plt : { *(.plt*) }
69 .interp : { *(.interp*) }
70 .gnu : { *(.gnu*) }
71 .ARM.exidx : { *(.ARM.exidx*) }
Albert ARIBAUD6277b192013-02-25 00:58:58 +000072}
73
Albert ARIBAUDe916e052013-04-12 05:14:30 +000074#if defined(CONFIG_SPL_MAX_SIZE)
75ASSERT(__image_copy_end - __image_copy_start < (CONFIG_SPL_MAX_SIZE), \
76 "SPL image too big");
77#endif
78
79#if defined(CONFIG_SPL_BSS_MAX_SIZE)
80ASSERT(__bss_end - __bss_start < (CONFIG_SPL_BSS_MAX_SIZE), \
81 "SPL image BSS too big");
82#endif
83
84#if defined(CONFIG_SPL_MAX_FOOTPRINT)
85ASSERT(__bss_end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \
86 "SPL image plus BSS too big");
Albert ARIBAUD6277b192013-02-25 00:58:58 +000087#endif