blob: 3541a17dceb9f40d38cf0a3694158c99b3281b31 [file] [log] [blame]
Patrick Delaunay50599142018-07-09 15:17:19 +02001// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
Patrick Delaunay06020d82018-03-12 10:46:17 +01002/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
Patrick Delaunay06020d82018-03-12 10:46:17 +01006/dts-v1/;
7
Patrick Delaunay48c5e902020-03-06 17:54:41 +01008#include "stm32mp157.dtsi"
9#include "stm32mp15xc.dtsi"
10#include "stm32mp15-pinctrl.dtsi"
11#include "stm32mp15xxaa-pinctrl.dtsi"
Patrick Delaunay06020d82018-03-12 10:46:17 +010012#include <dt-bindings/gpio/gpio.h>
Patrick Delaunay91be5942019-02-04 11:26:16 +010013#include <dt-bindings/mfd/st,stpmic1.h>
Patrick Delaunay06020d82018-03-12 10:46:17 +010014
15/ {
Patrick Delaunay50599142018-07-09 15:17:19 +020016 model = "STMicroelectronics STM32MP157C eval daughter";
Patrick Delaunay06020d82018-03-12 10:46:17 +010017 compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
18
Patrick Delaunay4597d262023-07-10 10:38:45 +020019 aliases {
20 serial0 = &uart4;
21 };
22
Patrick Delaunay06020d82018-03-12 10:46:17 +010023 chosen {
Patrice Chotard00442d02019-02-12 16:50:38 +010024 stdout-path = "serial0:115200n8";
Patrick Delaunay06020d82018-03-12 10:46:17 +010025 };
26
Patrick Delaunay50599142018-07-09 15:17:19 +020027 memory@c0000000 {
Patrick Delaunaya3705302019-07-11 11:15:28 +020028 device_type = "memory";
Patrick Delaunay06020d82018-03-12 10:46:17 +010029 reg = <0xC0000000 0x40000000>;
30 };
Patrice Chotardf6ef2292018-04-26 17:13:11 +020031
Patrick Delaunay708cae72019-07-30 19:16:12 +020032 reserved-memory {
33 #address-cells = <1>;
34 #size-cells = <1>;
35 ranges;
36
Patrick Delaunay8c6e6132019-11-06 16:16:33 +010037 mcuram2: mcuram2@10000000 {
38 compatible = "shared-dma-pool";
39 reg = <0x10000000 0x40000>;
40 no-map;
41 };
42
43 vdev0vring0: vdev0vring0@10040000 {
44 compatible = "shared-dma-pool";
45 reg = <0x10040000 0x1000>;
46 no-map;
47 };
48
49 vdev0vring1: vdev0vring1@10041000 {
50 compatible = "shared-dma-pool";
51 reg = <0x10041000 0x1000>;
52 no-map;
53 };
54
55 vdev0buffer: vdev0buffer@10042000 {
56 compatible = "shared-dma-pool";
57 reg = <0x10042000 0x4000>;
58 no-map;
59 };
60
61 mcuram: mcuram@30000000 {
62 compatible = "shared-dma-pool";
63 reg = <0x30000000 0x40000>;
64 no-map;
65 };
66
67 retram: retram@38000000 {
68 compatible = "shared-dma-pool";
69 reg = <0x38000000 0x10000>;
70 no-map;
71 };
Patrick Delaunay708cae72019-07-30 19:16:12 +020072 };
73
Patrice Chotardf6ef2292018-04-26 17:13:11 +020074 sd_switch: regulator-sd_switch {
75 compatible = "regulator-gpio";
76 regulator-name = "sd_switch";
77 regulator-min-microvolt = <1800000>;
78 regulator-max-microvolt = <2900000>;
79 regulator-type = "voltage";
80 regulator-always-on;
81
82 gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
83 gpios-states = <0>;
Patrick Delaunayb9c16b72020-01-28 10:11:00 +010084 states = <1800000 0x1>,
85 <2900000 0x0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +020086 };
Patrick Delaunay6d397052021-01-11 12:33:36 +010087
88 vin: vin {
89 compatible = "regulator-fixed";
90 regulator-name = "vin";
91 regulator-min-microvolt = <5000000>;
92 regulator-max-microvolt = <5000000>;
93 regulator-always-on;
94 };
Patrick Delaunay06020d82018-03-12 10:46:17 +010095};
96
Patrick Delaunay48c5e902020-03-06 17:54:41 +010097&adc {
98 /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */
99 pinctrl-0 = <&adc1_in6_pins_a>;
100 pinctrl-names = "default";
101 vdd-supply = <&vdd>;
102 vdda-supply = <&vdda>;
103 vref-supply = <&vdda>;
104 status = "disabled";
105 adc1: adc@0 {
106 st,adc-channels = <0 1 6>;
107 /* 16.5 ck_cycles sampling time */
108 st,min-sample-time-nsecs = <400>;
109 status = "okay";
110 };
111};
112
Patrick Delaunay0e20c1f2020-05-25 12:19:42 +0200113&cpu0{
114 cpu-supply = <&vddcore>;
115};
116
117&cpu1{
118 cpu-supply = <&vddcore>;
119};
120
Patrick Delaunay6d397052021-01-11 12:33:36 +0100121&crc1 {
122 status = "okay";
123};
124
125&cryp1 {
126 status = "okay";
127};
128
Patrick Delaunayb9c16b72020-01-28 10:11:00 +0100129&dac {
130 pinctrl-names = "default";
131 pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
132 vref-supply = <&vdda>;
133 status = "disabled";
134 dac1: dac@1 {
135 status = "okay";
136 };
137 dac2: dac@2 {
138 status = "okay";
139 };
140};
141
Patrick Delaunaya3705302019-07-11 11:15:28 +0200142&dts {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100143 status = "okay";
Patrick Delaunay06020d82018-03-12 10:46:17 +0100144};
145
Patrick Delaunay6d397052021-01-11 12:33:36 +0100146&hash1 {
147 status = "okay";
148};
149
Patrick Delaunay06020d82018-03-12 10:46:17 +0100150&i2c4 {
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200151 pinctrl-names = "default", "sleep";
Patrick Delaunay06020d82018-03-12 10:46:17 +0100152 pinctrl-0 = <&i2c4_pins_a>;
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200153 pinctrl-1 = <&i2c4_sleep_pins_a>;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100154 i2c-scl-rising-time-ns = <185>;
155 i2c-scl-falling-time-ns = <20>;
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200156 clock-frequency = <400000>;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100157 status = "okay";
Patrick Delaunaya3705302019-07-11 11:15:28 +0200158 /* spare dmas for other usage */
159 /delete-property/dmas;
160 /delete-property/dma-names;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100161
Patrick Delaunaya3705302019-07-11 11:15:28 +0200162 pmic: stpmic@33 {
Patrick Delaunayd79218f2019-02-04 11:26:17 +0100163 compatible = "st,stpmic1";
Patrick Delaunay06020d82018-03-12 10:46:17 +0100164 reg = <0x33>;
Patrick Delaunaya3705302019-07-11 11:15:28 +0200165 interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100166 interrupt-controller;
167 #interrupt-cells = <2>;
168 status = "okay";
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200169
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200170 regulators {
Patrick Delaunayd79218f2019-02-04 11:26:17 +0100171 compatible = "st,stpmic1-regulators";
Patrick Delaunay6d397052021-01-11 12:33:36 +0100172 buck1-supply = <&vin>;
173 buck2-supply = <&vin>;
174 buck3-supply = <&vin>;
175 buck4-supply = <&vin>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200176 ldo1-supply = <&v3v3>;
177 ldo2-supply = <&v3v3>;
178 ldo3-supply = <&vdd_ddr>;
Patrick Delaunay6d397052021-01-11 12:33:36 +0100179 ldo4-supply = <&vin>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200180 ldo5-supply = <&v3v3>;
181 ldo6-supply = <&v3v3>;
Patrick Delaunay6d397052021-01-11 12:33:36 +0100182 vref_ddr-supply = <&vin>;
183 boost-supply = <&vin>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200184 pwr_sw1-supply = <&bst_out>;
185 pwr_sw2-supply = <&bst_out>;
186
187 vddcore: buck1 {
188 regulator-name = "vddcore";
Patrick Delaunayb9c16b72020-01-28 10:11:00 +0100189 regulator-min-microvolt = <1200000>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200190 regulator-max-microvolt = <1350000>;
191 regulator-always-on;
Patrick Delaunaya3705302019-07-11 11:15:28 +0200192 regulator-initial-mode = <0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200193 regulator-over-current-protection;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200194 };
195
196 vdd_ddr: buck2 {
197 regulator-name = "vdd_ddr";
198 regulator-min-microvolt = <1350000>;
199 regulator-max-microvolt = <1350000>;
200 regulator-always-on;
Patrick Delaunaya3705302019-07-11 11:15:28 +0200201 regulator-initial-mode = <0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200202 regulator-over-current-protection;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200203 };
204
205 vdd: buck3 {
206 regulator-name = "vdd";
207 regulator-min-microvolt = <3300000>;
208 regulator-max-microvolt = <3300000>;
209 regulator-always-on;
Patrick Delaunaya3705302019-07-11 11:15:28 +0200210 st,mask-reset;
211 regulator-initial-mode = <0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200212 regulator-over-current-protection;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200213 };
214
215 v3v3: buck4 {
216 regulator-name = "v3v3";
217 regulator-min-microvolt = <3300000>;
218 regulator-max-microvolt = <3300000>;
Patrick Delaunaya3705302019-07-11 11:15:28 +0200219 regulator-always-on;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200220 regulator-over-current-protection;
Patrick Delaunaya3705302019-07-11 11:15:28 +0200221 regulator-initial-mode = <0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200222 };
223
224 vdda: ldo1 {
225 regulator-name = "vdda";
226 regulator-min-microvolt = <2900000>;
227 regulator-max-microvolt = <2900000>;
228 interrupts = <IT_CURLIM_LDO1 0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200229 };
230
231 v2v8: ldo2 {
232 regulator-name = "v2v8";
233 regulator-min-microvolt = <2800000>;
234 regulator-max-microvolt = <2800000>;
235 interrupts = <IT_CURLIM_LDO2 0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200236 };
237
238 vtt_ddr: ldo3 {
239 regulator-name = "vtt_ddr";
Patrick Delaunaya3705302019-07-11 11:15:28 +0200240 regulator-min-microvolt = <500000>;
241 regulator-max-microvolt = <750000>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200242 regulator-always-on;
243 regulator-over-current-protection;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200244 };
245
246 vdd_usb: ldo4 {
247 regulator-name = "vdd_usb";
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200248 interrupts = <IT_CURLIM_LDO4 0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200249 };
250
251 vdd_sd: ldo5 {
252 regulator-name = "vdd_sd";
253 regulator-min-microvolt = <2900000>;
254 regulator-max-microvolt = <2900000>;
255 interrupts = <IT_CURLIM_LDO5 0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200256 regulator-boot-on;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200257 };
258
259 v1v8: ldo6 {
260 regulator-name = "v1v8";
261 regulator-min-microvolt = <1800000>;
262 regulator-max-microvolt = <1800000>;
263 interrupts = <IT_CURLIM_LDO6 0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200264 };
265
266 vref_ddr: vref_ddr {
267 regulator-name = "vref_ddr";
268 regulator-always-on;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200269 };
270
Patrick Delaunayc5c90692019-11-06 16:16:32 +0100271 bst_out: boost {
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200272 regulator-name = "bst_out";
273 interrupts = <IT_OCP_BOOST 0>;
Patrick Delaunayc5c90692019-11-06 16:16:32 +0100274 };
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200275
276 vbus_otg: pwr_sw1 {
277 regulator-name = "vbus_otg";
278 interrupts = <IT_OCP_OTG 0>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200279 };
280
281 vbus_sw: pwr_sw2 {
282 regulator-name = "vbus_sw";
283 interrupts = <IT_OCP_SWOUT 0>;
Patrick Delaunayb9c16b72020-01-28 10:11:00 +0100284 regulator-active-discharge = <1>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200285 };
286 };
Patrick Delaunaya3705302019-07-11 11:15:28 +0200287
288 onkey {
289 compatible = "st,stpmic1-onkey";
290 interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
291 interrupt-names = "onkey-falling", "onkey-rising";
292 power-off-time-sec = <10>;
293 status = "okay";
294 };
295
296 watchdog {
297 compatible = "st,stpmic1-wdt";
298 status = "disabled";
299 };
Patrick Delaunay06020d82018-03-12 10:46:17 +0100300 };
301};
302
Fabien Dessennec2a97d32019-05-14 11:20:37 +0200303&ipcc {
304 status = "okay";
305};
306
Patrice Chotard00442d02019-02-12 16:50:38 +0100307&iwdg2 {
308 timeout-sec = <32>;
309 status = "okay";
310};
311
Patrick Delaunay26c24b42019-08-02 15:07:18 +0200312&m4_rproc {
Patrick Delaunay8c6e6132019-11-06 16:16:33 +0100313 memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
314 <&vdev0vring1>, <&vdev0buffer>;
Patrick Delaunayc4c5c5f2021-10-21 11:54:11 +0200315 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
316 mbox-names = "vq0", "vq1", "shutdown", "detach";
Patrick Delaunay8c6e6132019-11-06 16:16:33 +0100317 interrupt-parent = <&exti>;
318 interrupts = <68 1>;
Patrick Delaunay26c24b42019-08-02 15:07:18 +0200319 status = "okay";
320};
321
Patrick Delaunay900494d2020-01-28 10:10:59 +0100322&pwr_regulators {
323 vdd-supply = <&vdd>;
324 vdd_3v3_usbfs-supply = <&vdd_usb>;
Patrick Delaunay50599142018-07-09 15:17:19 +0200325};
326
Patrice Chotard00442d02019-02-12 16:50:38 +0100327&rng1 {
328 status = "okay";
329};
330
331&rtc {
332 status = "okay";
333};
334
Patrick Delaunay06020d82018-03-12 10:46:17 +0100335&sdmmc1 {
Patrick Delaunaya3705302019-07-11 11:15:28 +0200336 pinctrl-names = "default", "opendrain", "sleep";
Patrick Delaunay06020d82018-03-12 10:46:17 +0100337 pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
Patrick Delaunaya3705302019-07-11 11:15:28 +0200338 pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
339 pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200340 cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
341 disable-wp;
Patrice Chotard882d72e2019-02-12 17:17:58 +0100342 st,sig-dir;
343 st,neg-edge;
344 st,use-ckin;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100345 bus-width = <4>;
Patrice Chotardf6ef2292018-04-26 17:13:11 +0200346 vmmc-supply = <&vdd_sd>;
347 vqmmc-supply = <&sd_switch>;
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200348 sd-uhs-sdr12;
349 sd-uhs-sdr25;
350 sd-uhs-sdr50;
351 sd-uhs-ddr50;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100352 status = "okay";
353};
354
Patrick Delaunay8d050102018-03-20 10:54:52 +0100355&sdmmc2 {
Patrick Delaunay2b0bbf52019-11-06 16:16:34 +0100356 pinctrl-names = "default", "opendrain", "sleep";
Patrick Delaunay8d050102018-03-20 10:54:52 +0100357 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
Patrick Delaunay2b0bbf52019-11-06 16:16:34 +0100358 pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
359 pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
Patrick Delaunay8d050102018-03-20 10:54:52 +0100360 non-removable;
361 no-sd;
362 no-sdio;
Patrice Chotard882d72e2019-02-12 17:17:58 +0100363 st,neg-edge;
Patrick Delaunay8d050102018-03-20 10:54:52 +0100364 bus-width = <8>;
Patrick Delaunay50599142018-07-09 15:17:19 +0200365 vmmc-supply = <&v3v3>;
Patrick Delaunaydf0d20a2020-04-30 15:52:46 +0200366 vqmmc-supply = <&vdd>;
Patrick Delaunay2b0bbf52019-11-06 16:16:34 +0100367 mmc-ddr-3_3v;
Patrick Delaunay8d050102018-03-20 10:54:52 +0100368 status = "okay";
369};
370
Patrice Chotard00442d02019-02-12 16:50:38 +0100371&timers6 {
372 status = "okay";
Patrick Delaunaya3705302019-07-11 11:15:28 +0200373 /* spare dmas for other usage */
374 /delete-property/dmas;
375 /delete-property/dma-names;
Patrice Chotard00442d02019-02-12 16:50:38 +0100376 timer@5 {
377 status = "okay";
378 };
379};
380
Patrick Delaunay06020d82018-03-12 10:46:17 +0100381&uart4 {
Patrick Delaunay551efca2020-09-16 10:01:32 +0200382 pinctrl-names = "default", "sleep", "idle";
Patrick Delaunay06020d82018-03-12 10:46:17 +0100383 pinctrl-0 = <&uart4_pins_a>;
Patrick Delaunay551efca2020-09-16 10:01:32 +0200384 pinctrl-1 = <&uart4_sleep_pins_a>;
385 pinctrl-2 = <&uart4_idle_pins_a>;
Patrick Delaunay6f182192022-04-26 15:38:05 +0200386 /delete-property/dmas;
387 /delete-property/dma-names;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100388 status = "okay";
389};
Patrick Delaunay50599142018-07-09 15:17:19 +0200390
Patrick Delaunaya3705302019-07-11 11:15:28 +0200391&usbotg_hs {
392 vbus-supply = <&vbus_otg>;
393};
394
Patrick Delaunay50599142018-07-09 15:17:19 +0200395&usbphyc_port0 {
396 phy-supply = <&vdd_usb>;
Patrick Delaunay50599142018-07-09 15:17:19 +0200397};
398
399&usbphyc_port1 {
400 phy-supply = <&vdd_usb>;
Patrick Delaunay50599142018-07-09 15:17:19 +0200401};