Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 7 | #include <asm/arch/device.h> |
| 8 | #include <asm/arch/msg_port.h> |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 9 | #include <asm/arch/quark.h> |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 10 | |
| 11 | void msg_port_setup(int op, int port, int reg) |
| 12 | { |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 13 | qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG, |
| 14 | (((op) << 24) | ((port) << 16) | |
| 15 | (((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE)); |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 16 | } |
| 17 | |
| 18 | u32 msg_port_read(u8 port, u32 reg) |
| 19 | { |
| 20 | u32 value; |
| 21 | |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 22 | qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, |
| 23 | reg & 0xffffff00); |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 24 | msg_port_setup(MSG_OP_READ, port, reg); |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 25 | qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 26 | |
| 27 | return value; |
| 28 | } |
| 29 | |
| 30 | void msg_port_write(u8 port, u32 reg, u32 value) |
| 31 | { |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 32 | qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); |
| 33 | qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, |
| 34 | reg & 0xffffff00); |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 35 | msg_port_setup(MSG_OP_WRITE, port, reg); |
| 36 | } |
| 37 | |
| 38 | u32 msg_port_alt_read(u8 port, u32 reg) |
| 39 | { |
| 40 | u32 value; |
| 41 | |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 42 | qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, |
| 43 | reg & 0xffffff00); |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 44 | msg_port_setup(MSG_OP_ALT_READ, port, reg); |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 45 | qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 46 | |
| 47 | return value; |
| 48 | } |
| 49 | |
| 50 | void msg_port_alt_write(u8 port, u32 reg, u32 value) |
| 51 | { |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 52 | qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); |
| 53 | qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, |
| 54 | reg & 0xffffff00); |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 55 | msg_port_setup(MSG_OP_ALT_WRITE, port, reg); |
| 56 | } |
| 57 | |
| 58 | u32 msg_port_io_read(u8 port, u32 reg) |
| 59 | { |
| 60 | u32 value; |
| 61 | |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 62 | qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, |
| 63 | reg & 0xffffff00); |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 64 | msg_port_setup(MSG_OP_IO_READ, port, reg); |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 65 | qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 66 | |
| 67 | return value; |
| 68 | } |
| 69 | |
| 70 | void msg_port_io_write(u8 port, u32 reg, u32 value) |
| 71 | { |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 72 | qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); |
| 73 | qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, |
| 74 | reg & 0xffffff00); |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 75 | msg_port_setup(MSG_OP_IO_WRITE, port, reg); |
| 76 | } |