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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Bin Meng96c05fc2015-02-02 22:35:24 +08002/*
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
Bin Meng96c05fc2015-02-02 22:35:24 +08004 */
5
6#include <common.h>
Bin Meng96c05fc2015-02-02 22:35:24 +08007#include <asm/arch/device.h>
8#include <asm/arch/msg_port.h>
Bin Meng7ba52a02015-09-03 05:37:23 -07009#include <asm/arch/quark.h>
Bin Meng96c05fc2015-02-02 22:35:24 +080010
11void msg_port_setup(int op, int port, int reg)
12{
Bin Meng7ba52a02015-09-03 05:37:23 -070013 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
14 (((op) << 24) | ((port) << 16) |
15 (((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE));
Bin Meng96c05fc2015-02-02 22:35:24 +080016}
17
18u32 msg_port_read(u8 port, u32 reg)
19{
20 u32 value;
21
Bin Meng7ba52a02015-09-03 05:37:23 -070022 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
23 reg & 0xffffff00);
Bin Meng96c05fc2015-02-02 22:35:24 +080024 msg_port_setup(MSG_OP_READ, port, reg);
Bin Meng7ba52a02015-09-03 05:37:23 -070025 qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
Bin Meng96c05fc2015-02-02 22:35:24 +080026
27 return value;
28}
29
30void msg_port_write(u8 port, u32 reg, u32 value)
31{
Bin Meng7ba52a02015-09-03 05:37:23 -070032 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
33 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
34 reg & 0xffffff00);
Bin Meng96c05fc2015-02-02 22:35:24 +080035 msg_port_setup(MSG_OP_WRITE, port, reg);
36}
37
38u32 msg_port_alt_read(u8 port, u32 reg)
39{
40 u32 value;
41
Bin Meng7ba52a02015-09-03 05:37:23 -070042 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
43 reg & 0xffffff00);
Bin Meng96c05fc2015-02-02 22:35:24 +080044 msg_port_setup(MSG_OP_ALT_READ, port, reg);
Bin Meng7ba52a02015-09-03 05:37:23 -070045 qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
Bin Meng96c05fc2015-02-02 22:35:24 +080046
47 return value;
48}
49
50void msg_port_alt_write(u8 port, u32 reg, u32 value)
51{
Bin Meng7ba52a02015-09-03 05:37:23 -070052 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
53 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
54 reg & 0xffffff00);
Bin Meng96c05fc2015-02-02 22:35:24 +080055 msg_port_setup(MSG_OP_ALT_WRITE, port, reg);
56}
57
58u32 msg_port_io_read(u8 port, u32 reg)
59{
60 u32 value;
61
Bin Meng7ba52a02015-09-03 05:37:23 -070062 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
63 reg & 0xffffff00);
Bin Meng96c05fc2015-02-02 22:35:24 +080064 msg_port_setup(MSG_OP_IO_READ, port, reg);
Bin Meng7ba52a02015-09-03 05:37:23 -070065 qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
Bin Meng96c05fc2015-02-02 22:35:24 +080066
67 return value;
68}
69
70void msg_port_io_write(u8 port, u32 reg, u32 value)
71{
Bin Meng7ba52a02015-09-03 05:37:23 -070072 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
73 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
74 reg & 0xffffff00);
Bin Meng96c05fc2015-02-02 22:35:24 +080075 msg_port_setup(MSG_OP_IO_WRITE, port, reg);
76}