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Mingkai Hu0e58b512015-10-26 19:47:50 +08001/*
2 * Copyright 2014-2015, Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _FSL_LAYERSCAPE_CPU_H
8#define _FSL_LAYERSCAPE_CPU_H
9
10static struct cpu_type cpu_type_list[] = {
Prabhakar Kushwahaac7f2422016-06-24 13:48:13 +053011 CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
12 CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
13 CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
Priyanka Jain4a6f1732016-11-17 12:29:55 +053014 CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
15 CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
16 CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
17 CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
Prabhakar Kushwahaac7f2422016-06-24 13:48:13 +053018 CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
19 CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
Mingkai Hucd54c0f2016-07-05 16:01:55 +080020 CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
21 CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
Prabhakar Kushwahaac7f2422016-06-24 13:48:13 +053022 CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
23 CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
Mingkai Hu0e58b512015-10-26 19:47:50 +080024};
25
26#ifndef CONFIG_SYS_DCACHE_OFF
27
Mingkai Hu0e58b512015-10-26 19:47:50 +080028#ifdef CONFIG_FSL_LSCH3
29#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
30#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
31#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
32#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
33#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
34#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
35#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
36#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
37#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
38#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
39#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
40#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
41#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
42#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
43#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
44#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
45#define CONFIG_SYS_FSL_MC_SIZE 0x4000000
46#define CONFIG_SYS_FSL_NI_BASE 0x810000000
47#define CONFIG_SYS_FSL_NI_SIZE 0x8000000
48#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
49#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
50#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
51#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
52#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
53#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
54#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
55#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
56#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
57#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
58#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
59#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
60#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
61#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
62#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
Mingkai Hue4e93ea2015-10-26 19:47:51 +080063#elif defined(CONFIG_FSL_LSCH2)
64#define CONFIG_SYS_FSL_BOOTROM_BASE 0x0
65#define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000
66#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000
67#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
68#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
69#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
70#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
71#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
72#define CONFIG_SYS_FSL_IFC_BASE 0x60000000
73#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
74#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
75#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
76#define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000
77#define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000
78#define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000
79#define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
80#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000
81#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
82#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
83#define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000
84#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
Mingkai Hu0e58b512015-10-26 19:47:50 +080085#endif
86
York Sun9da8f502016-06-24 16:46:23 -070087#define EARLY_PGTABLE_SIZE 0x5000
88static struct mm_region early_map[] = {
Mingkai Hu0e58b512015-10-26 19:47:50 +080089#ifdef CONFIG_FSL_LSCH3
90 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
York Sun9da8f502016-06-24 16:46:23 -070091 CONFIG_SYS_FSL_CCSR_SIZE,
92 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
93 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
94 },
Mingkai Hu0e58b512015-10-26 19:47:50 +080095 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
York Sun9da8f502016-06-24 16:46:23 -070096 CONFIG_SYS_FSL_OCRAM_SIZE,
97 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
98 },
Yuan Yao331c87c2016-06-08 18:25:00 +080099 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
York Sun9da8f502016-06-24 16:46:23 -0700100 CONFIG_SYS_FSL_QSPI_SIZE1,
101 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
Mingkai Hu0e58b512015-10-26 19:47:50 +0800102 /* For IFC Region #1, only the first 4MB is cache-enabled */
103 { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
York Sun9da8f502016-06-24 16:46:23 -0700104 CONFIG_SYS_FSL_IFC_SIZE1_1,
105 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
106 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800107 { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
108 CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
109 CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
York Sun9da8f502016-06-24 16:46:23 -0700110 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
111 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800112 { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
York Sun9da8f502016-06-24 16:46:23 -0700113 CONFIG_SYS_FSL_IFC_SIZE1,
114 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
115 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800116 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
York Sun9da8f502016-06-24 16:46:23 -0700117 CONFIG_SYS_FSL_DRAM_SIZE1,
118 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
119 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
120 },
York Sun97ceebd2015-11-25 14:56:40 -0800121 /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
122 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
123 CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
York Sun9da8f502016-06-24 16:46:23 -0700124 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
125 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800126 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700127 CONFIG_SYS_FSL_DCSR_SIZE,
128 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
129 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
130 },
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800131 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
York Sun9da8f502016-06-24 16:46:23 -0700132 CONFIG_SYS_FSL_DRAM_SIZE2,
133 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
134 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
135 },
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800136#elif defined(CONFIG_FSL_LSCH2)
137 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700138 CONFIG_SYS_FSL_CCSR_SIZE,
139 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
140 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
141 },
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800142 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700143 CONFIG_SYS_FSL_OCRAM_SIZE,
144 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
145 },
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800146 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700147 CONFIG_SYS_FSL_DCSR_SIZE,
148 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
149 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
150 },
Qianyu Gong138a36a2016-01-25 15:16:07 +0800151 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700152 CONFIG_SYS_FSL_QSPI_SIZE,
153 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
154 },
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800155 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700156 CONFIG_SYS_FSL_IFC_SIZE,
157 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
158 },
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800159 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
York Sun9da8f502016-06-24 16:46:23 -0700160 CONFIG_SYS_FSL_DRAM_SIZE1,
161 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
162 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
163 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800164 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
York Sun9da8f502016-06-24 16:46:23 -0700165 CONFIG_SYS_FSL_DRAM_SIZE2,
166 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
167 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
168 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800169#endif
York Sun9da8f502016-06-24 16:46:23 -0700170 {}, /* list terminator */
Mingkai Hu0e58b512015-10-26 19:47:50 +0800171};
172
York Sun9da8f502016-06-24 16:46:23 -0700173static struct mm_region final_map[] = {
Mingkai Hu0e58b512015-10-26 19:47:50 +0800174#ifdef CONFIG_FSL_LSCH3
175 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700176 CONFIG_SYS_FSL_CCSR_SIZE,
177 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
178 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
179 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800180 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700181 CONFIG_SYS_FSL_OCRAM_SIZE,
182 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
183 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800184 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
York Sun9da8f502016-06-24 16:46:23 -0700185 CONFIG_SYS_FSL_DRAM_SIZE1,
186 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
187 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
188 },
Yuan Yao331c87c2016-06-08 18:25:00 +0800189 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
York Sun9da8f502016-06-24 16:46:23 -0700190 CONFIG_SYS_FSL_QSPI_SIZE1,
191 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
192 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800193 { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
York Sun9da8f502016-06-24 16:46:23 -0700194 CONFIG_SYS_FSL_QSPI_SIZE2,
195 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
196 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
197 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800198 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
York Sun9da8f502016-06-24 16:46:23 -0700199 CONFIG_SYS_FSL_IFC_SIZE2,
200 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
201 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800202 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700203 CONFIG_SYS_FSL_DCSR_SIZE,
204 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
205 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
206 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800207 { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700208 CONFIG_SYS_FSL_MC_SIZE,
209 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
210 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
211 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800212 { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700213 CONFIG_SYS_FSL_NI_SIZE,
214 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
215 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
216 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800217 /* For QBMAN portal, only the first 64MB is cache-enabled */
218 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700219 CONFIG_SYS_FSL_QBMAN_SIZE_1,
220 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
221 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
222 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800223 { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
224 CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
225 CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
York Sun9da8f502016-06-24 16:46:23 -0700226 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
227 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
228 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800229 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
York Sun9da8f502016-06-24 16:46:23 -0700230 CONFIG_SYS_PCIE1_PHYS_SIZE,
231 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
232 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
233 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800234 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
York Sun9da8f502016-06-24 16:46:23 -0700235 CONFIG_SYS_PCIE2_PHYS_SIZE,
236 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
237 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
238 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800239 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
York Sun9da8f502016-06-24 16:46:23 -0700240 CONFIG_SYS_PCIE3_PHYS_SIZE,
241 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
242 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
243 },
York Suncbe8e1c2016-04-04 11:41:26 -0700244#ifdef CONFIG_LS2080A
Mingkai Hu0e58b512015-10-26 19:47:50 +0800245 { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
York Sun9da8f502016-06-24 16:46:23 -0700246 CONFIG_SYS_PCIE4_PHYS_SIZE,
247 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
248 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
249 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800250#endif
251 { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700252 CONFIG_SYS_FSL_WRIOP1_SIZE,
253 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
254 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
255 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800256 { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700257 CONFIG_SYS_FSL_AIOP1_SIZE,
258 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
259 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
260 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800261 { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700262 CONFIG_SYS_FSL_PEBUF_SIZE,
263 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
264 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
265 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800266 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
York Sun9da8f502016-06-24 16:46:23 -0700267 CONFIG_SYS_FSL_DRAM_SIZE2,
268 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
269 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
270 },
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800271#elif defined(CONFIG_FSL_LSCH2)
272 { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700273 CONFIG_SYS_FSL_BOOTROM_SIZE,
274 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
275 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
276 },
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800277 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700278 CONFIG_SYS_FSL_CCSR_SIZE,
279 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
280 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
281 },
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800282 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700283 CONFIG_SYS_FSL_OCRAM_SIZE,
284 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
285 },
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800286 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700287 CONFIG_SYS_FSL_DCSR_SIZE,
288 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
289 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
290 },
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800291 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700292 CONFIG_SYS_FSL_QSPI_SIZE,
293 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
294 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
295 },
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800296 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700297 CONFIG_SYS_FSL_IFC_SIZE,
298 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
299 },
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800300 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
York Sun9da8f502016-06-24 16:46:23 -0700301 CONFIG_SYS_FSL_DRAM_SIZE1,
302 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
303 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
304 },
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800305 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
York Sun9da8f502016-06-24 16:46:23 -0700306 CONFIG_SYS_FSL_QBMAN_SIZE,
307 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
308 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
309 },
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800310 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
York Sun9da8f502016-06-24 16:46:23 -0700311 CONFIG_SYS_FSL_DRAM_SIZE2,
312 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
313 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
314 },
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800315 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
York Sun9da8f502016-06-24 16:46:23 -0700316 CONFIG_SYS_PCIE1_PHYS_SIZE,
317 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
318 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
319 },
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800320 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
York Sun9da8f502016-06-24 16:46:23 -0700321 CONFIG_SYS_PCIE2_PHYS_SIZE,
322 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
323 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
324 },
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800325 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
York Sun9da8f502016-06-24 16:46:23 -0700326 CONFIG_SYS_PCIE3_PHYS_SIZE,
327 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
328 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
329 },
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800330 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
York Sun9da8f502016-06-24 16:46:23 -0700331 CONFIG_SYS_FSL_DRAM_SIZE3,
332 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
333 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
334 },
Mingkai Hu0e58b512015-10-26 19:47:50 +0800335#endif
York Sun9da8f502016-06-24 16:46:23 -0700336#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
337 {}, /* space holder for secure mem */
Mingkai Hu0e58b512015-10-26 19:47:50 +0800338#endif
York Sun9da8f502016-06-24 16:46:23 -0700339 {},
340};
341#endif /* !CONFIG_SYS_DCACHE_OFF */
Mingkai Hu0e58b512015-10-26 19:47:50 +0800342
343int fsl_qoriq_core_to_cluster(unsigned int core);
344u32 cpu_mask(void);
345#endif /* _FSL_LAYERSCAPE_CPU_H */