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git01.mediatek.com / filogic / uboot / 022c2e2bfd718e402692dbbc080cbc3552059033 / . / include / asm-m68k / immap_5275.h
blob: 46426a33d62406bdc4dbafdffa9a54c9f33d9c89 [file] [log] [blame]
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]1/*
2 * MCF5274/5 Internal Memory Map
3 *
4 * Copyright (c) 2005 Arthur Shipkowski <art@videon-central.com>
5 * Based on work Copyright (c) 2003 Josef Baumgartner
6 * <josef.baumgartner@telex.de>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __IMMAP_5275__
28#define __IMMAP_5275__
29
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]30#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
31#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
32#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
33#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
34#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
35#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
36#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
37#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
38#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
39#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
40#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300)
41#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340)
42#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400)
43#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440)
44#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480)
45#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0)
46#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00)
47#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00)
48#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00)
49#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00001000)
50#define MMAP_FEC0FIFO (CONFIG_SYS_MBAR + 0x00001400)
51#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00001800)
52#define MMAP_FEC1FIFO (CONFIG_SYS_MBAR + 0x00001C00)
53#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000)
54#define MMAP_RCM (CONFIG_SYS_MBAR + 0x00110000)
55#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110004)
56#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000)
57#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000)
58#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000)
59#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000)
60#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000)
61#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000)
62#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000)
63#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000)
64#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000)
65#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000)
66#define MMAP_USB (CONFIG_SYS_MBAR + 0x001C0000)
67#define MMAP_PWM0 (CONFIG_SYS_MBAR + 0x001D0000)
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]68
TsiChung Liew7f1a0462008-10-21 10:03:07 +0000[diff] [blame]69#include <asm/coldfire/eport.h>
70#include <asm/coldfire/flexbus.h>
71#include <asm/coldfire/intctrl.h>
72#include <asm/coldfire/mdha.h>
73#include <asm/coldfire/pwm.h>
74#include <asm/coldfire/qspi.h>
75#include <asm/coldfire/rng.h>
76#include <asm/coldfire/skha.h>
77
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]78/* System configuration registers
79*/
80typedef struct sys_ctrl {
81 u32 ipsbar;
82 u32 res1;
83 u32 rambar;
84 u32 res2;
85 u8 crsr;
86 u8 cwcr;
87 u8 lpicr;
88 u8 cwsr;
89 u8 res3[8];
90 u32 mpark;
91 u8 mpr;
92 u8 res4[3];
93 u8 pacr0;
94 u8 pacr1;
95 u8 pacr2;
96 u8 pacr3;
97 u8 pacr4;
98 u8 res5;
99 u8 pacr5;
100 u8 pacr6;
101 u8 pacr7;
102 u8 res6;
103 u8 pacr8;
104 u8 res7;
105 u8 gpacr;
106 u8 res8[3];
107} sysctrl_t;
108/* SDRAM controller registers, offset: 0x040
109 */
110typedef struct sdram_ctrl {
111 u32 sdmr;
112 u32 sdcr;
113 u32 sdcfg1;
114 u32 sdcfg2;
115 u32 sdbar0;
116 u32 sdbmr0;
117 u32 sdbar1;
118 u32 sdbmr1;
119} sdramctrl_t;
120
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]121/* DMA module registers, offset 0x100
122 */
123typedef struct dma_ctrl {
124 u32 sar;
125 u32 dar;
126 u32 dsrbcr;
127 u32 dcr;
128} dma_t;
129
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]130/* GPIO port registers
131*/
132typedef struct gpio_ctrl {
133 /* Port Output Data Registers */
134 u8 podr_res1[4];
135 u8 podr_busctl;
136 u8 podr_addr;
137 u8 podr_res2[2];
138 u8 podr_cs;
139 u8 podr_res3;
140 u8 podr_fec0h;
141 u8 podr_fec0l;
142 u8 podr_feci2c;
143 u8 podr_qspi;
144 u8 podr_sdram;
145 u8 podr_timerh;
146 u8 podr_timerl;
147 u8 podr_uartl;
148 u8 podr_fec1h;
149 u8 podr_fec1l;
150 u8 podr_bs;
151 u8 podr_res4;
152 u8 podr_usbh;
153 u8 podr_usbl;
154 u8 podr_uarth;
155 u8 podr_res5[3];
156 /* Port Data Direction Registers */
157 u8 pddr_res1[4];
158 u8 pddr_busctl;
159 u8 pddr_addr;
160 u8 pddr_res2[2];
161 u8 pddr_cs;
162 u8 pddr_res3;
163 u8 pddr_fec0h;
164 u8 pddr_fec0l;
165 u8 pddr_feci2c;
166 u8 pddr_qspi;
167 u8 pddr_sdram;
168 u8 pddr_timerh;
169 u8 pddr_timerl;
170 u8 pddr_uartl;
171 u8 pddr_fec1h;
172 u8 pddr_fec1l;
173 u8 pddr_bs;
174 u8 pddr_res4;
175 u8 pddr_usbh;
176 u8 pddr_usbl;
177 u8 pddr_uarth;
178 u8 pddr_res5[3];
179 /* Port Pin Data/Set Registers */
180 u8 ppdsdr_res1[4];
181 u8 ppdsdr_busctl;
182 u8 ppdsdr_addr;
183 u8 ppdsdr_res2[2];
184 u8 ppdsdr_cs;
185 u8 ppdsdr_res3;
186 u8 ppdsdr_fec0h;
187 u8 ppdsdr_fec0l;
188 u8 ppdsdr_feci2c;
189 u8 ppdsdr_qspi;
190 u8 ppdsdr_sdram;
191 u8 ppdsdr_timerh;
192 u8 ppdsdr_timerl;
193 u8 ppdsdr_uartl;
194 u8 ppdsdr_fec1h;
195 u8 ppdsdr_fec1l;
196 u8 ppdsdr_bs;
197 u8 ppdsdr_res4;
198 u8 ppdsdr_usbh;
199 u8 ppdsdr_usbl;
200 u8 ppdsdr_uarth;
201 u8 ppdsdr_res5[3];
202 /* Port Clear Output Data Registers */
203 u8 pclrr_res1[4];
204 u8 pclrr_busctl;
205 u8 pclrr_addr;
206 u8 pclrr_res2[2];
207 u8 pclrr_cs;
208 u8 pclrr_res3;
209 u8 pclrr_fec0h;
210 u8 pclrr_fec0l;
211 u8 pclrr_feci2c;
212 u8 pclrr_qspi;
213 u8 pclrr_sdram;
214 u8 pclrr_timerh;
215 u8 pclrr_timerl;
216 u8 pclrr_uartl;
217 u8 pclrr_fec1h;
218 u8 pclrr_fec1l;
219 u8 pclrr_bs;
220 u8 pclrr_res4;
221 u8 pclrr_usbh;
222 u8 pclrr_usbl;
223 u8 pclrr_uarth;
224 u8 pclrr_res5[3];
225 /* Pin Assignment Registers */
226 u8 par_addr;
227 u8 par_cs;
228 u16 par_busctl;
229 u8 par_res1[2];
230 u16 par_usb;
231 u8 par_fec0hl;
232 u8 par_fec1hl;
233 u16 par_timer;
234 u16 par_uart;
235 u16 par_qspi;
236 u16 par_sdram;
237 u16 par_feci2c;
238 u8 par_bs;
239 u8 par_res2[3];
240} gpio_t;
241
242
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]243/* Watchdog registers
244 */
245typedef struct wdog_ctrl {
246 u16 wcr;
247 u16 wmr;
248 u16 wcntr;
249 u16 wsr;
250 u8 res4[114];
251} wdog_t;
252
253/* USB module registers
254*/
255typedef struct usb {
256 u16 res1;
257 u16 fnr;
258 u16 res2;
259 u16 fnmr;
260 u16 res3;
261 u16 rfmr;
262 u16 res4;
263 u16 rfmmr;
264 u8 res5[3];
265 u8 far;
266 u32 asr;
267 u32 drr1;
268 u32 drr2;
269 u16 res6;
270 u16 specr;
271 u16 res7;
272 u16 ep0sr;
273 u32 iep0cfg;
274 u32 oep0cfg;
275 u32 ep1cfg;
276 u32 ep2cfg;
277 u32 ep3cfg;
278 u32 ep4cfg;
279 u32 ep5cfg;
280 u32 ep6cfg;
281 u32 ep7cfg;
282 u32 ep0ctl;
283 u16 res8;
284 u16 ep1ctl;
285 u16 res9;
286 u16 ep2ctl;
287 u16 res10;
288 u16 ep3ctl;
289 u16 res11;
290 u16 ep4ctl;
291 u16 res12;
292 u16 ep5ctl;
293 u16 res13;
294 u16 ep6ctl;
295 u16 res14;
296 u16 ep7ctl;
297 u32 ep0isr;
298 u16 res15;
299 u16 ep1isr;
300 u16 res16;
301 u16 ep2isr;
302 u16 res17;
303 u16 ep3isr;
304 u16 res18;
305 u16 ep4isr;
306 u16 res19;
307 u16 ep5isr;
308 u16 res20;
309 u16 ep6isr;
310 u16 res21;
311 u16 ep7isr;
312 u32 ep0imr;
313 u16 res22;
314 u16 ep1imr;
315 u16 res23;
316 u16 ep2imr;
317 u16 res24;
318 u16 ep3imr;
319 u16 res25;
320 u16 ep4imr;
321 u16 res26;
322 u16 ep5imr;
323 u16 res27;
324 u16 ep6imr;
325 u16 res28;
326 u16 ep7imr;
327 u32 ep0dr;
328 u32 ep1dr;
329 u32 ep2dr;
330 u32 ep3dr;
331 u32 ep4dr;
332 u32 ep5dr;
333 u32 ep6dr;
334 u32 ep7dr;
335 u16 res29;
336 u16 ep0dpr;
337 u16 res30;
338 u16 ep1dpr;
339 u16 res31;
340 u16 ep2dpr;
341 u16 res32;
342 u16 ep3dpr;
343 u16 res33;
344 u16 ep4dpr;
345 u16 res34;
346 u16 ep5dpr;
347 u16 res35;
348 u16 ep6dpr;
349 u16 res36;
350 u16 ep7dpr;
351 u8 res37[788];
352 u8 cfgram[1024];
353} usb_t;
354
355/* PLL module registers
356 */
357typedef struct pll_ctrl {
358 u32 syncr;
359 u32 synsr;
360} pll_t;
361
362typedef struct rcm {
363 u8 rcr;
364 u8 rsr;
365} rcm_t;
366
367#endif /* __IMMAP_5275__ */