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wdenk9c53f402003-10-15 23:53:47 +00001/*
wdenk13eb2212004-07-09 23:27:13 +00002 * Copyright 2004 Freescale Semiconductor.
wdenk9c53f402003-10-15 23:53:47 +00003 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
wdenk13eb2212004-07-09 23:27:13 +000025/*
26 * mpc8560ads board configuration file
27 *
28 * Please refer to doc/README.mpc85xx for more info.
29 *
30 * Make sure you change the MAC address and other network params first,
31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
wdenk9c53f402003-10-15 23:53:47 +000032 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/* High Level Configuration Options */
wdenk13eb2212004-07-09 23:27:13 +000038#define CONFIG_BOOKE 1 /* BOOKE */
39#define CONFIG_E500 1 /* BOOKE e500 family */
40#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
Jon Loeligerf5ad3782005-07-23 10:37:35 -050041#define CONFIG_CPM2 1 /* has CPM2 */
wdenk13eb2212004-07-09 23:27:13 +000042#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
Kumar Gala75639e02008-06-11 00:44:10 -050043#define CONFIG_MPC8560 1
wdenk9c53f402003-10-15 23:53:47 +000044
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020045/*
46 * default CCARBAR is at 0xff700000
47 * assume U-Boot is less than 0.5MB
48 */
49#define CONFIG_SYS_TEXT_BASE 0xfff80000
50
wdenk13eb2212004-07-09 23:27:13 +000051#define CONFIG_PCI
Kumar Gala7738d5c2008-10-21 11:33:58 -050052#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denka1be4762008-05-20 16:00:29 +020053#define CONFIG_TSEC_ENET /* tsec ethernet support */
Andy Fleming8ed11962007-05-08 17:27:43 -050054#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
wdenk9c53f402003-10-15 23:53:47 +000055#define CONFIG_ENV_OVERWRITE
Kumar Gala5e0cf8b2008-01-16 01:32:06 -060056#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Peter Tyserd3d9a502009-09-16 22:03:08 -050057#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenk9c53f402003-10-15 23:53:47 +000058
wdenk13eb2212004-07-09 23:27:13 +000059/*
60 * sysclk for MPC85xx
61 *
62 * Two valid values are:
63 * 33000000
64 * 66000000
65 *
66 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
wdenk492b9e72004-08-01 23:02:45 +000067 * is likely the desired value here, so that is now the default.
68 * The board, however, can run at 66MHz. In any event, this value
69 * must match the settings of some switches. Details can be found
70 * in the README.mpc85xxads.
wdenk13eb2212004-07-09 23:27:13 +000071 */
72
wdenk492b9e72004-08-01 23:02:45 +000073#ifndef CONFIG_SYS_CLK_FREQ
74#define CONFIG_SYS_CLK_FREQ 33000000
wdenk9c53f402003-10-15 23:53:47 +000075#endif
76
wdenk492b9e72004-08-01 23:02:45 +000077
wdenk13eb2212004-07-09 23:27:13 +000078/*
79 * These can be toggled for performance analysis, otherwise use default.
80 */
81#define CONFIG_L2_CACHE /* toggle L2 cache */
82#define CONFIG_BTB /* toggle branch predition */
wdenk13eb2212004-07-09 23:27:13 +000083
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020084#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
wdenk9c53f402003-10-15 23:53:47 +000085
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020086#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
87#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk9c53f402003-10-15 23:53:47 +000088
wdenk9c53f402003-10-15 23:53:47 +000089
90/*
91 * Base addresses -- Note these are effective addresses where the
92 * actual resources get mapped (not physical addresses)
93 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020094#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
95#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
96#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
97#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
wdenk9c53f402003-10-15 23:53:47 +000098
Jon Loeliger99d50712008-03-18 11:12:44 -050099/* DDR Setup */
100#define CONFIG_FSL_DDR1
101#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
102#define CONFIG_DDR_SPD
103#undef CONFIG_FSL_DDR_INTERACTIVE
wdenk492b9e72004-08-01 23:02:45 +0000104
Jon Loeliger99d50712008-03-18 11:12:44 -0500105#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
106
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200107#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
108#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk492b9e72004-08-01 23:02:45 +0000109
Jon Loeliger99d50712008-03-18 11:12:44 -0500110#define CONFIG_NUM_DDR_CONTROLLERS 1
111#define CONFIG_DIMM_SLOTS_PER_CTLR 1
112#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
wdenk492b9e72004-08-01 23:02:45 +0000113
Jon Loeliger99d50712008-03-18 11:12:44 -0500114/* I2C addresses of SPD EEPROMs */
115#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
wdenk492b9e72004-08-01 23:02:45 +0000116
Jon Loeliger99d50712008-03-18 11:12:44 -0500117/* These are used when DDR doesn't use SPD. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200118#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
119#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
120#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
121#define CONFIG_SYS_DDR_TIMING_1 0x37344321
122#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
123#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
124#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
125#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
wdenk9c53f402003-10-15 23:53:47 +0000126
wdenk13eb2212004-07-09 23:27:13 +0000127/*
128 * SDRAM on the Local Bus
129 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200130#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
131#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk9c53f402003-10-15 23:53:47 +0000132
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
134#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk9c53f402003-10-15 23:53:47 +0000135
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200136#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
137#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
138#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
139#undef CONFIG_SYS_FLASH_CHECKSUM
140#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
141#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk9c53f402003-10-15 23:53:47 +0000142
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200143#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk13eb2212004-07-09 23:27:13 +0000144
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200145#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
146#define CONFIG_SYS_RAMBOOT
wdenk9c53f402003-10-15 23:53:47 +0000147#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200148#undef CONFIG_SYS_RAMBOOT
wdenk9c53f402003-10-15 23:53:47 +0000149#endif
150
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200151#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200152#define CONFIG_SYS_FLASH_CFI
153#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk13eb2212004-07-09 23:27:13 +0000154
155#undef CONFIG_CLOCKS_IN_MHZ
wdenk9c53f402003-10-15 23:53:47 +0000156
wdenk13eb2212004-07-09 23:27:13 +0000157
158/*
159 * Local Bus Definitions
160 */
161
162/*
163 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200164 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk13eb2212004-07-09 23:27:13 +0000165 *
166 * For BR2, need:
167 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
168 * port-size = 32-bits = BR2[19:20] = 11
169 * no parity checking = BR2[21:22] = 00
170 * SDRAM for MSEL = BR2[24:26] = 011
171 * Valid = BR[31] = 1
172 *
173 * 0 4 8 12 16 20 24 28
174 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
175 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200176 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk13eb2212004-07-09 23:27:13 +0000177 * FIXME: the top 17 bits of BR2.
178 */
wdenk9c53f402003-10-15 23:53:47 +0000179
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200180#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk13eb2212004-07-09 23:27:13 +0000181
182/*
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200183 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk13eb2212004-07-09 23:27:13 +0000184 *
185 * For OR2, need:
186 * 64MB mask for AM, OR2[0:7] = 1111 1100
187 * XAM, OR2[17:18] = 11
188 * 9 columns OR2[19-21] = 010
189 * 13 rows OR2[23-25] = 100
190 * EAD set for extra time OR[31] = 1
191 *
192 * 0 4 8 12 16 20 24 28
193 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
194 */
195
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200196#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk13eb2212004-07-09 23:27:13 +0000197
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200198#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
199#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
200#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
201#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
wdenk13eb2212004-07-09 23:27:13 +0000202
Kumar Gala727c6a62009-03-26 01:34:38 -0500203#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
204 | LSDMR_RFCR5 \
205 | LSDMR_PRETOACT3 \
206 | LSDMR_ACTTORW3 \
207 | LSDMR_BL8 \
208 | LSDMR_WRC2 \
209 | LSDMR_CL3 \
210 | LSDMR_RFEN \
wdenk13eb2212004-07-09 23:27:13 +0000211 )
212
213/*
214 * SDRAM Controller configuration sequence.
215 */
Kumar Gala727c6a62009-03-26 01:34:38 -0500216#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
217#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
218#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
219#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
220#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
wdenk13eb2212004-07-09 23:27:13 +0000221
wdenk9c53f402003-10-15 23:53:47 +0000222
wdenk492b9e72004-08-01 23:02:45 +0000223/*
224 * 32KB, 8-bit wide for ADS config reg
225 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200226#define CONFIG_SYS_BR4_PRELIM 0xf8000801
227#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
228#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
wdenk9c53f402003-10-15 23:53:47 +0000229
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200230#define CONFIG_SYS_INIT_RAM_LOCK 1
231#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200232#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk9c53f402003-10-15 23:53:47 +0000233
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200234#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200235#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200236#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk9c53f402003-10-15 23:53:47 +0000237
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200238#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
239#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk9c53f402003-10-15 23:53:47 +0000240
241/* Serial Port */
wdenk13eb2212004-07-09 23:27:13 +0000242#define CONFIG_CONS_ON_SCC /* define if console on SCC */
243#undef CONFIG_CONS_NONE /* define if console on something else */
244#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
wdenk9c53f402003-10-15 23:53:47 +0000245
Wolfgang Denka1be4762008-05-20 16:00:29 +0200246#define CONFIG_BAUDRATE 115200
wdenk9c53f402003-10-15 23:53:47 +0000247
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200248#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk9c53f402003-10-15 23:53:47 +0000249 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
250
251/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200252#define CONFIG_SYS_HUSH_PARSER
253#ifdef CONFIG_SYS_HUSH_PARSER
254#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk9c53f402003-10-15 23:53:47 +0000255#endif
256
Matthew McClintock3d403172006-06-28 10:43:36 -0500257/* pass open firmware flat tree */
Kumar Galaf2982fa2007-11-28 22:40:31 -0600258#define CONFIG_OF_LIBFDT 1
259#define CONFIG_OF_BOARD_SETUP 1
260#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock3d403172006-06-28 10:43:36 -0500261
Jon Loeliger43d818f2006-10-20 15:50:15 -0500262/*
263 * I2C
264 */
265#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
266#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk9c53f402003-10-15 23:53:47 +0000267#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200268#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
269#define CONFIG_SYS_I2C_SLAVE 0x7F
270#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
271#define CONFIG_SYS_I2C_OFFSET 0x3000
wdenk9c53f402003-10-15 23:53:47 +0000272
wdenk13eb2212004-07-09 23:27:13 +0000273/* RapidIO MMU */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600274#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
Kumar Gala3fe80872008-12-02 16:08:36 -0600275#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600276#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200277#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
wdenk9c53f402003-10-15 23:53:47 +0000278
wdenk13eb2212004-07-09 23:27:13 +0000279/*
280 * General PCI
Sergei Shtylyov6ffad932006-12-27 22:07:15 +0300281 * Memory space is mapped 1-1, but I/O space must start from 0.
wdenk13eb2212004-07-09 23:27:13 +0000282 */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600283#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala3fe80872008-12-02 16:08:36 -0600284#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600285#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200286#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600287#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600288#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200289#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
290#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk13eb2212004-07-09 23:27:13 +0000291
292#if defined(CONFIG_PCI)
293
wdenk9c53f402003-10-15 23:53:47 +0000294#define CONFIG_NET_MULTI
Wolfgang Denka1be4762008-05-20 16:00:29 +0200295#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk13eb2212004-07-09 23:27:13 +0000296
297#undef CONFIG_EEPRO100
wdenk9c53f402003-10-15 23:53:47 +0000298#undef CONFIG_TULIP
wdenk13eb2212004-07-09 23:27:13 +0000299
300#if !defined(CONFIG_PCI_PNP)
301 #define PCI_ENET0_IOADDR 0xe0000000
302 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denka1be4762008-05-20 16:00:29 +0200303 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk9c53f402003-10-15 23:53:47 +0000304#endif
wdenk13eb2212004-07-09 23:27:13 +0000305
306#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200307#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk13eb2212004-07-09 23:27:13 +0000308
309#endif /* CONFIG_PCI */
310
311
Andy Fleming8ed11962007-05-08 17:27:43 -0500312#ifdef CONFIG_TSEC_ENET
wdenk13eb2212004-07-09 23:27:13 +0000313
314#ifndef CONFIG_NET_MULTI
Wolfgang Denka1be4762008-05-20 16:00:29 +0200315#define CONFIG_NET_MULTI 1
wdenk13eb2212004-07-09 23:27:13 +0000316#endif
317
Andy Fleming8ed11962007-05-08 17:27:43 -0500318#ifndef CONFIG_MII
wdenk13eb2212004-07-09 23:27:13 +0000319#define CONFIG_MII 1 /* MII PHY management */
Andy Fleming8ed11962007-05-08 17:27:43 -0500320#endif
Kim Phillips177e58f2007-05-16 16:52:19 -0500321#define CONFIG_TSEC1 1
322#define CONFIG_TSEC1_NAME "TSEC0"
323#define CONFIG_TSEC2 1
324#define CONFIG_TSEC2_NAME "TSEC1"
wdenk13eb2212004-07-09 23:27:13 +0000325#define TSEC1_PHY_ADDR 0
326#define TSEC2_PHY_ADDR 1
327#define TSEC1_PHYIDX 0
328#define TSEC2_PHYIDX 0
Andy Fleming09b88df2007-08-15 20:03:25 -0500329#define TSEC1_FLAGS TSEC_GIGABIT
330#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500331
332/* Options are: TSEC[0-1] */
333#define CONFIG_ETHPRIME "TSEC0"
wdenk13eb2212004-07-09 23:27:13 +0000334
Andy Fleming8ed11962007-05-08 17:27:43 -0500335#endif /* CONFIG_TSEC_ENET */
336
Wolfgang Denka1be4762008-05-20 16:00:29 +0200337#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
wdenk13eb2212004-07-09 23:27:13 +0000338
Wolfgang Denka1be4762008-05-20 16:00:29 +0200339#undef CONFIG_ETHER_NONE /* define if ether on something else */
wdenk13eb2212004-07-09 23:27:13 +0000340#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
341
342#if (CONFIG_ETHER_INDEX == 2)
wdenk9c53f402003-10-15 23:53:47 +0000343 /*
344 * - Rx-CLK is CLK13
345 * - Tx-CLK is CLK14
346 * - Select bus for bd/buffers
347 * - Full duplex
348 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200349 #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
350 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
351 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
352 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
wdenk9c53f402003-10-15 23:53:47 +0000353 #define FETH2_RST 0x01
wdenk13eb2212004-07-09 23:27:13 +0000354#elif (CONFIG_ETHER_INDEX == 3)
wdenk9c53f402003-10-15 23:53:47 +0000355 /* need more definitions here for FE3 */
356 #define FETH3_RST 0x80
Wolfgang Denka1be4762008-05-20 16:00:29 +0200357#endif /* CONFIG_ETHER_INDEX */
wdenk13eb2212004-07-09 23:27:13 +0000358
Andy Fleming8ed11962007-05-08 17:27:43 -0500359#ifndef CONFIG_MII
360#define CONFIG_MII 1 /* MII PHY management */
361#endif
362
wdenk13eb2212004-07-09 23:27:13 +0000363#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
364
wdenk9c53f402003-10-15 23:53:47 +0000365/*
366 * GPIO pins used for bit-banged MII communications
367 */
368#define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellini25e30722009-10-10 12:42:22 +0200369#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
370 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
371#define MDC_DECLARE MDIO_DECLARE
372
wdenk9c53f402003-10-15 23:53:47 +0000373#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
374#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
375#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
376
377#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
378 else iop->pdat &= ~0x00400000
379
380#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
381 else iop->pdat &= ~0x00200000
382
383#define MIIDELAY udelay(1)
wdenk13eb2212004-07-09 23:27:13 +0000384
wdenk9c53f402003-10-15 23:53:47 +0000385#endif
386
wdenk13eb2212004-07-09 23:27:13 +0000387
388/*
389 * Environment
390 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200391#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200392 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200393 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200394 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
395 #define CONFIG_ENV_SIZE 0x2000
wdenk9c53f402003-10-15 23:53:47 +0000396#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200397 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD68a87562008-09-10 22:48:00 +0200398 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200399 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200400 #define CONFIG_ENV_SIZE 0x2000
wdenk9c53f402003-10-15 23:53:47 +0000401#endif
402
wdenk13eb2212004-07-09 23:27:13 +0000403#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200404#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk9c53f402003-10-15 23:53:47 +0000405
Jon Loeligere63319f2007-06-13 13:22:08 -0500406/*
Jon Loeligered26c742007-07-10 09:10:49 -0500407 * BOOTP options
408 */
409#define CONFIG_BOOTP_BOOTFILESIZE
410#define CONFIG_BOOTP_BOOTPATH
411#define CONFIG_BOOTP_GATEWAY
412#define CONFIG_BOOTP_HOSTNAME
413
414
415/*
Jon Loeligere63319f2007-06-13 13:22:08 -0500416 * Command line configuration.
417 */
418#include <config_cmd_default.h>
419
420#define CONFIG_CMD_PING
421#define CONFIG_CMD_I2C
Kumar Gala260fac32007-12-07 12:04:30 -0600422#define CONFIG_CMD_ELF
Kumar Gala489675d2008-09-22 23:40:42 -0500423#define CONFIG_CMD_IRQ
424#define CONFIG_CMD_SETEXPR
Becky Bruceee888da2010-06-17 11:37:25 -0500425#define CONFIG_CMD_REGINFO
Jon Loeligere63319f2007-06-13 13:22:08 -0500426
427#if defined(CONFIG_PCI)
428 #define CONFIG_CMD_PCI
429#endif
430
431#if defined(CONFIG_ETHER_ON_FCC)
432 #define CONFIG_CMD_MII
433#endif
434
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200435#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysinger78dcaf42009-01-28 19:08:14 -0500436 #undef CONFIG_CMD_SAVEENV
Jon Loeligere63319f2007-06-13 13:22:08 -0500437 #undef CONFIG_CMD_LOADS
wdenk9c53f402003-10-15 23:53:47 +0000438#endif
wdenk13eb2212004-07-09 23:27:13 +0000439
wdenk9c53f402003-10-15 23:53:47 +0000440
wdenk13eb2212004-07-09 23:27:13 +0000441#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk9c53f402003-10-15 23:53:47 +0000442
443/*
444 * Miscellaneous configurable options
445 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200446#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillipsf7758c12010-07-14 19:47:18 -0500447#define CONFIG_CMDLINE_EDITING /* Command-line editing */
448#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200449#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
450#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk13eb2212004-07-09 23:27:13 +0000451
Jon Loeligere63319f2007-06-13 13:22:08 -0500452#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200453 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk9c53f402003-10-15 23:53:47 +0000454#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200455 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk9c53f402003-10-15 23:53:47 +0000456#endif
wdenk13eb2212004-07-09 23:27:13 +0000457
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200458#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
459#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
460#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
461#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
wdenk9c53f402003-10-15 23:53:47 +0000462
463/*
464 * For booting Linux, the board info and command line data
Kumar Gala1535d812009-07-15 08:54:50 -0500465 * have to be in the first 16 MB of memory, since this is
wdenk9c53f402003-10-15 23:53:47 +0000466 * the maximum mapped by the Linux kernel during initialization.
467 */
Kumar Gala1535d812009-07-15 08:54:50 -0500468#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
wdenk9c53f402003-10-15 23:53:47 +0000469
Jon Loeligere63319f2007-06-13 13:22:08 -0500470#if defined(CONFIG_CMD_KGDB)
wdenk9c53f402003-10-15 23:53:47 +0000471#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
472#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
473#endif
474
wdenk492b9e72004-08-01 23:02:45 +0000475
476/*
477 * Environment Configuration
478 */
479
wdenk13eb2212004-07-09 23:27:13 +0000480/* The mac addresses for all ethernet interface */
wdenk9c53f402003-10-15 23:53:47 +0000481#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Andy Fleming458c3892007-08-16 16:35:02 -0500482#define CONFIG_HAS_ETH0
wdenk13eb2212004-07-09 23:27:13 +0000483#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
wdenk54070ab2004-12-31 09:32:47 +0000484#define CONFIG_HAS_ETH1
wdenk13eb2212004-07-09 23:27:13 +0000485#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
wdenk54070ab2004-12-31 09:32:47 +0000486#define CONFIG_HAS_ETH2
wdenk13eb2212004-07-09 23:27:13 +0000487#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
Kumar Galaf2982fa2007-11-28 22:40:31 -0600488#define CONFIG_HAS_ETH3
489#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
wdenk9c53f402003-10-15 23:53:47 +0000490#endif
491
wdenk13eb2212004-07-09 23:27:13 +0000492#define CONFIG_IPADDR 192.168.1.253
493
494#define CONFIG_HOSTNAME unknown
495#define CONFIG_ROOTPATH /nfsroot
496#define CONFIG_BOOTFILE your.uImage
497
498#define CONFIG_SERVERIP 192.168.1.1
499#define CONFIG_GATEWAYIP 192.168.1.1
500#define CONFIG_NETMASK 255.255.255.0
501
502#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
503
wdenk492b9e72004-08-01 23:02:45 +0000504#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
wdenk13eb2212004-07-09 23:27:13 +0000505#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
506
507#define CONFIG_BAUDRATE 115200
508
wdenk492b9e72004-08-01 23:02:45 +0000509#define CONFIG_EXTRA_ENV_SETTINGS \
Andy Fleming29e484e2008-07-14 20:04:40 -0500510 "netdev=eth0\0" \
511 "consoledev=ttyCPM\0" \
512 "ramdiskaddr=1000000\0" \
513 "ramdiskfile=your.ramdisk.u-boot\0" \
514 "fdtaddr=400000\0" \
515 "fdtfile=mpc8560ads.dtb\0"
wdenk13eb2212004-07-09 23:27:13 +0000516
wdenk492b9e72004-08-01 23:02:45 +0000517#define CONFIG_NFSBOOTCOMMAND \
Andy Fleming29e484e2008-07-14 20:04:40 -0500518 "setenv bootargs root=/dev/nfs rw " \
519 "nfsroot=$serverip:$rootpath " \
520 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
521 "console=$consoledev,$baudrate $othbootargs;" \
522 "tftp $loadaddr $bootfile;" \
523 "tftp $fdtaddr $fdtfile;" \
524 "bootm $loadaddr - $fdtaddr"
wdenk13eb2212004-07-09 23:27:13 +0000525
526#define CONFIG_RAMBOOTCOMMAND \
Andy Fleming29e484e2008-07-14 20:04:40 -0500527 "setenv bootargs root=/dev/ram rw " \
528 "console=$consoledev,$baudrate $othbootargs;" \
529 "tftp $ramdiskaddr $ramdiskfile;" \
530 "tftp $loadaddr $bootfile;" \
531 "tftp $fdtaddr $fdtfile;" \
532 "bootm $loadaddr $ramdiskaddr $fdtaddr"
wdenk13eb2212004-07-09 23:27:13 +0000533
534#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
wdenk9c53f402003-10-15 23:53:47 +0000535
536#endif /* __CONFIG_H */