blob: 6535a19d7f80494efae4341f4bd14a2581cd12ac [file] [log] [blame]
wdenk153d5112002-08-30 11:07:04 +00001/*
2 * (C) Copyright 2001
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include "ar405.h"
26#include <asm/processor.h>
27#include <command.h>
wdenk153d5112002-08-30 11:07:04 +000028
wdenk57b2d802003-06-27 21:31:46 +000029/*cmd_boot.c*/
30extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
wdenk153d5112002-08-30 11:07:04 +000031
32/* ------------------------------------------------------------------------- */
33
34#if 0
35#define FPGA_DEBUG
36#endif
37
38/* fpga configuration data - generated by bin2cc */
39const unsigned char fpgadata[] = {
40#include "fpgadata.c"
41};
42
43/*
44 * include common fpga code (for esd boards)
45 */
46#include "../common/fpga.c"
47
48
wdenkda55c6e2004-01-20 23:12:12 +000049int board_early_init_f (void)
wdenk153d5112002-08-30 11:07:04 +000050{
51 DECLARE_GLOBAL_DATA_PTR;
52
53 int index, len, i;
54 int status;
55
56#ifdef FPGA_DEBUG
57 /* set up serial port with default baudrate */
58 (void) get_clocks ();
59 gd->baudrate = CONFIG_BAUDRATE;
60 serial_init ();
61 console_init_f ();
62#endif
63
64 /*
65 * Boot onboard FPGA
66 */
67 status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
68 if (status != 0) {
69 /* booting FPGA failed */
70#ifndef FPGA_DEBUG
71 /* set up serial port with default baudrate */
72 (void) get_clocks ();
73 gd->baudrate = CONFIG_BAUDRATE;
74 serial_init ();
75 console_init_f ();
76#endif
77 printf ("\nFPGA: Booting failed ");
78 switch (status) {
79 case ERROR_FPGA_PRG_INIT_LOW:
80 printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
81 break;
82 case ERROR_FPGA_PRG_INIT_HIGH:
83 printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
84 break;
85 case ERROR_FPGA_PRG_DONE:
86 printf ("(Timeout: DONE not high after programming FPGA)\n ");
87 break;
88 }
89
90 /* display infos on fpgaimage */
91 index = 15;
92 for (i = 0; i < 4; i++) {
93 len = fpgadata[index];
94 printf ("FPGA: %s\n", &(fpgadata[index + 1]));
95 index += len + 3;
96 }
97 putc ('\n');
98 /* delayed reboot */
99 for (i = 20; i > 0; i--) {
100 printf ("Rebooting in %2d seconds \r", i);
101 for (index = 0; index < 1000; index++)
102 udelay (1000);
103 }
104 putc ('\n');
105 do_reset (NULL, 0, 0, NULL);
106 }
107
108 /*
109 * IRQ 0-15 405GP internally generated; active high; level sensitive
110 * IRQ 16 405GP internally generated; active low; level sensitive
111 * IRQ 17-24 RESERVED
112 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
113 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
114 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
115 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
116 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
117 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
118 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
119 */
120 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
121 mtdcr (uicer, 0x00000000); /* disable all ints */
122 mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
123 mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */
124 mtdcr (uictr, 0x10000000); /* set int trigger levels */
125 mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
126 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
127
128 *(ushort *) 0xf03000ec = 0x0fff; /* enable all interrupts in fpga */
129
130 return 0;
131}
132
133
134/* ------------------------------------------------------------------------- */
135
136/*
137 * Check Board Identity:
138 */
139
140int checkboard (void)
141{
142 int index;
143 int len;
144 unsigned char str[64];
145 int i = getenv_r ("serial#", str, sizeof (str));
146
147 puts ("Board: ");
148
149 if (!i || strncmp (str, "AR405", 5)) {
150 puts ("### No HW ID - assuming AR405\n");
151 return (0);
152 }
153
154 puts (str);
155
156 puts ("\nFPGA: ");
157
158 /* display infos on fpgaimage */
159 index = 15;
160 for (i = 0; i < 4; i++) {
161 len = fpgadata[index];
162 printf ("%s ", &(fpgadata[index + 1]));
163 index += len + 3;
164 }
165
166 putc ('\n');
167
168 return 0;
169}
170
171/* ------------------------------------------------------------------------- */
172
173long int initdram (int board_type)
174{
175 return (16 * 1024 * 1024);
176}
177
178/* ------------------------------------------------------------------------- */
179
180int testdram (void)
181{
182 /* TODO: XXX XXX XXX */
183 printf ("test: 16 MB - ok\n");
184
185 return (0);
186}
187
188/* ------------------------------------------------------------------------- */