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Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +01001/*
2 * Copyright (C) 2004-2007 ARM Limited.
3 * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * As a special exception, if other files instantiate templates or use macros
19 * or inline functions from this file, or you compile this file and link it
20 * with other works to produce a work based on this file, this file does not
21 * by itself cause the resulting work to be covered by the GNU General Public
22 * License. However the source code for this file must still be made available
23 * in accordance with section (3) of the GNU General Public License.
24
25 * This exception does not invalidate any other reasons why a work based on
26 * this file might be covered by the GNU General Public License.
27 */
28
29#include <common.h>
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010030
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020031#if defined(CONFIG_CPU_V6)
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010032/*
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020033 * ARMV6
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010034 */
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020035#define DCC_RBIT (1 << 30)
36#define DCC_WBIT (1 << 29)
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010037
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020038#define write_dcc(x) \
39 __asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x))
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010040
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020041#define read_dcc(x) \
42 __asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x))
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010043
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020044#define status_dcc(x) \
45 __asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x))
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010046
Jean-Christophe PLAGNIOL-VILLARD195bb7c2009-05-15 23:47:14 +020047#elif defined(CONFIG_CPU_XSCALE)
48/*
49 * XSCALE
50 */
51#define DCC_RBIT (1 << 31)
52#define DCC_WBIT (1 << 28)
53
54#define write_dcc(x) \
55 __asm__ volatile ("mcr p14, 0, %0, c8, c0, 0\n" : : "r" (x))
56
57#define read_dcc(x) \
58 __asm__ volatile ("mrc p14, 0, %0, c9, c0, 0\n" : "=r" (x))
59
60#define status_dcc(x) \
61 __asm__ volatile ("mrc p14, 0, %0, c14, c0, 0\n" : "=r" (x))
62
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020063#else
64#define DCC_RBIT (1 << 0)
65#define DCC_WBIT (1 << 1)
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010066
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020067#define write_dcc(x) \
68 __asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x))
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010069
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020070#define read_dcc(x) \
71 __asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x))
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010072
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020073#define status_dcc(x) \
74 __asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x))
75
76#endif
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010077
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020078#define can_read_dcc(x) do { \
79 status_dcc(x); \
80 x &= DCC_RBIT; \
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010081 } while (0);
82
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +020083#define can_write_dcc(x) do { \
84 status_dcc(x); \
85 x &= DCC_WBIT; \
86 x = (x == 0); \
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010087 } while (0);
88
89#define TIMEOUT_COUNT 0x4000000
90
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010091int arm_dcc_init(void)
92{
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +010093 return 0;
94}
95
96int arm_dcc_getc(void)
97{
98 int ch;
99 register unsigned int reg;
100
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +0200101 do {
102 can_read_dcc(reg);
103 } while (!reg);
104 read_dcc(ch);
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +0100105
106 return ch;
107}
108
109void arm_dcc_putc(char ch)
110{
111 register unsigned int reg;
112 unsigned int timeout_count = TIMEOUT_COUNT;
113
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +0200114 while (--timeout_count) {
115 can_write_dcc(reg);
116 if (reg)
117 break;
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +0100118 }
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +0200119 if (timeout_count == 0)
120 return;
121 else
122 write_dcc(ch);
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +0100123}
124
125void arm_dcc_puts(const char *s)
126{
127 while (*s)
128 arm_dcc_putc(*s++);
129}
130
131int arm_dcc_tstc(void)
132{
133 register unsigned int reg;
134
Jean-Christophe PLAGNIOL-VILLARD6c82f4d2009-05-15 23:47:14 +0200135 can_read_dcc(reg);
Jean-Christophe PLAGNIOL-VILLARDb8023102009-02-22 15:49:28 +0100136
137 return reg;
138}
139
Michal Simek0828cf22013-01-22 23:40:06 +0000140__weak struct serial_device *default_serial_console(void)
141{
142 return NULL;
143}