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git01.mediatek.com / filogic / uboot / 00d7e5bf234e2fbef112fee2d8fc4001d2fd0211 / . / board / freescale / t208xqds / spl.c
blob: a71c6171218cc47efb54a07c2cbad1cb20901082 [file] [log] [blame]
Shengzhou Liud11b3cb2014-04-18 16:43:39 +0800[diff] [blame]1/* Copyright 2013 Freescale Semiconductor, Inc.
2 *
3 * SPDX-License-Identifier: GPL-2.0+
4 */
5
6#include <common.h>
7#include <malloc.h>
8#include <ns16550.h>
9#include <nand.h>
10#include <i2c.h>
11#include <mmc.h>
12#include <fsl_esdhc.h>
13#include <spi_flash.h>
14#include "../common/qixis.h"
15#include "t208xqds_qixis.h"
16
17DECLARE_GLOBAL_DATA_PTR;
18
19phys_size_t get_effective_memsize(void)
20{
21 return CONFIG_SYS_L3_SIZE;
22}
23
24unsigned long get_board_sys_clk(void)
25{
26 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
27
28 switch (sysclk_conf & 0x0F) {
29 case QIXIS_SYSCLK_83:
30 return 83333333;
31 case QIXIS_SYSCLK_100:
32 return 100000000;
33 case QIXIS_SYSCLK_125:
34 return 125000000;
35 case QIXIS_SYSCLK_133:
36 return 133333333;
37 case QIXIS_SYSCLK_150:
38 return 150000000;
39 case QIXIS_SYSCLK_160:
40 return 160000000;
41 case QIXIS_SYSCLK_166:
42 return 166666666;
43 }
44 return 66666666;
45}
46
47unsigned long get_board_ddr_clk(void)
48{
49 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
50
51 switch ((ddrclk_conf & 0x30) >> 4) {
52 case QIXIS_DDRCLK_100:
53 return 100000000;
54 case QIXIS_DDRCLK_125:
55 return 125000000;
56 case QIXIS_DDRCLK_133:
57 return 133333333;
58 }
59 return 66666666;
60}
61
62void board_init_f(ulong bootflag)
63{
64 u32 plat_ratio, sys_clk, ccb_clk;
65 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
66
67 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
68 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
69
70 /* Update GD pointer */
71 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
72
73 console_init_f();
74
75 /* initialize selected port with appropriate baud rate */
76 sys_clk = get_board_sys_clk();
77 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
78 ccb_clk = sys_clk * plat_ratio / 2;
79
80 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
81 ccb_clk / 16 / CONFIG_BAUDRATE);
82
83#if defined(CONFIG_SPL_MMC_BOOT)
84 puts("\nSD boot...\n");
85#elif defined(CONFIG_SPL_SPI_BOOT)
86 puts("\nSPI boot...\n");
87#elif defined(CONFIG_SPL_NAND_BOOT)
88 puts("\nNAND boot...\n");
89#endif
90
91 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
92}
93
94void board_init_r(gd_t *gd, ulong dest_addr)
95{
96 bd_t *bd;
97
98 bd = (bd_t *)(gd + sizeof(gd_t));
99 memset(bd, 0, sizeof(bd_t));
100 gd->bd = bd;
101 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
102 bd->bi_memsize = CONFIG_SYS_L3_SIZE;
103
104 probecpu();
105 get_clocks();
106 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
107 CONFIG_SPL_RELOC_MALLOC_SIZE);
108
109#ifdef CONFIG_SPL_NAND_BOOT
110 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
111 (uchar *)CONFIG_ENV_ADDR);
112#endif
113#ifdef CONFIG_SPL_MMC_BOOT
114 mmc_initialize(bd);
115 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
116 (uchar *)CONFIG_ENV_ADDR);
117#endif
118#ifdef CONFIG_SPL_SPI_BOOT
119 spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
120 (uchar *)CONFIG_ENV_ADDR);
121#endif
122
123 gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
124 gd->env_valid = 1;
125
126 i2c_init_all();
127
128 gd->ram_size = initdram(0);
129
130#ifdef CONFIG_SPL_MMC_BOOT
131 mmc_boot();
132#elif defined(CONFIG_SPL_SPI_BOOT)
133 spi_boot();
134#elif defined(CONFIG_SPL_NAND_BOOT)
135 nand_boot();
136#endif
137}