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git01.mediatek.com / filogic / uboot / 0082b2e23040f8ad808745f5541dc5e5ae300a68 / . / arch / x86 / cpu / apollolake / Kconfig
blob: c7f26d171cb0374e431020b796becfc56fa9fd8b [file] [log] [blame]
Simon Glassfcc2ce92019-12-08 17:40:17 -0700[diff] [blame]1# SPDX-License-Identifier: GPL-2.0
2#
3# Copyright 2019 Google LLC
4#
5
6config INTEL_APOLLOLAKE
7 bool
8 select FSP_VERSION2
9 select HAVE_FSP
10 select ARCH_MISC_INIT
11 select USE_CAR
Simon Glassc6eeff92021-02-23 05:35:42 -0500[diff] [blame]12 select INTEL_SOC
Simon Glassfcc2ce92019-12-08 17:40:17 -0700[diff] [blame]13 select INTEL_PMC
14 select TPL_X86_TSC_TIMER_NATIVE
Simon Glassff67f232021-08-08 12:20:10 -0600[diff] [blame]15 select SPL_PCH
16 select TPL_PCH
Simon Glass741ce462020-09-22 12:44:51 -0600[diff] [blame]17 select PCIEX_LENGTH_256MB
Simon Glassff67f232021-08-08 12:20:10 -0600[diff] [blame]18 select PCH
Simon Glassfcc2ce92019-12-08 17:40:17 -0700[diff] [blame]19 select P2SB
Simon Glass4a30bbb2020-07-17 08:48:16 -0600[diff] [blame]20 select SMP_AP_WORK
Simon Glassc32fbb62020-09-22 12:45:15 -0600[diff] [blame]21 select INTEL_GMA_SWSMISCI
Simon Glass6fe570a2020-09-22 12:44:53 -0600[diff] [blame]22 select ACPI_GNVS_EXTERNAL
Simon Glass37ad5f32020-12-22 19:30:25 -0700[diff] [blame]23 select TPL_OF_PLATDATA_PARENT
Simon Glass02849162021-03-15 17:25:52 +1300[diff] [blame]24 select TPL_OF_PLATDATA_INST
25 select TPL_READ_ONLY
Simon Glassfcc2ce92019-12-08 17:40:17 -0700[diff] [blame]26 imply ENABLE_MRC_CACHE
27 imply AHCI_PCI
28 imply SCSI
29 imply SCSI_AHCI
30 imply SPI_FLASH
31 imply USB
32 imply USB_EHCI_HCD
33 imply TPL
34 imply SPL
35 imply TPL_X86_16BIT_INIT
36 imply TPL_OF_PLATDATA
37 imply ACPI_PMC
38 imply MMC
39 imply DM_MMC
40 imply MMC_PCI
41 imply MMC_SDHCI
42 imply CMD_MMC
43 imply VIDEO_FSP
44 imply PINCTRL_INTEL
45 imply PINCTRL_INTEL_APL
46 imply HAVE_VBT
47 imply HAVE_X86_FIT
48 imply INTEL_GPIO
49 imply SMP
Wolfgang Wallnerb5460dd2020-02-03 14:06:45 +0100[diff] [blame]50 imply HAVE_ITSS
Wolfgang Wallner21fae582020-02-04 09:04:56 +0100[diff] [blame]51 imply HAVE_P2SB
Simon Glass4a2c26a2020-02-06 09:54:54 -0700[diff] [blame]52 imply CLK
53 imply CMD_CLK
54 imply CLK_INTEL
Simon Glassc0619742020-02-06 09:55:02 -0700[diff] [blame]55 imply ACPI_GPE
Simon Glass057427c2020-09-22 12:45:03 -0600[diff] [blame]56 imply INTEL_GMA_ACPI
Simon Glassfcc2ce92019-12-08 17:40:17 -0700[diff] [blame]57
58if INTEL_APOLLOLAKE
59
60config DCACHE_RAM_BASE
61 default 0xfef00000
62
63config DCACHE_RAM_SIZE
64 default 0xc0000
65
66config DCACHE_RAM_MRC_VAR_SIZE
67 default 0xb0000
68
69config CPU_SPECIFIC_OPTIONS
70 def_bool y
71 select SMM_TSEG
72 select X86_RAMTEST
73
74config SMM_TSEG_SIZE
75 hex
76 default 0x800000
77
78config MMCONF_BASE_ADDRESS
79 hex
80 default 0xe0000000
81
82config TPL_SIZE_LIMIT
83 default 0x7800
84
85config CPU_ADDR_BITS
86 default 39
87
88config APL_SPI_FLASH_BOOT
89 bool "Support booting with SPI-flash driver instead memory-mapped SPI"
90 select TPL_SPI_FLASH_SUPPORT
Simon Glassa5820472021-08-08 12:20:14 -0600[diff] [blame]91 select TPL_SPI
Simon Glassecdc4b32020-10-03 11:31:38 -0600[diff] [blame]92 select TPL_DM_SPI
93 select TPL_DM_SPI_FLASH
Simon Glassfcc2ce92019-12-08 17:40:17 -0700[diff] [blame]94 help
95 This enables SPI and SPI flash in TPL. Without the this only
96 available boot method is to use memory-mapped SPI. Since this is
97 actually fast and produces a TPL which is 7KB smaller, memory-mapped
98 SPI is the default.
99
100config APL_BOOT_FROM_FAST_SPI_FLASH
101 bool "Boot using SPI flash driver"
102 select APL_SPI_FLASH_BOOT
103 help
104 This option is separate from APL_SPI_FLASH_BOOT since it is useful to
105 be able to compare booting speed with the same build. Enable this to
106 use the SPI-flash driver to load SPL, U-Boot and FSP-M. For technical
107 reasons FSP-S is currently always loaded from memory-mapped SPI. See
108 Apollo Lake's arch_fsp_init_r() for details about that.
109
110config VBT_ADDR
111 default 0xff3f1000
112
113endif