| commit | 16523268cf8c77846f40d51878356390535537d4 | [log] [tgz] |
|---|---|---|
| author | Lokesh Vutla <lokeshvutla@ti.com> | Thu May 30 03:19:38 2013 +0000 |
| committer | Tom Rini <trini@ti.com> | Mon Jun 10 08:43:10 2013 -0400 |
| tree | 13c4b866c44ebbbb7033f7490921fcb6dffa6004 | |
| parent | 4b4b9a8ed441a7a2fc3b7a1daa9f6fdd0430703f [diff] |
ARM: DRA7xx: clocks: Update PLL values Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com>