pci: zynqmp: Fix the pcireg base
The pcireg base is not assigned to any address, reading the
pcireg base with PS_LINKUP_OFFSET which is incorrect and
giving random values. So update the pcireg base from
devicetree so that we can read the valid PCIE link status
and PHY ready status.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Link: https://lore.kernel.org/r/20250516092314.939424-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
diff --git a/drivers/pci/pcie-xilinx-nwl.c b/drivers/pci/pcie-xilinx-nwl.c
index 7ef2bdf..e03ab3b 100644
--- a/drivers/pci/pcie-xilinx-nwl.c
+++ b/drivers/pci/pcie-xilinx-nwl.c
@@ -303,6 +303,13 @@
return PTR_ERR(pcie->breg_base);
pcie->phys_breg_base = res.start;
+ ret = dev_read_resource_byname(dev, "pcireg", &res);
+ if (ret)
+ return ret;
+ pcie->pcireg_base = devm_ioremap(dev, res.start, resource_size(&res));
+ if (IS_ERR(pcie->pcireg_base))
+ return PTR_ERR(pcie->pcireg_base);
+
ret = dev_read_resource_byname(dev, "cfg", &res);
if (ret)
return ret;