Merge git://git.denx.de/u-boot-usb
diff --git a/MAINTAINERS b/MAINTAINERS
index a97c439..6c7f3ae 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -111,7 +111,6 @@
T: git git://git.denx.de/u-boot-imx.git
F: arch/arm/cpu/arm1136/mx*/
F: arch/arm/cpu/arm926ejs/mx*/
-F: arch/arm/cpu/armv7/mx*/
F: arch/arm/cpu/armv7/vf610/
F: arch/arm/mach-imx/
F: arch/arm/include/asm/arch-imx/
@@ -124,7 +123,7 @@
M: Peter Griffin <peter.griffin@linaro.org>
S: Maintained
F: arch/arm/cpu/armv8/hisilicon
-F: arm/include/asm/arch-hi6220/
+F: arch/arm/include/asm/arch-hi6220/
ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X
M: Prafulla Wadaskar <prafulla@marvell.com>
@@ -174,11 +173,9 @@
M: Minkyu Kang <mk7.kang@samsung.com>
S: Maintained
T: git git://git.denx.de/u-boot-samsung.git
-F: arch/arm/cpu/arm920t/s3c24x0/
F: arch/arm/mach-exynos/
F: arch/arm/mach-s5pc1xx/
F: arch/arm/cpu/armv7/s5p-common/
-F: arch/arm/include/asm/arch-s3c24x0/
ARM SNAPDRAGON
M: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
@@ -198,6 +195,13 @@
F: arch/arm/cpu/arm926ejs/spear/
F: arch/arm/include/asm/arch-spear/
+ARM STM STM32MP
+M: Patrick Delaunay <patrick.delaunay@st.com>
+S: Maintained
+F: arch/arm/mach-stm32mp
+F: clk/clk_stm32mp1.c
+F: ram/stm32mp1
+
ARM STM STV0991
M: Vikas Manocha <vikas.manocha@st.com>
S: Maintained
@@ -227,8 +231,6 @@
T: git git://git.denx.de/u-boot-ti.git
F: arch/arm/mach-davinci/
F: arch/arm/mach-keystone/
-F: arch/arm/cpu/arm926ejs/omap/
-F: arch/arm/cpu/armv7/omap*/
F: arch/arm/include/asm/arch-omap*/
F: arch/arm/include/asm/ti-common/
@@ -307,7 +309,7 @@
F: lib/fdtdec*
F: lib/libfdt/
F: include/fdt*
-F: include/libfdt*
+F: include/linux/libfdt*
F: cmd/fdt.c
F: common/fdt_support.c
@@ -426,12 +428,6 @@
T: git git://git.denx.de/u-boot-mpc86xx.git
F: arch/powerpc/cpu/mpc86xx/
-POWERPC PPC4XX
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-T: git git://git.denx.de/u-boot-ppc4xx.git
-F: arch/powerpc/cpu/ppc4xx/
-
RISC-V
M: Rick Chen <rick@andestech.com>
S: Maintained
@@ -475,7 +471,6 @@
M: Andrew F. Davis <afd@ti.com>
S: Supported
F: arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
-F: arch/arm/mach-omap2/omap5/sec-fxns.c
F: arch/arm/mach-omap2/sec-common.c
F: arch/arm/mach-omap2/config_secure.mk
F: configs/am335x_hs_evm_defconfig
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 95553be..b8f7a98 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1132,7 +1132,7 @@
(formerly, System LSI Business Division of Panasonic Corporation)
config STM32
- bool "Support STM32"
+ bool "Support STMicroelectronics STM32 MCU with cortex M"
select CPU_V7M
select DM
select DM_SERIAL
@@ -1150,6 +1150,27 @@
Support for STMicroelectronics STiH407/10 SoC family.
This SoC is used on Linaro 96Board STiH410-B2260
+config ARCH_STM32MP
+ bool "Support STMicroelectronics STM32MP Socs with cortex A"
+ select BOARD_LATE_INIT
+ select CLK
+ select DM
+ select DM_GPIO
+ select DM_RESET
+ select DM_SERIAL
+ select OF_CONTROL
+ select OF_LIBFDT
+ select PINCTRL
+ select REGMAP
+ select SUPPORT_SPL
+ select SYSCON
+ select SYS_THUMB_BUILD
+ help
+ Support for STM32MP SoC family developed by STMicroelectronics,
+ MPUs based on ARM cortex A core
+ U-BOOT is running in DDR and SPL support is the unsecure First Stage
+ BootLoader (FSBL)
+
config ARCH_ROCKCHIP
bool "Support Rockchip SoCs"
select OF_CONTROL
@@ -1262,6 +1283,8 @@
source "arch/arm/mach-stm32/Kconfig"
+source "arch/arm/mach-stm32mp/Kconfig"
+
source "arch/arm/mach-sunxi/Kconfig"
source "arch/arm/mach-tegra/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5881fdc..4fa8b38 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -72,6 +72,7 @@
machine-$(CONFIG_ARCH_RMOBILE) += rmobile
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_STM32) += stm32
+machine-$(CONFIG_ARCH_STM32MP) += stm32mp
machine-$(CONFIG_TEGRA) += tegra
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_ZYNQ) += zynq
diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c
index 30915d2..545c518 100644
--- a/arch/arm/cpu/armv7/arch_timer.c
+++ b/arch/arm/cpu/armv7/arch_timer.c
@@ -17,7 +17,7 @@
gd->arch.tbl = 0;
gd->arch.tbu = 0;
- gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
+ gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
return 0;
}
@@ -34,27 +34,9 @@
}
-ulong get_timer(ulong base)
-{
- return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base;
-}
-
ulong timer_get_boot_us(void)
{
- return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / (CONFIG_SYS_HZ * 1000));
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long endtime;
-
- endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
- 1000UL);
-
- endtime += get_ticks();
-
- while (get_ticks() < endtime)
- ;
+ return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / 1000000);
}
ulong get_tbclk(void)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 83e13ec..7dd1dff 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -500,6 +500,9 @@
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
+dtb-$(CONFIG_TARGET_STM32MP1) += \
+ stm32mp157c-ed1.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts
index 9e8d2a0..e47f762 100644
--- a/arch/arm/dts/stm32f746-disco.dts
+++ b/arch/arm/dts/stm32f746-disco.dts
@@ -89,6 +89,37 @@
compatible = "st,button1";
button-gpio = <&gpioi 11 0>;
};
+
+ backlight: backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpiok 3 0>;
+ status = "okay";
+ };
+
+ panel-rgb@0 {
+ compatible = "simple-panel";
+ backlight = <&backlight>;
+ enable-gpios = <&gpioi 12 0>;
+ status = "okay";
+
+ display-timings {
+ timing@0 {
+ clock-frequency = <9000000>;
+ hactive = <480>;
+ vactive = <272>;
+ hfront-porch = <2>;
+ hback-porch = <2>;
+ hsync-len = <41>;
+ vfront-porch = <2>;
+ vback-porch = <2>;
+ vsync-len = <10>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <0>;
+ pixelclk-active = <1>;
+ };
+ };
+ };
};
&clk_hse {
@@ -183,6 +214,40 @@
slew-rate = <2>;
};
};
+
+ ltdc_pins: ltdc@0 {
+ pins {
+ pinmux = <STM32F746_PE4_FUNC_LCD_B0>,
+ <STM32F746_PG12_FUNC_LCD_B4>,
+ <STM32F746_PI9_FUNC_LCD_VSYNC>,
+ <STM32F746_PI10_FUNC_LCD_HSYNC>,
+ <STM32F746_PI14_FUNC_LCD_CLK>,
+ <STM32F746_PI15_FUNC_LCD_R0>,
+ <STM32F746_PJ0_FUNC_LCD_R1>,
+ <STM32F746_PJ1_FUNC_LCD_R2>,
+ <STM32F746_PJ2_FUNC_LCD_R3>,
+ <STM32F746_PJ3_FUNC_LCD_R4>,
+ <STM32F746_PJ4_FUNC_LCD_R5>,
+ <STM32F746_PJ5_FUNC_LCD_R6>,
+ <STM32F746_PJ6_FUNC_LCD_R7>,
+ <STM32F746_PJ7_FUNC_LCD_G0>,
+ <STM32F746_PJ8_FUNC_LCD_G1>,
+ <STM32F746_PJ9_FUNC_LCD_G2>,
+ <STM32F746_PJ10_FUNC_LCD_G3>,
+ <STM32F746_PJ11_FUNC_LCD_G4>,
+ <STM32F746_PJ13_FUNC_LCD_B1>,
+ <STM32F746_PJ14_FUNC_LCD_B2>,
+ <STM32F746_PJ15_FUNC_LCD_B3>,
+ <STM32F746_PK0_FUNC_LCD_G5>,
+ <STM32F746_PK1_FUNC_LCD_G6>,
+ <STM32F746_PK2_FUNC_LCD_G7>,
+ <STM32F746_PK4_FUNC_LCD_B5>,
+ <STM32F746_PK5_FUNC_LCD_B6>,
+ <STM32F746_PK6_FUNC_LCD_B7>,
+ <STM32F746_PK7_FUNC_LCD_DE>;
+ slew-rate = <2>;
+ };
+ };
};
&usart1 {
@@ -250,3 +315,8 @@
bus-width = <4>;
max-frequency = <25000000>;
};
+
+<dc {
+ status = "okay";
+ pinctrl-0 = <<dc_pins>;
+};
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 8c6fa13..8581df9 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -330,6 +330,15 @@
interrupts = <50>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
};
+
+ ltdc: display-controller@40016800 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x40016800 0x200>;
+ resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
+ u-boot,dm-pre-reloc;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi
new file mode 100644
index 0000000..ddfa079
--- /dev/null
+++ b/arch/arm/dts/stm32mp15-ddr.dtsi
@@ -0,0 +1,155 @@
+/*
+ * Copyright : STMicroelectronics 2018
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+/ {
+ soc {
+ ddr: ddr@0x5A003000{
+ u-boot,dm-pre-reloc;
+
+ compatible = "st,stm32mp1-ddr";
+
+ reg = <0x5A003000 0x550
+ 0x5A004000 0x234>;
+
+ clocks = <&rcc_clk AXIDCG>,
+ <&rcc_clk DDRC1>,
+ <&rcc_clk DDRC2>,
+ <&rcc_clk DDRPHYC>,
+ <&rcc_clk DDRCAPB>,
+ <&rcc_clk DDRPHYCAPB>;
+
+ clock-names = "axidcg",
+ "ddrc1",
+ "ddrc2",
+ "ddrphyc",
+ "ddrcapb",
+ "ddrphycapb";
+
+ st,mem-name = DDR_MEM_NAME;
+ st,mem-speed = <DDR_MEM_SPEED>;
+ st,mem-size = <DDR_MEM_SIZE>;
+
+ st,ctl-reg = <
+ DDR_MSTR
+ DDR_MRCTRL0
+ DDR_MRCTRL1
+ DDR_DERATEEN
+ DDR_DERATEINT
+ DDR_PWRCTL
+ DDR_PWRTMG
+ DDR_HWLPCTL
+ DDR_RFSHCTL0
+ DDR_RFSHCTL3
+ DDR_CRCPARCTL0
+ DDR_ZQCTL0
+ DDR_DFITMG0
+ DDR_DFITMG1
+ DDR_DFILPCFG0
+ DDR_DFIUPD0
+ DDR_DFIUPD1
+ DDR_DFIUPD2
+ DDR_DFIPHYMSTR
+ DDR_ODTMAP
+ DDR_DBG0
+ DDR_DBG1
+ DDR_DBGCMD
+ DDR_POISONCFG
+ DDR_PCCFG
+ >;
+
+ st,ctl-timing = <
+ DDR_RFSHTMG
+ DDR_DRAMTMG0
+ DDR_DRAMTMG1
+ DDR_DRAMTMG2
+ DDR_DRAMTMG3
+ DDR_DRAMTMG4
+ DDR_DRAMTMG5
+ DDR_DRAMTMG6
+ DDR_DRAMTMG7
+ DDR_DRAMTMG8
+ DDR_DRAMTMG14
+ DDR_ODTCFG
+ >;
+
+ st,ctl-map = <
+ DDR_ADDRMAP1
+ DDR_ADDRMAP2
+ DDR_ADDRMAP3
+ DDR_ADDRMAP4
+ DDR_ADDRMAP5
+ DDR_ADDRMAP6
+ DDR_ADDRMAP9
+ DDR_ADDRMAP10
+ DDR_ADDRMAP11
+ >;
+
+ st,ctl-perf = <
+ DDR_SCHED
+ DDR_SCHED1
+ DDR_PERFHPR1
+ DDR_PERFLPR1
+ DDR_PERFWR1
+ DDR_PCFGR_0
+ DDR_PCFGW_0
+ DDR_PCFGQOS0_0
+ DDR_PCFGQOS1_0
+ DDR_PCFGWQOS0_0
+ DDR_PCFGWQOS1_0
+ DDR_PCFGR_1
+ DDR_PCFGW_1
+ DDR_PCFGQOS0_1
+ DDR_PCFGQOS1_1
+ DDR_PCFGWQOS0_1
+ DDR_PCFGWQOS1_1
+ >;
+
+ st,phy-reg = <
+ DDR_PGCR
+ DDR_ACIOCR
+ DDR_DXCCR
+ DDR_DSGCR
+ DDR_DCR
+ DDR_ODTCR
+ DDR_ZQ0CR1
+ DDR_DX0GCR
+ DDR_DX1GCR
+ DDR_DX2GCR
+ DDR_DX3GCR
+ >;
+
+ st,phy-timing = <
+ DDR_PTR0
+ DDR_PTR1
+ DDR_PTR2
+ DDR_DTPR0
+ DDR_DTPR1
+ DDR_DTPR2
+ DDR_MR0
+ DDR_MR1
+ DDR_MR2
+ DDR_MR3
+ >;
+
+ st,phy-cal = <
+ DDR_DX0DLLCR
+ DDR_DX0DQTR
+ DDR_DX0DQSTR
+ DDR_DX1DLLCR
+ DDR_DX1DQTR
+ DDR_DX1DQSTR
+ DDR_DX2DLLCR
+ DDR_DX2DQTR
+ DDR_DX2DQSTR
+ DDR_DX3DLLCR
+ DDR_DX3DQTR
+ DDR_DX3DQSTR
+ >;
+
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
new file mode 100644
index 0000000..352e470
--- /dev/null
+++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
@@ -0,0 +1,122 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+/* STM32MP157C ED1 and ED2 BOARD configuration
+ * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
+ * Reference used NT5CC256M16DP-DI from NANYA
+ *
+ * DDR type / Platform DDR3/3L
+ * freq 533MHz
+ * width 32
+ * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
+ * DDR density 8
+ * timing mode optimized
+ * Scheduling/QoS options : type = 2
+ * address mapping : RBC
+ */
+
+#define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.36"
+#define DDR_MEM_SPEED 533
+#define DDR_MEM_SIZE 0x40000000
+
+#define DDR_MSTR 0x00040401
+#define DDR_MRCTRL0 0x00000010
+#define DDR_MRCTRL1 0x00000000
+#define DDR_DERATEEN 0x00000000
+#define DDR_DERATEINT 0x00800000
+#define DDR_PWRCTL 0x00000000
+#define DDR_PWRTMG 0x00400010
+#define DDR_HWLPCTL 0x00000000
+#define DDR_RFSHCTL0 0x00210000
+#define DDR_RFSHCTL3 0x00000000
+#define DDR_RFSHTMG 0x0081008B
+#define DDR_CRCPARCTL0 0x00000000
+#define DDR_DRAMTMG0 0x121B2414
+#define DDR_DRAMTMG1 0x000A041C
+#define DDR_DRAMTMG2 0x0608090F
+#define DDR_DRAMTMG3 0x0050400C
+#define DDR_DRAMTMG4 0x08040608
+#define DDR_DRAMTMG5 0x06060403
+#define DDR_DRAMTMG6 0x02020002
+#define DDR_DRAMTMG7 0x00000202
+#define DDR_DRAMTMG8 0x00001005
+#define DDR_DRAMTMG14 0x000000A0
+#define DDR_ZQCTL0 0xC2000040
+#define DDR_DFITMG0 0x02060105
+#define DDR_DFITMG1 0x00000202
+#define DDR_DFILPCFG0 0x07000000
+#define DDR_DFIUPD0 0xC0400003
+#define DDR_DFIUPD1 0x00000000
+#define DDR_DFIUPD2 0x00000000
+#define DDR_DFIPHYMSTR 0x00000000
+#define DDR_ADDRMAP1 0x00080808
+#define DDR_ADDRMAP2 0x00000000
+#define DDR_ADDRMAP3 0x00000000
+#define DDR_ADDRMAP4 0x00001F1F
+#define DDR_ADDRMAP5 0x07070707
+#define DDR_ADDRMAP6 0x0F070707
+#define DDR_ADDRMAP9 0x00000000
+#define DDR_ADDRMAP10 0x00000000
+#define DDR_ADDRMAP11 0x00000000
+#define DDR_ODTCFG 0x06000600
+#define DDR_ODTMAP 0x00000001
+#define DDR_SCHED 0x00001201
+#define DDR_SCHED1 0x00000000
+#define DDR_PERFHPR1 0x01000001
+#define DDR_PERFLPR1 0x08000200
+#define DDR_PERFWR1 0x08000400
+#define DDR_DBG0 0x00000000
+#define DDR_DBG1 0x00000000
+#define DDR_DBGCMD 0x00000000
+#define DDR_POISONCFG 0x00000000
+#define DDR_PCCFG 0x00000010
+#define DDR_PCFGR_0 0x00010000
+#define DDR_PCFGW_0 0x00000000
+#define DDR_PCFGQOS0_0 0x02100B03
+#define DDR_PCFGQOS1_0 0x00800100
+#define DDR_PCFGWQOS0_0 0x01100B03
+#define DDR_PCFGWQOS1_0 0x01000200
+#define DDR_PCFGR_1 0x00010000
+#define DDR_PCFGW_1 0x00000000
+#define DDR_PCFGQOS0_1 0x02100B03
+#define DDR_PCFGQOS1_1 0x00800100
+#define DDR_PCFGWQOS0_1 0x01100B03
+#define DDR_PCFGWQOS1_1 0x01000200
+#define DDR_PGCR 0x01442E02
+#define DDR_PTR0 0x0022AA5B
+#define DDR_PTR1 0x04841104
+#define DDR_PTR2 0x042DA068
+#define DDR_ACIOCR 0x10400812
+#define DDR_DXCCR 0x00000C40
+#define DDR_DSGCR 0xF200001F
+#define DDR_DCR 0x0000000B
+#define DDR_DTPR0 0x38D488D0
+#define DDR_DTPR1 0x098B00D8
+#define DDR_DTPR2 0x10023600
+#define DDR_MR0 0x00000840
+#define DDR_MR1 0x00000000
+#define DDR_MR2 0x00000208
+#define DDR_MR3 0x00000000
+#define DDR_ODTCR 0x00010000
+#define DDR_ZQ0CR1 0x0000005B
+#define DDR_DX0GCR 0x0000CE81
+#define DDR_DX0DLLCR 0x40000000
+#define DDR_DX0DQTR 0xFFFFFFFF
+#define DDR_DX0DQSTR 0x3DB02000
+#define DDR_DX1GCR 0x0000CE81
+#define DDR_DX1DLLCR 0x40000000
+#define DDR_DX1DQTR 0xFFFFFFFF
+#define DDR_DX1DQSTR 0x3DB02000
+#define DDR_DX2GCR 0x0000CE81
+#define DDR_DX2DLLCR 0x40000000
+#define DDR_DX2DQTR 0xFFFFFFFF
+#define DDR_DX2DQSTR 0x3DB02000
+#define DDR_DX3GCR 0x0000CE81
+#define DDR_DX3DLLCR 0x40000000
+#define DDR_DX3DQTR 0xFFFFFFFF
+#define DDR_DX3DQSTR 0x3DB02000
+
+#include "stm32mp15-ddr.dtsi"
diff --git a/arch/arm/dts/stm32mp157-u-boot.dtsi b/arch/arm/dts/stm32mp157-u-boot.dtsi
new file mode 100644
index 0000000..d374b2b
--- /dev/null
+++ b/arch/arm/dts/stm32mp157-u-boot.dtsi
@@ -0,0 +1,134 @@
+/*
+ * Copyright : STMicroelectronics 2018
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+/ {
+ aliases {
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
+ gpio25 = &gpioz;
+ };
+
+ config {
+ u-boot,dm-pre-reloc;
+ };
+
+ clocks {
+ u-boot,dm-pre-reloc;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&clk_hsi {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_hse {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_lse {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_lsi {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_csi {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc_rst {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_z {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioa {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiob {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioc {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiod {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioe {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiof {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiog {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioh {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioi {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioj {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiok {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioz {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi
new file mode 100644
index 0000000..32d3984
--- /dev/null
+++ b/arch/arm/dts/stm32mp157.dtsi
@@ -0,0 +1,303 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/stm32mp1-clks.h>
+#include <dt-bindings/reset-controller/stm32mp1-resets.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+ };
+
+ aliases {
+ serial3 = &uart4;
+ };
+
+ intc: interrupt-controller@a0021000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xa0021000 0x1000>,
+ <0xa0022000 0x2000>;
+ };
+
+ clocks {
+ clk_hse: clk-hse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ clk_hsi: clk-hsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <64000000>;
+ };
+
+ clk_lse: clk-lse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ clk_lsi: clk-lsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ };
+
+ clk_csi: clk-csi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <4000000>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+
+ uart4: serial@40010000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40010000 0x400>;
+ clocks = <&rcc_clk UART4_K>;
+ status = "disabled";
+ };
+
+ rcc: rcc@50000000 {
+ compatible = "syscon", "simple-mfd";
+
+ reg = <0x50000000 0x1000>;
+
+ rcc_clk: rcc-clk@50000000 {
+ #clock-cells = <1>;
+ compatible = "st,stm32mp1-rcc-clk";
+ };
+
+ rcc_rst: rcc-reset@50000000 {
+ #reset-cells = <1>;
+ compatible = "st,stm32mp1-rcc-rst";
+ };
+ };
+
+ pinctrl: pin-controller {
+ compatible = "st,stm32mp157-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x50002000 0xa400>;
+ pins-are-numbered;
+
+ gpioa: gpio@50002000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&rcc_clk GPIOA>;
+ st,bank-name = "GPIOA";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ status = "disabled";
+ };
+
+ gpiob: gpio@50003000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1000 0x400>;
+ clocks = <&rcc_clk GPIOB>;
+ st,bank-name = "GPIOB";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ status = "disabled";
+ };
+
+ gpioc: gpio@50004000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2000 0x400>;
+ clocks = <&rcc_clk GPIOC>;
+ st,bank-name = "GPIOC";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ status = "disabled";
+ };
+
+ gpiod: gpio@50005000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x3000 0x400>;
+ clocks = <&rcc_clk GPIOD>;
+ st,bank-name = "GPIOD";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ status = "disabled";
+ };
+
+ gpioe: gpio@50006000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x4000 0x400>;
+ clocks = <&rcc_clk GPIOE>;
+ st,bank-name = "GPIOE";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ status = "disabled";
+ };
+
+ gpiof: gpio@50007000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x5000 0x400>;
+ clocks = <&rcc_clk GPIOF>;
+ st,bank-name = "GPIOF";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ status = "disabled";
+ };
+
+ gpiog: gpio@50008000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x6000 0x400>;
+ clocks = <&rcc_clk GPIOG>;
+ st,bank-name = "GPIOG";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ status = "disabled";
+ };
+
+ gpioh: gpio@50009000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x7000 0x400>;
+ clocks = <&rcc_clk GPIOH>;
+ st,bank-name = "GPIOH";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 112 16>;
+ status = "disabled";
+ };
+
+ gpioi: gpio@5000a000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x8000 0x400>;
+ clocks = <&rcc_clk GPIOI>;
+ st,bank-name = "GPIOI";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 128 16>;
+ status = "disabled";
+ };
+
+ gpioj: gpio@5000b000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x9000 0x400>;
+ clocks = <&rcc_clk GPIOJ>;
+ st,bank-name = "GPIOJ";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 144 16>;
+ status = "disabled";
+ };
+
+ gpiok: gpio@5000c000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0xa000 0x400>;
+ clocks = <&rcc_clk GPIOK>;
+ st,bank-name = "GPIOK";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl 0 160 8>;
+ status = "disabled";
+ };
+ };
+
+ pinctrl_z: pin-controller-z {
+ compatible = "st,stm32mp157-z-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x54004000 0x400>;
+ pins-are-numbered;
+
+ gpioz: gpio@54004000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0 0x400>;
+ clocks = <&rcc_clk GPIOZ>;
+ st,bank-name = "GPIOZ";
+ st,bank-ioport = <11>;
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl_z 0 400 8>;
+ status = "disabled";
+ };
+ };
+
+ sdmmc1: sdmmc@58005000 {
+ compatible = "st,stm32-sdmmc2";
+ reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
+ reg-names = "sdmmc", "delay";
+ clocks = <&rcc_clk SDMMC1_K>;
+ resets = <&rcc_rst SDMMC1_R>;
+ st,idma = <1>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <120000000>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@5c002000 {
+ compatible = "st,stm32f7-i2c";
+ reg = <0x5c002000 0x400>;
+ interrupt-names = "event", "error", "wakeup";
+ clocks = <&rcc_clk I2C4_K>;
+ resets = <&rcc_rst I2C4_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wakeup-source;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
new file mode 100644
index 0000000..94d27fb
--- /dev/null
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
@@ -0,0 +1,133 @@
+/*
+ * Copyright : STMicroelectronics 2018
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
+#include "stm32mp157-u-boot.dtsi"
+#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &sdmmc1;
+ i2c3 = &i2c4;
+ };
+};
+
+&uart4_pins_a {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&i2c4_pins_a {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&uart4 {
+ u-boot,dm-pre-reloc;
+};
+
+&i2c4 {
+ u-boot,dm-pre-reloc;
+};
+
+&pmic {
+ u-boot,dm-pre-reloc;
+};
+
+/* CLOCK init */
+&rcc_clk {
+ st,clksrc = <
+ CLK_MPU_PLL1P
+ CLK_AXI_PLL2P
+ CLK_MCU_PLL3P
+ CLK_PLL12_HSE
+ CLK_PLL3_HSE
+ CLK_PLL4_HSE
+ CLK_RTC_LSE
+ CLK_MCO1_DISABLED
+ CLK_MCO2_DISABLED
+ >;
+
+ st,clkdiv = <
+ 1 /*MPU*/
+ 0 /*AXI*/
+ 0 /*MCU*/
+ 1 /*APB1*/
+ 1 /*APB2*/
+ 1 /*APB3*/
+ 1 /*APB4*/
+ 2 /*APB5*/
+ 23 /*RTC*/
+ 0 /*MCO1*/
+ 0 /*MCO2*/
+ >;
+
+ st,pkcs = <
+ CLK_CKPER_DISABLED
+ CLK_SDMMC12_PLL3R
+ CLK_I2C46_PCLK5
+ CLK_I2C12_PCLK1
+ CLK_I2C35_PCLK1
+ CLK_UART1_PCLK5
+ CLK_UART24_PCLK1
+ CLK_UART35_PCLK1
+ CLK_UART6_PCLK2
+ CLK_UART78_PCLK1
+ >;
+
+ /* VCO = 1300.0 MHz => P = 650 (CPU) */
+ pll1: st,pll@0 {
+ cfg = < 2 80 0 0 0 PQR(1,0,0) >;
+ frac = < 0x800 >;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
+ pll2: st,pll@1 {
+ cfg = < 2 65 1 0 0 PQR(1,1,1) >;
+ frac = < 0x1400 >;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* VCO = 774.0 MHz => P = 194, Q = 37, R = 97 */
+ pll3: st,pll@2 {
+ cfg = < 3 128 3 20 7 PQR(1,1,1) >;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */
+ pll4: st,pll@3 {
+ cfg = < 5 126 8 8 8 PQR(1,1,1) >;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+/* SPL part **************************************/
+/* MMC1 boot */
+&sdmmc1_b4_pins_a {
+ u-boot,dm-spl;
+ pins {
+ u-boot,dm-spl;
+ };
+};
+
+&sdmmc1_dir_pins_a {
+ u-boot,dm-spl;
+ pins {
+ u-boot,dm-spl;
+ };
+};
+
+&sdmmc1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
new file mode 100644
index 0000000..4b20fab
--- /dev/null
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -0,0 +1,167 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+/ {
+ model = "STMicroelectronics STM32MP157C pmic eval daughter";
+ compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
+
+ chosen {
+ bootargs = "earlyprintk console=ttyS3,115200 root=/dev/ram";
+ stdout-path = "serial3:115200n8";
+ };
+
+ memory {
+ reg = <0xC0000000 0x40000000>;
+ };
+};
+
+&gpioa {
+ status = "okay";
+};
+
+&gpiob {
+ status = "okay";
+};
+
+&gpioc {
+ status = "okay";
+};
+
+&gpiod {
+ status = "okay";
+};
+
+&gpioe {
+ status = "okay";
+};
+
+&gpiof {
+ status = "okay";
+};
+
+&gpiog {
+ status = "okay";
+};
+
+&gpioh {
+ status = "okay";
+};
+
+&gpioi {
+ status = "okay";
+};
+
+&gpioj {
+ status = "okay";
+};
+
+&gpiok {
+ status = "okay";
+};
+
+&gpioz {
+ status = "okay";
+};
+
+&pinctrl {
+ uart4_pins_a: uart4@0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ sdmmc1_b4_pins_a: sdmmc1-b4@0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ slew-rate = <3>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sdmmc1_dir_pins_a: sdmmc1-dir@0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
+ <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
+ <STM32_PINMUX('B', 9, AF11)>, /* SDMMC1_CDIR */
+ <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
+ slew-rate = <3>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+};
+
+&pinctrl_z {
+ i2c4_pins_a: i2c4@0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
+ <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+
+ pmic: stpmu1@33 {
+ compatible = "st,stpmu1";
+ reg = <0x33>;
+ interrupts = <0 2>;
+ interrupt-parent = <&gpioa>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "okay";
+ };
+};
+
+&sdmmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
+ broken-cd;
+ st,dirpol;
+ st,negedge;
+ st,pin-ckin;
+ bus-width = <4>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-ddr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_a>;
+ status = "okay";
+};
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
new file mode 100644
index 0000000..8c755f8
--- /dev/null
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -0,0 +1,43 @@
+if ARCH_STM32MP
+
+config SPL
+ select SPL_BOARD_INIT
+ select SPL_CLK
+ select SPL_DM
+ select SPL_DM_SEQ_ALIAS
+ select SPL_FRAMEWORK
+ select SPL_GPIO_SUPPORT
+ select SPL_LIBCOMMON_SUPPORT
+ select SPL_LIBGENERIC_SUPPORT
+ select SPL_OF_CONTROL
+ select SPL_OF_TRANSLATE
+ select SPL_PINCTRL
+ select SPL_REGMAP
+ select SPL_RESET_SUPPORT
+ select SPL_SERIAL_SUPPORT
+ select SPL_SYSCON
+ imply SPL_LIBDISK_SUPPORT
+
+config SYS_SOC
+ default "stm32mp"
+
+config TARGET_STM32MP1
+ bool "Support stm32mp1xx"
+ select CPU_V7
+ select PINCTRL_STM32
+ select STM32_RESET
+ help
+ target STMicroelectronics SOC STM32MP1 family
+ STMicroelectronics MPU with core ARMv7
+
+config SYS_TEXT_BASE
+ prompt "U-Boot base address"
+ default 0xC0100000
+ help
+ configure the U-Boot base address
+ when DDR driver is used:
+ DDR + 1MB (0xC0100000)
+
+source "board/st/stm32mp1/Kconfig"
+
+endif
diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile
new file mode 100644
index 0000000..4620869
--- /dev/null
+++ b/arch/arm/mach-stm32mp/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+#
+
+obj-y += cpu.o
+obj-y += dram_init.o
+
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/arch/arm/mach-stm32mp/config.mk b/arch/arm/mach-stm32mp/config.mk
new file mode 100644
index 0000000..34e59c6
--- /dev/null
+++ b/arch/arm/mach-stm32mp/config.mk
@@ -0,0 +1,14 @@
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+#
+
+ALL-$(CONFIG_SPL_BUILD) += spl/u-boot-spl.stm32
+
+MKIMAGEFLAGS_u-boot-spl.stm32 = -T stm32image -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE)
+
+spl/u-boot-spl.stm32: MKIMAGEOUTPUT = spl/u-boot-spl.stm32.log
+
+spl/u-boot-spl.stm32: spl/u-boot-spl.bin FORCE
+ $(call if_changed,mkimage)
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
new file mode 100644
index 0000000..7c43dc1
--- /dev/null
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+#include <common.h>
+#include <clk.h>
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+/**********************************************
+ * Security init
+ *********************************************/
+#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
+#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
+
+#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
+#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
+#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
+
+#define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
+
+#define PWR_CR1 (STM32_PWR_BASE + 0x00)
+#define PWR_CR1_DBP BIT(8)
+
+#define RCC_TZCR (STM32_RCC_BASE + 0x00)
+#define RCC_BDCR (STM32_RCC_BASE + 0x0140)
+#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
+
+#define RCC_BDCR_VSWRST BIT(31)
+#define RCC_BDCR_RTCSRC GENMASK(17, 16)
+
+static void security_init(void)
+{
+ /* Disable the backup domain write protection */
+ /* the protection is enable at each reset by hardware */
+ /* And must be disable by software */
+ setbits_le32(PWR_CR1, PWR_CR1_DBP);
+
+ while (!(readl(PWR_CR1) & PWR_CR1_DBP))
+ ;
+
+ /* If RTC clock isn't enable so this is a cold boot then we need
+ * to reset the backup domain
+ */
+ if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
+ setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
+ while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
+ ;
+ clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
+ }
+
+ /* allow non secure access in Write/Read for all peripheral */
+ writel(GENMASK(25, 0), ETZPC_DECPROT0);
+
+ /* Open SYSRAM for no secure access */
+ writel(0x0, ETZPC_TZMA1_SIZE);
+
+ /* enable TZC1 TZC2 clock */
+ writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
+
+ /* Region 0 set to no access by default */
+ /* bit 0 / 16 => nsaid0 read/write Enable
+ * bit 1 / 17 => nsaid1 read/write Enable
+ * ...
+ * bit 15 / 31 => nsaid15 read/write Enable
+ */
+ writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
+ /* bit 30 / 31 => Secure Global Enable : write/read */
+ /* bit 0 / 1 => Region Enable for filter 0/1 */
+ writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
+
+ /* Enable Filter 0 and 1 */
+ setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
+
+ /* RCC trust zone deactivated */
+ writel(0x0, RCC_TZCR);
+
+ /* TAMP: deactivate the internal tamper
+ * Bit 23 ITAMP8E: monotonic counter overflow
+ * Bit 20 ITAMP5E: RTC calendar overflow
+ * Bit 19 ITAMP4E: HSE monitoring
+ * Bit 18 ITAMP3E: LSE monitoring
+ * Bit 16 ITAMP1E: RTC power domain supply monitoring
+ */
+ writel(0x0, TAMP_CR1);
+}
+
+/**********************************************
+ * Debug init
+ *********************************************/
+#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
+#define RCC_DBGCFGR_DBGCKEN BIT(8)
+
+#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
+#define DBGMCU_APB4FZ1_IWDG2 BIT(2)
+
+static void dbgmcu_init(void)
+{
+ setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
+
+ /* Freeze IWDG2 if Cortex-A7 is in debug mode */
+ setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
+}
+#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
+
+int arch_cpu_init(void)
+{
+ /* early armv7 timer init: needed for polling */
+ timer_init();
+
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+ dbgmcu_init();
+
+ security_init();
+#endif
+
+ return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ printf("CPU: STM32MP15x\n");
+
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c
new file mode 100644
index 0000000..ecb4c98
--- /dev/null
+++ b/arch/arm/mach-stm32mp/dram_init.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ struct ram_info ram;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("RAM init failed: %d\n", ret);
+ return ret;
+ }
+ ret = ram_get_info(dev, &ram);
+ if (ret) {
+ debug("Cannot get RAM size: %d\n", ret);
+ return ret;
+ }
+ debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
+
+ gd->ram_size = ram.size;
+
+ return 0;
+}
diff --git a/arch/arm/mach-stm32mp/include/mach/ddr.h b/arch/arm/mach-stm32mp/include/mach/ddr.h
new file mode 100644
index 0000000..b635001
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/ddr.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#ifndef __MACH_STM32MP_DDR_H_
+#define __MACH_STM32MP_DDR_H_
+
+int board_ddr_power_init(void);
+
+#endif
diff --git a/arch/arm/mach-stm32mp/include/mach/gpio.h b/arch/arm/mach-stm32mp/include/mach/gpio.h
new file mode 100644
index 0000000..5952557
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/gpio.h
@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _STM32_GPIO_H_
+#define _STM32_GPIO_H_
+#include <asm/gpio.h>
+
+enum stm32_gpio_port {
+ STM32_GPIO_PORT_A = 0,
+ STM32_GPIO_PORT_B,
+ STM32_GPIO_PORT_C,
+ STM32_GPIO_PORT_D,
+ STM32_GPIO_PORT_E,
+ STM32_GPIO_PORT_F,
+ STM32_GPIO_PORT_G,
+ STM32_GPIO_PORT_H,
+ STM32_GPIO_PORT_I
+};
+
+enum stm32_gpio_pin {
+ STM32_GPIO_PIN_0 = 0,
+ STM32_GPIO_PIN_1,
+ STM32_GPIO_PIN_2,
+ STM32_GPIO_PIN_3,
+ STM32_GPIO_PIN_4,
+ STM32_GPIO_PIN_5,
+ STM32_GPIO_PIN_6,
+ STM32_GPIO_PIN_7,
+ STM32_GPIO_PIN_8,
+ STM32_GPIO_PIN_9,
+ STM32_GPIO_PIN_10,
+ STM32_GPIO_PIN_11,
+ STM32_GPIO_PIN_12,
+ STM32_GPIO_PIN_13,
+ STM32_GPIO_PIN_14,
+ STM32_GPIO_PIN_15
+};
+
+enum stm32_gpio_mode {
+ STM32_GPIO_MODE_IN = 0,
+ STM32_GPIO_MODE_OUT,
+ STM32_GPIO_MODE_AF,
+ STM32_GPIO_MODE_AN
+};
+
+enum stm32_gpio_otype {
+ STM32_GPIO_OTYPE_PP = 0,
+ STM32_GPIO_OTYPE_OD
+};
+
+enum stm32_gpio_speed {
+ STM32_GPIO_SPEED_2M = 0,
+ STM32_GPIO_SPEED_25M,
+ STM32_GPIO_SPEED_50M,
+ STM32_GPIO_SPEED_100M
+};
+
+enum stm32_gpio_pupd {
+ STM32_GPIO_PUPD_NO = 0,
+ STM32_GPIO_PUPD_UP,
+ STM32_GPIO_PUPD_DOWN
+};
+
+enum stm32_gpio_af {
+ STM32_GPIO_AF0 = 0,
+ STM32_GPIO_AF1,
+ STM32_GPIO_AF2,
+ STM32_GPIO_AF3,
+ STM32_GPIO_AF4,
+ STM32_GPIO_AF5,
+ STM32_GPIO_AF6,
+ STM32_GPIO_AF7,
+ STM32_GPIO_AF8,
+ STM32_GPIO_AF9,
+ STM32_GPIO_AF10,
+ STM32_GPIO_AF11,
+ STM32_GPIO_AF12,
+ STM32_GPIO_AF13,
+ STM32_GPIO_AF14,
+ STM32_GPIO_AF15
+};
+
+struct stm32_gpio_dsc {
+ enum stm32_gpio_port port;
+ enum stm32_gpio_pin pin;
+};
+
+struct stm32_gpio_ctl {
+ enum stm32_gpio_mode mode;
+ enum stm32_gpio_otype otype;
+ enum stm32_gpio_speed speed;
+ enum stm32_gpio_pupd pupd;
+ enum stm32_gpio_af af;
+};
+
+struct stm32_gpio_regs {
+ u32 moder; /* GPIO port mode */
+ u32 otyper; /* GPIO port output type */
+ u32 ospeedr; /* GPIO port output speed */
+ u32 pupdr; /* GPIO port pull-up/pull-down */
+ u32 idr; /* GPIO port input data */
+ u32 odr; /* GPIO port output data */
+ u32 bsrr; /* GPIO port bit set/reset */
+ u32 lckr; /* GPIO port configuration lock */
+ u32 afr[2]; /* GPIO alternate function */
+};
+
+struct stm32_gpio_priv {
+ struct stm32_gpio_regs *regs;
+};
+#endif /* _STM32_GPIO_H_ */
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
new file mode 100644
index 0000000..ffbe0b1
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#ifndef _MACH_STM32_H_
+#define _MACH_STM32_H_
+
+/*
+ * Peripheral memory map
+ * only address used before device tree parsing
+ */
+#define STM32_RCC_BASE 0x50000000
+#define STM32_PWR_BASE 0x50001000
+#define STM32_DBGMCU_BASE 0x50081000
+#define STM32_TZC_BASE 0x5C006000
+#define STM32_ETZPC_BASE 0x5C007000
+#define STM32_TAMP_BASE 0x5C00A000
+
+#define STM32_SYSRAM_BASE 0x2FFC0000
+#define STM32_SYSRAM_SIZE SZ_256K
+
+#define STM32_DDR_BASE 0xC0000000
+#define STM32_DDR_SIZE SZ_1G
+
+#endif /* _MACH_STM32_H_ */
diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c
new file mode 100644
index 0000000..8f5962a
--- /dev/null
+++ b/arch/arm/mach-stm32mp/spl.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spl.h>
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_MMC1;
+}
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+ return MMCSD_MODE_RAW;
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *dev;
+ int ret;
+
+ arch_cpu_init();
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+ if (ret) {
+ debug("Clock init failed: %d\n", ret);
+ return;
+ }
+
+ ret = uclass_get_device(UCLASS_RESET, 0, &dev);
+ if (ret) {
+ debug("Reset init failed: %d\n", ret);
+ return;
+ }
+
+ ret = uclass_get_device(UCLASS_PINCTRL, 0, &dev);
+ if (ret) {
+ debug("%s: Cannot find pinctrl device\n", __func__);
+ return;
+ }
+
+ /* enable console uart printing */
+ preloader_console_init();
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return;
+ }
+}
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 15cc014..b868f0e 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -6,6 +6,73 @@
config IDENT_STRING
default " Allwinner Technology"
+config DRAM_SUN4I
+ bool
+ help
+ Select this dram controller driver for Sun4/5/7i platforms,
+ like A10/A13/A20.
+
+config DRAM_SUN6I
+ bool
+ help
+ Select this dram controller driver for Sun6i platforms,
+ like A31/A31s.
+
+config DRAM_SUN8I_A23
+ bool
+ help
+ Select this dram controller driver for Sun8i platforms,
+ for A23 SOC.
+
+config DRAM_SUN8I_A33
+ bool
+ help
+ Select this dram controller driver for Sun8i platforms,
+ for A33 SOC.
+
+config DRAM_SUN8I_A83T
+ bool
+ help
+ Select this dram controller driver for Sun8i platforms,
+ for A83T SOC.
+
+config DRAM_SUN9I
+ bool
+ help
+ Select this dram controller driver for Sun9i platforms,
+ like A80.
+
+config SUN6I_P2WI
+ bool "Allwinner sun6i internal P2WI controller"
+ help
+ If you say yes to this option, support will be included for the
+ P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
+ SOCs.
+ The P2WI looks like an SMBus controller (which supports only byte
+ accesses), except that it only supports one slave device.
+ This interface is used to connect to specific PMIC devices (like the
+ AXP221).
+
+config SUN6I_PRCM
+ bool
+ help
+ Support for the PRCM (Power/Reset/Clock Management) unit available
+ in A31 SoC.
+
+config AXP_PMIC_BUS
+ bool "Sunxi AXP PMIC bus access helpers"
+ help
+ Select this PMIC bus access helpers for Sunxi platform PRCM or other
+ AXP family PMIC devices.
+
+config SUN8I_RSB
+ bool "Allwinner sunXi Reduced Serial Bus Driver"
+ help
+ Say y here to enable support for Allwinner's Reduced Serial Bus
+ (RSB) support. This controller is responsible for communicating
+ with various RSB based devices, such as AXP223, AXP8XX PMICs,
+ and AC100/AC200 ICs.
+
config SUNXI_HIGH_SRAM
bool
default n
@@ -71,6 +138,7 @@
bool "sun4i (Allwinner A10)"
select CPU_V7
select ARM_CORTEX_CPU_IS_UP
+ select DRAM_SUN4I
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
@@ -78,6 +146,7 @@
bool "sun5i (Allwinner A13)"
select CPU_V7
select ARM_CORTEX_CPU_IS_UP
+ select DRAM_SUN4I
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
imply CONS_INDEX_2 if !DM_SERIAL
@@ -88,6 +157,9 @@
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
+ select DRAM_SUN6I
+ select SUN6I_P2WI
+ select SUN6I_PRCM
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
@@ -98,6 +170,7 @@
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
+ select DRAM_SUN4I
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
@@ -108,6 +181,7 @@
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
+ select DRAM_SUN8I_A23
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
@@ -119,6 +193,7 @@
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
+ select DRAM_SUN8I_A33
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
@@ -127,6 +202,7 @@
config MACH_SUN8I_A83T
bool "sun8i (Allwinner A83T)"
select CPU_V7
+ select DRAM_SUN8I_A83T
select SUNXI_GEN_SUN6I
select MMC_SUNXI_HAS_NEW_MODE
select SUPPORT_SPL
@@ -166,8 +242,11 @@
config MACH_SUN9I
bool "sun9i (Allwinner A80)"
select CPU_V7
+ select DRAM_SUN9I
+ select SUN6I_PRCM
select SUNXI_HIGH_SRAM
select SUNXI_GEN_SUN6I
+ select SUN8I_RSB
select SUPPORT_SPL
config MACH_SUN50I
@@ -196,6 +275,8 @@
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
config MACH_SUN8I
bool
+ select SUN8I_RSB
+ select SUN6I_PRCM
default y if MACH_SUN8I_A23
default y if MACH_SUN8I_A33
default y if MACH_SUN8I_A83T
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 6ddf682..1831753 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -16,12 +16,10 @@
ifndef CONFIG_MACH_SUN9I
obj-y += usb_phy.o
endif
-obj-$(CONFIG_MACH_SUN6I) += prcm.o
-obj-$(CONFIG_MACH_SUN8I) += prcm.o
-obj-$(CONFIG_MACH_SUN9I) += prcm.o
-obj-$(CONFIG_MACH_SUN6I) += p2wi.o
-obj-$(CONFIG_MACH_SUN8I) += rsb.o
-obj-$(CONFIG_MACH_SUN9I) += rsb.o
+obj-$(CONFIG_SUN6I_P2WI) += p2wi.o
+obj-$(CONFIG_SUN6I_PRCM) += prcm.o
+obj-$(CONFIG_AXP_PMIC_BUS) += pmic_bus.o
+obj-$(CONFIG_SUN8I_RSB) += rsb.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
@@ -34,22 +32,14 @@
endif
obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o gtbus_sun9i.o
-obj-$(CONFIG_AXP152_POWER) += pmic_bus.o
-obj-$(CONFIG_AXP209_POWER) += pmic_bus.o
-obj-$(CONFIG_AXP221_POWER) += pmic_bus.o
-obj-$(CONFIG_AXP809_POWER) += pmic_bus.o
-obj-$(CONFIG_AXP818_POWER) += pmic_bus.o
-
ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_MACH_SUN4I) += dram_sun4i.o
-obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
-obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
-obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
-obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o
-obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o
-obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o
+obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o
+obj-$(CONFIG_DRAM_SUN6I) += dram_sun6i.o
+obj-$(CONFIG_DRAM_SUN8I_A23) += dram_sun8i_a23.o
+obj-$(CONFIG_DRAM_SUN8I_A33) += dram_sun8i_a33.o
+obj-$(CONFIG_DRAM_SUN8I_A83T) += dram_sun8i_a83t.o
+obj-$(CONFIG_DRAM_SUN9I) += dram_sun9i.o
obj-$(CONFIG_SPL_SPI_SUNXI) += spl_spi_sunxi.o
obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o
obj-$(CONFIG_SUNXI_DRAM_DW) += dram_timings/
-obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o
endif
diff --git a/arch/powerpc/include/asm/xilinx_irq.h b/arch/powerpc/include/asm/xilinx_irq.h
deleted file mode 100644
index 5766bde..0000000
--- a/arch/powerpc/include/asm/xilinx_irq.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
- * This work has been supported by: QTechnology http://qtec.com/
- * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
- * SPDX-License-Identifier: GPL-2.0+
-*/
-#ifndef XILINX_IRQ_H
-#define XILINX_IRQ_H
-
-#define intc XPAR_INTC_0_BASEADDR
-#define ISR (intc + (0 * 4)) /* Interrupt Status Register */
-#define IPR (intc + (1 * 4)) /* Interrupt Pending Register */
-#define IER (intc + (2 * 4)) /* Interrupt Enable Register */
-#define IAR (intc + (3 * 4)) /* Interrupt Acknowledge Register */
-#define SIE (intc + (4 * 4)) /* Set Interrupt Enable bits */
-#define CIE (intc + (5 * 4)) /* Clear Interrupt Enable bits */
-#define IVR (intc + (6 * 4)) /* Interrupt Vector Register */
-#define MER (intc + (7 * 4)) /* Master Enable Register */
-
-#define IRQ_MASK(irq) (1 << (irq & 0x1f))
-
-#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS
-
-#endif
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index 832a5d7..7c32245 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -6,7 +6,6 @@
#include <common.h>
#include <debug_uart.h>
-#include <init_helpers.h>
#include <spl.h>
#include <asm/cpu.h>
#include <asm/mtrr.h>
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index 05b316f..c4f2633 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -7,8 +7,12 @@
#include <common.h>
#include <dm.h>
+#include <lcd.h>
#include <ram.h>
#include <spl.h>
+#include <splash.h>
+#include <st_logo_data.h>
+#include <video.h>
#include <asm/io.h>
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
@@ -153,5 +157,10 @@
STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
#endif
+#if defined(CONFIG_CMD_BMP)
+ bmp_display((ulong)stmicroelectronics_uboot_logo_8bit_rle,
+ BMP_ALIGN_CENTER, BMP_ALIGN_CENTER);
+#endif /* CONFIG_CMD_BMP */
+
return 0;
}
diff --git a/board/st/stm32mp1/Kconfig b/board/st/stm32mp1/Kconfig
new file mode 100644
index 0000000..5ab9415
--- /dev/null
+++ b/board/st/stm32mp1/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_STM32MP1
+
+config SYS_BOARD
+ default "stm32mp1"
+
+config SYS_VENDOR
+ default "st"
+
+config SYS_CONFIG_NAME
+ default "stm32mp1"
+
+endif
diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS
new file mode 100644
index 0000000..65266bc
--- /dev/null
+++ b/board/st/stm32mp1/MAINTAINERS
@@ -0,0 +1,7 @@
+STM32MP1 BOARD
+M: Patrick Delaunay <patrick.delaunay@st.com>
+S: Maintained
+F: board/st/stm32mp1
+F: include/configs/stm32mp1.h
+F: configs/stm32mp15_basic_defconfig
+F: arch/arm/dts/stm32mp157*
diff --git a/board/st/stm32mp1/Makefile b/board/st/stm32mp1/Makefile
new file mode 100644
index 0000000..eaf45b7
--- /dev/null
+++ b/board/st/stm32mp1/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y += stm32mp1.o
+endif
+
+obj-y += board.o
diff --git a/board/st/stm32mp1/README b/board/st/stm32mp1/README
new file mode 100644
index 0000000..4adc978
--- /dev/null
+++ b/board/st/stm32mp1/README
@@ -0,0 +1,191 @@
+#
+# Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+#
+# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+#
+
+U-Boot on STMicroelectronics STM32MP1
+======================================
+
+1. Summary
+==========
+This is a quick instruction for setup stm32mp1 boards.
+
+2. Supported devices
+====================
+U-Boot supports one STMP32MP1 SoCs: STM32MP157
+
+The STM32MP157 is a Cortex-A MPU aimed at various applications.
+It features:
+- Dual core Cortex-A7 application core
+- 2D/3D image composition with GPU
+- Standard memories interface support
+- Standard connectivity, widely inherited from the STM32 MCU family
+- Comprehensive security support
+
+Everything is supported in Linux but U-Boot is limited to:
+1. UART
+2. SDCard/MMC controller (SDMMC)
+
+And the necessary drivers
+1. I2C
+2. STPMU1
+3. Clock, Reset
+
+Currently the following boards are supported:
++ stm32mp157c-ed1
+
+3. Boot Sequences
+=================
+
+BootRom => FSBL in SYSRAM => SSBL in DDR => OS (Linux Kernel)
+
+with FSBL = First Stage Bootloader
+ SSBL = Second Stage Bootloader
+
+One boot configuration is supported:
+
+ The "Basic" boot chain (defconfig_file : stm32mp15_basic_defconfig)
+ BootRom => FSBL = U-Boot SPL => SSBL = U-Boot
+ SPL has limited security initialisation
+ U-Boot is running in secure mode and provide a secure monitor to the kernel
+ with only PSCI support (Power State Coordination Interface defined by ARM)
+
+All the STM32MP1 board supported by U-Boot use the same generic board
+stm32mp1 which support all the bootable devices.
+
+Each board is configurated only with the associated device tree.
+
+4. Device Tree Selection
+========================
+
+You need to select the appropriate device tree for your board,
+the supported device trees for stm32mp157 are:
+
++ ed1: daughter board with pmic stpmu1
+ dts: stm32mp157c-ed1
+
+5. Build Procedure
+==================
+
+1. Install required tools for U-Boot
+
+ + install package needed in U-Boot makefile
+ (libssl-dev, swig, libpython-dev...)
+ + install ARMv7 toolchain for 32bit Cortex-A (from Linaro,
+ from SDK for STM32MP1, or any crosstoolchains from your distribution)
+
+2. Set the cross compiler:
+
+ # export CROSS_COMPILE=/path/to/toolchain/arm-linux-gnueabi-
+ (you can use any gcc cross compiler compatible with U-Boot)
+
+3. Select the output directory (optional)
+
+ # export KBUILD_OUTPUT=/path/to/output
+
+ for example: use one output directory for each configuration
+ # export KBUILD_OUTPUT=stm32mp15_basic
+
+4. Configure the U-Boot:
+
+ # make <defconfig_file>
+
+ - For basic boot mode: "stm32mp15_basic_defconfig"
+
+5. Configure the device-tree and build the U-Boot image:
+
+ # make DEVICE_TREE=<name> all
+
+
+ example:
+ basic boot on ed1
+ # export KBUILD_OUTPUT=stm32mp15_basic
+ # make stm32mp15_basic_defconfig
+ # make DEVICE_TREE=stm32mp157c-ed1 all
+
+6. Output files
+
+ BootRom and ATF expect binaries with STM32 image header
+ SPL expects file with U-Boot uImage header
+
+ So in the output directory (selected by KBUILD_OUTPUT),
+ you can found the needed files:
+
+ + FSBL = spl/u-boot-spl.stm32
+ + SSBL = u-boot.img
+
+6. Prepare an SDCard
+===================
+
+The minimal requirements for STMP32MP1 boot up to U-Boot are:
+- GPT partitioning (with gdisk or with sgdisk)
+- 2 fsbl partitions, named fsbl1 and fsbl2, size at least 256KiB
+- one ssbl partition for U-Boot
+
+Then the minimal GPT partition is:
+ ----- ------- --------- -------------
+ | Num | Name | Size | Content |
+ ----- ------- -------- --------------
+ | 1 | fsbl1 | 256 KiB | ATF or SPL |
+ | 2 | fsbl2 | 256 KiB | ATF or SPL |
+ | 3 | ssbl | enought | U-Boot |
+ | * | - | - | Boot/Rootfs|
+ ----- ------- --------- -------------
+
+(*) add bootable partition for extlinux.conf
+ following Generic Distribution
+ (doc/README.distro for use)
+
+ according the used card reader select the block device
+ (/dev/sdx or /dev/mmcblk0)
+ in the next example I use /dev/mmcblk0
+
+for example: with gpt table with 128 entries
+
+ a) remove previous formatting
+ # sgdisk -o /dev/<SDCard dev>
+
+ b) create minimal image
+ # sgdisk --resize-table=128 -a 1 \
+ -n 1:34:545 -c 1:fsbl1 \
+ -n 2:546:1057 -c 2:fsbl2 \
+ -n 3:1058:5153 -c 3:ssbl \
+ -p /dev/<SDCard dev>
+
+ you can add other partition for kernel (rootfs)
+
+ c) copy the FSBL (2 times) and SSBL file on the correct partition.
+ in this example in partition 1 to 3
+
+ for basic boot mode : <SDCard dev> = /dev/mmcblk0
+ # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p1
+ # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p2
+ # dd if=u-boot.img of=/dev/mmcblk0p3
+
+7. Switch Setting
+==================
+
+You can select the boot mode, on the board ed1 with the switch SW1
+
+ -----------------------------------
+ Boot Mode BOOT2 BOOT1 BOOT0
+ -----------------------------------
+ Reserved 0 0 0
+ NOR 0 0 1
+ SD-Card 1 1 1
+ SD-Card 1 0 1
+ eMMC 0 1 0
+ NAND 0 1 1
+ Recovery 1 1 0
+ Recovery 0 0 0
+
+
+To boot from SDCard, select BootPinMode = 1 1 1 and reset.
+
+Recovery is a boot from serial link (UART/USB) and it is used with
+STM32CubeProgrammer tool to load executable in RAM and to update the flash
+devices available on the board (NOR/NAND/eMMC/SDCARD).
+The communication between HOST and board is based on
+- for UARTs : the uart protocol used with all MCU STM32
+- for USB : based on USB DFU 1.1 (without the ST extensions used on MCU STM32)
diff --git a/board/st/stm32mp1/board.c b/board/st/stm32mp1/board.c
new file mode 100644
index 0000000..03f900a
--- /dev/null
+++ b/board/st/stm32mp1/board.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <power/pmic.h>
+#include <power/stpmu1.h>
+
+#ifdef CONFIG_PMIC_STPMU1
+int board_ddr_power_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_PMIC,
+ DM_GET_DRIVER(pmic_stpmu1), &dev);
+ if (ret)
+ /* No PMIC on board */
+ return 0;
+
+ /* Set LDO3 to sync mode */
+ ret = pmic_reg_read(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3));
+ if (ret < 0)
+ return ret;
+
+ ret &= ~STPMU1_LDO3_MODE;
+ ret &= ~STPMU1_LDO12356_OUTPUT_MASK;
+ ret |= STPMU1_LDO3_DDR_SEL << STPMU1_LDO12356_OUTPUT_SHIFT;
+
+ ret = pmic_reg_write(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
+ ret);
+ if (ret < 0)
+ return ret;
+
+ /* Set BUCK2 to 1.35V */
+ ret = pmic_clrsetbits(dev,
+ STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
+ STPMU1_BUCK_OUTPUT_MASK,
+ STPMU1_BUCK2_1350000V);
+ if (ret < 0)
+ return ret;
+
+ /* Enable BUCK2 and VREF */
+ ret = pmic_clrsetbits(dev,
+ STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
+ STPMU1_BUCK_EN, STPMU1_BUCK_EN);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
+
+ ret = pmic_clrsetbits(dev, STPMU1_VREF_CTRL_REG,
+ STPMU1_VREF_EN, STPMU1_VREF_EN);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
+
+ /* Enable LDO3 */
+ ret = pmic_clrsetbits(dev,
+ STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
+ STPMU1_LDO_EN, STPMU1_LDO_EN);
+ if (ret < 0)
+ return ret;
+
+ mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
+
+ return 0;
+}
+#endif
diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c
new file mode 100644
index 0000000..b7e5f24
--- /dev/null
+++ b/board/st/stm32mp1/spl.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <config.h>
+#include <common.h>
+#include <spl.h>
+#include <dm.h>
+#include <ram.h>
+#include <asm/io.h>
+#include <post.h>
+#include <power/pmic.h>
+#include <power/stpmu1.h>
+#include <asm/arch/ddr.h>
+
+void spl_board_init(void)
+{
+ /* Keep vdd on during the reset cycle */
+#if defined(CONFIG_PMIC_STPMU1) && defined(CONFIG_SPL_POWER_SUPPORT)
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_PMIC,
+ DM_GET_DRIVER(pmic_stpmu1), &dev);
+ if (!ret)
+ pmic_clrsetbits(dev,
+ STPMU1_MASK_RESET_BUCK,
+ STPMU1_MASK_RESET_BUCK3,
+ STPMU1_MASK_RESET_BUCK3);
+#endif
+}
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
new file mode 100644
index 0000000..84c971c
--- /dev/null
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+#include <config.h>
+#include <common.h>
+#include <asm/arch/stm32.h>
+
+/*
+ * Get a global data pointer
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+/* board dependent setup after realloc */
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
+
+ return 0;
+}
diff --git a/common/board_f.c b/common/board_f.c
index c6bc53e..62588c5b 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -18,7 +18,6 @@
#include <fs.h>
#include <i2c.h>
#include <initcall.h>
-#include <init_helpers.h>
#include <malloc.h>
#include <mapmem.h>
#include <os.h>
@@ -489,7 +488,7 @@
return 0;
}
-int arch_reserve_stacks(void)
+__weak int arch_reserve_stacks(void)
{
return 0;
}
diff --git a/common/board_r.c b/common/board_r.c
index 482f506..89f2e16 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -23,7 +23,6 @@
#include <fdtdec.h>
#include <ide.h>
#include <initcall.h>
-#include <init_helpers.h>
#ifdef CONFIG_PS2KBD
#include <keyboard.h>
#endif
diff --git a/common/bootm_os.c b/common/bootm_os.c
index 5e6b177..b84a8e2 100644
--- a/common/bootm_os.c
+++ b/common/bootm_os.c
@@ -11,6 +11,7 @@
#include <linux/libfdt.h>
#include <malloc.h>
#include <vxworks.h>
+#include <tee/optee.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -433,6 +434,34 @@
}
#endif
+#ifdef CONFIG_BOOTM_OPTEE
+static int do_bootm_tee(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
+{
+ int ret;
+
+ /* Verify OS type */
+ if (images->os.os != IH_OS_TEE) {
+ return 1;
+ };
+
+ /* Validate OPTEE header */
+ ret = optee_verify_bootm_image(images->os.image_start,
+ images->os.load,
+ images->os.image_len);
+ if (ret)
+ return ret;
+
+ /* Locate FDT etc */
+ ret = bootm_find_images(flag, argc, argv);
+ if (ret)
+ return ret;
+
+ /* From here we can run the regular linux boot path */
+ return do_bootm_linux(flag, argc, argv, images);
+}
+#endif
+
static boot_os_fn *boot_os[] = {
[IH_OS_U_BOOT] = do_bootm_standalone,
#ifdef CONFIG_BOOTM_LINUX
@@ -466,6 +495,9 @@
#ifdef CONFIG_BOOTM_OPENRTOS
[IH_OS_OPENRTOS] = do_bootm_openrtos,
#endif
+#ifdef CONFIG_BOOTM_OPTEE
+ [IH_OS_TEE] = do_bootm_tee,
+#endif
};
/* Allow for arch specific config before we boot */
diff --git a/common/image-fit.c b/common/image-fit.c
index f6e956a..4b03390 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -1068,34 +1068,14 @@
return 0;
}
-/**
- * fit_image_verify - verify data integrity
- * @fit: pointer to the FIT format image header
- * @image_noffset: component image node offset
- *
- * fit_image_verify() goes over component image hash nodes,
- * re-calculates each data hash and compares with the value stored in hash
- * node.
- *
- * returns:
- * 1, if all hashes are valid
- * 0, otherwise (or on error)
- */
-int fit_image_verify(const void *fit, int image_noffset)
+int fit_image_verify_with_data(const void *fit, int image_noffset,
+ const void *data, size_t size)
{
- const void *data;
- size_t size;
int noffset = 0;
char *err_msg = "";
int verify_all = 1;
int ret;
- /* Get image data and data length */
- if (fit_image_get_data(fit, image_noffset, &data, &size)) {
- err_msg = "Can't get image data/size";
- goto error;
- }
-
/* Verify all required signatures */
if (IMAGE_ENABLE_VERIFY &&
fit_image_verify_required_sigs(fit, image_noffset, data, size,
@@ -1153,6 +1133,38 @@
}
/**
+ * fit_image_verify - verify data integrity
+ * @fit: pointer to the FIT format image header
+ * @image_noffset: component image node offset
+ *
+ * fit_image_verify() goes over component image hash nodes,
+ * re-calculates each data hash and compares with the value stored in hash
+ * node.
+ *
+ * returns:
+ * 1, if all hashes are valid
+ * 0, otherwise (or on error)
+ */
+int fit_image_verify(const void *fit, int image_noffset)
+{
+ const void *data;
+ size_t size;
+ int noffset = 0;
+ char *err_msg = "";
+
+ /* Get image data and data length */
+ if (fit_image_get_data(fit, image_noffset, &data, &size)) {
+ err_msg = "Can't get image data/size";
+ printf("error!\n%s for '%s' hash node in '%s' image node\n",
+ err_msg, fit_get_name(fit, noffset, NULL),
+ fit_get_name(fit, image_noffset, NULL));
+ return 0;
+ }
+
+ return fit_image_verify_with_data(fit, image_noffset, data, size);
+}
+
+/**
* fit_all_image_verify - verify data integrity for all images
* @fit: pointer to the FIT format image header
*
diff --git a/common/image.c b/common/image.c
index 14be3ca..f5278a0 100644
--- a/common/image.c
+++ b/common/image.c
@@ -100,6 +100,7 @@
{ IH_OS_OSE, "ose", "Enea OSE", },
{ IH_OS_PLAN9, "plan9", "Plan 9", },
{ IH_OS_RTEMS, "rtems", "RTEMS", },
+ { IH_OS_TEE, "tee", "Trusted Execution Environment" },
{ IH_OS_U_BOOT, "u-boot", "U-Boot", },
{ IH_OS_VXWORKS, "vxworks", "VxWorks", },
#if defined(CONFIG_CMD_ELF) || defined(USE_HOSTCC)
@@ -161,6 +162,7 @@
{ IH_TYPE_TEE, "tee", "Trusted Execution Environment Image",},
{ IH_TYPE_FIRMWARE_IVT, "firmware_ivt", "Firmware with HABv4 IVT" },
{ IH_TYPE_PMMC, "pmmc", "TI Power Management Micro-Controller Firmware",},
+ { IH_TYPE_STM32IMAGE, "stm32image", "STMicroelectronics STM32 Image" },
{ -1, "", "", },
};
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 9609fce..b9b9e0f 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -568,6 +568,15 @@
performed before booting. This enables the drivers in post/drivers
as part of an SPL build.
+config SPL_RESET_SUPPORT
+ bool "Support reset drivers"
+ depends on SPL
+ help
+ Enable support for reset control in SPL.
+ That can be useful in SPL to handle IP reset in driver, as in U-Boot,
+ by using the generic reset API provided by driver model.
+ This enables the drivers in drivers/reset as part of an SPL build.
+
config SPL_POWER_SUPPORT
bool "Support power drivers"
help
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index b705d03..be92ca4 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -174,6 +174,9 @@
uint8_t image_comp = -1, type = -1;
const void *data;
bool external_data = false;
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+ int ret;
+#endif
if (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP)) {
if (fit_image_get_comp(fit, node, &image_comp))
@@ -252,7 +255,16 @@
image_info->entry_point = fdt_getprop_u32(fit, node, "entry");
}
+#ifdef CONFIG_SPL_FIT_SIGNATURE
+ printf("## Checking hash(es) for Image %s ...\n",
+ fit_get_name(fit, node, NULL));
+ ret = fit_image_verify_with_data(fit, node,
+ (const void *)load_addr, length);
+ printf("\n");
+ return !ret;
+#else
return 0;
+#endif
}
static int spl_fit_append_fdt(struct spl_image_info *spl_image,
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index 99eecd6..8139ab1 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -29,6 +29,7 @@
CONFIG_CMD_SNTP=y
CONFIG_CMD_DNS=y
CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
@@ -53,5 +54,10 @@
# CONFIG_PINCTRL_FULL is not set
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_VIDEO_STM32=y
+CONFIG_VIDEO_STM32_MAX_XRES=480
+CONFIG_VIDEO_STM32_MAX_YRES=640
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
new file mode 100644
index 0000000..4ab1d4c
--- /dev/null
+++ b/configs/stm32mp15_basic_defconfig
@@ -0,0 +1,36 @@
+CONFIG_ARM=y
+CONFIG_ARCH_STM32MP=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_TARGET_STM32MP1=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ed1"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SYS_PROMPT="STM32MP> "
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_STM32F7=y
+CONFIG_DM_MMC=y
+CONFIG_STM32_SDMMC2=y
+# CONFIG_SPL_PINCTRL_FULL is not set
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_STPMU1=y
+CONFIG_STM32_SERIAL=y
+# CONFIG_EFI_LOADER is not set
diff --git a/doc/README.POST b/doc/README.POST
index a9335f4..43f424f 100644
--- a/doc/README.POST
+++ b/doc/README.POST
@@ -159,17 +159,6 @@
Also, the following board-specific routines will be called from the
U-Boot common code:
- o) int board_power_mode(void)
-
- This routine will return the mode the system is running in
- (POST_POWERON, POST_NORMAL or POST_SHUTDOWN).
-
- o) void board_poweroff(void)
-
- This routine will turn off the power supply of the board. It
- will be called on power-fail booting after running all POST
- tests.
-
o) int post_hotkeys_pressed(gd_t *gd)
This routine will scan the keyboard to detect if a magic key
diff --git a/doc/device-tree-bindings/clock/st,stm32mp1.txt b/doc/device-tree-bindings/clock/st,stm32mp1.txt
new file mode 100644
index 0000000..c29d90f
--- /dev/null
+++ b/doc/device-tree-bindings/clock/st,stm32mp1.txt
@@ -0,0 +1,226 @@
+STMicroelectronics STM32MP1 clock tree initialization
+=====================================================
+
+The STM32MP clock tree initialization is based on device tree information
+for RCC IP and on fixed clocks.
+
+-------------------------------
+RCC CLOCK = st,stm32mp1-rcc-clk
+-------------------------------
+
+The RCC IP is both a reset and a clock controller but this documentation only
+describes the fields added for clock tree initialization which are not present
+in Linux binding.
+
+Please refer to ../mfd/st,stm32-rcc.txt for all the other properties common
+with Linux.
+
+Required properties:
+
+- compatible: Should be "st,stm32mp1-rcc-clk"
+
+- st,clksrc : The clock source in this order
+
+ for STM32MP15x: 9 clock sources are requested
+ MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
+
+ with value equals to RCC clock specifier as defined in
+ dt-bindings/clock/stm32mp1-clksrc.h: CLK_<NAME>_<SOURCE>
+
+- st,clkdiv : The div parameters in this order
+ for STM32MP15x: 11 dividers value are requested
+ MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2
+
+ with DIV coding defined in RCC associated register RCC_xxxDIVR
+
+ most the case, it is:
+ 0x0: not divided
+ 0x1: division by 2
+ 0x2: division by 4
+ 0x3: division by 8
+ ...
+
+ but for RTC MCO1 MCO2, the coding is different:
+ 0x0: not divided
+ 0x1: division by 2
+ 0x2: division by 3
+ 0x3: division by 4
+ ...
+
+Optional Properties:
+- st,pll
+ PLL children node for PLL1 to PLL4 : (see ref manual for details)
+ with associated index 0 to 3 (st,pll@0 to st,pll@4)
+ PLLx is off when the associated node is absent
+
+ - Sub-nodes:
+
+ - cfg: The parameters for PLL configuration in this order:
+ DIVM DIVN DIVP DIVQ DIVR Output
+
+ with DIV value as defined in RCC spec:
+ 0x0: bypass (division by 1)
+ 0x1: division by 2
+ 0x2: division by 3
+ 0x3: division by 4
+ ...
+
+ and Output = bitfield for each output value = 1:ON/0:OFF
+ BIT(0) => output P : DIVPEN
+ BIT(1) => output Q : DIVQEN
+ BIT(2) => output R : DIVREN
+ NB : macro PQR(p,q,r) can be used to build this value
+ with p,p,r = 0 or 1
+
+ - frac : Fractional part of the multiplication factor
+ (optional, PLL is in integer mode when absent)
+
+ - csg : Clock Spreading Generator (optional)
+ with parameters in this order:
+ MOD_PER INC_STEP SSCG_MODE
+
+ * MOD_PER: Modulation Period Adjustment
+ * INC_STEP: Modulation Depth Adjustment
+ * SSCG_MODE: Spread spectrum clock generator mode
+ you can use associated defines from stm32mp1-clksrc.h
+ * SSCG_MODE_CENTER_SPREAD = 0
+ * SSCG_MODE_DOWN_SPREAD = 1
+
+
+- st,pkcs : used to configure the peripherals kernel clock selection
+ containing a list of peripheral kernel clock source identifier as defined
+ in the file dt-bindings/clock/stm32mp1-clksrc.h
+
+ Example:
+
+ rcc: rcc@50000000 {
+ compatible = "syscon", "simple-mfd";
+
+ reg = <0x50000000 0x1000>;
+
+ rcc_clk: rcc-clk@50000000 {
+ #clock-cells = <1>;
+ compatible = "st,stm32mp1-rcc-clk";
+
+ st,clksrc = < CLK_MPU_PLL1P
+ CLK_AXI_PLL2P
+ CLK_MCU_HSI
+ CLK_PLL12_HSE
+ CLK_PLL3_HSE
+ CLK_PLL4_HSE
+ CLK_RTC_HSE
+ CLK_MCO1_DISABLED
+ CLK_MCO2_DISABLED
+ >;
+
+ st,clkdiv = <
+ 1 /*MPU*/
+ 0 /*AXI*/
+ 0 /*MCU*/
+ 1 /*APB1*/
+ 1 /*APB2*/
+ 1 /*APB3*/
+ 1 /*APB4*/
+ 5 /*APB5*/
+ 23 /*RTC*/
+ 0 /*MCO1*/
+ 0 /*MCO2*/
+ >;
+
+ st,pll@0 {
+ cfg = < 1 53 0 0 0 1 >;
+ frac = < 0x810 >;
+ };
+ st,pll@1 {
+ cfg = < 1 43 1 0 0 PQR(0,1,1)>;
+ csg = <10 20 1>;
+ };
+ st,pll@2 {
+ cfg = < 2 85 3 13 3 0>;
+ csg = <10 20 SSCG_MODE_CENTER_SPREAD>;
+ };
+ st,pll@3 {
+ cfg = < 2 78 4 7 9 3>;
+ };
+ st,pkcs = <
+ CLK_STGEN_HSE
+ CLK_CKPER_HSI
+ CLK_USBPHY_PLL2P
+ CLK_DSI_PLL2Q
+ >;
+ };
+ };
+
+--------------------------
+other clocks = fixed-clock
+--------------------------
+The clock tree is also based on 5 fixed-clock in clocks node
+used to define the state of associated ST32MP1 oscillators:
+- clk-lsi
+- clk-lse
+- clk-hsi
+- clk-hse
+- clk-csi
+
+At boot the clock tree initialization will
+- enable the oscillator present in device tree
+- disable HSI oscillator if the node is absent (always activated by bootrom)
+
+Optional properties :
+
+a) for external oscillator: "clk-lse", "clk-hse"
+
+ 3 optional fields are managed
+ - "st,bypass" Configure the oscillator bypass mode (HSEBYP, LSEBYP)
+ - "st,css" Activate the clock security system (HSECSSON, LSECSSON)
+ - "st,drive" (only for LSE) value of the drive for the oscillator
+ (see LSEDRV_ define in the file dt-bindings/clock/stm32mp1-clksrc.h)
+
+ Example board file:
+
+ / {
+ clocks {
+ clk_hse: clk-hse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <64000000>;
+ st,bypass;
+ };
+
+ clk_lse: clk-lse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ st,css;
+ st,drive = <LSEDRV_LOWEST>;
+ };
+ };
+
+b) for internal oscillator: "clk-hsi"
+
+ internally HSI clock is fixed to 64MHz for STM32MP157 soc
+ in device tree clk-hsi is the clock after HSIDIV (ck_hsi in RCC doc)
+ So this clock frequency is used to compute the expected HSI_DIV
+ for the clock tree initialisation
+
+ ex: for HSIDIV = /1
+
+ / {
+ clocks {
+ clk_hsi: clk-hsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <64000000>;
+ };
+ };
+
+ ex: for HSIDIV = /2
+
+ / {
+ clocks {
+ clk_hsi: clk-hsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000000>;
+ };
+ };
diff --git a/doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt b/doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt
new file mode 100644
index 0000000..3028636
--- /dev/null
+++ b/doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt
@@ -0,0 +1,299 @@
+ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
+
+--------------------
+Required properties:
+--------------------
+- compatible : Should be "st,stm32mp1-ddr"
+- reg : controleur (DDRCTRL) and phy (DDRPHYC) base address
+- clocks : controller clocks handle
+- clock-names : associated controller clock names
+ the "ddrphyc" clock is used to check the DDR frequency
+ at phy level according the expected value in "mem-speed" field
+
+the next attributes are DDR parameters, they are generated by DDR tools
+included in STM32 Cube tool
+
+info attributes:
+----------------
+- st,mem-name : name for DDR configuration, simple string for information
+- st,mem-speed : DDR expected speed for the setting in MHz
+- st,mem-size : DDR mem size in byte
+
+
+controlleur attributes:
+-----------------------
+- st,ctl-reg : controleur values depending of the DDR type
+ (DDR3/LPDDR2/LPDDR3)
+ for STM32MP15x: 25 values are requested in this order
+ MSTR
+ MRCTRL0
+ MRCTRL1
+ DERATEEN
+ DERATEINT
+ PWRCTL
+ PWRTMG
+ HWLPCTL
+ RFSHCTL0
+ RFSHCTL3
+ CRCPARCTL0
+ ZQCTL0
+ DFITMG0
+ DFITMG1
+ DFILPCFG0
+ DFIUPD0
+ DFIUPD1
+ DFIUPD2
+ DFIPHYMSTR
+ ODTMAP
+ DBG0
+ DBG1
+ DBGCMD
+ POISONCFG
+ PCCFG
+
+- st,ctl-timing : controleur values depending of frequency and timing parameter
+ of DDR
+ for STM32MP15x: 12 values are requested in this order
+ RFSHTMG
+ DRAMTMG0
+ DRAMTMG1
+ DRAMTMG2
+ DRAMTMG3
+ DRAMTMG4
+ DRAMTMG5
+ DRAMTMG6
+ DRAMTMG7
+ DRAMTMG8
+ DRAMTMG14
+ ODTCFG
+
+- st,ctl-map : controleur values depending of address mapping
+ for STM32MP15x: 9 values are requested in this order
+ ADDRMAP1
+ ADDRMAP2
+ ADDRMAP3
+ ADDRMAP4
+ ADDRMAP5
+ ADDRMAP6
+ ADDRMAP9
+ ADDRMAP10
+ ADDRMAP11
+
+- st,ctl-perf : controleur values depending of performance and scheduling
+ for STM32MP15x: 17 values are requested in this order
+ SCHED
+ SCHED1
+ PERFHPR1
+ PERFLPR1
+ PERFWR1
+ PCFGR_0
+ PCFGW_0
+ PCFGQOS0_0
+ PCFGQOS1_0
+ PCFGWQOS0_0
+ PCFGWQOS1_0
+ PCFGR_1
+ PCFGW_1
+ PCFGQOS0_1
+ PCFGQOS1_1
+ PCFGWQOS0_1
+ PCFGWQOS1_1
+
+phyc attributes:
+----------------
+- st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
+ for STM32MP15x: 10 values are requested in this order
+ PGCR
+ ACIOCR
+ DXCCR
+ DSGCR
+ DCR
+ ODTCR
+ ZQ0CR1
+ DX0GCR
+ DX1GCR
+ DX2GCR
+ DX3GCR
+
+- st,phy-timing : phy values depending of frequency and timing parameter of DDR
+ for STM32MP15x: 10 values are requested in this order
+ PTR0
+ PTR1
+ PTR2
+ DTPR0
+ DTPR1
+ DTPR2
+ MR0
+ MR1
+ MR2
+ MR3
+
+- st,phy-cal : phy cal depending of calibration or tuning of DDR
+ for STM32MP15x: 12 values are requested in this order
+ DX0DLLCR
+ DX0DQTR
+ DX0DQSTR
+ DX1DLLCR
+ DX1DQTR
+ DX1DQSTR
+ DX2DLLCR
+ DX2DQTR
+ DX2DQSTR
+ DX3DLLCR
+ DX3DQTR
+ DX3DQSTR
+
+Example:
+
+/ {
+ soc {
+ u-boot,dm-spl;
+
+ ddr: ddr@0x5A003000{
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+
+ compatible = "st,stm32mp1-ddr";
+
+ reg = <0x5A003000 0x550
+ 0x5A004000 0x234>;
+
+ clocks = <&rcc_clk AXIDCG>,
+ <&rcc_clk DDRC1>,
+ <&rcc_clk DDRC2>,
+ <&rcc_clk DDRPHYC>,
+ <&rcc_clk DDRCAPB>,
+ <&rcc_clk DDRPHYCAPB>;
+
+ clock-names = "axidcg",
+ "ddrc1",
+ "ddrc2",
+ "ddrphyc",
+ "ddrcapb",
+ "ddrphycapb";
+
+ st,mem-name = "DDR3 2x4Gb 533MHz";
+ st,mem-speed = <533>;
+ st,mem-size = <0x40000000>;
+
+ st,ctl-reg = <
+ 0x00040401 /*MSTR*/
+ 0x00000010 /*MRCTRL0*/
+ 0x00000000 /*MRCTRL1*/
+ 0x00000000 /*DERATEEN*/
+ 0x00800000 /*DERATEINT*/
+ 0x00000000 /*PWRCTL*/
+ 0x00400010 /*PWRTMG*/
+ 0x00000000 /*HWLPCTL*/
+ 0x00210000 /*RFSHCTL0*/
+ 0x00000000 /*RFSHCTL3*/
+ 0x00000000 /*CRCPARCTL0*/
+ 0xC2000040 /*ZQCTL0*/
+ 0x02050105 /*DFITMG0*/
+ 0x00000202 /*DFITMG1*/
+ 0x07000000 /*DFILPCFG0*/
+ 0xC0400003 /*DFIUPD0*/
+ 0x00000000 /*DFIUPD1*/
+ 0x00000000 /*DFIUPD2*/
+ 0x00000000 /*DFIPHYMSTR*/
+ 0x00000001 /*ODTMAP*/
+ 0x00000000 /*DBG0*/
+ 0x00000000 /*DBG1*/
+ 0x00000000 /*DBGCMD*/
+ 0x00000000 /*POISONCFG*/
+ 0x00000010 /*PCCFG*/
+ >;
+
+ st,ctl-timing = <
+ 0x0080008A /*RFSHTMG*/
+ 0x121B2414 /*DRAMTMG0*/
+ 0x000D041B /*DRAMTMG1*/
+ 0x0607080E /*DRAMTMG2*/
+ 0x0050400C /*DRAMTMG3*/
+ 0x07040407 /*DRAMTMG4*/
+ 0x06060303 /*DRAMTMG5*/
+ 0x02020002 /*DRAMTMG6*/
+ 0x00000202 /*DRAMTMG7*/
+ 0x00001005 /*DRAMTMG8*/
+ 0x000D041B /*DRAMTMG1*/4
+ 0x06000600 /*ODTCFG*/
+ >;
+
+ st,ctl-map = <
+ 0x00080808 /*ADDRMAP1*/
+ 0x00000000 /*ADDRMAP2*/
+ 0x00000000 /*ADDRMAP3*/
+ 0x00001F1F /*ADDRMAP4*/
+ 0x07070707 /*ADDRMAP5*/
+ 0x0F070707 /*ADDRMAP6*/
+ 0x00000000 /*ADDRMAP9*/
+ 0x00000000 /*ADDRMAP10*/
+ 0x00000000 /*ADDRMAP11*/
+ >;
+
+ st,ctl-perf = <
+ 0x00001201 /*SCHED*/
+ 0x00001201 /*SCHED*/1
+ 0x01000001 /*PERFHPR1*/
+ 0x08000200 /*PERFLPR1*/
+ 0x08000400 /*PERFWR1*/
+ 0x00010000 /*PCFGR_0*/
+ 0x00000000 /*PCFGW_0*/
+ 0x02100B03 /*PCFGQOS0_0*/
+ 0x00800100 /*PCFGQOS1_0*/
+ 0x01100B03 /*PCFGWQOS0_0*/
+ 0x01000200 /*PCFGWQOS1_0*/
+ 0x00010000 /*PCFGR_1*/
+ 0x00000000 /*PCFGW_1*/
+ 0x02100B03 /*PCFGQOS0_1*/
+ 0x00800000 /*PCFGQOS1_1*/
+ 0x01100B03 /*PCFGWQOS0_1*/
+ 0x01000200 /*PCFGWQOS1_1*/
+ >;
+
+ st,phy-reg = <
+ 0x01442E02 /*PGCR*/
+ 0x10400812 /*ACIOCR*/
+ 0x00000C40 /*DXCCR*/
+ 0xF200001F /*DSGCR*/
+ 0x0000000B /*DCR*/
+ 0x00010000 /*ODTCR*/
+ 0x0000007B /*ZQ0CR1*/
+ 0x0000CE81 /*DX0GCR*/
+ 0x0000CE81 /*DX1GCR*/
+ 0x0000CE81 /*DX2GCR*/
+ 0x0000CE81 /*DX3GCR*/
+ >;
+
+ st,phy-timing = <
+ 0x0022A41B /*PTR0*/
+ 0x047C0740 /*PTR1*/
+ 0x042D9C80 /*PTR2*/
+ 0x369477D0 /*DTPR0*/
+ 0x098A00D8 /*DTPR1*/
+ 0x10023600 /*DTPR2*/
+ 0x00000830 /*MR0*/
+ 0x00000000 /*MR1*/
+ 0x00000208 /*MR2*/
+ 0x00000000 /*MR3*/
+ >;
+
+ st,phy-cal = <
+ 0x40000000 /*DX0DLLCR*/
+ 0xFFFFFFFF /*DX0DQTR*/
+ 0x3DB02000 /*DX0DQSTR*/
+ 0x40000000 /*DX1DLLCR*/
+ 0xFFFFFFFF /*DX1DQTR*/
+ 0x3DB02000 /*DX1DQSTR*/
+ 0x40000000 /*DX2DLLCR*/
+ 0xFFFFFFFF /*DX2DQTR*/
+ 0x3DB02000 /*DX2DQSTR*/
+ 0x40000000 /*DX3DLLCR*/
+ 0xFFFFFFFF /*DX3DQTR*/
+ 0x3DB02000 /*DX3DQSTR*/
+ >;
+
+ status = "okay";
+ };
+ };
+};
diff --git a/drivers/Makefile b/drivers/Makefile
index 2673428..6846d18 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -29,6 +29,7 @@
obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/
+obj-$(CONFIG_SPL_RESET_SUPPORT) += reset/
obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd/
obj-$(CONFIG_SPL_ONENAND_SUPPORT) += mtd/onenand/
obj-$(CONFIG_SPL_UBI) += mtd/ubispl/
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index cdfa052..c382e88 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -75,6 +75,14 @@
This clock driver adds support for clock realted settings for
ZynqMP platform.
+config CLK_STM32MP1
+ bool "Enable RCC clock driver for STM32MP1"
+ depends on ARCH_STM32MP && CLK
+ default y
+ help
+ Enable the STM32 clock (RCC) driver. Enable support for
+ manipulating STM32MP1's on-SoC clocks.
+
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/uniphier/Kconfig"
source "drivers/clk/exynos/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index dab106a..e05c607 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -17,6 +17,7 @@
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
obj-$(CONFIG_CLK_RENESAS) += renesas/
obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
+obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
new file mode 100644
index 0000000..55b0f79
--- /dev/null
+++ b/drivers/clk/clk_stm32mp1.c
@@ -0,0 +1,1733 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <regmap.h>
+#include <spl.h>
+#include <syscon.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <dt-bindings/clock/stm32mp1-clks.h>
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
+
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+/* activate clock tree initialization in the driver */
+#define STM32MP1_CLOCK_TREE_INIT
+#endif
+
+#define MAX_HSI_HZ 64000000
+
+/* TIMEOUT */
+#define TIMEOUT_200MS 200000
+#define TIMEOUT_1S 1000000
+
+/* RCC registers */
+#define RCC_OCENSETR 0x0C
+#define RCC_OCENCLRR 0x10
+#define RCC_HSICFGR 0x18
+#define RCC_MPCKSELR 0x20
+#define RCC_ASSCKSELR 0x24
+#define RCC_RCK12SELR 0x28
+#define RCC_MPCKDIVR 0x2C
+#define RCC_AXIDIVR 0x30
+#define RCC_APB4DIVR 0x3C
+#define RCC_APB5DIVR 0x40
+#define RCC_RTCDIVR 0x44
+#define RCC_MSSCKSELR 0x48
+#define RCC_PLL1CR 0x80
+#define RCC_PLL1CFGR1 0x84
+#define RCC_PLL1CFGR2 0x88
+#define RCC_PLL1FRACR 0x8C
+#define RCC_PLL1CSGR 0x90
+#define RCC_PLL2CR 0x94
+#define RCC_PLL2CFGR1 0x98
+#define RCC_PLL2CFGR2 0x9C
+#define RCC_PLL2FRACR 0xA0
+#define RCC_PLL2CSGR 0xA4
+#define RCC_I2C46CKSELR 0xC0
+#define RCC_CPERCKSELR 0xD0
+#define RCC_STGENCKSELR 0xD4
+#define RCC_DDRITFCR 0xD8
+#define RCC_BDCR 0x140
+#define RCC_RDLSICR 0x144
+#define RCC_MP_APB4ENSETR 0x200
+#define RCC_MP_APB5ENSETR 0x208
+#define RCC_MP_AHB5ENSETR 0x210
+#define RCC_MP_AHB6ENSETR 0x218
+#define RCC_OCRDYR 0x808
+#define RCC_DBGCFGR 0x80C
+#define RCC_RCK3SELR 0x820
+#define RCC_RCK4SELR 0x824
+#define RCC_MCUDIVR 0x830
+#define RCC_APB1DIVR 0x834
+#define RCC_APB2DIVR 0x838
+#define RCC_APB3DIVR 0x83C
+#define RCC_PLL3CR 0x880
+#define RCC_PLL3CFGR1 0x884
+#define RCC_PLL3CFGR2 0x888
+#define RCC_PLL3FRACR 0x88C
+#define RCC_PLL3CSGR 0x890
+#define RCC_PLL4CR 0x894
+#define RCC_PLL4CFGR1 0x898
+#define RCC_PLL4CFGR2 0x89C
+#define RCC_PLL4FRACR 0x8A0
+#define RCC_PLL4CSGR 0x8A4
+#define RCC_I2C12CKSELR 0x8C0
+#define RCC_I2C35CKSELR 0x8C4
+#define RCC_UART6CKSELR 0x8E4
+#define RCC_UART24CKSELR 0x8E8
+#define RCC_UART35CKSELR 0x8EC
+#define RCC_UART78CKSELR 0x8F0
+#define RCC_SDMMC12CKSELR 0x8F4
+#define RCC_SDMMC3CKSELR 0x8F8
+#define RCC_ETHCKSELR 0x8FC
+#define RCC_QSPICKSELR 0x900
+#define RCC_FMCCKSELR 0x904
+#define RCC_USBCKSELR 0x91C
+#define RCC_MP_APB1ENSETR 0xA00
+#define RCC_MP_APB2ENSETR 0XA08
+#define RCC_MP_AHB2ENSETR 0xA18
+#define RCC_MP_AHB4ENSETR 0xA28
+
+/* used for most of SELR register */
+#define RCC_SELR_SRC_MASK GENMASK(2, 0)
+#define RCC_SELR_SRCRDY BIT(31)
+
+/* Values of RCC_MPCKSELR register */
+#define RCC_MPCKSELR_HSI 0
+#define RCC_MPCKSELR_HSE 1
+#define RCC_MPCKSELR_PLL 2
+#define RCC_MPCKSELR_PLL_MPUDIV 3
+
+/* Values of RCC_ASSCKSELR register */
+#define RCC_ASSCKSELR_HSI 0
+#define RCC_ASSCKSELR_HSE 1
+#define RCC_ASSCKSELR_PLL 2
+
+/* Values of RCC_MSSCKSELR register */
+#define RCC_MSSCKSELR_HSI 0
+#define RCC_MSSCKSELR_HSE 1
+#define RCC_MSSCKSELR_CSI 2
+#define RCC_MSSCKSELR_PLL 3
+
+/* Values of RCC_CPERCKSELR register */
+#define RCC_CPERCKSELR_HSI 0
+#define RCC_CPERCKSELR_CSI 1
+#define RCC_CPERCKSELR_HSE 2
+
+/* used for most of DIVR register : max div for RTC */
+#define RCC_DIVR_DIV_MASK GENMASK(5, 0)
+#define RCC_DIVR_DIVRDY BIT(31)
+
+/* Masks for specific DIVR registers */
+#define RCC_APBXDIV_MASK GENMASK(2, 0)
+#define RCC_MPUDIV_MASK GENMASK(2, 0)
+#define RCC_AXIDIV_MASK GENMASK(2, 0)
+#define RCC_MCUDIV_MASK GENMASK(3, 0)
+
+/* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
+#define RCC_MP_ENCLRR_OFFSET 4
+
+/* Fields of RCC_BDCR register */
+#define RCC_BDCR_LSEON BIT(0)
+#define RCC_BDCR_LSEBYP BIT(1)
+#define RCC_BDCR_LSERDY BIT(2)
+#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
+#define RCC_BDCR_LSEDRV_SHIFT 4
+#define RCC_BDCR_LSECSSON BIT(8)
+#define RCC_BDCR_RTCCKEN BIT(20)
+#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
+#define RCC_BDCR_RTCSRC_SHIFT 16
+
+/* Fields of RCC_RDLSICR register */
+#define RCC_RDLSICR_LSION BIT(0)
+#define RCC_RDLSICR_LSIRDY BIT(1)
+
+/* used for ALL PLLNCR registers */
+#define RCC_PLLNCR_PLLON BIT(0)
+#define RCC_PLLNCR_PLLRDY BIT(1)
+#define RCC_PLLNCR_DIVPEN BIT(4)
+#define RCC_PLLNCR_DIVQEN BIT(5)
+#define RCC_PLLNCR_DIVREN BIT(6)
+#define RCC_PLLNCR_DIVEN_SHIFT 4
+
+/* used for ALL PLLNCFGR1 registers */
+#define RCC_PLLNCFGR1_DIVM_SHIFT 16
+#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
+#define RCC_PLLNCFGR1_DIVN_SHIFT 0
+#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
+/* only for PLL3 and PLL4 */
+#define RCC_PLLNCFGR1_IFRGE_SHIFT 24
+#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
+
+/* used for ALL PLLNCFGR2 registers */
+#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
+#define RCC_PLLNCFGR2_DIVP_SHIFT 0
+#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
+#define RCC_PLLNCFGR2_DIVQ_SHIFT 8
+#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
+#define RCC_PLLNCFGR2_DIVR_SHIFT 16
+#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
+
+/* used for ALL PLLNFRACR registers */
+#define RCC_PLLNFRACR_FRACV_SHIFT 3
+#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
+#define RCC_PLLNFRACR_FRACLE BIT(16)
+
+/* used for ALL PLLNCSGR registers */
+#define RCC_PLLNCSGR_INC_STEP_SHIFT 16
+#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
+#define RCC_PLLNCSGR_MOD_PER_SHIFT 0
+#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
+#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
+#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
+
+/* used for RCC_OCENSETR and RCC_OCENCLRR registers */
+#define RCC_OCENR_HSION BIT(0)
+#define RCC_OCENR_CSION BIT(4)
+#define RCC_OCENR_HSEON BIT(8)
+#define RCC_OCENR_HSEBYP BIT(10)
+#define RCC_OCENR_HSECSSON BIT(11)
+
+/* Fields of RCC_OCRDYR register */
+#define RCC_OCRDYR_HSIRDY BIT(0)
+#define RCC_OCRDYR_HSIDIVRDY BIT(2)
+#define RCC_OCRDYR_CSIRDY BIT(4)
+#define RCC_OCRDYR_HSERDY BIT(8)
+
+/* Fields of DDRITFCR register */
+#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
+#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
+#define RCC_DDRITFCR_DDRCKMOD_SSR 0
+
+/* Fields of RCC_HSICFGR register */
+#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
+
+/* used for MCO related operations */
+#define RCC_MCOCFG_MCOON BIT(12)
+#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
+#define RCC_MCOCFG_MCODIV_SHIFT 4
+#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
+
+enum stm32mp1_parent_id {
+/*
+ * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
+ * they are used as index in osc[] as entry point
+ */
+ _HSI,
+ _HSE,
+ _CSI,
+ _LSI,
+ _LSE,
+ _I2S_CKIN,
+ _USB_PHY_48,
+ NB_OSC,
+
+/* other parent source */
+ _HSI_KER = NB_OSC,
+ _HSE_KER,
+ _HSE_KER_DIV2,
+ _CSI_KER,
+ _PLL1_P,
+ _PLL1_Q,
+ _PLL1_R,
+ _PLL2_P,
+ _PLL2_Q,
+ _PLL2_R,
+ _PLL3_P,
+ _PLL3_Q,
+ _PLL3_R,
+ _PLL4_P,
+ _PLL4_Q,
+ _PLL4_R,
+ _ACLK,
+ _PCLK1,
+ _PCLK2,
+ _PCLK3,
+ _PCLK4,
+ _PCLK5,
+ _HCLK6,
+ _HCLK2,
+ _CK_PER,
+ _CK_MPU,
+ _CK_MCU,
+ _PARENT_NB,
+ _UNKNOWN_ID = 0xff,
+};
+
+enum stm32mp1_parent_sel {
+ _I2C12_SEL,
+ _I2C35_SEL,
+ _I2C46_SEL,
+ _UART6_SEL,
+ _UART24_SEL,
+ _UART35_SEL,
+ _UART78_SEL,
+ _SDMMC12_SEL,
+ _SDMMC3_SEL,
+ _ETH_SEL,
+ _QSPI_SEL,
+ _FMC_SEL,
+ _USBPHY_SEL,
+ _USBO_SEL,
+ _STGEN_SEL,
+ _PARENT_SEL_NB,
+ _UNKNOWN_SEL = 0xff,
+};
+
+enum stm32mp1_pll_id {
+ _PLL1,
+ _PLL2,
+ _PLL3,
+ _PLL4,
+ _PLL_NB
+};
+
+enum stm32mp1_div_id {
+ _DIV_P,
+ _DIV_Q,
+ _DIV_R,
+ _DIV_NB,
+};
+
+enum stm32mp1_clksrc_id {
+ CLKSRC_MPU,
+ CLKSRC_AXI,
+ CLKSRC_MCU,
+ CLKSRC_PLL12,
+ CLKSRC_PLL3,
+ CLKSRC_PLL4,
+ CLKSRC_RTC,
+ CLKSRC_MCO1,
+ CLKSRC_MCO2,
+ CLKSRC_NB
+};
+
+enum stm32mp1_clkdiv_id {
+ CLKDIV_MPU,
+ CLKDIV_AXI,
+ CLKDIV_MCU,
+ CLKDIV_APB1,
+ CLKDIV_APB2,
+ CLKDIV_APB3,
+ CLKDIV_APB4,
+ CLKDIV_APB5,
+ CLKDIV_RTC,
+ CLKDIV_MCO1,
+ CLKDIV_MCO2,
+ CLKDIV_NB
+};
+
+enum stm32mp1_pllcfg {
+ PLLCFG_M,
+ PLLCFG_N,
+ PLLCFG_P,
+ PLLCFG_Q,
+ PLLCFG_R,
+ PLLCFG_O,
+ PLLCFG_NB
+};
+
+enum stm32mp1_pllcsg {
+ PLLCSG_MOD_PER,
+ PLLCSG_INC_STEP,
+ PLLCSG_SSCG_MODE,
+ PLLCSG_NB
+};
+
+enum stm32mp1_plltype {
+ PLL_800,
+ PLL_1600,
+ PLL_TYPE_NB
+};
+
+struct stm32mp1_pll {
+ u8 refclk_min;
+ u8 refclk_max;
+ u8 divn_max;
+};
+
+struct stm32mp1_clk_gate {
+ u16 offset;
+ u8 bit;
+ u8 index;
+ u8 set_clr;
+ u8 sel;
+ u8 fixed;
+};
+
+struct stm32mp1_clk_sel {
+ u16 offset;
+ u8 src;
+ u8 msk;
+ u8 nb_parent;
+ const u8 *parent;
+};
+
+#define REFCLK_SIZE 4
+struct stm32mp1_clk_pll {
+ enum stm32mp1_plltype plltype;
+ u16 rckxselr;
+ u16 pllxcfgr1;
+ u16 pllxcfgr2;
+ u16 pllxfracr;
+ u16 pllxcr;
+ u16 pllxcsgr;
+ u8 refclk[REFCLK_SIZE];
+};
+
+struct stm32mp1_clk_data {
+ const struct stm32mp1_clk_gate *gate;
+ const struct stm32mp1_clk_sel *sel;
+ const struct stm32mp1_clk_pll *pll;
+ const int nb_gate;
+};
+
+struct stm32mp1_clk_priv {
+ fdt_addr_t base;
+ const struct stm32mp1_clk_data *data;
+ ulong osc[NB_OSC];
+ struct udevice *osc_dev[NB_OSC];
+};
+
+#define STM32MP1_CLK(off, b, idx, s) \
+ { \
+ .offset = (off), \
+ .bit = (b), \
+ .index = (idx), \
+ .set_clr = 0, \
+ .sel = (s), \
+ .fixed = _UNKNOWN_ID, \
+ }
+
+#define STM32MP1_CLK_F(off, b, idx, f) \
+ { \
+ .offset = (off), \
+ .bit = (b), \
+ .index = (idx), \
+ .set_clr = 0, \
+ .sel = _UNKNOWN_SEL, \
+ .fixed = (f), \
+ }
+
+#define STM32MP1_CLK_SET_CLR(off, b, idx, s) \
+ { \
+ .offset = (off), \
+ .bit = (b), \
+ .index = (idx), \
+ .set_clr = 1, \
+ .sel = (s), \
+ .fixed = _UNKNOWN_ID, \
+ }
+
+#define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \
+ { \
+ .offset = (off), \
+ .bit = (b), \
+ .index = (idx), \
+ .set_clr = 1, \
+ .sel = _UNKNOWN_SEL, \
+ .fixed = (f), \
+ }
+
+#define STM32MP1_CLK_PARENT(idx, off, s, m, p) \
+ [(idx)] = { \
+ .offset = (off), \
+ .src = (s), \
+ .msk = (m), \
+ .parent = (p), \
+ .nb_parent = ARRAY_SIZE((p)) \
+ }
+
+#define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
+ p1, p2, p3, p4) \
+ [(idx)] = { \
+ .plltype = (type), \
+ .rckxselr = (off1), \
+ .pllxcfgr1 = (off2), \
+ .pllxcfgr2 = (off3), \
+ .pllxfracr = (off4), \
+ .pllxcr = (off5), \
+ .pllxcsgr = (off6), \
+ .refclk[0] = (p1), \
+ .refclk[1] = (p2), \
+ .refclk[2] = (p3), \
+ .refclk[3] = (p4), \
+ }
+
+static const u8 stm32mp1_clks[][2] = {
+ {CK_PER, _CK_PER},
+ {CK_MPU, _CK_MPU},
+ {CK_AXI, _ACLK},
+ {CK_MCU, _CK_MCU},
+ {CK_HSE, _HSE},
+ {CK_CSI, _CSI},
+ {CK_LSI, _LSI},
+ {CK_LSE, _LSE},
+ {CK_HSI, _HSI},
+ {CK_HSE_DIV2, _HSE_KER_DIV2},
+};
+
+static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
+ STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
+ STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
+ STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
+ STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
+ STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
+ STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
+ STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
+ STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
+ STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
+ STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
+ STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
+
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
+
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
+
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
+
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
+
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
+
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
+
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
+
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 10, ETHMAC_K, _ETH_SEL),
+ STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
+
+ STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
+};
+
+static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
+static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
+static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
+static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
+ _HSE_KER};
+static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
+ _HSE_KER};
+static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
+ _HSE_KER};
+static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
+ _HSE_KER};
+static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
+static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
+static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
+static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
+static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
+static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
+static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
+static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
+
+static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
+ STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
+ STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
+ STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
+ STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
+ STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
+ uart24_parents),
+ STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
+ uart35_parents),
+ STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
+ uart78_parents),
+ STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
+ sdmmc12_parents),
+ STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
+ sdmmc3_parents),
+ STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
+ STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
+ STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
+ STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
+ STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
+ STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
+};
+
+#ifdef STM32MP1_CLOCK_TREE_INIT
+/* define characteristic of PLL according type */
+#define DIVN_MIN 24
+static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
+ [PLL_800] = {
+ .refclk_min = 4,
+ .refclk_max = 16,
+ .divn_max = 99,
+ },
+ [PLL_1600] = {
+ .refclk_min = 8,
+ .refclk_max = 16,
+ .divn_max = 199,
+ },
+};
+#endif /* STM32MP1_CLOCK_TREE_INIT */
+
+static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
+ STM32MP1_CLK_PLL(_PLL1, PLL_1600,
+ RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
+ RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
+ _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
+ STM32MP1_CLK_PLL(_PLL2, PLL_1600,
+ RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
+ RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
+ _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
+ STM32MP1_CLK_PLL(_PLL3, PLL_800,
+ RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
+ RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
+ _HSI, _HSE, _CSI, _UNKNOWN_ID),
+ STM32MP1_CLK_PLL(_PLL4, PLL_800,
+ RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
+ RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
+ _HSI, _HSE, _CSI, _I2S_CKIN),
+};
+
+/* Prescaler table lookups for clock computation */
+/* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
+static const u8 stm32mp1_mcu_div[16] = {
+ 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
+};
+
+/* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
+#define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
+#define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
+static const u8 stm32mp1_mpu_apbx_div[8] = {
+ 0, 1, 2, 3, 4, 4, 4, 4
+};
+
+/* div = /1 /2 /3 /4 */
+static const u8 stm32mp1_axi_div[8] = {
+ 1, 2, 3, 4, 4, 4, 4, 4
+};
+
+#ifdef DEBUG
+static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
+ [_HSI] = "HSI",
+ [_HSE] = "HSE",
+ [_CSI] = "CSI",
+ [_LSI] = "LSI",
+ [_LSE] = "LSE",
+ [_I2S_CKIN] = "I2S_CKIN",
+ [_HSI_KER] = "HSI_KER",
+ [_HSE_KER] = "HSE_KER",
+ [_HSE_KER_DIV2] = "HSE_KER_DIV2",
+ [_CSI_KER] = "CSI_KER",
+ [_PLL1_P] = "PLL1_P",
+ [_PLL1_Q] = "PLL1_Q",
+ [_PLL1_R] = "PLL1_R",
+ [_PLL2_P] = "PLL2_P",
+ [_PLL2_Q] = "PLL2_Q",
+ [_PLL2_R] = "PLL2_R",
+ [_PLL3_P] = "PLL3_P",
+ [_PLL3_Q] = "PLL3_Q",
+ [_PLL3_R] = "PLL3_R",
+ [_PLL4_P] = "PLL4_P",
+ [_PLL4_Q] = "PLL4_Q",
+ [_PLL4_R] = "PLL4_R",
+ [_ACLK] = "ACLK",
+ [_PCLK1] = "PCLK1",
+ [_PCLK2] = "PCLK2",
+ [_PCLK3] = "PCLK3",
+ [_PCLK4] = "PCLK4",
+ [_PCLK5] = "PCLK5",
+ [_HCLK6] = "KCLK6",
+ [_HCLK2] = "HCLK2",
+ [_CK_PER] = "CK_PER",
+ [_CK_MPU] = "CK_MPU",
+ [_CK_MCU] = "CK_MCU",
+ [_USB_PHY_48] = "USB_PHY_48"
+};
+
+static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
+ [_I2C12_SEL] = "I2C12",
+ [_I2C35_SEL] = "I2C35",
+ [_I2C46_SEL] = "I2C46",
+ [_UART6_SEL] = "UART6",
+ [_UART24_SEL] = "UART24",
+ [_UART35_SEL] = "UART35",
+ [_UART78_SEL] = "UART78",
+ [_SDMMC12_SEL] = "SDMMC12",
+ [_SDMMC3_SEL] = "SDMMC3",
+ [_ETH_SEL] = "ETH",
+ [_QSPI_SEL] = "QSPI",
+ [_FMC_SEL] = "FMC",
+ [_USBPHY_SEL] = "USBPHY",
+ [_USBO_SEL] = "USBO",
+ [_STGEN_SEL] = "STGEN"
+};
+#endif
+
+static const struct stm32mp1_clk_data stm32mp1_data = {
+ .gate = stm32mp1_clk_gate,
+ .sel = stm32mp1_clk_sel,
+ .pll = stm32mp1_clk_pll,
+ .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
+};
+
+static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
+{
+ if (idx >= NB_OSC) {
+ debug("%s: clk id %d not found\n", __func__, idx);
+ return 0;
+ }
+
+ debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
+ (u32)priv->osc[idx], priv->osc[idx] / 1000);
+
+ return priv->osc[idx];
+}
+
+static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
+{
+ const struct stm32mp1_clk_gate *gate = priv->data->gate;
+ int i, nb_clks = priv->data->nb_gate;
+
+ for (i = 0; i < nb_clks; i++) {
+ if (gate[i].index == id)
+ break;
+ }
+
+ if (i == nb_clks) {
+ printf("%s: clk id %d not found\n", __func__, (u32)id);
+ return -EINVAL;
+ }
+
+ return i;
+}
+
+static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
+ int i)
+{
+ const struct stm32mp1_clk_gate *gate = priv->data->gate;
+
+ if (gate[i].sel > _PARENT_SEL_NB) {
+ printf("%s: parents for clk id %d not found\n",
+ __func__, i);
+ return -EINVAL;
+ }
+
+ return gate[i].sel;
+}
+
+static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
+ int i)
+{
+ const struct stm32mp1_clk_gate *gate = priv->data->gate;
+
+ if (gate[i].fixed == _UNKNOWN_ID)
+ return -ENOENT;
+
+ return gate[i].fixed;
+}
+
+static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
+ unsigned long id)
+{
+ const struct stm32mp1_clk_sel *sel = priv->data->sel;
+ int i;
+ int s, p;
+
+ for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
+ if (stm32mp1_clks[i][0] == id)
+ return stm32mp1_clks[i][1];
+
+ i = stm32mp1_clk_get_id(priv, id);
+ if (i < 0)
+ return i;
+
+ p = stm32mp1_clk_get_fixed_parent(priv, i);
+ if (p >= 0 && p < _PARENT_NB)
+ return p;
+
+ s = stm32mp1_clk_get_sel(priv, i);
+ if (s < 0)
+ return s;
+
+ p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
+
+ if (p < sel[s].nb_parent) {
+#ifdef DEBUG
+ debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
+ stm32mp1_clk_parent_name[sel[s].parent[p]],
+ stm32mp1_clk_parent_sel_name[s],
+ (u32)id);
+#endif
+ return sel[s].parent[p];
+ }
+
+ pr_err("%s: no parents defined for clk id %d\n",
+ __func__, (u32)id);
+
+ return -EINVAL;
+}
+
+static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
+ int pll_id, int div_id)
+{
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ int divm, divn, divy, src;
+ ulong refclk, dfout;
+ u32 selr, cfgr1, cfgr2, fracr;
+ const u8 shift[_DIV_NB] = {
+ [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
+ [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
+ [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT };
+
+ debug("%s(%d, %d)\n", __func__, pll_id, div_id);
+ if (div_id > _DIV_NB)
+ return 0;
+
+ selr = readl(priv->base + pll[pll_id].rckxselr);
+ cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
+ cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
+ fracr = readl(priv->base + pll[pll_id].pllxfracr);
+
+ debug("PLL%d : selr=%x cfgr1=%x cfgr2=%x fracr=%x\n",
+ pll_id, selr, cfgr1, cfgr2, fracr);
+
+ divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
+ divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
+ divy = (cfgr2 >> shift[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
+
+ debug(" DIVN=%d DIVM=%d DIVY=%d\n", divn, divm, divy);
+
+ src = selr & RCC_SELR_SRC_MASK;
+ refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
+
+ debug(" refclk = %d kHz\n", (u32)(refclk / 1000));
+
+ /*
+ * For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
+ * So same final result than PLL2 et 4
+ * with FRACV :
+ * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
+ * / (DIVM + 1) * (DIVy + 1)
+ * without FRACV
+ * Fck_pll_y = Fck_ref * ((DIVN + 1) / (DIVM + 1) *(DIVy + 1)
+ */
+ if (fracr & RCC_PLLNFRACR_FRACLE) {
+ u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
+ >> RCC_PLLNFRACR_FRACV_SHIFT;
+ dfout = (ulong)lldiv((unsigned long long)refclk *
+ (((divn + 1) << 13) + fracv),
+ ((unsigned long long)(divm + 1) *
+ (divy + 1)) << 13);
+ } else {
+ dfout = (ulong)(refclk * (divn + 1) / (divm + 1) * (divy + 1));
+ }
+ debug(" => dfout = %d kHz\n", (u32)(dfout / 1000));
+
+ return dfout;
+}
+
+static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
+{
+ u32 reg;
+ ulong clock = 0;
+
+ switch (p) {
+ case _CK_MPU:
+ /* MPU sub system */
+ reg = readl(priv->base + RCC_MPCKSELR);
+ switch (reg & RCC_SELR_SRC_MASK) {
+ case RCC_MPCKSELR_HSI:
+ clock = stm32mp1_clk_get_fixed(priv, _HSI);
+ break;
+ case RCC_MPCKSELR_HSE:
+ clock = stm32mp1_clk_get_fixed(priv, _HSE);
+ break;
+ case RCC_MPCKSELR_PLL:
+ case RCC_MPCKSELR_PLL_MPUDIV:
+ clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
+ if (p == RCC_MPCKSELR_PLL_MPUDIV) {
+ reg = readl(priv->base + RCC_MPCKDIVR);
+ clock /= stm32mp1_mpu_div[reg &
+ RCC_MPUDIV_MASK];
+ }
+ break;
+ }
+ break;
+ /* AXI sub system */
+ case _ACLK:
+ case _HCLK2:
+ case _HCLK6:
+ case _PCLK4:
+ case _PCLK5:
+ reg = readl(priv->base + RCC_ASSCKSELR);
+ switch (reg & RCC_SELR_SRC_MASK) {
+ case RCC_ASSCKSELR_HSI:
+ clock = stm32mp1_clk_get_fixed(priv, _HSI);
+ break;
+ case RCC_ASSCKSELR_HSE:
+ clock = stm32mp1_clk_get_fixed(priv, _HSE);
+ break;
+ case RCC_ASSCKSELR_PLL:
+ clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
+ break;
+ }
+
+ /* System clock divider */
+ reg = readl(priv->base + RCC_AXIDIVR);
+ clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
+
+ switch (p) {
+ case _PCLK4:
+ reg = readl(priv->base + RCC_APB4DIVR);
+ clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
+ break;
+ case _PCLK5:
+ reg = readl(priv->base + RCC_APB5DIVR);
+ clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
+ break;
+ default:
+ break;
+ }
+ break;
+ /* MCU sub system */
+ case _CK_MCU:
+ case _PCLK1:
+ case _PCLK2:
+ case _PCLK3:
+ reg = readl(priv->base + RCC_MSSCKSELR);
+ switch (reg & RCC_SELR_SRC_MASK) {
+ case RCC_MSSCKSELR_HSI:
+ clock = stm32mp1_clk_get_fixed(priv, _HSI);
+ break;
+ case RCC_MSSCKSELR_HSE:
+ clock = stm32mp1_clk_get_fixed(priv, _HSE);
+ break;
+ case RCC_MSSCKSELR_CSI:
+ clock = stm32mp1_clk_get_fixed(priv, _CSI);
+ break;
+ case RCC_MSSCKSELR_PLL:
+ clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
+ break;
+ }
+
+ /* MCU clock divider */
+ reg = readl(priv->base + RCC_MCUDIVR);
+ clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
+
+ switch (p) {
+ case _PCLK1:
+ reg = readl(priv->base + RCC_APB1DIVR);
+ clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
+ break;
+ case _PCLK2:
+ reg = readl(priv->base + RCC_APB2DIVR);
+ clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
+ break;
+ case _PCLK3:
+ reg = readl(priv->base + RCC_APB3DIVR);
+ clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
+ break;
+ case _CK_MCU:
+ default:
+ break;
+ }
+ break;
+ case _CK_PER:
+ reg = readl(priv->base + RCC_CPERCKSELR);
+ switch (reg & RCC_SELR_SRC_MASK) {
+ case RCC_CPERCKSELR_HSI:
+ clock = stm32mp1_clk_get_fixed(priv, _HSI);
+ break;
+ case RCC_CPERCKSELR_HSE:
+ clock = stm32mp1_clk_get_fixed(priv, _HSE);
+ break;
+ case RCC_CPERCKSELR_CSI:
+ clock = stm32mp1_clk_get_fixed(priv, _CSI);
+ break;
+ }
+ break;
+ case _HSI:
+ case _HSI_KER:
+ clock = stm32mp1_clk_get_fixed(priv, _HSI);
+ break;
+ case _CSI:
+ case _CSI_KER:
+ clock = stm32mp1_clk_get_fixed(priv, _CSI);
+ break;
+ case _HSE:
+ case _HSE_KER:
+ case _HSE_KER_DIV2:
+ clock = stm32mp1_clk_get_fixed(priv, _HSE);
+ if (p == _HSE_KER_DIV2)
+ clock >>= 1;
+ break;
+ case _LSI:
+ clock = stm32mp1_clk_get_fixed(priv, _LSI);
+ break;
+ case _LSE:
+ clock = stm32mp1_clk_get_fixed(priv, _LSE);
+ break;
+ /* PLL */
+ case _PLL1_P:
+ case _PLL1_Q:
+ case _PLL1_R:
+ clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
+ break;
+ case _PLL2_P:
+ case _PLL2_Q:
+ case _PLL2_R:
+ clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
+ break;
+ case _PLL3_P:
+ case _PLL3_Q:
+ case _PLL3_R:
+ clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
+ break;
+ case _PLL4_P:
+ case _PLL4_Q:
+ case _PLL4_R:
+ clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
+ break;
+ /* other */
+ case _USB_PHY_48:
+ clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48);
+ break;
+
+ default:
+ break;
+ }
+
+ debug("%s(%d) clock = %lx : %ld kHz\n",
+ __func__, p, clock, clock / 1000);
+
+ return clock;
+}
+
+static int stm32mp1_clk_enable(struct clk *clk)
+{
+ struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
+ const struct stm32mp1_clk_gate *gate = priv->data->gate;
+ int i = stm32mp1_clk_get_id(priv, clk->id);
+
+ if (i < 0)
+ return i;
+
+ if (gate[i].set_clr)
+ writel(BIT(gate[i].bit), priv->base + gate[i].offset);
+ else
+ setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
+
+ debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
+
+ return 0;
+}
+
+static int stm32mp1_clk_disable(struct clk *clk)
+{
+ struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
+ const struct stm32mp1_clk_gate *gate = priv->data->gate;
+ int i = stm32mp1_clk_get_id(priv, clk->id);
+
+ if (i < 0)
+ return i;
+
+ if (gate[i].set_clr)
+ writel(BIT(gate[i].bit),
+ priv->base + gate[i].offset
+ + RCC_MP_ENCLRR_OFFSET);
+ else
+ clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
+
+ debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
+
+ return 0;
+}
+
+static ulong stm32mp1_clk_get_rate(struct clk *clk)
+{
+ struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
+ int p = stm32mp1_clk_get_parent(priv, clk->id);
+ ulong rate;
+
+ if (p < 0)
+ return 0;
+
+ rate = stm32mp1_clk_get(priv, p);
+
+#ifdef DEBUG
+ debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
+ __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
+#endif
+ return rate;
+}
+
+#ifdef STM32MP1_CLOCK_TREE_INIT
+static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
+ u32 mask_on)
+{
+ u32 address = rcc + offset;
+
+ if (enable)
+ setbits_le32(address, mask_on);
+ else
+ clrbits_le32(address, mask_on);
+}
+
+static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
+{
+ if (enable)
+ setbits_le32(rcc + RCC_OCENSETR, mask_on);
+ else
+ setbits_le32(rcc + RCC_OCENCLRR, mask_on);
+}
+
+static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
+ u32 mask_rdy)
+{
+ u32 mask_test = 0;
+ u32 address = rcc + offset;
+ u32 val;
+ int ret;
+
+ if (enable)
+ mask_test = mask_rdy;
+
+ ret = readl_poll_timeout(address, val,
+ (val & mask_rdy) == mask_test,
+ TIMEOUT_1S);
+
+ if (ret)
+ pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
+ mask_rdy, address, enable, readl(address));
+
+ return ret;
+}
+
+static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int lsedrv)
+{
+ u32 value;
+
+ if (bypass)
+ setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
+
+ /*
+ * warning: not recommended to switch directly from "high drive"
+ * to "medium low drive", and vice-versa.
+ */
+ value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
+ >> RCC_BDCR_LSEDRV_SHIFT;
+
+ while (value != lsedrv) {
+ if (value > lsedrv)
+ value--;
+ else
+ value++;
+
+ clrsetbits_le32(rcc + RCC_BDCR,
+ RCC_BDCR_LSEDRV_MASK,
+ value << RCC_BDCR_LSEDRV_SHIFT);
+ }
+
+ stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
+}
+
+static void stm32mp1_lse_wait(fdt_addr_t rcc)
+{
+ stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
+}
+
+static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
+{
+ stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
+ stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
+}
+
+static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int css)
+{
+ if (bypass)
+ setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP);
+
+ stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
+ stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
+
+ if (css)
+ setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON);
+}
+
+static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
+{
+ stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION);
+ stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
+}
+
+static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
+{
+ stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
+ stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
+}
+
+static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
+{
+ u32 address = rcc + RCC_OCRDYR;
+ u32 val;
+ int ret;
+
+ clrsetbits_le32(rcc + RCC_HSICFGR,
+ RCC_HSICFGR_HSIDIV_MASK,
+ RCC_HSICFGR_HSIDIV_MASK & hsidiv);
+
+ ret = readl_poll_timeout(address, val,
+ val & RCC_OCRDYR_HSIDIVRDY,
+ TIMEOUT_200MS);
+ if (ret)
+ pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
+ address, readl(address));
+
+ return ret;
+}
+
+static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
+{
+ u8 hsidiv;
+ u32 hsidivfreq = MAX_HSI_HZ;
+
+ for (hsidiv = 0; hsidiv < 4; hsidiv++,
+ hsidivfreq = hsidivfreq / 2)
+ if (hsidivfreq == hsifreq)
+ break;
+
+ if (hsidiv == 4) {
+ pr_err("clk-hsi frequency invalid");
+ return -1;
+ }
+
+ if (hsidiv > 0)
+ return stm32mp1_set_hsidiv(rcc, hsidiv);
+
+ return 0;
+}
+
+static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
+{
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+
+ writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr);
+}
+
+static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
+{
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ u32 pllxcr = priv->base + pll[pll_id].pllxcr;
+ u32 val;
+ int ret;
+
+ ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
+ TIMEOUT_200MS);
+
+ if (ret) {
+ pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
+ pll_id, pllxcr, readl(pllxcr));
+ return ret;
+ }
+
+ /* start the requested output */
+ setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
+
+ return 0;
+}
+
+static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
+{
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ u32 pllxcr = priv->base + pll[pll_id].pllxcr;
+ u32 val;
+
+ /* stop all output */
+ clrbits_le32(pllxcr,
+ RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
+
+ /* stop PLL */
+ clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
+
+ /* wait PLL stopped */
+ return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
+ TIMEOUT_200MS);
+}
+
+static void pll_config_output(struct stm32mp1_clk_priv *priv,
+ int pll_id, u32 *pllcfg)
+{
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ fdt_addr_t rcc = priv->base;
+ u32 value;
+
+ value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
+ & RCC_PLLNCFGR2_DIVP_MASK;
+ value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
+ & RCC_PLLNCFGR2_DIVQ_MASK;
+ value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
+ & RCC_PLLNCFGR2_DIVR_MASK;
+ writel(value, rcc + pll[pll_id].pllxcfgr2);
+}
+
+static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
+ u32 *pllcfg, u32 fracv)
+{
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ fdt_addr_t rcc = priv->base;
+ enum stm32mp1_plltype type = pll[pll_id].plltype;
+ int src;
+ ulong refclk;
+ u8 ifrge = 0;
+ u32 value;
+
+ src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
+
+ refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
+ (pllcfg[PLLCFG_M] + 1);
+
+ if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
+ refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
+ debug("invalid refclk = %x\n", (u32)refclk);
+ return -EINVAL;
+ }
+ if (type == PLL_800 && refclk >= 8000000)
+ ifrge = 1;
+
+ value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
+ & RCC_PLLNCFGR1_DIVN_MASK;
+ value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
+ & RCC_PLLNCFGR1_DIVM_MASK;
+ value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
+ & RCC_PLLNCFGR1_IFRGE_MASK;
+ writel(value, rcc + pll[pll_id].pllxcfgr1);
+
+ /* fractional configuration: load sigma-delta modulator (SDM) */
+
+ /* Write into FRACV the new fractional value , and FRACLE to 0 */
+ writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
+ rcc + pll[pll_id].pllxfracr);
+
+ /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
+ setbits_le32(rcc + pll[pll_id].pllxfracr,
+ RCC_PLLNFRACR_FRACLE);
+
+ pll_config_output(priv, pll_id, pllcfg);
+
+ return 0;
+}
+
+static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
+{
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ u32 pllxcsg;
+
+ pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
+ RCC_PLLNCSGR_MOD_PER_MASK) |
+ ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
+ RCC_PLLNCSGR_INC_STEP_MASK) |
+ ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
+ RCC_PLLNCSGR_SSCG_MODE_MASK);
+
+ writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
+}
+
+static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
+{
+ u32 address = priv->base + (clksrc >> 4);
+ u32 val;
+ int ret;
+
+ clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
+ ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
+ TIMEOUT_200MS);
+ if (ret)
+ pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
+ clksrc, address, readl(address));
+
+ return ret;
+}
+
+static int set_clkdiv(unsigned int clkdiv, u32 address)
+{
+ u32 val;
+ int ret;
+
+ clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
+ ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
+ TIMEOUT_200MS);
+ if (ret)
+ pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
+ clkdiv, address, readl(address));
+
+ return ret;
+}
+
+static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
+ u32 clksrc, u32 clkdiv)
+{
+ u32 address = priv->base + (clksrc >> 4);
+
+ /*
+ * binding clksrc : bit15-4 offset
+ * bit3: disable
+ * bit2-0: MCOSEL[2:0]
+ */
+ if (clksrc & 0x8) {
+ clrbits_le32(address, RCC_MCOCFG_MCOON);
+ } else {
+ clrsetbits_le32(address,
+ RCC_MCOCFG_MCOSRC_MASK,
+ clksrc & RCC_MCOCFG_MCOSRC_MASK);
+ clrsetbits_le32(address,
+ RCC_MCOCFG_MCODIV_MASK,
+ clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
+ setbits_le32(address, RCC_MCOCFG_MCOON);
+ }
+}
+
+static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
+ unsigned int clksrc,
+ int lse_css)
+{
+ u32 address = priv->base + RCC_BDCR;
+
+ if (readl(address) & RCC_BDCR_RTCCKEN)
+ goto skip_rtc;
+
+ if (clksrc == CLK_RTC_DISABLED)
+ goto skip_rtc;
+
+ clrsetbits_le32(address,
+ RCC_BDCR_RTCSRC_MASK,
+ clksrc << RCC_BDCR_RTCSRC_SHIFT);
+
+ setbits_le32(address, RCC_BDCR_RTCCKEN);
+
+skip_rtc:
+ if (lse_css)
+ setbits_le32(address, RCC_BDCR_LSECSSON);
+}
+
+static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
+{
+ u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
+ u32 value = pkcs & 0xF;
+ u32 mask = 0xF;
+
+ if (pkcs & BIT(31)) {
+ mask <<= 4;
+ value <<= 4;
+ }
+ clrsetbits_le32(address, mask, value);
+}
+
+static int stm32mp1_clktree(struct udevice *dev)
+{
+ struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
+ fdt_addr_t rcc = priv->base;
+ unsigned int clksrc[CLKSRC_NB];
+ unsigned int clkdiv[CLKDIV_NB];
+ unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
+ ofnode plloff[_PLL_NB];
+ int ret;
+ int i, len;
+ int lse_css = 0;
+ const u32 *pkcs_cell;
+
+ /* check mandatory field */
+ ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
+ if (ret < 0) {
+ debug("field st,clksrc invalid: error %d\n", ret);
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
+ if (ret < 0) {
+ debug("field st,clkdiv invalid: error %d\n", ret);
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ /* check mandatory field in each pll */
+ for (i = 0; i < _PLL_NB; i++) {
+ char name[12];
+
+ sprintf(name, "st,pll@%d", i);
+ plloff[i] = dev_read_subnode(dev, name);
+ if (!ofnode_valid(plloff[i]))
+ continue;
+ ret = ofnode_read_u32_array(plloff[i], "cfg",
+ pllcfg[i], PLLCFG_NB);
+ if (ret < 0) {
+ debug("field cfg invalid: error %d\n", ret);
+ return -FDT_ERR_NOTFOUND;
+ }
+ }
+
+ debug("configuration MCO\n");
+ stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
+ stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
+
+ debug("switch ON osillator\n");
+ /*
+ * switch ON oscillator found in device-tree,
+ * HSI already ON after bootrom
+ */
+ if (priv->osc[_LSI])
+ stm32mp1_lsi_set(rcc, 1);
+
+ if (priv->osc[_LSE]) {
+ int bypass;
+ int lsedrv;
+ struct udevice *dev = priv->osc_dev[_LSE];
+
+ bypass = dev_read_bool(dev, "st,bypass");
+ lse_css = dev_read_bool(dev, "st,css");
+ lsedrv = dev_read_u32_default(dev, "st,drive",
+ LSEDRV_MEDIUM_HIGH);
+
+ stm32mp1_lse_enable(rcc, bypass, lsedrv);
+ }
+
+ if (priv->osc[_HSE]) {
+ int bypass, css;
+ struct udevice *dev = priv->osc_dev[_HSE];
+
+ bypass = dev_read_bool(dev, "st,bypass");
+ css = dev_read_bool(dev, "st,css");
+
+ stm32mp1_hse_enable(rcc, bypass, css);
+ }
+ /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
+ * => switch on CSI even if node is not present in device tree
+ */
+ stm32mp1_csi_set(rcc, 1);
+
+ /* come back to HSI */
+ debug("come back to HSI\n");
+ set_clksrc(priv, CLK_MPU_HSI);
+ set_clksrc(priv, CLK_AXI_HSI);
+ set_clksrc(priv, CLK_MCU_HSI);
+
+ debug("pll stop\n");
+ for (i = 0; i < _PLL_NB; i++)
+ pll_stop(priv, i);
+
+ /* configure HSIDIV */
+ debug("configure HSIDIV\n");
+ if (priv->osc[_HSI])
+ stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
+
+ /* select DIV */
+ debug("select DIV\n");
+ /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
+ writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
+ set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
+ set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
+ set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
+ set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
+ set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
+ set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
+ set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
+
+ /* no ready bit for RTC */
+ writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
+
+ /* configure PLLs source */
+ debug("configure PLLs source\n");
+ set_clksrc(priv, clksrc[CLKSRC_PLL12]);
+ set_clksrc(priv, clksrc[CLKSRC_PLL3]);
+ set_clksrc(priv, clksrc[CLKSRC_PLL4]);
+
+ /* configure and start PLLs */
+ debug("configure PLLs\n");
+ for (i = 0; i < _PLL_NB; i++) {
+ u32 fracv;
+ u32 csg[PLLCSG_NB];
+
+ debug("configure PLL %d @ %d\n", i,
+ ofnode_to_offset(plloff[i]));
+ if (!ofnode_valid(plloff[i]))
+ continue;
+
+ fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
+ pll_config(priv, i, pllcfg[i], fracv);
+ ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
+ if (!ret) {
+ pll_csg(priv, i, csg);
+ } else if (ret != -FDT_ERR_NOTFOUND) {
+ debug("invalid csg node for pll@%d res=%d\n", i, ret);
+ return ret;
+ }
+ pll_start(priv, i);
+ }
+
+ /* wait and start PLLs ouptut when ready */
+ for (i = 0; i < _PLL_NB; i++) {
+ if (!ofnode_valid(plloff[i]))
+ continue;
+ debug("output PLL %d\n", i);
+ pll_output(priv, i, pllcfg[i][PLLCFG_O]);
+ }
+
+ /* wait LSE ready before to use it */
+ if (priv->osc[_LSE])
+ stm32mp1_lse_wait(rcc);
+
+ /* configure with expected clock source */
+ debug("CLKSRC\n");
+ set_clksrc(priv, clksrc[CLKSRC_MPU]);
+ set_clksrc(priv, clksrc[CLKSRC_AXI]);
+ set_clksrc(priv, clksrc[CLKSRC_MCU]);
+ set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
+
+ /* configure PKCK */
+ debug("PKCK\n");
+ pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
+ if (pkcs_cell) {
+ bool ckper_disabled = false;
+
+ for (i = 0; i < len / sizeof(u32); i++) {
+ u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
+
+ if (pkcs == CLK_CKPER_DISABLED) {
+ ckper_disabled = true;
+ continue;
+ }
+ pkcs_config(priv, pkcs);
+ }
+ /* CKPER is source for some peripheral clock
+ * (FMC-NAND / QPSI-NOR) and switching source is allowed
+ * only if previous clock is still ON
+ * => deactivated CKPER only after switching clock
+ */
+ if (ckper_disabled)
+ pkcs_config(priv, CLK_CKPER_DISABLED);
+ }
+
+ debug("oscillator off\n");
+ /* switch OFF HSI if not found in device-tree */
+ if (!priv->osc[_HSI])
+ stm32mp1_hsi_set(rcc, 0);
+
+ /* Software Self-Refresh mode (SSR) during DDR initilialization */
+ clrsetbits_le32(priv->base + RCC_DDRITFCR,
+ RCC_DDRITFCR_DDRCKMOD_MASK,
+ RCC_DDRITFCR_DDRCKMOD_SSR <<
+ RCC_DDRITFCR_DDRCKMOD_SHIFT);
+
+ return 0;
+}
+#endif /* STM32MP1_CLOCK_TREE_INIT */
+
+static void stm32mp1_osc_clk_init(const char *name,
+ struct stm32mp1_clk_priv *priv,
+ int index)
+{
+ struct clk clk;
+ struct udevice *dev = NULL;
+
+ priv->osc[index] = 0;
+ clk.id = 0;
+ if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
+ if (clk_request(dev, &clk))
+ pr_err("%s request", name);
+ else
+ priv->osc[index] = clk_get_rate(&clk);
+ }
+ priv->osc_dev[index] = dev;
+}
+
+static void stm32mp1_osc_init(struct udevice *dev)
+{
+ struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
+ int i;
+ const char *name[NB_OSC] = {
+ [_LSI] = "clk-lsi",
+ [_LSE] = "clk-lse",
+ [_HSI] = "clk-hsi",
+ [_HSE] = "clk-hse",
+ [_CSI] = "clk-csi",
+ [_I2S_CKIN] = "i2s_ckin",
+ [_USB_PHY_48] = "ck_usbo_48m"};
+
+ for (i = 0; i < NB_OSC; i++) {
+ stm32mp1_osc_clk_init(name[i], priv, i);
+ debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
+ }
+}
+
+static int stm32mp1_clk_probe(struct udevice *dev)
+{
+ int result = 0;
+ struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr(dev->parent);
+ if (priv->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->data = (void *)&stm32mp1_data;
+
+ if (!priv->data->gate || !priv->data->sel ||
+ !priv->data->pll)
+ return -EINVAL;
+
+ stm32mp1_osc_init(dev);
+
+#ifdef STM32MP1_CLOCK_TREE_INIT
+ /* clock tree init is done only one time, before relocation */
+ if (!(gd->flags & GD_FLG_RELOC))
+ result = stm32mp1_clktree(dev);
+#endif
+
+ return result;
+}
+
+static const struct clk_ops stm32mp1_clk_ops = {
+ .enable = stm32mp1_clk_enable,
+ .disable = stm32mp1_clk_disable,
+ .get_rate = stm32mp1_clk_get_rate,
+};
+
+static const struct udevice_id stm32mp1_clk_ids[] = {
+ { .compatible = "st,stm32mp1-rcc-clk" },
+ { }
+};
+
+U_BOOT_DRIVER(stm32mp1_clock) = {
+ .name = "stm32mp1_clk",
+ .id = UCLASS_CLK,
+ .of_match = stm32mp1_clk_ids,
+ .ops = &stm32mp1_clk_ops,
+ .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
+ .probe = stm32mp1_clk_probe,
+};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index cc75aec..b7e4ffb 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -234,7 +234,7 @@
config STM32F7_GPIO
bool "ST STM32 GPIO driver"
- depends on DM_GPIO && STM32
+ depends on DM_GPIO && (STM32 || ARCH_STM32MP)
default y
help
Device model driver support for STM32 GPIO controller. It should be
diff --git a/drivers/gpio/stm32f7_gpio.c b/drivers/gpio/stm32f7_gpio.c
index a7cfb8c..376e86c 100644
--- a/drivers/gpio/stm32f7_gpio.c
+++ b/drivers/gpio/stm32f7_gpio.c
@@ -16,14 +16,11 @@
#include <linux/errno.h>
#include <linux/io.h>
-#define MAX_SIZE_BANK_NAME 5
#define STM32_GPIOS_PER_BANK 16
#define MODE_BITS(gpio_pin) (gpio_pin * 2)
#define MODE_BITS_MASK 3
#define IN_OUT_BIT_INDEX(gpio_pin) (1UL << (gpio_pin))
-DECLARE_GLOBAL_DATA_PTR;
-
static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
@@ -82,21 +79,19 @@
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct stm32_gpio_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
- char *name;
+ const char *name;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->regs = (struct stm32_gpio_regs *)addr;
- name = (char *)fdtdec_locate_byte_array(gd->fdt_blob,
- dev_of_offset(dev),
- "st,bank-name",
- MAX_SIZE_BANK_NAME);
+ name = dev_read_string(dev, "st,bank-name");
if (!name)
return -EINVAL;
uc_priv->bank_name = name;
- uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
+ uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios",
+ STM32_GPIOS_PER_BANK);
debug("%s, addr = 0x%p, bank_name = %s\n", __func__, (u32 *)priv->regs,
uc_priv->bank_name);
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 932abd3..3299ef0 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -207,7 +207,7 @@
config SYS_I2C_STM32F7
bool "STMicroelectronics STM32F7 I2C support"
- depends on (STM32F7 || STM32H7) && DM_I2C
+ depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C
help
Enable this option to add support for STM32 I2C controller
introduced with STM32F7/H7 SoCs. This I2C controller supports :
diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c
index 8662487..81f061a 100644
--- a/drivers/i2c/stm32f7_i2c.c
+++ b/drivers/i2c/stm32f7_i2c.c
@@ -533,7 +533,7 @@
if (((sdadel >= sdadel_min) &&
(sdadel <= sdadel_max)) &&
(p != p_prev)) {
- v = kmalloc(sizeof(*v), GFP_KERNEL);
+ v = calloc(1, sizeof(*v));
if (!v)
return -ENOMEM;
@@ -689,7 +689,7 @@
/* Release list and memory */
list_for_each_entry_safe(v, _v, &solutions, node) {
list_del(&v->node);
- kfree(v);
+ free(v);
}
return ret;
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 9f7d9d6..332d905 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -57,7 +57,6 @@
obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
obj-$(CONFIG_NAND_MXS) += mxs_nand.o
-obj-$(CONFIG_NAND_NDFC) += ndfc.o
obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o
obj-$(CONFIG_NAND_SPEAR) += spr_nand.o
obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
diff --git a/drivers/mtd/nand/nand_ecc.c b/drivers/mtd/nand/nand_ecc.c
index 8b548b2..13a6535 100644
--- a/drivers/mtd/nand/nand_ecc.c
+++ b/drivers/mtd/nand/nand_ecc.c
@@ -29,11 +29,6 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand_ecc.h>
-/* The PPC4xx NDFC uses Smart Media (SMC) bytes order */
-#ifdef CONFIG_NAND_NDFC
-#define CONFIG_MTD_NAND_ECC_SMC
-#endif
-
/*
* NAND-SPL has no sofware ECC for now, so don't include nand_calculate_ecc(),
* only nand_correct_data() is needed
@@ -110,13 +105,8 @@
tmp2 |= (reg2 & 0x01) << 0; /* B7 -> B0 */
/* Calculate final ECC code */
-#ifdef CONFIG_MTD_NAND_ECC_SMC
- ecc_code[0] = ~tmp2;
- ecc_code[1] = ~tmp1;
-#else
ecc_code[0] = ~tmp1;
ecc_code[1] = ~tmp2;
-#endif
ecc_code[2] = ((~reg1) << 2) | 0x03;
return 0;
@@ -146,15 +136,9 @@
{
uint8_t s0, s1, s2;
-#ifdef CONFIG_MTD_NAND_ECC_SMC
- s0 = calc_ecc[0] ^ read_ecc[0];
- s1 = calc_ecc[1] ^ read_ecc[1];
- s2 = calc_ecc[2] ^ read_ecc[2];
-#else
s1 = calc_ecc[0] ^ read_ecc[0];
s0 = calc_ecc[1] ^ read_ecc[1];
s2 = calc_ecc[2] ^ read_ecc[2];
-#endif
if ((s0 | s1 | s2) == 0)
return 0;
diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
deleted file mode 100644
index 0a9849e..0000000
--- a/drivers/mtd/nand/ndfc.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * Overview:
- * Platform independent driver for NDFC (NanD Flash Controller)
- * integrated into IBM/AMCC PPC4xx cores
- *
- * (C) Copyright 2006-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Based on original work by
- * Thomas Gleixner
- * Copyright 2006 IBM
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <nand.h>
-#include <linux/mtd/ndfc.h>
-#include <linux/mtd/nand_ecc.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx.h>
-
-#ifndef CONFIG_SYS_NAND_BCR
-#define CONFIG_SYS_NAND_BCR 0x80002222
-#endif
-#ifndef CONFIG_SYS_NDFC_EBC0_CFG
-#define CONFIG_SYS_NDFC_EBC0_CFG 0xb8400000
-#endif
-
-/*
- * We need to store the info, which chip-select (CS) is used for the
- * chip number. For example on Sequoia NAND chip #0 uses
- * CS #3.
- */
-static int ndfc_cs[NDFC_MAX_BANKS];
-
-static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd_to_nand(mtd);
- ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
-
- if (cmd == NAND_CMD_NONE)
- return;
-
- if (ctrl & NAND_CLE)
- out_8((u8 *)(base + NDFC_CMD), cmd & 0xFF);
- else
- out_8((u8 *)(base + NDFC_ALE), cmd & 0xFF);
-}
-
-static int ndfc_dev_ready(struct mtd_info *mtdinfo)
-{
- struct nand_chip *this = mtd_to_nand(mtdinfo);
- ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
-
- return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY);
-}
-
-static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
-{
- struct nand_chip *this = mtd_to_nand(mtdinfo);
- ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
- u32 ccr;
-
- ccr = in_be32((u32 *)(base + NDFC_CCR));
- ccr |= NDFC_CCR_RESET_ECC;
- out_be32((u32 *)(base + NDFC_CCR), ccr);
-}
-
-static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
- const u_char *dat, u_char *ecc_code)
-{
- struct nand_chip *this = mtd_to_nand(mtdinfo);
- ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
- u32 ecc;
- u8 *p = (u8 *)&ecc;
-
- ecc = in_be32((u32 *)(base + NDFC_ECC));
-
- /* The NDFC uses Smart Media (SMC) bytes order
- */
- ecc_code[0] = p[1];
- ecc_code[1] = p[2];
- ecc_code[2] = p[3];
-
- return 0;
-}
-
-/*
- * Speedups for buffer read/write/verify
- *
- * NDFC allows 32bit read/write of data. So we can speed up the buffer
- * functions. No further checking, as nand_base will always read/write
- * page aligned.
- */
-static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
-{
- struct nand_chip *this = mtd_to_nand(mtdinfo);
- ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
- uint32_t *p = (uint32_t *) buf;
-
- for (;len > 0; len -= 4)
- *p++ = in_be32((u32 *)(base + NDFC_DATA));
-}
-
-/*
- * Don't use these speedup functions in NAND boot image, since the image
- * has to fit into 4kByte.
- */
-static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
-{
- struct nand_chip *this = mtd_to_nand(mtdinfo);
- ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
- uint32_t *p = (uint32_t *) buf;
-
- for (; len > 0; len -= 4)
- out_be32((u32 *)(base + NDFC_DATA), *p++);
-}
-
-/*
- * Read a byte from the NDFC.
- */
-static uint8_t ndfc_read_byte(struct mtd_info *mtd)
-{
-
- struct nand_chip *chip = mtd_to_nand(mtd);
-
-#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
- return (uint8_t) readw(chip->IO_ADDR_R);
-#else
- return readb(chip->IO_ADDR_R);
-#endif
-
-}
-
-void board_nand_select_device(struct nand_chip *nand, int chip)
-{
- /*
- * Don't use "chip" to address the NAND device,
- * generate the cs from the address where it is encoded.
- */
- ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
- int cs = ndfc_cs[chip];
-
- /* Set NandFlash Core Configuration Register */
- /* 1 col x 2 rows */
- out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24));
- out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CONFIG_SYS_NAND_BCR);
-}
-
-static void ndfc_select_chip(struct mtd_info *mtd, int chip)
-{
- /*
- * Nothing to do here!
- */
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
- ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
- static int chip = 0;
-
- /*
- * Save chip-select for this chip #
- */
- ndfc_cs[chip] = cs;
-
- /*
- * Select required NAND chip in NDFC
- */
- board_nand_select_device(nand, chip);
-
- nand->IO_ADDR_R = (void __iomem *)(base + NDFC_DATA);
- nand->IO_ADDR_W = (void __iomem *)(base + NDFC_DATA);
- nand->cmd_ctrl = ndfc_hwcontrol;
- nand->chip_delay = 50;
- nand->read_buf = ndfc_read_buf;
- nand->dev_ready = ndfc_dev_ready;
- nand->ecc.correct = nand_correct_data;
- nand->ecc.hwctl = ndfc_enable_hwecc;
- nand->ecc.calculate = ndfc_calculate_ecc;
- nand->ecc.mode = NAND_ECC_HW;
- nand->ecc.size = 256;
- nand->ecc.bytes = 3;
- nand->ecc.strength = 1;
- nand->select_chip = ndfc_select_chip;
-
-#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
- nand->options |= NAND_BUSWIDTH_16;
-#endif
-
- nand->write_buf = ndfc_write_buf;
- nand->read_byte = ndfc_read_byte;
-
- chip++;
-
- return 0;
-}
diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index 2066e11..31285cd 100644
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -41,9 +41,10 @@
return 0;
}
+
static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
{
- gpio_dsc->port = (port_pin & 0xF000) >> 12;
+ gpio_dsc->port = (port_pin & 0x1F000) >> 12;
gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
gpio_dsc->pin);
@@ -115,11 +116,13 @@
return -EINVAL;
for (i = 0; i < len; i++) {
struct gpio_desc desc;
+
debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
rv = uclass_get_device_by_seq(UCLASS_GPIO,
- gpio_dsc.port, &desc.dev);
+ gpio_dsc.port,
+ &desc.dev);
if (rv)
return rv;
desc.offset = gpio_dsc.pin;
@@ -186,6 +189,8 @@
{ .compatible = "st,stm32f469-pinctrl" },
{ .compatible = "st,stm32f746-pinctrl" },
{ .compatible = "st,stm32h743-pinctrl" },
+ { .compatible = "st,stm32mp157-pinctrl" },
+ { .compatible = "st,stm32mp157-z-pinctrl" },
{ }
};
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index d8c107e..1a38524 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -22,6 +22,7 @@
config AXP152_POWER
bool "axp152 pmic support"
depends on MACH_SUN5I
+ select AXP_PMIC_BUS
select CMD_POWEROFF
---help---
Select this to enable support for the axp152 pmic found on most
@@ -30,6 +31,7 @@
config AXP209_POWER
bool "axp209 pmic support"
depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
+ select AXP_PMIC_BUS
select CMD_POWEROFF
---help---
Select this to enable support for the axp209 pmic found on most
@@ -38,6 +40,7 @@
config AXP221_POWER
bool "axp221 / axp223 pmic support"
depends on MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40
+ select AXP_PMIC_BUS
select CMD_POWEROFF
---help---
Select this to enable support for the axp221/axp223 pmic found on most
@@ -46,6 +49,7 @@
config AXP809_POWER
bool "axp809 pmic support"
depends on MACH_SUN9I
+ select AXP_PMIC_BUS
select CMD_POWEROFF
---help---
Say y here to enable support for the axp809 pmic found on A80 boards.
@@ -53,6 +57,7 @@
config AXP818_POWER
bool "axp818 pmic support"
depends on MACH_SUN8I_A83T
+ select AXP_PMIC_BUS
select CMD_POWEROFF
---help---
Say y here to enable support for the axp818 pmic found on
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 5d49c93..40ab9f7 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -209,3 +209,11 @@
The TPS65910 is a PMIC containing 3 buck DC-DC converters, one boost
DC-DC converter, 8 LDOs and a RTC. This driver binds the SMPS and LDO
pmic children.
+
+config PMIC_STPMU1
+ bool "Enable support for STMicroelectronics STPMU1 PMIC"
+ depends on DM_PMIC && DM_I2C
+ ---help---
+ The STPMU1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches.
+ It is accessed via an I2C interface. The device is used with STM32MP1
+ SoCs. This driver implements register read/write operations.
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index fc19fdc..ad32068 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -23,6 +23,7 @@
obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o
obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o
obj-$(CONFIG_$(SPL_)PMIC_LP87565) += lp87565.o
+obj-$(CONFIG_PMIC_STPMU1) += stpmu1.o
obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o
diff --git a/drivers/power/pmic/stpmu1.c b/drivers/power/pmic/stpmu1.c
new file mode 100644
index 0000000..4615365
--- /dev/null
+++ b/drivers/power/pmic/stpmu1.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/stpmu1.h>
+
+#define STMPU1_NUM_OF_REGS 0x100
+
+static int stpmu1_reg_count(struct udevice *dev)
+{
+ return STMPU1_NUM_OF_REGS;
+}
+
+static int stpmu1_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
+{
+ int ret;
+
+ ret = dm_i2c_write(dev, reg, buff, len);
+ if (ret)
+ dev_err(dev, "%s: failed to write register %#x :%d",
+ __func__, reg, ret);
+
+ return ret;
+}
+
+static int stpmu1_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+ int ret;
+
+ ret = dm_i2c_read(dev, reg, buff, len);
+ if (ret)
+ dev_err(dev, "%s: failed to read register %#x : %d",
+ __func__, reg, ret);
+
+ return ret;
+}
+
+static struct dm_pmic_ops stpmu1_ops = {
+ .reg_count = stpmu1_reg_count,
+ .read = stpmu1_read,
+ .write = stpmu1_write,
+};
+
+static const struct udevice_id stpmu1_ids[] = {
+ { .compatible = "st,stpmu1" },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_stpmu1) = {
+ .name = "stpmu1_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = stpmu1_ids,
+ .ops = &stpmu1_ops,
+};
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 47969f3..496e2b7 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -33,3 +33,5 @@
STM32F7 family devices support flexible memory controller(FMC) to
support external memories like sdram, psram & nand.
This driver is for the sdram memory interface with the FMC.
+
+source "drivers/ram/stm32mp1/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 51ae6be..3820d03 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -6,6 +6,7 @@
#
obj-$(CONFIG_RAM) += ram-uclass.o
obj-$(CONFIG_SANDBOX) += sandbox_ram.o
+obj-$(CONFIG_STM32MP1_DDR) += stm32mp1/
obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o
obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
diff --git a/drivers/ram/stm32mp1/Kconfig b/drivers/ram/stm32mp1/Kconfig
new file mode 100644
index 0000000..b9c8166
--- /dev/null
+++ b/drivers/ram/stm32mp1/Kconfig
@@ -0,0 +1,12 @@
+
+config STM32MP1_DDR
+ bool "STM32MP1 DDR driver"
+ depends on DM && OF_CONTROL && ARCH_STM32MP
+ select RAM
+ select SPL_RAM if SPL
+ default y
+ help
+ activate STM32MP1 DDR controller driver for STM32MP1 soc
+ family: support for LPDDR2, LPDDR3 and DDR3
+ the SDRAM parameters for controleur and phy need to be provided
+ in device tree (computed by DDR tuning tools)
diff --git a/drivers/ram/stm32mp1/Makefile b/drivers/ram/stm32mp1/Makefile
new file mode 100644
index 0000000..9f05cd4
--- /dev/null
+++ b/drivers/ram/stm32mp1/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+#
+
+obj-y += stm32mp1_ram.o
+obj-y += stm32mp1_ddr.o
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c
new file mode 100644
index 0000000..ffe50d9
--- /dev/null
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c
@@ -0,0 +1,496 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <ram.h>
+#include <reset.h>
+#include <timer.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <linux/iopoll.h>
+#include "stm32mp1_ddr.h"
+#include "stm32mp1_ddr_regs.h"
+
+#define RCC_DDRITFCR 0xD8
+
+#define RCC_DDRITFCR_DDRCAPBRST (BIT(14))
+#define RCC_DDRITFCR_DDRCAXIRST (BIT(15))
+#define RCC_DDRITFCR_DDRCORERST (BIT(16))
+#define RCC_DDRITFCR_DPHYAPBRST (BIT(17))
+#define RCC_DDRITFCR_DPHYRST (BIT(18))
+#define RCC_DDRITFCR_DPHYCTLRST (BIT(19))
+
+struct reg_desc {
+ const char *name;
+ u16 offset; /* offset for base address */
+ u8 par_offset; /* offset for parameter array */
+};
+
+#define INVALID_OFFSET 0xFF
+
+#define DDRCTL_REG(x, y) \
+ {#x,\
+ offsetof(struct stm32mp1_ddrctl, x),\
+ offsetof(struct y, x)}
+
+#define DDRPHY_REG(x, y) \
+ {#x,\
+ offsetof(struct stm32mp1_ddrphy, x),\
+ offsetof(struct y, x)}
+
+#define DDRCTL_REG_REG(x) DDRCTL_REG(x, stm32mp1_ddrctrl_reg)
+static const struct reg_desc ddr_reg[] = {
+ DDRCTL_REG_REG(mstr),
+ DDRCTL_REG_REG(mrctrl0),
+ DDRCTL_REG_REG(mrctrl1),
+ DDRCTL_REG_REG(derateen),
+ DDRCTL_REG_REG(derateint),
+ DDRCTL_REG_REG(pwrctl),
+ DDRCTL_REG_REG(pwrtmg),
+ DDRCTL_REG_REG(hwlpctl),
+ DDRCTL_REG_REG(rfshctl0),
+ DDRCTL_REG_REG(rfshctl3),
+ DDRCTL_REG_REG(crcparctl0),
+ DDRCTL_REG_REG(zqctl0),
+ DDRCTL_REG_REG(dfitmg0),
+ DDRCTL_REG_REG(dfitmg1),
+ DDRCTL_REG_REG(dfilpcfg0),
+ DDRCTL_REG_REG(dfiupd0),
+ DDRCTL_REG_REG(dfiupd1),
+ DDRCTL_REG_REG(dfiupd2),
+ DDRCTL_REG_REG(dfiphymstr),
+ DDRCTL_REG_REG(odtmap),
+ DDRCTL_REG_REG(dbg0),
+ DDRCTL_REG_REG(dbg1),
+ DDRCTL_REG_REG(dbgcmd),
+ DDRCTL_REG_REG(poisoncfg),
+ DDRCTL_REG_REG(pccfg),
+};
+
+#define DDRCTL_REG_TIMING(x) DDRCTL_REG(x, stm32mp1_ddrctrl_timing)
+static const struct reg_desc ddr_timing[] = {
+ DDRCTL_REG_TIMING(rfshtmg),
+ DDRCTL_REG_TIMING(dramtmg0),
+ DDRCTL_REG_TIMING(dramtmg1),
+ DDRCTL_REG_TIMING(dramtmg2),
+ DDRCTL_REG_TIMING(dramtmg3),
+ DDRCTL_REG_TIMING(dramtmg4),
+ DDRCTL_REG_TIMING(dramtmg5),
+ DDRCTL_REG_TIMING(dramtmg6),
+ DDRCTL_REG_TIMING(dramtmg7),
+ DDRCTL_REG_TIMING(dramtmg8),
+ DDRCTL_REG_TIMING(dramtmg14),
+ DDRCTL_REG_TIMING(odtcfg),
+};
+
+#define DDRCTL_REG_MAP(x) DDRCTL_REG(x, stm32mp1_ddrctrl_map)
+static const struct reg_desc ddr_map[] = {
+ DDRCTL_REG_MAP(addrmap1),
+ DDRCTL_REG_MAP(addrmap2),
+ DDRCTL_REG_MAP(addrmap3),
+ DDRCTL_REG_MAP(addrmap4),
+ DDRCTL_REG_MAP(addrmap5),
+ DDRCTL_REG_MAP(addrmap6),
+ DDRCTL_REG_MAP(addrmap9),
+ DDRCTL_REG_MAP(addrmap10),
+ DDRCTL_REG_MAP(addrmap11),
+};
+
+#define DDRCTL_REG_PERF(x) DDRCTL_REG(x, stm32mp1_ddrctrl_perf)
+static const struct reg_desc ddr_perf[] = {
+ DDRCTL_REG_PERF(sched),
+ DDRCTL_REG_PERF(sched1),
+ DDRCTL_REG_PERF(perfhpr1),
+ DDRCTL_REG_PERF(perflpr1),
+ DDRCTL_REG_PERF(perfwr1),
+ DDRCTL_REG_PERF(pcfgr_0),
+ DDRCTL_REG_PERF(pcfgw_0),
+ DDRCTL_REG_PERF(pcfgqos0_0),
+ DDRCTL_REG_PERF(pcfgqos1_0),
+ DDRCTL_REG_PERF(pcfgwqos0_0),
+ DDRCTL_REG_PERF(pcfgwqos1_0),
+ DDRCTL_REG_PERF(pcfgr_1),
+ DDRCTL_REG_PERF(pcfgw_1),
+ DDRCTL_REG_PERF(pcfgqos0_1),
+ DDRCTL_REG_PERF(pcfgqos1_1),
+ DDRCTL_REG_PERF(pcfgwqos0_1),
+ DDRCTL_REG_PERF(pcfgwqos1_1),
+};
+
+#define DDRPHY_REG_REG(x) DDRPHY_REG(x, stm32mp1_ddrphy_reg)
+static const struct reg_desc ddrphy_reg[] = {
+ DDRPHY_REG_REG(pgcr),
+ DDRPHY_REG_REG(aciocr),
+ DDRPHY_REG_REG(dxccr),
+ DDRPHY_REG_REG(dsgcr),
+ DDRPHY_REG_REG(dcr),
+ DDRPHY_REG_REG(odtcr),
+ DDRPHY_REG_REG(zq0cr1),
+ DDRPHY_REG_REG(dx0gcr),
+ DDRPHY_REG_REG(dx1gcr),
+ DDRPHY_REG_REG(dx2gcr),
+ DDRPHY_REG_REG(dx3gcr),
+};
+
+#define DDRPHY_REG_TIMING(x) DDRPHY_REG(x, stm32mp1_ddrphy_timing)
+static const struct reg_desc ddrphy_timing[] = {
+ DDRPHY_REG_TIMING(ptr0),
+ DDRPHY_REG_TIMING(ptr1),
+ DDRPHY_REG_TIMING(ptr2),
+ DDRPHY_REG_TIMING(dtpr0),
+ DDRPHY_REG_TIMING(dtpr1),
+ DDRPHY_REG_TIMING(dtpr2),
+ DDRPHY_REG_TIMING(mr0),
+ DDRPHY_REG_TIMING(mr1),
+ DDRPHY_REG_TIMING(mr2),
+ DDRPHY_REG_TIMING(mr3),
+};
+
+#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal)
+static const struct reg_desc ddrphy_cal[] = {
+ DDRPHY_REG_CAL(dx0dllcr),
+ DDRPHY_REG_CAL(dx0dqtr),
+ DDRPHY_REG_CAL(dx0dqstr),
+ DDRPHY_REG_CAL(dx1dllcr),
+ DDRPHY_REG_CAL(dx1dqtr),
+ DDRPHY_REG_CAL(dx1dqstr),
+ DDRPHY_REG_CAL(dx2dllcr),
+ DDRPHY_REG_CAL(dx2dqtr),
+ DDRPHY_REG_CAL(dx2dqstr),
+ DDRPHY_REG_CAL(dx3dllcr),
+ DDRPHY_REG_CAL(dx3dqtr),
+ DDRPHY_REG_CAL(dx3dqstr),
+};
+
+enum reg_type {
+ REG_REG,
+ REG_TIMING,
+ REG_PERF,
+ REG_MAP,
+ REGPHY_REG,
+ REGPHY_TIMING,
+ REGPHY_CAL,
+ REG_TYPE_NB
+};
+
+enum base_type {
+ DDR_BASE,
+ DDRPHY_BASE,
+ NONE_BASE
+};
+
+struct ddr_reg_info {
+ const char *name;
+ const struct reg_desc *desc;
+ u8 size;
+ enum base_type base;
+};
+
+#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal)
+
+const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = {
+[REG_REG] = {
+ "static", ddr_reg, ARRAY_SIZE(ddr_reg), DDR_BASE},
+[REG_TIMING] = {
+ "timing", ddr_timing, ARRAY_SIZE(ddr_timing), DDR_BASE},
+[REG_PERF] = {
+ "perf", ddr_perf, ARRAY_SIZE(ddr_perf), DDR_BASE},
+[REG_MAP] = {
+ "map", ddr_map, ARRAY_SIZE(ddr_map), DDR_BASE},
+[REGPHY_REG] = {
+ "static", ddrphy_reg, ARRAY_SIZE(ddrphy_reg), DDRPHY_BASE},
+[REGPHY_TIMING] = {
+ "timing", ddrphy_timing, ARRAY_SIZE(ddrphy_timing), DDRPHY_BASE},
+[REGPHY_CAL] = {
+ "cal", ddrphy_cal, ARRAY_SIZE(ddrphy_cal), DDRPHY_BASE},
+};
+
+const char *base_name[] = {
+ [DDR_BASE] = "ctl",
+ [DDRPHY_BASE] = "phy",
+};
+
+static u32 get_base_addr(const struct ddr_info *priv, enum base_type base)
+{
+ if (base == DDRPHY_BASE)
+ return (u32)priv->phy;
+ else
+ return (u32)priv->ctl;
+}
+
+static void set_reg(const struct ddr_info *priv,
+ enum reg_type type,
+ const void *param)
+{
+ unsigned int i;
+ unsigned int *ptr, value;
+ enum base_type base = ddr_registers[type].base;
+ u32 base_addr = get_base_addr(priv, base);
+ const struct reg_desc *desc = ddr_registers[type].desc;
+
+ debug("init %s\n", ddr_registers[type].name);
+ for (i = 0; i < ddr_registers[type].size; i++) {
+ ptr = (unsigned int *)(base_addr + desc[i].offset);
+ if (desc[i].par_offset == INVALID_OFFSET) {
+ pr_err("invalid parameter offset for %s", desc[i].name);
+ } else {
+ value = *((u32 *)((u32)param +
+ desc[i].par_offset));
+ writel(value, ptr);
+ debug("[0x%x] %s= 0x%08x\n",
+ (u32)ptr, desc[i].name, value);
+ }
+ }
+}
+
+static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
+{
+ u32 pgsr;
+ int ret;
+
+ ret = readl_poll_timeout(&phy->pgsr, pgsr,
+ pgsr & (DDRPHYC_PGSR_IDONE |
+ DDRPHYC_PGSR_DTERR |
+ DDRPHYC_PGSR_DTIERR |
+ DDRPHYC_PGSR_DFTERR |
+ DDRPHYC_PGSR_RVERR |
+ DDRPHYC_PGSR_RVEIRR),
+ 1000000);
+ debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n",
+ (u32)&phy->pgsr, pgsr, ret);
+}
+
+void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir)
+{
+ pir |= DDRPHYC_PIR_INIT;
+ writel(pir, &phy->pir);
+ debug("[0x%08x] pir = 0x%08x -> 0x%08x\n",
+ (u32)&phy->pir, pir, readl(&phy->pir));
+
+ /* need to wait 10 configuration clock before start polling */
+ udelay(10);
+
+ /* Wait DRAM initialization and Gate Training Evaluation complete */
+ ddrphy_idone_wait(phy);
+}
+
+/* start quasi dynamic register update */
+static void start_sw_done(struct stm32mp1_ddrctl *ctl)
+{
+ clrbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
+}
+
+/* wait quasi dynamic register update */
+static void wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
+{
+ int ret;
+ u32 swstat;
+
+ setbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
+
+ ret = readl_poll_timeout(&ctl->swstat, swstat,
+ swstat & DDRCTRL_SWSTAT_SW_DONE_ACK,
+ 1000000);
+ if (ret)
+ panic("Timeout initialising DRAM : DDR->swstat = %x\n",
+ swstat);
+
+ debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat);
+}
+
+/* wait quasi dynamic register update */
+static void wait_operating_mode(struct ddr_info *priv, int mode)
+{
+ u32 stat, val, mask, val2 = 0, mask2 = 0;
+ int ret;
+
+ mask = DDRCTRL_STAT_OPERATING_MODE_MASK;
+ val = mode;
+ /* self-refresh due to software => check also STAT.selfref_type */
+ if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) {
+ mask |= DDRCTRL_STAT_SELFREF_TYPE_MASK;
+ stat |= DDRCTRL_STAT_SELFREF_TYPE_SR;
+ } else if (mode == DDRCTRL_STAT_OPERATING_MODE_NORMAL) {
+ /* normal mode: handle also automatic self refresh */
+ mask2 = DDRCTRL_STAT_OPERATING_MODE_MASK |
+ DDRCTRL_STAT_SELFREF_TYPE_MASK;
+ val2 = DDRCTRL_STAT_OPERATING_MODE_SR |
+ DDRCTRL_STAT_SELFREF_TYPE_ASR;
+ }
+
+ ret = readl_poll_timeout(&priv->ctl->stat, stat,
+ ((stat & mask) == val) ||
+ (mask2 && ((stat & mask2) == val2)),
+ 1000000);
+
+ if (ret)
+ panic("Timeout DRAM : DDR->stat = %x\n", stat);
+
+ debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
+}
+
+void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
+{
+ start_sw_done(ctl);
+ /* quasi-dynamic register update*/
+ setbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
+ clrbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
+ clrbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
+ wait_sw_done_ack(ctl);
+}
+
+void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
+ u32 rfshctl3, u32 pwrctl)
+{
+ start_sw_done(ctl);
+ if (!(rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH))
+ clrbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
+ if (pwrctl & DDRCTRL_PWRCTL_POWERDOWN_EN)
+ setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
+ setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
+ wait_sw_done_ack(ctl);
+}
+
+/* board-specific DDR power initializations. */
+__weak int board_ddr_power_init(void)
+{
+ return 0;
+}
+
+__maybe_unused
+void stm32mp1_ddr_init(struct ddr_info *priv,
+ const struct stm32mp1_ddr_config *config)
+{
+ u32 pir;
+ int ret;
+
+ ret = board_ddr_power_init();
+
+ if (ret)
+ panic("ddr power init failed\n");
+
+ debug("name = %s\n", config->info.name);
+ debug("speed = %d MHz\n", config->info.speed);
+ debug("size = 0x%x\n", config->info.size);
+/*
+ * 1. Program the DWC_ddr_umctl2 registers
+ * 1.1 RESETS: presetn, core_ddrc_rstn, aresetn
+ */
+ /* Assert All DDR part */
+ setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
+ setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
+ setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
+ setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
+ setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
+ setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
+
+/* 1.2. start CLOCK */
+ if (stm32mp1_ddr_clk_enable(priv, config->info.speed))
+ panic("invalid DRAM clock : %d MHz\n",
+ config->info.speed);
+
+/* 1.3. deassert reset */
+ /* de-assert PHY rstn and ctl_rstn via DPHYRST and DPHYCTLRST */
+ clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
+ clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
+ /* De-assert presetn once the clocks are active
+ * and stable via DDRCAPBRST bit
+ */
+ clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
+
+/* 1.4. wait 4 cycles for synchronization */
+ asm(" nop");
+ asm(" nop");
+ asm(" nop");
+ asm(" nop");
+
+/* 1.5. initialize registers ddr_umctl2 */
+ /* Stop uMCTL2 before PHY is ready */
+ clrbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
+ debug("[0x%08x] dfimisc = 0x%08x\n",
+ (u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc));
+
+ set_reg(priv, REG_REG, &config->c_reg);
+ set_reg(priv, REG_TIMING, &config->c_timing);
+ set_reg(priv, REG_MAP, &config->c_map);
+
+ /* skip CTRL init, SDRAM init is done by PHY PUBL */
+ clrsetbits_le32(&priv->ctl->init0,
+ DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK,
+ DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL);
+
+ set_reg(priv, REG_PERF, &config->c_perf);
+
+/* 2. deassert reset signal core_ddrc_rstn, aresetn and presetn */
+ clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
+ clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
+ clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
+
+/* 3. start PHY init by accessing relevant PUBL registers
+ * (DXGCR, DCR, PTR*, MR*, DTPR*)
+ */
+ set_reg(priv, REGPHY_REG, &config->p_reg);
+ set_reg(priv, REGPHY_TIMING, &config->p_timing);
+ set_reg(priv, REGPHY_CAL, &config->p_cal);
+
+/* 4. Monitor PHY init status by polling PUBL register PGSR.IDONE
+ * Perform DDR PHY DRAM initialization and Gate Training Evaluation
+ */
+ ddrphy_idone_wait(priv->phy);
+
+/* 5. Indicate to PUBL that controller performs SDRAM initialization
+ * by setting PIR.INIT and PIR CTLDINIT and pool PGSR.IDONE
+ * DRAM init is done by PHY, init0.skip_dram.init = 1
+ */
+ pir = DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK | DDRPHYC_PIR_ZCAL |
+ DDRPHYC_PIR_ITMSRST | DDRPHYC_PIR_DRAMINIT | DDRPHYC_PIR_ICPC;
+
+ if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
+ pir |= DDRPHYC_PIR_DRAMRST; /* only for DDR3 */
+
+ stm32mp1_ddrphy_init(priv->phy, pir);
+
+/* 6. SET DFIMISC.dfi_init_complete_en to 1 */
+ /* Enable quasi-dynamic register programming*/
+ start_sw_done(priv->ctl);
+ setbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
+ wait_sw_done_ack(priv->ctl);
+
+/* 7. Wait for DWC_ddr_umctl2 to move to normal operation mode
+ * by monitoring STAT.operating_mode signal
+ */
+ /* wait uMCTL2 ready */
+
+ wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
+
+ debug("DDR DQS training : ");
+/* 8. Disable Auto refresh and power down by setting
+ * - RFSHCTL3.dis_au_refresh = 1
+ * - PWRCTL.powerdown_en = 0
+ * - DFIMISC.dfiinit_complete_en = 0
+ */
+ stm32mp1_refresh_disable(priv->ctl);
+
+/* 9. Program PUBL PGCR to enable refresh during training and rank to train
+ * not done => keep the programed value in PGCR
+ */
+
+/* 10. configure PUBL PIR register to specify which training step to run */
+ /* warning : RVTRN is not supported by this PUBL */
+ stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN);
+
+/* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */
+ ddrphy_idone_wait(priv->phy);
+
+/* 12. set back registers in step 8 to the orginal values if desidered */
+ stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
+ config->c_reg.pwrctl);
+
+ /* enable uMCTL2 AXI port 0 and 1 */
+ setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
+ setbits_le32(&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);
+}
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.h b/drivers/ram/stm32mp1/stm32mp1_ddr.h
new file mode 100644
index 0000000..b77d823
--- /dev/null
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr.h
@@ -0,0 +1,210 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#ifndef _RAM_STM32MP1_DDR_H
+#define _RAM_STM32MP1_DDR_H
+
+enum stm32mp1_ddr_interact_step {
+ STEP_DDR_RESET,
+ STEP_CTL_INIT,
+ STEP_PHY_INIT,
+ STEP_DDR_READY,
+ STEP_RUN,
+};
+
+/* DDR CTL and DDR PHY REGISTERS */
+struct stm32mp1_ddrctl;
+struct stm32mp1_ddrphy;
+
+/**
+ * struct ddr_info
+ *
+ * @dev: pointer for the device
+ * @info: UCLASS RAM information
+ * @ctl: DDR controleur base address
+ * @clk: DDR clock
+ * @phy: DDR PHY base address
+ * @rcc: rcc base address
+ */
+struct ddr_info {
+ struct udevice *dev;
+ struct ram_info info;
+ struct clk clk;
+ struct stm32mp1_ddrctl *ctl;
+ struct stm32mp1_ddrphy *phy;
+ u32 rcc;
+};
+
+struct stm32mp1_ddrctrl_reg {
+ u32 mstr;
+ u32 mrctrl0;
+ u32 mrctrl1;
+ u32 derateen;
+ u32 derateint;
+ u32 pwrctl;
+ u32 pwrtmg;
+ u32 hwlpctl;
+ u32 rfshctl0;
+ u32 rfshctl3;
+ u32 crcparctl0;
+ u32 zqctl0;
+ u32 dfitmg0;
+ u32 dfitmg1;
+ u32 dfilpcfg0;
+ u32 dfiupd0;
+ u32 dfiupd1;
+ u32 dfiupd2;
+ u32 dfiphymstr;
+ u32 odtmap;
+ u32 dbg0;
+ u32 dbg1;
+ u32 dbgcmd;
+ u32 poisoncfg;
+ u32 pccfg;
+
+};
+
+struct stm32mp1_ddrctrl_timing {
+ u32 rfshtmg;
+ u32 dramtmg0;
+ u32 dramtmg1;
+ u32 dramtmg2;
+ u32 dramtmg3;
+ u32 dramtmg4;
+ u32 dramtmg5;
+ u32 dramtmg6;
+ u32 dramtmg7;
+ u32 dramtmg8;
+ u32 dramtmg14;
+ u32 odtcfg;
+};
+
+struct stm32mp1_ddrctrl_map {
+ u32 addrmap1;
+ u32 addrmap2;
+ u32 addrmap3;
+ u32 addrmap4;
+ u32 addrmap5;
+ u32 addrmap6;
+ u32 addrmap9;
+ u32 addrmap10;
+ u32 addrmap11;
+};
+
+struct stm32mp1_ddrctrl_perf {
+ u32 sched;
+ u32 sched1;
+ u32 perfhpr1;
+ u32 perflpr1;
+ u32 perfwr1;
+ u32 pcfgr_0;
+ u32 pcfgw_0;
+ u32 pcfgqos0_0;
+ u32 pcfgqos1_0;
+ u32 pcfgwqos0_0;
+ u32 pcfgwqos1_0;
+ u32 pcfgr_1;
+ u32 pcfgw_1;
+ u32 pcfgqos0_1;
+ u32 pcfgqos1_1;
+ u32 pcfgwqos0_1;
+ u32 pcfgwqos1_1;
+};
+
+struct stm32mp1_ddrphy_reg {
+ u32 pgcr;
+ u32 aciocr;
+ u32 dxccr;
+ u32 dsgcr;
+ u32 dcr;
+ u32 odtcr;
+ u32 zq0cr1;
+ u32 dx0gcr;
+ u32 dx1gcr;
+ u32 dx2gcr;
+ u32 dx3gcr;
+};
+
+struct stm32mp1_ddrphy_timing {
+ u32 ptr0;
+ u32 ptr1;
+ u32 ptr2;
+ u32 dtpr0;
+ u32 dtpr1;
+ u32 dtpr2;
+ u32 mr0;
+ u32 mr1;
+ u32 mr2;
+ u32 mr3;
+};
+
+struct stm32mp1_ddrphy_cal {
+ u32 dx0dllcr;
+ u32 dx0dqtr;
+ u32 dx0dqstr;
+ u32 dx1dllcr;
+ u32 dx1dqtr;
+ u32 dx1dqstr;
+ u32 dx2dllcr;
+ u32 dx2dqtr;
+ u32 dx2dqstr;
+ u32 dx3dllcr;
+ u32 dx3dqtr;
+ u32 dx3dqstr;
+};
+
+struct stm32mp1_ddr_info {
+ const char *name;
+ u16 speed; /* in MHZ */
+ u32 size; /* memory size in byte = col * row * width */
+};
+
+struct stm32mp1_ddr_config {
+ struct stm32mp1_ddr_info info;
+ struct stm32mp1_ddrctrl_reg c_reg;
+ struct stm32mp1_ddrctrl_timing c_timing;
+ struct stm32mp1_ddrctrl_map c_map;
+ struct stm32mp1_ddrctrl_perf c_perf;
+ struct stm32mp1_ddrphy_reg p_reg;
+ struct stm32mp1_ddrphy_timing p_timing;
+ struct stm32mp1_ddrphy_cal p_cal;
+};
+
+int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u16 mem_speed);
+void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir);
+void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl);
+void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
+ u32 rfshctl3,
+ u32 pwrctl);
+
+void stm32mp1_ddr_init(
+ struct ddr_info *priv,
+ const struct stm32mp1_ddr_config *config);
+
+int stm32mp1_dump_reg(const struct ddr_info *priv,
+ const char *name);
+
+void stm32mp1_edit_reg(const struct ddr_info *priv,
+ char *name,
+ char *string);
+
+int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config,
+ const char *name);
+
+void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config,
+ char *name,
+ char *string);
+
+void stm32mp1_dump_info(
+ const struct ddr_info *priv,
+ const struct stm32mp1_ddr_config *config);
+
+bool stm32mp1_ddr_interactive(
+ void *priv,
+ enum stm32mp1_ddr_interact_step step,
+ const struct stm32mp1_ddr_config *config);
+
+#endif
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
new file mode 100644
index 0000000..82c254b
--- /dev/null
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
@@ -0,0 +1,365 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#ifndef _RAM_STM32MP1_DDR_REGS_H
+#define _RAM_STM32MP1_DDR_REGS_H
+
+/* DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL) registers */
+struct stm32mp1_ddrctl {
+ u32 mstr ; /* 0x0 Master*/
+ u32 stat; /* 0x4 Operating Mode Status*/
+ u8 reserved008[0x10 - 0x8];
+ u32 mrctrl0; /* 0x10 Control 0.*/
+ u32 mrctrl1; /* 0x14 Control 1*/
+ u32 mrstat; /* 0x18 Status*/
+ u32 reserved01c; /* 0x1c */
+ u32 derateen; /* 0x20 Temperature Derate Enable*/
+ u32 derateint; /* 0x24 Temperature Derate Interval*/
+ u8 reserved028[0x30 - 0x28];
+ u32 pwrctl; /* 0x30 Low Power Control*/
+ u32 pwrtmg; /* 0x34 Low Power Timing*/
+ u32 hwlpctl; /* 0x38 Hardware Low Power Control*/
+ u8 reserved03c[0x50 - 0x3C];
+ u32 rfshctl0; /* 0x50 Refresh Control 0*/
+ u32 reserved054; /* 0x54 Refresh Control 1*/
+ u32 reserved058; /* 0x58 Refresh Control 2*/
+ u32 reserved05C;
+ u32 rfshctl3; /* 0x60 Refresh Control 0*/
+ u32 rfshtmg; /* 0x64 Refresh Timing*/
+ u8 reserved068[0xc0 - 0x68];
+ u32 crcparctl0; /* 0xc0 CRC Parity Control0*/
+ u32 reserved0c4; /* 0xc4 CRC Parity Control1*/
+ u32 reserved0c8; /* 0xc8 CRC Parity Control2*/
+ u32 crcparstat; /* 0xcc CRC Parity Status*/
+ u32 init0; /* 0xd0 SDRAM Initialization 0*/
+ u32 init1; /* 0xd4 SDRAM Initialization 1*/
+ u32 init2; /* 0xd8 SDRAM Initialization 2*/
+ u32 init3; /* 0xdc SDRAM Initialization 3*/
+ u32 init4; /* 0xe0 SDRAM Initialization 4*/
+ u32 init5; /* 0xe4 SDRAM Initialization 5*/
+ u32 reserved0e8;
+ u32 reserved0ec;
+ u32 dimmctl; /* 0xf0 DIMM Control*/
+ u8 reserved0f4[0x100 - 0xf4];
+ u32 dramtmg0; /* 0x100 SDRAM Timing 0*/
+ u32 dramtmg1; /* 0x104 SDRAM Timing 1*/
+ u32 dramtmg2; /* 0x108 SDRAM Timing 2*/
+ u32 dramtmg3; /* 0x10c SDRAM Timing 3*/
+ u32 dramtmg4; /* 0x110 SDRAM Timing 4*/
+ u32 dramtmg5; /* 0x114 SDRAM Timing 5*/
+ u32 dramtmg6; /* 0x118 SDRAM Timing 6*/
+ u32 dramtmg7; /* 0x11c SDRAM Timing 7*/
+ u32 dramtmg8; /* 0x120 SDRAM Timing 8*/
+ u8 reserved124[0x138 - 0x124];
+ u32 dramtmg14; /* 0x138 SDRAM Timing 14*/
+ u32 dramtmg15; /* 0x13C SDRAM Timing 15*/
+ u8 reserved140[0x180 - 0x140];
+ u32 zqctl0; /* 0x180 ZQ Control 0*/
+ u32 zqctl1; /* 0x184 ZQ Control 1*/
+ u32 zqctl2; /* 0x188 ZQ Control 2*/
+ u32 zqstat; /* 0x18c ZQ Status*/
+ u32 dfitmg0; /* 0x190 DFI Timing 0*/
+ u32 dfitmg1; /* 0x194 DFI Timing 1*/
+ u32 dfilpcfg0; /* 0x198 DFI Low Power Configuration 0*/
+ u32 reserved19c;
+ u32 dfiupd0; /* 0x1a0 DFI Update 0*/
+ u32 dfiupd1; /* 0x1a4 DFI Update 1*/
+ u32 dfiupd2; /* 0x1a8 DFI Update 2*/
+ u32 reserved1ac;
+ u32 dfimisc; /* 0x1b0 DFI Miscellaneous Control*/
+ u8 reserved1b4[0x1bc - 0x1b4];
+ u32 dfistat; /* 0x1bc DFI Miscellaneous Control*/
+ u8 reserved1c0[0x1c4 - 0x1c0];
+ u32 dfiphymstr; /* 0x1c4 DFI PHY Master interface*/
+ u8 reserved1c8[0x204 - 0x1c8];
+ u32 addrmap1; /* 0x204 Address Map 1*/
+ u32 addrmap2; /* 0x208 Address Map 2*/
+ u32 addrmap3; /* 0x20c Address Map 3*/
+ u32 addrmap4; /* 0x210 Address Map 4*/
+ u32 addrmap5; /* 0x214 Address Map 5*/
+ u32 addrmap6; /* 0x218 Address Map 6*/
+ u8 reserved21c[0x224 - 0x21c];
+ u32 addrmap9; /* 0x224 Address Map 9*/
+ u32 addrmap10; /* 0x228 Address Map 10*/
+ u32 addrmap11; /* 0x22C Address Map 11*/
+ u8 reserved230[0x240 - 0x230];
+ u32 odtcfg; /* 0x240 ODT Configuration*/
+ u32 odtmap; /* 0x244 ODT/Rank Map*/
+ u8 reserved248[0x250 - 0x248];
+ u32 sched; /* 0x250 Scheduler Control*/
+ u32 sched1; /* 0x254 Scheduler Control 1*/
+ u32 reserved258;
+ u32 perfhpr1; /* 0x25c High Priority Read CAM 1*/
+ u32 reserved260;
+ u32 perflpr1; /* 0x264 Low Priority Read CAM 1*/
+ u32 reserved268;
+ u32 perfwr1; /* 0x26c Write CAM 1*/
+ u8 reserved27c[0x300 - 0x270];
+ u32 dbg0; /* 0x300 Debug 0*/
+ u32 dbg1; /* 0x304 Debug 1*/
+ u32 dbgcam; /* 0x308 CAM Debug*/
+ u32 dbgcmd; /* 0x30c Command Debug*/
+ u32 dbgstat; /* 0x310 Status Debug*/
+ u8 reserved314[0x320 - 0x314];
+ u32 swctl; /* 0x320 Software Programming Control Enable*/
+ u32 swstat; /* 0x324 Software Programming Control Status*/
+ u8 reserved328[0x36c - 0x328];
+ u32 poisoncfg; /* 0x36c AXI Poison Configuration Register*/
+ u32 poisonstat; /* 0x370 AXI Poison Status Register*/
+ u8 reserved374[0x3fc - 0x374];
+
+ /* Multi Port registers */
+ u32 pstat; /* 0x3fc Port Status*/
+ u32 pccfg; /* 0x400 Port Common Configuration*/
+
+ /* PORT 0 */
+ u32 pcfgr_0; /* 0x404 Configuration Read*/
+ u32 pcfgw_0; /* 0x408 Configuration Write*/
+ u8 reserved40c[0x490 - 0x40c];
+ u32 pctrl_0; /* 0x490 Port Control Register */
+ u32 pcfgqos0_0; /* 0x494 Read QoS Configuration 0*/
+ u32 pcfgqos1_0; /* 0x498 Read QoS Configuration 1*/
+ u32 pcfgwqos0_0; /* 0x49c Write QoS Configuration 0*/
+ u32 pcfgwqos1_0; /* 0x4a0 Write QoS Configuration 1*/
+ u8 reserved4a4[0x4b4 - 0x4a4];
+
+ /* PORT 1 */
+ u32 pcfgr_1; /* 0x4b4 Configuration Read*/
+ u32 pcfgw_1; /* 0x4b8 Configuration Write*/
+ u8 reserved4bc[0x540 - 0x4bc];
+ u32 pctrl_1; /* 0x540 Port 2 Control Register */
+ u32 pcfgqos0_1; /* 0x544 Read QoS Configuration 0*/
+ u32 pcfgqos1_1; /* 0x548 Read QoS Configuration 1*/
+ u32 pcfgwqos0_1; /* 0x54c Write QoS Configuration 0*/
+ u32 pcfgwqos1_1; /* 0x550 Write QoS Configuration 1*/
+};
+
+/* DDR Physical Interface Control (DDRPHYC) registers*/
+struct stm32mp1_ddrphy {
+ u32 ridr; /* 0x00 R Revision Identification*/
+ u32 pir; /* 0x04 R/W PHY Initialization*/
+ u32 pgcr; /* 0x08 R/W PHY General Configuration*/
+ u32 pgsr; /* 0x0C PHY General Status*/
+ u32 dllgcr; /* 0x10 R/W DLL General Control*/
+ u32 acdllcr; /* 0x14 R/W AC DLL Control*/
+ u32 ptr0; /* 0x18 R/W PHY Timing 0*/
+ u32 ptr1; /* 0x1C R/W PHY Timing 1*/
+ u32 ptr2; /* 0x20 R/W PHY Timing 2*/
+ u32 aciocr; /* 0x24 AC I/O Configuration*/
+ u32 dxccr; /* 0x28 DATX8 Common Configuration*/
+ u32 dsgcr; /* 0x2C DDR System General Configuration*/
+ u32 dcr; /* 0x30 DRAM Configuration*/
+ u32 dtpr0; /* 0x34 DRAM Timing Parameters0*/
+ u32 dtpr1; /* 0x38 DRAM Timing Parameters1*/
+ u32 dtpr2; /* 0x3C DRAM Timing Parameters2*/
+ u32 mr0; /* 0x40 Mode 0*/
+ u32 mr1; /* 0x44 Mode 1*/
+ u32 mr2; /* 0x48 Mode 2*/
+ u32 mr3; /* 0x4C Mode 3*/
+ u32 odtcr; /* 0x50 ODT Configuration*/
+ u32 dtar; /* 0x54 data training address*/
+ u32 dtdr0; /* 0x58 */
+ u32 dtdr1; /* 0x5c */
+ u8 res1[0x0c0 - 0x060]; /* 0x60 */
+ u32 dcuar; /* 0xc0 Address*/
+ u32 dcudr; /* 0xc4 DCU Data*/
+ u32 dcurr; /* 0xc8 DCU Run*/
+ u32 dculr; /* 0xcc DCU Loop*/
+ u32 dcugcr; /* 0xd0 DCU General Configuration*/
+ u32 dcutpr; /* 0xd4 DCU Timing Parameters */
+ u32 dcusr0; /* 0xd8 DCU Status 0*/
+ u32 dcusr1; /* 0xdc DCU Status 1*/
+ u8 res2[0x100 - 0xe0]; /* 0xe0 */
+ u32 bistrr; /* 0x100 BIST Run*/
+ u32 bistmskr0; /* 0x104 BIST Mask 0*/
+ u32 bistmskr1; /* 0x108 BIST Mask 0*/
+ u32 bistwcr; /* 0x10c BIST Word Count*/
+ u32 bistlsr; /* 0x110 BIST LFSR Seed*/
+ u32 bistar0; /* 0x114 BIST Address 0*/
+ u32 bistar1; /* 0x118 BIST Address 1*/
+ u32 bistar2; /* 0x11c BIST Address 2*/
+ u32 bistupdr; /* 0x120 BIST User Data Pattern*/
+ u32 bistgsr; /* 0x124 BIST General Status*/
+ u32 bistwer; /* 0x128 BIST Word Error*/
+ u32 bistber0; /* 0x12c BIST Bit Error 0*/
+ u32 bistber1; /* 0x130 BIST Bit Error 1*/
+ u32 bistber2; /* 0x134 BIST Bit Error 2*/
+ u32 bistwcsr; /* 0x138 BIST Word Count Status*/
+ u32 bistfwr0; /* 0x13c BIST Fail Word 0*/
+ u32 bistfwr1; /* 0x140 BIST Fail Word 1*/
+ u8 res3[0x178 - 0x144]; /* 0x144 */
+ u32 gpr0; /* 0x178 General Purpose 0 (GPR0)*/
+ u32 gpr1; /* 0x17C General Purpose 1 (GPR1)*/
+ u32 zq0cr0; /* 0x180 zq 0 control 0 */
+ u32 zq0cr1; /* 0x184 zq 0 control 1 */
+ u32 zq0sr0; /* 0x188 zq 0 status 0 */
+ u32 zq0sr1; /* 0x18C zq 0 status 1 */
+ u8 res4[0x1C0 - 0x190]; /* 0x190 */
+ u32 dx0gcr; /* 0x1c0 Byte lane 0 General Configuration*/
+ u32 dx0gsr0; /* 0x1c4 Byte lane 0 General Status 0*/
+ u32 dx0gsr1; /* 0x1c8 Byte lane 0 General Status 1*/
+ u32 dx0dllcr; /* 0x1cc Byte lane 0 DLL Control*/
+ u32 dx0dqtr; /* 0x1d0 Byte lane 0 DQ Timing*/
+ u32 dx0dqstr; /* 0x1d4 Byte lane 0 DQS Timing*/
+ u8 res5[0x200 - 0x1d8]; /* 0x1d8 */
+ u32 dx1gcr; /* 0x200 Byte lane 1 General Configuration*/
+ u32 dx1gsr0; /* 0x204 Byte lane 1 General Status 0*/
+ u32 dx1gsr1; /* 0x208 Byte lane 1 General Status 1*/
+ u32 dx1dllcr; /* 0x20c Byte lane 1 DLL Control*/
+ u32 dx1dqtr; /* 0x210 Byte lane 1 DQ Timing*/
+ u32 dx1dqstr; /* 0x214 Byte lane 1 QS Timing*/
+ u8 res6[0x240 - 0x218]; /* 0x218 */
+ u32 dx2gcr; /* 0x240 Byte lane 2 General Configuration*/
+ u32 dx2gsr0; /* 0x244 Byte lane 2 General Status 0*/
+ u32 dx2gsr1; /* 0x248 Byte lane 2 General Status 1*/
+ u32 dx2dllcr; /* 0x24c Byte lane 2 DLL Control*/
+ u32 dx2dqtr; /* 0x250 Byte lane 2 DQ Timing*/
+ u32 dx2dqstr; /* 0x254 Byte lane 2 QS Timing*/
+ u8 res7[0x280 - 0x258]; /* 0x258 */
+ u32 dx3gcr; /* 0x280 Byte lane 3 General Configuration*/
+ u32 dx3gsr0; /* 0x284 Byte lane 3 General Status 0*/
+ u32 dx3gsr1; /* 0x288 Byte lane 3 General Status 1*/
+ u32 dx3dllcr; /* 0x28c Byte lane 3 DLL Control*/
+ u32 dx3dqtr; /* 0x290 Byte lane 3 DQ Timing*/
+ u32 dx3dqstr; /* 0x294 Byte lane 3 QS Timing*/
+};
+
+#define DXN(phy, offset, byte) ((u32)(phy) + (offset) + ((u32)(byte) * 0x40))
+#define DXNGCR(phy, byte) DXN(phy, 0x1c0, byte)
+#define DXNDLLCR(phy, byte) DXN(phy, 0x1cc, byte)
+#define DXNDQTR(phy, byte) DXN(phy, 0x1d0, byte)
+#define DXNDQSTR(phy, byte) DXN(phy, 0x1d4, byte)
+
+/* DDRCTRL REGISTERS */
+#define DDRCTRL_MSTR_DDR3 BIT(0)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL (0 << 12)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF (1 << 12)
+#define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER (2 << 12)
+#define DDRCTRL_MSTR_DLL_OFF_MODE BIT(15)
+
+#define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0)
+#define DDRCTRL_STAT_OPERATING_MODE_NORMAL 1
+#define DDRCTRL_STAT_OPERATING_MODE_SR 3
+#define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4)
+#define DDRCTRL_STAT_SELFREF_TYPE_ASR (3 << 4)
+#define DDRCTRL_STAT_SELFREF_TYPE_SR (2 << 4)
+
+#define DDRCTRL_MRCTRL0_MR_TYPE_WRITE 0
+/* only one rank supported */
+#define DDRCTRL_MRCTRL0_MR_RANK_SHIFT 4
+#define DDRCTRL_MRCTRL0_MR_RANK_ALL \
+ (0x1 << DDRCTRL_MRCTRL0_MR_RANK_SHIFT)
+#define DDRCTRL_MRCTRL0_MR_ADDR_SHIFT 12
+#define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12)
+#define DDRCTRL_MRCTRL0_MR_WR BIT(31)
+
+#define DDRCTRL_MRSTAT_MR_WR_BUSY BIT(0)
+
+#define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1)
+#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5)
+
+#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH BIT(0)
+
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16)
+#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_SHIFT 16
+
+#define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK (0xC0000000)
+#define DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL (BIT(30))
+
+#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0)
+
+#define DDRCTRL_DBG1_DIS_HIF BIT(1)
+
+#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY BIT(29)
+#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY BIT(28)
+#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY BIT(26)
+#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8)
+#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0)
+#define DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY \
+ (DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY | \
+ DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY)
+#define DDRCTRL_DBGCAM_DBG_Q_DEPTH \
+ (DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY | \
+ DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH | \
+ DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH)
+
+#define DDRCTRL_DBGCMD_RANK0_REFRESH BIT(0)
+
+#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY BIT(0)
+
+#define DDRCTRL_SWCTL_SW_DONE BIT(0)
+
+#define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0)
+
+#define DDRCTRL_PCTRL_N_PORT_EN BIT(0)
+
+/* DDRPHYC registers */
+#define DDRPHYC_PIR_INIT BIT(0)
+#define DDRPHYC_PIR_DLLSRST BIT(1)
+#define DDRPHYC_PIR_DLLLOCK BIT(2)
+#define DDRPHYC_PIR_ZCAL BIT(3)
+#define DDRPHYC_PIR_ITMSRST BIT(4)
+#define DDRPHYC_PIR_DRAMRST BIT(5)
+#define DDRPHYC_PIR_DRAMINIT BIT(6)
+#define DDRPHYC_PIR_QSTRN BIT(7)
+#define DDRPHYC_PIR_ICPC BIT(16)
+#define DDRPHYC_PIR_ZCALBYP BIT(30)
+#define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7)
+
+#define DDRPHYC_PGCR_DFTCMP BIT(2)
+#define DDRPHYC_PGCR_PDDISDX BIT(24)
+#define DDRPHYC_PGCR_RFSHDT_MASK GENMASK(28, 25)
+
+#define DDRPHYC_PGSR_IDONE BIT(0)
+#define DDRPHYC_PGSR_DTERR BIT(5)
+#define DDRPHYC_PGSR_DTIERR BIT(6)
+#define DDRPHYC_PGSR_DFTERR BIT(7)
+#define DDRPHYC_PGSR_RVERR BIT(8)
+#define DDRPHYC_PGSR_RVEIRR BIT(9)
+
+#define DDRPHYC_DLLGCR_BPS200 BIT(23)
+
+#define DDRPHYC_ACDLLCR_DLLDIS BIT(31)
+
+#define DDRPHYC_ZQ0CRN_ZDATA_MASK GENMASK(27, 0)
+#define DDRPHYC_ZQ0CRN_ZDATA_SHIFT 0
+#define DDRPHYC_ZQ0CRN_ZDEN BIT(28)
+
+#define DDRPHYC_DXNGCR_DXEN BIT(0)
+
+#define DDRPHYC_DXNDLLCR_DLLDIS BIT(31)
+#define DDRPHYC_DXNDLLCR_SDPHASE_MASK GENMASK(17, 14)
+#define DDRPHYC_DXNDLLCR_SDPHASE_SHIFT 14
+
+#define DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit) (4 * (bit))
+#define DDRPHYC_DXNDQTR_DQDLY_MASK GENMASK(3, 0)
+#define DDRPHYC_DXNDQTR_DQDLY_LOW_MASK GENMASK(1, 0)
+#define DDRPHYC_DXNDQTR_DQDLY_HIGH_MASK GENMASK(3, 2)
+
+#define DDRPHYC_DXNDQSTR_DQSDLY_MASK GENMASK(22, 20)
+#define DDRPHYC_DXNDQSTR_DQSDLY_SHIFT 20
+#define DDRPHYC_DXNDQSTR_DQSNDLY_MASK GENMASK(25, 23)
+#define DDRPHYC_DXNDQSTR_DQSNDLY_SHIFT 23
+#define DDRPHYC_DXNDQSTR_R0DGSL_MASK GENMASK(2, 0)
+#define DDRPHYC_DXNDQSTR_R0DGSL_SHIFT 0
+#define DDRPHYC_DXNDQSTR_R0DGPS_MASK GENMASK(13, 12)
+#define DDRPHYC_DXNDQSTR_R0DGPS_SHIFT 12
+
+#define DDRPHYC_BISTRR_BDXSEL_MASK GENMASK(22, 19)
+#define DDRPHYC_BISTRR_BDXSEL_SHIFT 19
+
+#define DDRPHYC_BISTGSR_BDDONE BIT(0)
+#define DDRPHYC_BISTGSR_BDXERR BIT(2)
+
+#define DDRPHYC_BISTWCSR_DXWCNT_SHIFT 16
+
+/* PWR registers */
+#define PWR_CR3 0x00C
+#define PWR_CR3_DDRSRDIS BIT(11)
+#define PWR_CR3_DDRRETEN BIT(12)
+
+#endif
diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c
new file mode 100644
index 0000000..9599444
--- /dev/null
+++ b/drivers/ram/stm32mp1/stm32mp1_ram.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <ram.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include "stm32mp1_ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char *const clkname[] = {
+ "ddrc1",
+ "ddrc2",
+ "ddrcapb",
+ "ddrphycapb",
+ "ddrphyc" /* LAST clock => used for get_rate() */
+};
+
+int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint16_t mem_speed)
+{
+ unsigned long ddrphy_clk;
+ unsigned long ddr_clk;
+ struct clk clk;
+ int ret;
+ int idx;
+
+ for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) {
+ ret = clk_get_by_name(priv->dev, clkname[idx], &clk);
+
+ if (!ret)
+ ret = clk_enable(&clk);
+
+ if (ret) {
+ printf("error for %s : %d\n", clkname[idx], ret);
+ return ret;
+ }
+ }
+
+ priv->clk = clk;
+ ddrphy_clk = clk_get_rate(&priv->clk);
+
+ debug("DDR: mem_speed (%d MHz), RCC %d MHz\n",
+ mem_speed, (u32)(ddrphy_clk / 1000 / 1000));
+ /* max 10% frequency delta */
+ ddr_clk = abs(ddrphy_clk - mem_speed * 1000 * 1000);
+ if (ddr_clk > (mem_speed * 1000 * 100)) {
+ pr_err("DDR expected freq %d MHz, current is %d MHz\n",
+ mem_speed, (u32)(ddrphy_clk / 1000 / 1000));
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
+{
+ struct ddr_info *priv = dev_get_priv(dev);
+ int ret, idx;
+ struct clk axidcg;
+ struct stm32mp1_ddr_config config;
+
+#define PARAM(x, y) \
+ { x,\
+ offsetof(struct stm32mp1_ddr_config, y),\
+ sizeof(config.y) / sizeof(u32)}
+
+#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x)
+#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x)
+
+ const struct {
+ const char *name; /* name in DT */
+ const u32 offset; /* offset in config struct */
+ const u32 size; /* size of parameters */
+ } param[] = {
+ CTL_PARAM(reg),
+ CTL_PARAM(timing),
+ CTL_PARAM(map),
+ CTL_PARAM(perf),
+ PHY_PARAM(reg),
+ PHY_PARAM(timing),
+ PHY_PARAM(cal)
+ };
+
+ config.info.speed = dev_read_u32_default(dev, "st,mem-speed", 0);
+ config.info.size = dev_read_u32_default(dev, "st,mem-size", 0);
+ config.info.name = dev_read_string(dev, "st,mem-name");
+ if (!config.info.name) {
+ debug("%s: no st,mem-name\n", __func__);
+ return -EINVAL;
+ }
+ printf("RAM: %s\n", config.info.name);
+
+ for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
+ ret = dev_read_u32_array(dev, param[idx].name,
+ (void *)((u32)&config +
+ param[idx].offset),
+ param[idx].size);
+ debug("%s: %s[0x%x] = %d\n", __func__,
+ param[idx].name, param[idx].size, ret);
+ if (ret) {
+ pr_err("%s: Cannot read %s\n",
+ __func__, param[idx].name);
+ return -EINVAL;
+ }
+ }
+
+ ret = clk_get_by_name(dev, "axidcg", &axidcg);
+ if (ret) {
+ debug("%s: Cannot found axidcg\n", __func__);
+ return -EINVAL;
+ }
+ clk_disable(&axidcg); /* disable clock gating during init */
+
+ stm32mp1_ddr_init(priv, &config);
+
+ clk_enable(&axidcg); /* enable clock gating */
+
+ /* check size */
+ debug("%s : get_ram_size(%x, %x)\n", __func__,
+ (u32)priv->info.base, (u32)STM32_DDR_SIZE);
+
+ priv->info.size = get_ram_size((long *)priv->info.base,
+ STM32_DDR_SIZE);
+
+ debug("%s : %x\n", __func__, (u32)priv->info.size);
+
+ /* check memory access for all memory */
+ if (config.info.size != priv->info.size) {
+ printf("DDR invalid size : 0x%x, expected 0x%x\n",
+ priv->info.size, config.info.size);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int stm32mp1_ddr_probe(struct udevice *dev)
+{
+ struct ddr_info *priv = dev_get_priv(dev);
+ struct regmap *map;
+ int ret;
+
+ debug("STM32MP1 DDR probe\n");
+ priv->dev = dev;
+
+ ret = regmap_init_mem(dev, &map);
+ if (ret)
+ return ret;
+
+ priv->ctl = regmap_get_range(map, 0);
+ priv->phy = regmap_get_range(map, 1);
+
+ priv->rcc = STM32_RCC_BASE;
+
+ priv->info.base = STM32_DDR_BASE;
+
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+ priv->info.size = 0;
+ return stm32mp1_ddr_setup(dev);
+#else
+ priv->info.size = dev_read_u32_default(dev, "st,mem-size", 0);
+ return 0;
+#endif
+}
+
+static int stm32mp1_ddr_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct ddr_info *priv = dev_get_priv(dev);
+
+ *info = priv->info;
+
+ return 0;
+}
+
+static struct ram_ops stm32mp1_ddr_ops = {
+ .get_info = stm32mp1_ddr_get_info,
+};
+
+static const struct udevice_id stm32mp1_ddr_ids[] = {
+ { .compatible = "st,stm32mp1-ddr" },
+ { }
+};
+
+U_BOOT_DRIVER(ddr_stm32mp1) = {
+ .name = "stm32mp1_ddr",
+ .id = UCLASS_RAM,
+ .of_match = stm32mp1_ddr_ids,
+ .ops = &stm32mp1_ddr_ops,
+ .probe = stm32mp1_ddr_probe,
+ .priv_auto_alloc_size = sizeof(struct ddr_info),
+};
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 3964b9e..71a786b 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -30,7 +30,7 @@
config STM32_RESET
bool "Enable the STM32 reset"
- depends on STM32
+ depends on STM32 || ARCH_STM32MP
help
Support for reset controllers on STMicroelectronics STM32 family SoCs.
This resset driver is compatible with STM32 F4/F7 and H7 SoCs.
diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c
index b266f46..e98f34b 100644
--- a/drivers/reset/stm32-reset.c
+++ b/drivers/reset/stm32-reset.c
@@ -11,7 +11,13 @@
#include <reset-uclass.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
+/* reset clear offset for STM32MP RCC */
+#define RCC_CL 0x4
+
+enum rcc_type {
+ RCC_STM32 = 0,
+ RCC_STM32MP,
+};
struct stm32_reset_priv {
fdt_addr_t base;
@@ -35,7 +41,11 @@
debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
reset_ctl->id, bank, offset);
- setbits_le32(priv->base + bank, BIT(offset));
+ if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP)
+ /* reset assert is done in rcc set register */
+ writel(BIT(offset), priv->base + bank);
+ else
+ setbits_le32(priv->base + bank, BIT(offset));
return 0;
}
@@ -48,7 +58,11 @@
debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
reset_ctl->id, bank, offset);
- clrbits_le32(priv->base + bank, BIT(offset));
+ if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP)
+ /* reset deassert is done in rcc clr register */
+ writel(BIT(offset), priv->base + bank + RCC_CL);
+ else
+ clrbits_le32(priv->base + bank, BIT(offset));
return 0;
}
@@ -64,16 +78,26 @@
{
struct stm32_reset_priv *priv = dev_get_priv(dev);
- priv->base = devfdt_get_addr(dev);
- if (priv->base == FDT_ADDR_T_NONE)
- return -EINVAL;
+ priv->base = dev_read_addr(dev);
+ if (priv->base == FDT_ADDR_T_NONE) {
+ /* for MFD, get address of parent */
+ priv->base = dev_read_addr(dev->parent);
+ if (priv->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ }
return 0;
}
+static const struct udevice_id stm32_reset_ids[] = {
+ { .compatible = "st,stm32mp1-rcc-rst", .data = RCC_STM32MP },
+ { }
+};
+
U_BOOT_DRIVER(stm32_rcc_reset) = {
.name = "stm32_rcc_reset",
.id = UCLASS_RESET,
+ .of_match = stm32_reset_ids,
.probe = stm32_reset_probe,
.priv_auto_alloc_size = sizeof(struct stm32_reset_priv),
.ops = &stm32_reset_ops,
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 76d5e99..eb718a6 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -609,10 +609,10 @@
config STM32_SERIAL
bool "STMicroelectronics STM32 SoCs on-chip UART"
- depends on DM_SERIAL && (STM32F4 || STM32F7 || STM32H7)
+ depends on DM_SERIAL && (STM32F4 || STM32F7 || STM32H7 || ARCH_STM32MP)
help
- If you have a machine based on a STM32 F4, F7 or H7 SoC you can
- enable its onboard serial ports, say Y to this option.
+ If you have a machine based on a STM32 F4, F7, H7 or MP1 SOC
+ you can enable its onboard serial ports, say Y to this option.
If unsure, say N.
config ZYNQ_SERIAL
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 0b25897..5b7795d 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -768,7 +768,7 @@
break;
case '\n': /* next line */
- if (console_col || (!console_col && nl))
+ if (console_col || nl)
console_newline(1);
nl = 1;
break;
diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
index 6ec4f89..26db73b 100644
--- a/drivers/video/da8xx-fb.c
+++ b/drivers/video/da8xx-fb.c
@@ -853,9 +853,10 @@
do {
ret = lcdc_irq_handler();
udelay(1000);
- } while (!(ret & event));
+ --timeout;
+ } while (!(ret & event) && timeout);
- if (timeout <= 0) {
+ if (!(ret & event)) {
printf("%s: event %d not hit\n", __func__, event);
return -1;
}
diff --git a/drivers/video/exynos/exynos_dp.c b/drivers/video/exynos/exynos_dp.c
index 30e4020..3a6ef62 100644
--- a/drivers/video/exynos/exynos_dp.c
+++ b/drivers/video/exynos/exynos_dp.c
@@ -321,7 +321,7 @@
static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *regs)
{
- unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned int ret;
exynos_dp_set_training_pattern(regs, DP_NONE);
@@ -339,7 +339,7 @@
struct exynos_dp *regs, unsigned char enable)
{
unsigned char data;
- unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned int ret;
ret = exynos_dp_read_byte_from_dpcd(regs, DPCD_LANE_COUNT_SET,
&data);
@@ -366,7 +366,7 @@
static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *regs,
unsigned char enhance_mode)
{
- unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned int ret;
ret = exynos_dp_enable_rx_to_enhanced_mode(regs, enhance_mode);
if (ret != EXYNOS_DP_SUCCESS) {
@@ -416,7 +416,7 @@
static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *regs,
unsigned char lane_num, unsigned char *sw, unsigned char *em)
{
- unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned int ret;
unsigned char buf;
unsigned int dpcd_addr;
unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
@@ -484,7 +484,7 @@
static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs,
struct exynos_dp_priv *priv)
{
- unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned int ret;
unsigned char lane_stat;
unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, };
unsigned int i;
@@ -594,7 +594,7 @@
static unsigned int exynos_dp_process_equalizer_training(
struct exynos_dp *regs, struct exynos_dp_priv *priv)
{
- unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned int ret;
unsigned char lane_stat, adj_req_sw, adj_req_em, i;
unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,};
unsigned char interlane_aligned = 0;
diff --git a/drivers/video/stb_truetype.h b/drivers/video/stb_truetype.h
index 26e483c..5d00bff 100644
--- a/drivers/video/stb_truetype.h
+++ b/drivers/video/stb_truetype.h
@@ -1993,7 +1993,7 @@
STBTT_assert(fabs(area) <= 1.01f);
- scanline[x2] += area + sign * (1-((x2-x2)+(x_bottom-x2))/2) * (sy1-y_crossing);
+ scanline[x2] += area + sign * (1-(x_bottom-x2)/2) * (sy1-y_crossing);
scanline_fill[x2] += sign * (sy1-sy0);
}
diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index b417ac2..e160c77 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -1,8 +1,7 @@
/*
- * Copyright (C) STMicroelectronics SA 2017
- *
- * Authors: Philippe Cornu <philippe.cornu@st.com>
- * Yannick Fertre <yannick.fertre@st.com>
+ * Copyright (C) 2017-2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
+ * Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -11,6 +10,7 @@
#include <clk.h>
#include <dm.h>
#include <panel.h>
+#include <reset.h>
#include <video.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
@@ -138,7 +138,9 @@
#define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
#define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
+#define BF1_CA 0x400 /* Constant Alpha */
#define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
+#define BF2_1CA 0x005 /* 1 - Constant Alpha */
enum stm32_ltdc_pix_fmt {
PF_ARGB8888 = 0,
@@ -161,11 +163,17 @@
pf = PF_RGB565;
break;
+ case VIDEO_BPP32:
+ pf = PF_ARGB8888;
+ break;
+
+ case VIDEO_BPP8:
+ pf = PF_L8;
+ break;
+
case VIDEO_BPP1:
case VIDEO_BPP2:
case VIDEO_BPP4:
- case VIDEO_BPP8:
- case VIDEO_BPP32:
default:
debug("%s: warning %dbpp not supported yet, %dbpp instead\n",
__func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
@@ -178,6 +186,23 @@
return (u32)pf;
}
+static bool has_alpha(u32 fmt)
+{
+ switch (fmt) {
+ case PF_ARGB8888:
+ case PF_ARGB1555:
+ case PF_ARGB4444:
+ case PF_AL44:
+ case PF_AL88:
+ return true;
+ case PF_RGB888:
+ case PF_RGB565:
+ case PF_L8:
+ default:
+ return false;
+ }
+}
+
static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv)
{
/* Reload configuration immediately & enable LTDC */
@@ -219,6 +244,8 @@
val = (total_w << 16) | total_h;
clrsetbits_le32(regs + LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
+ setbits_le32(regs + LTDC_LIPCR, acc_act_h + 1);
+
/* Signal polarities */
val = 0;
debug("%s: timing->flags 0x%08x\n", __func__, timing->flags);
@@ -245,6 +272,7 @@
u32 line_length;
u32 bus_width;
u32 val, tmp, bpp;
+ u32 format;
x0 = priv->crop_x;
x1 = priv->crop_x + priv->crop_w - 1;
@@ -275,15 +303,18 @@
clrsetbits_le32(regs + LTDC_L1CFBLR, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
/* Pixel format */
- val = stm32_ltdc_get_pixel_format(priv->l2bpp);
- clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, val);
+ format = stm32_ltdc_get_pixel_format(priv->l2bpp);
+ clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, format);
/* Constant alpha value */
clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha);
+ /* Specifies the blending factors : with or without pixel alpha */
+ /* Manage hw-specific capabilities */
+ val = has_alpha(format) ? BF1_PAXCA | BF2_1PAXCA : BF1_CA | BF2_1CA;
+
/* Blending factors */
- clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1,
- BF1_PAXCA | BF2_1PAXCA);
+ clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1, val);
/* Frame buffer line number */
clrsetbits_le32(regs + LTDC_L1CFBLNR, LXCFBLNR_CFBLN, priv->crop_h);
@@ -301,8 +332,9 @@
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct stm32_ltdc_priv *priv = dev_get_priv(dev);
struct udevice *panel;
- struct clk pclk, pxclk;
- int ret;
+ struct clk pclk;
+ struct reset_ctl rst;
+ int rate, ret;
priv->regs = (void *)dev_read_addr(dev);
if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
@@ -310,45 +342,60 @@
return -EINVAL;
}
- ret = uclass_first_device(UCLASS_PANEL, &panel);
+ ret = clk_get_by_index(dev, 0, &pclk);
if (ret) {
- debug("%s: panel device error %d\n", __func__, ret);
+ debug("%s: peripheral clock get error %d\n", __func__, ret);
return ret;
}
- ret = panel_enable_backlight(panel);
+ ret = clk_enable(&pclk);
if (ret) {
- debug("%s: panel %s enable backlight error %d\n",
- __func__, panel->name, ret);
+ debug("%s: peripheral clock enable error %d\n",
+ __func__, ret);
return ret;
}
- ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev),
- 0, &priv->timing);
+ ret = reset_get_by_index(dev, 0, &rst);
if (ret) {
- debug("%s: decode display timing error %d\n", __func__, ret);
- return -EINVAL;
+ debug("%s: missing ltdc hardware reset\n", __func__);
+ return -ENODEV;
}
- ret = clk_get_by_name(dev, "pclk", &pclk);
+ /* Reset */
+ reset_deassert(&rst);
+
+ ret = uclass_first_device(UCLASS_PANEL, &panel);
if (ret) {
- debug("%s: peripheral clock get error %d\n", __func__, ret);
+ debug("%s: panel device error %d\n", __func__, ret);
return ret;
}
- ret = clk_enable(&pclk);
+ ret = panel_enable_backlight(panel);
if (ret) {
- debug("%s: peripheral clock enable error %d\n", __func__, ret);
+ debug("%s: panel %s enable backlight error %d\n",
+ __func__, panel->name, ret);
return ret;
}
- /* Verify pixel clock value if any & inform user accordingly */
- ret = clk_get_by_name(dev, "pxclk", &pxclk);
- if (!ret) {
- if (clk_get_rate(&pxclk) != priv->timing.pixelclock.typ)
- printf("Warning: please adjust ltdc pixel clock\n");
+ ret = fdtdec_decode_display_timing(gd->fdt_blob,
+ dev_of_offset(dev), 0,
+ &priv->timing);
+ if (ret) {
+ debug("%s: decode display timing error %d\n",
+ __func__, ret);
+ return -EINVAL;
+ }
+
+ rate = clk_set_rate(&pclk, priv->timing.pixelclock.typ);
+ if (rate < 0) {
+ debug("%s: fail to set pixel clock %d hz %d hz\n",
+ __func__, priv->timing.pixelclock.typ, rate);
+ return rate;
}
+ debug("%s: Set pixel clock req %d hz get %d hz\n", __func__,
+ priv->timing.pixelclock.typ, rate);
+
/* TODO Below parameters are hard-coded for the moment... */
priv->l2bpp = VIDEO_BPP16;
priv->bg_col_argb = 0xFFFFFFFF; /* white no transparency */
@@ -397,10 +444,10 @@
};
U_BOOT_DRIVER(stm32_ltdc) = {
- .name = "stm32_ltdc",
- .id = UCLASS_VIDEO,
- .of_match = stm32_ltdc_ids,
- .probe = stm32_ltdc_probe,
- .bind = stm32_ltdc_bind,
+ .name = "stm32_display",
+ .id = UCLASS_VIDEO,
+ .of_match = stm32_ltdc_ids,
+ .probe = stm32_ltdc_probe,
+ .bind = stm32_ltdc_bind,
.priv_auto_alloc_size = sizeof(struct stm32_ltdc_priv),
};
diff --git a/include/common.h b/include/common.h
index 0fe9439..3087505 100644
--- a/include/common.h
+++ b/include/common.h
@@ -62,31 +62,19 @@
#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
#endif
-/*
- * Function Prototypes
+/* startup functions, used in:
+ * common/board_f.c
+ * common/init/board_init.c
+ * common/board_r.c
+ * common/board_info.c
*/
-int dram_init(void);
+#include <init.h>
-/**
- * dram_init_banksize() - Set up DRAM bank sizes
- *
- * This can be implemented by boards to set up the DRAM bank information in
- * gd->bd->bi_dram(). It is called just before relocation, after dram_init()
- * is called.
- *
- * If this is not provided, a default implementation will try to set up a
- * single bank. It will do this if CONFIG_NR_DRAM_BANKS and
- * CONFIG_SYS_SDRAM_BASE are set. The bank will have a start address of
- * CONFIG_SYS_SDRAM_BASE and the size will be determined by a call to
- * get_effective_memsize().
- *
- * @return 0 if OK, -ve on error
+/*
+ * Function Prototypes
*/
-int dram_init_banksize(void);
-
void hang (void) __attribute__ ((noreturn));
-int timer_init(void);
int cpu_init(void);
#include <display_options.h>
@@ -109,107 +97,13 @@
*/
int run_command_list(const char *cmd, int len, int flag);
-/* arch/$(ARCH)/lib/board.c */
-void board_init_f(ulong);
-void board_init_r(gd_t *, ulong) __attribute__ ((noreturn));
-
-/**
- * ulong board_init_f_alloc_reserve - allocate reserved area
- *
- * This function is called by each architecture very early in the start-up
- * code to allow the C runtime to reserve space on the stack for writable
- * 'globals' such as GD and the malloc arena.
- *
- * @top: top of the reserve area, growing down.
- * @return: bottom of reserved area
- */
-ulong board_init_f_alloc_reserve(ulong top);
-
-/**
- * board_init_f_init_reserve - initialize the reserved area(s)
- *
- * This function is called once the C runtime has allocated the reserved
- * area on the stack. It must initialize the GD at the base of that area.
- *
- * @base: top from which reservation was done
- */
-void board_init_f_init_reserve(ulong base);
-
-/**
- * arch_setup_gd() - Set up the global_data pointer
- *
- * This pointer is special in some architectures and cannot easily be assigned
- * to. For example on x86 it is implemented by adding a specific record to its
- * Global Descriptor Table! So we we provide a function to carry out this task.
- * For most architectures this can simply be:
- *
- * gd = gd_ptr;
- *
- * @gd_ptr: Pointer to global data
- */
-void arch_setup_gd(gd_t *gd_ptr);
-
-int checkboard(void);
-int show_board_info(void);
int checkflash(void);
int checkdram(void);
-int last_stage_init(void);
-extern ulong monitor_flash_len;
-int mac_read_from_eeprom(void);
extern u8 __dtb_dt_begin[]; /* embedded device tree blob */
extern u8 __dtb_dt_spl_begin[]; /* embedded device tree blob for SPL/TPL */
-int set_cpu_clk_info(void);
int mdm_init(void);
-int print_cpuinfo(void);
-int update_flash_size(int flash_size);
-int arch_early_init_r(void);
-
-/*
- * setup_board_extra() - Fill in extra details in the bd_t structure
- *
- * @return 0 if OK, -ve on error
- */
-int setup_board_extra(void);
-
-/**
- * arch_fsp_init() - perform firmware support package init
- *
- * Where U-Boot relies on binary blobs to handle part of the system init, this
- * function can be used to set up the blobs. This is used on some Intel
- * platforms.
- */
-int arch_fsp_init(void);
-
-/**
- * arch_cpu_init_dm() - init CPU after driver model is available
- *
- * This is called immediately after driver model is available before
- * relocation. This is similar to arch_cpu_init() but is able to reference
- * devices
- *
- * @return 0 if OK, -ve on error
- */
-int arch_cpu_init_dm(void);
/**
- * Reserve all necessary stacks
- *
- * This is used in generic board init sequence in common/board_f.c. Each
- * architecture could provide this function to tailor the required stacks.
- *
- * On entry gd->start_addr_sp is pointing to the suggested top of the stack.
- * The callee ensures gd->start_add_sp is 16-byte aligned, so architectures
- * require only this can leave it untouched.
- *
- * On exit gd->start_addr_sp and gd->irq_sp should be set to the respective
- * positions of the stack. The stack pointer(s) will be set to this later.
- * gd->irq_sp is only required, if the architecture needs it.
- *
- * @return 0 if no error
- */
-__weak int arch_reserve_stacks(void);
-
-/**
* Show the DRAM size in a board-specific way
*
* This is used by boards to display DRAM information in their own way.
@@ -228,7 +122,6 @@
*/
int arch_fixup_fdt(void *blob);
-int reserve_mmu(void);
/* common/flash.c */
void flash_perror (int);
@@ -355,19 +248,8 @@
#endif
int get_env_id (void);
-void pci_init (void);
void pci_init_board(void);
-#if defined(CONFIG_DTB_RESELECT)
-int embedded_dtb_select(void);
-#endif
-
-int misc_init_f (void);
-int misc_init_r (void);
-#if defined(CONFIG_VID)
-int init_func_vid(void);
-#endif
-
/* common/exports.c */
void jumptable_init(void);
@@ -422,7 +304,6 @@
int board_late_init (void);
int board_postclk_init (void); /* after clocks/timebase, before env/serial */
int board_early_init_r (void);
-void board_poweroff (void);
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram(void);
@@ -464,16 +345,6 @@
u32 cpu_dsp_mask(void);
int is_core_valid (unsigned int);
-/**
- * arch_cpu_init() - basic cpu-dependent setup for an architecture
- *
- * This is called after early malloc is available. It should handle any
- * CPU- or SoC- specific init needed to continue the init sequence. See
- * board_f.c for where it is called. If this is not provided, a default
- * version (which does nothing) will be used.
- */
-int arch_cpu_init(void);
-
void s_init(void);
int checkcpu (void);
@@ -503,8 +374,6 @@
ulong get_bus_freq (ulong);
int get_serial_clock(void);
-int cpu_init_r (void);
-
/* $(CPU)/interrupts.c */
int interrupt_init (void);
void timer_interrupt (struct pt_regs *);
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index 801980e..8b8a73d 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -79,4 +79,14 @@
#endif
/* For SPL ends */
+/* For splashcreen */
+#ifdef CONFIG_DM_VIDEO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_BMP_16BPP
+#define CONFIG_BMP_24BPP
+#define CONFIG_BMP_32BPP
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#endif
+
#endif /* __CONFIG_H */
diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h
new file mode 100644
index 0000000..aae2cb8
--- /dev/null
+++ b/include/configs/stm32mp1.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * Configuration settings for the STM32MP15x CPU
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <linux/sizes.h>
+#include <asm/arch/stm32.h>
+
+#define CONFIG_PREBOOT
+
+/*
+ * Number of clock ticks in 1 sec
+ */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_ARCH_TIMER
+#define CONFIG_SYS_HZ_CLOCK 64000000
+
+/*
+ * malloc() pool size
+ */
+#define CONFIG_SYS_MALLOC_LEN SZ_32M
+
+/*
+ * Configuration of the external SRAM memory used by U-Boot
+ */
+#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+/*
+ * Console I/O buffer size
+ */
+#define CONFIG_SYS_CBSIZE SZ_1K
+
+/*
+ * Needed by "loadb"
+ */
+#define CONFIG_SYS_LOAD_ADDR STM32_DDR_BASE
+
+/*
+ * Env parameters
+ */
+#define CONFIG_ENV_SIZE SZ_4K
+
+/* ATAGs */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* SPL support */
+#ifdef CONFIG_SPL
+/* BOOTROM load address */
+#define CONFIG_SPL_TEXT_BASE 0x2FFC2500
+/* SPL use DDR */
+#define CONFIG_SPL_BSS_START_ADDR 0xC0200000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START 0xC0300000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
+
+/* limit SYSRAM usage to first 128 KB */
+#define CONFIG_SPL_MAX_SIZE 0x00020000
+#define CONFIG_SPL_STACK (STM32_SYSRAM_BASE + \
+ STM32_SYSRAM_SIZE)
+#endif /* #ifdef CONFIG_SPL */
+
+/*MMC SD*/
+#define CONFIG_SYS_MMC_MAX_DEVICE 3
+
+#if !defined(CONFIG_SPL) || !defined(CONFIG_SPL_BUILD)
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ func(MMC, mmc, 2)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "scriptaddr=0xC0000000\0" \
+ "pxefile_addr_r=0xC0000000\0" \
+ "kernel_addr_r=0xC1000000\0" \
+ "fdt_addr_r=0xC4000000\0" \
+ "ramdisk_addr_r=0xC4100000\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ BOOTENV
+
+#endif /* ifndef CONFIG_SPL_BUILD */
+
+#endif /* __CONFIG_H */
diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h
new file mode 100644
index 0000000..1643158
--- /dev/null
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -0,0 +1,243 @@
+/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
+ */
+/* OSCILLATOR clocks */
+#define CK_HSE 0
+#define CK_CSI 1
+#define CK_LSI 2
+#define CK_LSE 3
+#define CK_HSI 4
+#define CK_HSE_DIV2 5
+
+/* Bus clocks */
+#define TIM2 6
+#define TIM3 7
+#define TIM4 8
+#define TIM5 9
+#define TIM6 10
+#define TIM7 11
+#define TIM12 12
+#define TIM13 13
+#define TIM14 14
+#define LPTIM1 15
+#define SPI2 16
+#define SPI3 17
+#define USART2 18
+#define USART3 19
+#define UART4 20
+#define UART5 21
+#define UART7 22
+#define UART8 23
+#define I2C1 24
+#define I2C2 25
+#define I2C3 26
+#define I2C5 27
+#define SPDIF 28
+#define CEC 29
+#define DAC12 30
+#define MDIO 31
+#define TIM1 32
+#define TIM8 33
+#define TIM15 34
+#define TIM16 35
+#define TIM17 36
+#define SPI1 37
+#define SPI4 38
+#define SPI5 39
+#define USART6 40
+#define SAI1 41
+#define SAI2 42
+#define SAI3 43
+#define DFSDM 44
+#define FDCAN 45
+#define LPTIM2 46
+#define LPTIM3 47
+#define LPTIM4 48
+#define LPTIM5 49
+#define SAI4 50
+#define SYSCFG 51
+#define VREF 52
+#define TMPSENS 53
+#define PMBCTRL 54
+#define HDP 55
+#define LTDC 56
+#define DSI 57
+#define IWDG2 58
+#define USBPHY 59
+#define STGENRO 60
+#define SPI6 61
+#define I2C4 62
+#define I2C6 63
+#define USART1 64
+#define RTCAPB 65
+#define TZC 66
+#define TZPC 67
+#define IWDG1 68
+#define BSEC 69
+#define STGEN 70
+#define DMA1 71
+#define DMA2 72
+#define DMAMUX 73
+#define ADC12 74
+#define USBO 75
+#define SDMMC3 76
+#define DCMI 77
+#define CRYP2 78
+#define HASH2 79
+#define RNG2 80
+#define CRC2 81
+#define HSEM 82
+#define IPCC 83
+#define GPIOA 84
+#define GPIOB 85
+#define GPIOC 86
+#define GPIOD 87
+#define GPIOE 88
+#define GPIOF 89
+#define GPIOG 90
+#define GPIOH 91
+#define GPIOI 92
+#define GPIOJ 93
+#define GPIOK 94
+#define GPIOZ 95
+#define CRYP1 96
+#define HASH1 97
+#define RNG1 98
+#define BKPSRAM 99
+#define MDMA 100
+#define DMA2D 101
+#define GPU 102
+#define ETHCK 103
+#define ETHTX 104
+#define ETHRX 105
+#define ETHMAC 106
+#define FMC 107
+#define QSPI 108
+#define SDMMC1 109
+#define SDMMC2 110
+#define CRC1 111
+#define USBH 112
+#define ETHSTP 113
+
+/* Kernel clocks */
+#define SDMMC1_K 114
+#define SDMMC2_K 115
+#define SDMMC3_K 116
+#define FMC_K 117
+#define QSPI_K 118
+#define ETHMAC_K 119
+#define RNG1_K 120
+#define RNG2_K 121
+#define GPU_K 122
+#define USBPHY_K 123
+#define STGEN_K 124
+#define SPDIF_K 125
+#define SPI1_K 126
+#define SPI2_K 127
+#define SPI3_K 128
+#define SPI4_K 129
+#define SPI5_K 130
+#define SPI6_K 131
+#define CEC_K 132
+#define I2C1_K 133
+#define I2C2_K 134
+#define I2C3_K 135
+#define I2C4_K 136
+#define I2C5_K 137
+#define I2C6_K 138
+#define LPTIM1_K 139
+#define LPTIM2_K 140
+#define LPTIM3_K 141
+#define LPTIM4_K 142
+#define LPTIM5_K 143
+#define USART1_K 144
+#define USART2_K 145
+#define USART3_K 146
+#define UART4_K 147
+#define UART5_K 148
+#define USART6_K 149
+#define UART7_K 150
+#define UART8_K 151
+#define DFSDM_K 152
+#define FDCAN_K 153
+#define SAI1_K 154
+#define SAI2_K 155
+#define SAI3_K 156
+#define SAI4_K 157
+#define ADC12_K 158
+#define DSI_K 159
+#define ADFSDM_K 160
+#define USBO_K 161
+#define LTDC_K 162
+
+/* PLL */
+#define PLL1 163
+#define PLL2 164
+#define PLL3 165
+#define PLL4 166
+
+/* ODF */
+#define PLL1_P 167
+#define PLL1_Q 168
+#define PLL1_R 169
+#define PLL2_P 170
+#define PLL2_Q 171
+#define PLL2_R 172
+#define PLL3_P 173
+#define PLL3_Q 174
+#define PLL3_R 175
+#define PLL4_P 176
+#define PLL4_Q 177
+#define PLL4_R 178
+
+/* AUX */
+#define RTC 179
+
+/* MCLK */
+#define CK_PER 180
+#define CK_MPU 181
+#define CK_AXI 182
+#define CK_MCU 183
+
+/* Time base */
+#define TIM2_K 184
+#define TIM3_K 185
+#define TIM4_K 186
+#define TIM5_K 187
+#define TIM6_K 188
+#define TIM7_K 189
+#define TIM12_K 190
+#define TIM13_K 191
+#define TIM14_K 192
+#define TIM1_K 193
+#define TIM8_K 194
+#define TIM15_K 195
+#define TIM16_K 196
+#define TIM17_K 197
+
+/* MCO clocks */
+#define CK_MCO1 198
+#define CK_MCO2 199
+
+/* TRACE & DEBUG clocks */
+#define DBG 200
+#define CK_DBG 201
+#define CK_TRACE 202
+
+/* DDR */
+#define DDRC1 203
+#define DDRC1LP 204
+#define DDRC2 205
+#define DDRC2LP 206
+#define DDRPHYC 207
+#define DDRPHYCLP 208
+#define DDRCAPB 209
+#define DDRCAPBLP 210
+#define AXIDCG 211
+#define DDRPHYCAPB 212
+#define DDRPHYCAPBLP 213
+#define DDRPERFM 214
+
+#define STM32MP1_LAST_CLK 215
diff --git a/include/dt-bindings/clock/stm32mp1-clksrc.h b/include/dt-bindings/clock/stm32mp1-clksrc.h
new file mode 100644
index 0000000..19fd959
--- /dev/null
+++ b/include/dt-bindings/clock/stm32mp1-clksrc.h
@@ -0,0 +1,284 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_
+#define _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_
+
+/* PLL output is enable when x=1, with x=p,q or r */
+#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2))
+
+/* st,clksrc: mandatory clock source */
+
+#define CLK_MPU_HSI 0x00000200
+#define CLK_MPU_HSE 0x00000201
+#define CLK_MPU_PLL1P 0x00000202
+#define CLK_MPU_PLL1P_DIV 0x00000203
+
+#define CLK_AXI_HSI 0x00000240
+#define CLK_AXI_HSE 0x00000241
+#define CLK_AXI_PLL2P 0x00000242
+
+#define CLK_MCU_HSI 0x00000480
+#define CLK_MCU_HSE 0x00000481
+#define CLK_MCU_CSI 0x00000482
+#define CLK_MCU_PLL3P 0x00000483
+
+#define CLK_PLL12_HSI 0x00000280
+#define CLK_PLL12_HSE 0x00000281
+
+#define CLK_PLL3_HSI 0x00008200
+#define CLK_PLL3_HSE 0x00008201
+#define CLK_PLL3_CSI 0x00008202
+
+#define CLK_PLL4_HSI 0x00008240
+#define CLK_PLL4_HSE 0x00008241
+#define CLK_PLL4_CSI 0x00008242
+#define CLK_PLL4_I2SCKIN 0x00008243
+
+#define CLK_RTC_DISABLED 0x00001400
+#define CLK_RTC_LSE 0x00001401
+#define CLK_RTC_LSI 0x00001402
+#define CLK_RTC_HSE 0x00001403
+
+#define CLK_MCO1_HSI 0x00008000
+#define CLK_MCO1_HSE 0x00008001
+#define CLK_MCO1_CSI 0x00008002
+#define CLK_MCO1_LSI 0x00008003
+#define CLK_MCO1_LSE 0x00008004
+#define CLK_MCO1_DISABLED 0x0000800F
+
+#define CLK_MCO2_MPU 0x00008040
+#define CLK_MCO2_AXI 0x00008041
+#define CLK_MCO2_MCU 0x00008042
+#define CLK_MCO2_PLL4P 0x00008043
+#define CLK_MCO2_HSE 0x00008044
+#define CLK_MCO2_HSI 0x00008045
+#define CLK_MCO2_DISABLED 0x0000804F
+
+/* st,pkcs: peripheral kernel clock source */
+
+#define CLK_I2C12_PCLK1 0x00008C00
+#define CLK_I2C12_PLL4R 0x00008C01
+#define CLK_I2C12_HSI 0x00008C02
+#define CLK_I2C12_CSI 0x00008C03
+#define CLK_I2C12_DISABLED 0x00008C07
+
+#define CLK_I2C35_PCLK1 0x00008C40
+#define CLK_I2C35_PLL4R 0x00008C41
+#define CLK_I2C35_HSI 0x00008C42
+#define CLK_I2C35_CSI 0x00008C43
+#define CLK_I2C35_DISABLED 0x00008C47
+
+#define CLK_I2C46_PCLK5 0x00000C00
+#define CLK_I2C46_PLL3Q 0x00000C01
+#define CLK_I2C46_HSI 0x00000C02
+#define CLK_I2C46_CSI 0x00000C03
+#define CLK_I2C46_DISABLED 0x00000C07
+
+#define CLK_SAI1_PLL4Q 0x00008C80
+#define CLK_SAI1_PLL3Q 0x00008C81
+#define CLK_SAI1_I2SCKIN 0x00008C82
+#define CLK_SAI1_CKPER 0x00008C83
+#define CLK_SAI1_PLL3R 0x00008C84
+#define CLK_SAI1_DISABLED 0x00008C87
+
+#define CLK_SAI2_PLL4Q 0x00008CC0
+#define CLK_SAI2_PLL3Q 0x00008CC1
+#define CLK_SAI2_I2SCKIN 0x00008CC2
+#define CLK_SAI2_CKPER 0x00008CC3
+#define CLK_SAI2_SPDIF 0x00008CC4
+#define CLK_SAI2_PLL3R 0x00008CC5
+#define CLK_SAI2_DISABLED 0x00008CC7
+
+#define CLK_SAI3_PLL4Q 0x00008D00
+#define CLK_SAI3_PLL3Q 0x00008D01
+#define CLK_SAI3_I2SCKIN 0x00008D02
+#define CLK_SAI3_CKPER 0x00008D03
+#define CLK_SAI3_PLL3R 0x00008D04
+#define CLK_SAI3_DISABLED 0x00008D07
+
+#define CLK_SAI4_PLL4Q 0x00008D40
+#define CLK_SAI4_PLL3Q 0x00008D41
+#define CLK_SAI4_I2SCKIN 0x00008D42
+#define CLK_SAI4_CKPER 0x00008D43
+#define CLK_SAI4_PLL3R 0x00008D44
+#define CLK_SAI4_DISABLED 0x00008D47
+
+#define CLK_SPI2S1_PLL4P 0x00008D80
+#define CLK_SPI2S1_PLL3Q 0x00008D81
+#define CLK_SPI2S1_I2SCKIN 0x00008D82
+#define CLK_SPI2S1_CKPER 0x00008D83
+#define CLK_SPI2S1_PLL3R 0x00008D84
+#define CLK_SPI2S1_DISABLED 0x00008D87
+
+#define CLK_SPI2S23_PLL4P 0x00008DC0
+#define CLK_SPI2S23_PLL3Q 0x00008DC1
+#define CLK_SPI2S23_I2SCKIN 0x00008DC2
+#define CLK_SPI2S23_CKPER 0x00008DC3
+#define CLK_SPI2S23_PLL3R 0x00008DC4
+#define CLK_SPI2S23_DISABLED 0x00008DC7
+
+#define CLK_SPI45_PCLK2 0x00008E00
+#define CLK_SPI45_PLL4Q 0x00008E01
+#define CLK_SPI45_HSI 0x00008E02
+#define CLK_SPI45_CSI 0x00008E03
+#define CLK_SPI45_HSE 0x00008E04
+#define CLK_SPI45_DISABLED 0x00008E07
+
+#define CLK_SPI6_PCLK5 0x00000C40
+#define CLK_SPI6_PLL4Q 0x00000C41
+#define CLK_SPI6_HSI 0x00000C42
+#define CLK_SPI6_CSI 0x00000C43
+#define CLK_SPI6_HSE 0x00000C44
+#define CLK_SPI6_PLL3Q 0x00000C45
+#define CLK_SPI6_DISABLED 0x00000C47
+
+#define CLK_UART6_PCLK2 0x00008E40
+#define CLK_UART6_PLL4Q 0x00008E41
+#define CLK_UART6_HSI 0x00008E42
+#define CLK_UART6_CSI 0x00008E43
+#define CLK_UART6_HSE 0x00008E44
+#define CLK_UART6_DISABLED 0x00008E47
+
+#define CLK_UART24_PCLK1 0x00008E80
+#define CLK_UART24_PLL4Q 0x00008E81
+#define CLK_UART24_HSI 0x00008E82
+#define CLK_UART24_CSI 0x00008E83
+#define CLK_UART24_HSE 0x00008E84
+#define CLK_UART24_DISABLED 0x00008E87
+
+#define CLK_UART35_PCLK1 0x00008EC0
+#define CLK_UART35_PLL4Q 0x00008EC1
+#define CLK_UART35_HSI 0x00008EC2
+#define CLK_UART35_CSI 0x00008EC3
+#define CLK_UART35_HSE 0x00008EC4
+#define CLK_UART35_DISABLED 0x00008EC7
+
+#define CLK_UART78_PCLK1 0x00008F00
+#define CLK_UART78_PLL4Q 0x00008F01
+#define CLK_UART78_HSI 0x00008F02
+#define CLK_UART78_CSI 0x00008F03
+#define CLK_UART78_HSE 0x00008F04
+#define CLK_UART78_DISABLED 0x00008F07
+
+#define CLK_UART1_PCLK5 0x00000C80
+#define CLK_UART1_PLL3Q 0x00000C81
+#define CLK_UART1_HSI 0x00000C82
+#define CLK_UART1_CSI 0x00000C83
+#define CLK_UART1_PLL4Q 0x00000C84
+#define CLK_UART1_HSE 0x00000C85
+#define CLK_UART1_DISABLED 0x00000C87
+
+#define CLK_SDMMC12_HCLK6 0x00008F40
+#define CLK_SDMMC12_PLL3R 0x00008F41
+#define CLK_SDMMC12_PLL4P 0x00008F42
+#define CLK_SDMMC12_HSI 0x00008F43
+#define CLK_SDMMC12_DISABLED 0x00008F47
+
+#define CLK_SDMMC3_HCLK2 0x00008F80
+#define CLK_SDMMC3_PLL3R 0x00008F81
+#define CLK_SDMMC3_PLL4P 0x00008F82
+#define CLK_SDMMC3_HSI 0x00008F83
+#define CLK_SDMMC3_DISABLED 0x00008F87
+
+#define CLK_ETH_PLL4P 0x00008FC0
+#define CLK_ETH_PLL3Q 0x00008FC1
+#define CLK_ETH_DISABLED 0x00008FC3
+
+#define CLK_QSPI_ACLK 0x00009000
+#define CLK_QSPI_PLL3R 0x00009001
+#define CLK_QSPI_PLL4P 0x00009002
+#define CLK_QSPI_CKPER 0x00009003
+
+#define CLK_FMC_ACLK 0x00009040
+#define CLK_FMC_PLL3R 0x00009041
+#define CLK_FMC_PLL4P 0x00009042
+#define CLK_FMC_CKPER 0x00009043
+
+#define CLK_FDCAN_HSE 0x000090C0
+#define CLK_FDCAN_PLL3Q 0x000090C1
+#define CLK_FDCAN_PLL4Q 0x000090C2
+#define CLK_FDCAN_PLL4R 0x000090C3
+
+#define CLK_SPDIF_PLL4P 0x00009140
+#define CLK_SPDIF_PLL3Q 0x00009141
+#define CLK_SPDIF_HSI 0x00009142
+#define CLK_SPDIF_DISABLED 0x00009143
+
+#define CLK_CEC_LSE 0x00009180
+#define CLK_CEC_LSI 0x00009181
+#define CLK_CEC_CSI_DIV122 0x00009182
+#define CLK_CEC_DISABLED 0x00009183
+
+#define CLK_USBPHY_HSE 0x000091C0
+#define CLK_USBPHY_PLL4R 0x000091C1
+#define CLK_USBPHY_HSE_DIV2 0x000091C2
+#define CLK_USBPHY_DISABLED 0x000091C3
+
+#define CLK_USBO_PLL4R 0x800091C0
+#define CLK_USBO_USBPHY 0x800091C1
+
+#define CLK_RNG1_CSI 0x00000CC0
+#define CLK_RNG1_PLL4R 0x00000CC1
+#define CLK_RNG1_LSE 0x00000CC2
+#define CLK_RNG1_LSI 0x00000CC3
+
+#define CLK_RNG2_CSI 0x00009200
+#define CLK_RNG2_PLL4R 0x00009201
+#define CLK_RNG2_LSE 0x00009202
+#define CLK_RNG2_LSI 0x00009203
+
+#define CLK_CKPER_HSI 0x00000D00
+#define CLK_CKPER_CSI 0x00000D01
+#define CLK_CKPER_HSE 0x00000D02
+#define CLK_CKPER_DISABLED 0x00000D03
+
+#define CLK_STGEN_HSI 0x00000D40
+#define CLK_STGEN_HSE 0x00000D41
+#define CLK_STGEN_DISABLED 0x00000D43
+
+#define CLK_DSI_DSIPLL 0x00009240
+#define CLK_DSI_PLL4P 0x00009241
+
+#define CLK_ADC_PLL4R 0x00009280
+#define CLK_ADC_CKPER 0x00009281
+#define CLK_ADC_PLL3Q 0x00009282
+#define CLK_ADC_DISABLED 0x00009283
+
+#define CLK_LPTIM45_PCLK3 0x000092C0
+#define CLK_LPTIM45_PLL4P 0x000092C1
+#define CLK_LPTIM45_PLL3Q 0x000092C2
+#define CLK_LPTIM45_LSE 0x000092C3
+#define CLK_LPTIM45_LSI 0x000092C4
+#define CLK_LPTIM45_CKPER 0x000092C5
+#define CLK_LPTIM45_DISABLED 0x000092C7
+
+#define CLK_LPTIM23_PCLK3 0x00009300
+#define CLK_LPTIM23_PLL4Q 0x00009301
+#define CLK_LPTIM23_CKPER 0x00009302
+#define CLK_LPTIM23_LSE 0x00009303
+#define CLK_LPTIM23_LSI 0x00009304
+#define CLK_LPTIM23_DISABLED 0x00009307
+
+#define CLK_LPTIM1_PCLK1 0x00009340
+#define CLK_LPTIM1_PLL4P 0x00009341
+#define CLK_LPTIM1_PLL3Q 0x00009342
+#define CLK_LPTIM1_LSE 0x00009343
+#define CLK_LPTIM1_LSI 0x00009344
+#define CLK_LPTIM1_CKPER 0x00009345
+#define CLK_LPTIM1_DISABLED 0x00009347
+
+/* define for st,pll /csg */
+#define SSCG_MODE_CENTER_SPREAD 0
+#define SSCG_MODE_DOWN_SPREAD 1
+
+/* define for st,drive */
+#define LSEDRV_LOWEST 0
+#define LSEDRV_MEDIUM_LOW 1
+#define LSEDRV_MEDIUM_HIGH 2
+#define LSEDRV_HIGHEST 3
+
+#endif
diff --git a/include/dt-bindings/reset-controller/stm32mp1-resets.h b/include/dt-bindings/reset-controller/stm32mp1-resets.h
new file mode 100644
index 0000000..f279f8f
--- /dev/null
+++ b/include/dt-bindings/reset-controller/stm32mp1-resets.h
@@ -0,0 +1,97 @@
+#define LTDC_R 3072
+#define DSI_R 3076
+#define DDRPERFM_R 3080
+#define USBPHY_R 3088
+#define SPI6_R 3136
+#define I2C4_R 3138
+#define I2C6_R 3139
+#define USART1_R 3140
+#define STGEN_R 3156
+#define GPIOZ_R 3200
+#define CRYP1_R 3204
+#define HASH1_R 3205
+#define RNG1_R 3206
+#define AXIM_R 3216
+#define GPU_R 3269
+#define ETHMAC_R 3274
+#define FMC_R 3276
+#define QSPI_R 3278
+#define SDMMC1_R 3280
+#define SDMMC2_R 3281
+#define CRC1_R 3284
+#define USBH_R 3288
+#define MDMA_R 3328
+#define MCU_R 8225
+#define TIM2_R 19456
+#define TIM3_R 19457
+#define TIM4_R 19458
+#define TIM5_R 19459
+#define TIM6_R 19460
+#define TIM7_R 19461
+#define TIM12_R 16462
+#define TIM13_R 16463
+#define TIM14_R 16464
+#define LPTIM1_R 19465
+#define SPI2_R 19467
+#define SPI3_R 19468
+#define USART2_R 19470
+#define USART3_R 19471
+#define UART4_R 19472
+#define UART5_R 19473
+#define UART7_R 19474
+#define UART8_R 19475
+#define I2C1_R 19477
+#define I2C2_R 19478
+#define I2C3_R 19479
+#define I2C5_R 19480
+#define SPDIF_R 19482
+#define CEC_R 19483
+#define DAC12_R 19485
+#define MDIO_R 19847
+#define TIM1_R 19520
+#define TIM8_R 19521
+#define TIM15_R 19522
+#define TIM16_R 19523
+#define TIM17_R 19524
+#define SPI1_R 19528
+#define SPI4_R 19529
+#define SPI5_R 19530
+#define USART6_R 19533
+#define SAI1_R 19536
+#define SAI2_R 19537
+#define SAI3_R 19538
+#define DFSDM_R 19540
+#define FDCAN_R 19544
+#define LPTIM2_R 19584
+#define LPTIM3_R 19585
+#define LPTIM4_R 19586
+#define LPTIM5_R 19587
+#define SAI4_R 19592
+#define SYSCFG_R 19595
+#define VREF_R 19597
+#define TMPSENS_R 19600
+#define PMBCTRL_R 19601
+#define DMA1_R 19648
+#define DMA2_R 19649
+#define DMAMUX_R 19650
+#define ADC12_R 19653
+#define USBO_R 19656
+#define SDMMC3_R 19664
+#define CAMITF_R 19712
+#define CRYP2_R 19716
+#define HASH2_R 19717
+#define RNG2_R 19718
+#define CRC2_R 19719
+#define HSEM_R 19723
+#define MBOX_R 19724
+#define GPIOA_R 19776
+#define GPIOB_R 19777
+#define GPIOC_R 19778
+#define GPIOD_R 19779
+#define GPIOE_R 19780
+#define GPIOF_R 19781
+#define GPIOG_R 19782
+#define GPIOH_R 19783
+#define GPIOI_R 19784
+#define GPIOJ_R 19785
+#define GPIOK_R 19786
diff --git a/include/image.h b/include/image.h
index dbdaecb..621abf6 100644
--- a/include/image.h
+++ b/include/image.h
@@ -153,6 +153,7 @@
IH_OS_PLAN9, /* Plan 9 */
IH_OS_OPENRTOS, /* OpenRTOS */
IH_OS_ARM_TRUSTED_FIRMWARE, /* ARM Trusted Firmware */
+ IH_OS_TEE, /* Trusted Execution Environment */
IH_OS_COUNT,
};
@@ -272,6 +273,7 @@
IH_TYPE_TEE, /* Trusted Execution Environment OS Image */
IH_TYPE_FIRMWARE_IVT, /* Firmware Image with HABv4 IVT */
IH_TYPE_PMMC, /* TI Power Management Micro-Controller Firmware */
+ IH_TYPE_STM32IMAGE, /* STMicroelectronics STM32 Image */
IH_TYPE_COUNT, /* Number of image types */
};
@@ -1013,6 +1015,8 @@
const char *comment, int require_keys,
const char *engine_id);
+int fit_image_verify_with_data(const void *fit, int image_noffset,
+ const void *data, size_t size);
int fit_image_verify(const void *fit, int noffset);
int fit_config_verify(const void *fit, int conf_noffset);
int fit_all_image_verify(const void *fit);
diff --git a/include/init.h b/include/init.h
new file mode 100644
index 0000000..147ae6b
--- /dev/null
+++ b/include/init.h
@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copy the startup prototype, previously defined in common.h
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __INIT_H_
+#define __INIT_H_ 1
+
+#ifndef __ASSEMBLY__ /* put C only stuff in this section */
+
+/*
+ * Function Prototypes
+ */
+
+/* common/board_f.c */
+void board_init_f(ulong dummy);
+
+/**
+ * arch_cpu_init() - basic cpu-dependent setup for an architecture
+ *
+ * This is called after early malloc is available. It should handle any
+ * CPU- or SoC- specific init needed to continue the init sequence. See
+ * board_f.c for where it is called. If this is not provided, a default
+ * version (which does nothing) will be used.
+ *
+ * @return: 0 on success, otherwise error
+ */
+int arch_cpu_init(void);
+
+/**
+ * arch_cpu_init_dm() - init CPU after driver model is available
+ *
+ * This is called immediately after driver model is available before
+ * relocation. This is similar to arch_cpu_init() but is able to reference
+ * devices
+ *
+ * @return 0 if OK, -ve on error
+ */
+int arch_cpu_init_dm(void);
+
+/**
+ * mach_cpu_init() - SoC/machine dependent CPU setup
+ *
+ * This is called after arch_cpu_init(). It should handle any
+ * SoC or machine specific init needed to continue the init sequence. See
+ * board_f.c for where it is called. If this is not provided, a default
+ * version (which does nothing) will be used.
+ *
+ * @return: 0 on success, otherwise error
+ */
+int mach_cpu_init(void);
+
+/**
+ * arch_fsp_init() - perform firmware support package init
+ *
+ * Where U-Boot relies on binary blobs to handle part of the system init, this
+ * function can be used to set up the blobs. This is used on some Intel
+ * platforms.
+ */
+int arch_fsp_init(void);
+
+int dram_init(void);
+
+/**
+ * dram_init_banksize() - Set up DRAM bank sizes
+ *
+ * This can be implemented by boards to set up the DRAM bank information in
+ * gd->bd->bi_dram(). It is called just before relocation, after dram_init()
+ * is called.
+ *
+ * If this is not provided, a default implementation will try to set up a
+ * single bank. It will do this if CONFIG_NR_DRAM_BANKS and
+ * CONFIG_SYS_SDRAM_BASE are set. The bank will have a start address of
+ * CONFIG_SYS_SDRAM_BASE and the size will be determined by a call to
+ * get_effective_memsize().
+ *
+ * @return 0 if OK, -ve on error
+ */
+int dram_init_banksize(void);
+
+/**
+ * Reserve all necessary stacks
+ *
+ * This is used in generic board init sequence in common/board_f.c. Each
+ * architecture could provide this function to tailor the required stacks.
+ *
+ * On entry gd->start_addr_sp is pointing to the suggested top of the stack.
+ * The callee ensures gd->start_add_sp is 16-byte aligned, so architectures
+ * require only this can leave it untouched.
+ *
+ * On exit gd->start_addr_sp and gd->irq_sp should be set to the respective
+ * positions of the stack. The stack pointer(s) will be set to this later.
+ * gd->irq_sp is only required, if the architecture needs it.
+ *
+ * @return 0 if no error
+ */
+int arch_reserve_stacks(void);
+
+/**
+ * init_cache_f_r() - Turn on the cache in preparation for relocation
+ *
+ * @return 0 if OK, -ve on error
+ */
+int init_cache_f_r(void);
+
+int print_cpuinfo(void);
+int timer_init(void);
+int reserve_mmu(void);
+int misc_init_f(void);
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void);
+#endif
+
+/* common/init/board_init.c */
+extern ulong monitor_flash_len;
+
+/**
+ * ulong board_init_f_alloc_reserve - allocate reserved area
+ *
+ * This function is called by each architecture very early in the start-up
+ * code to allow the C runtime to reserve space on the stack for writable
+ * 'globals' such as GD and the malloc arena.
+ *
+ * @top: top of the reserve area, growing down.
+ * @return: bottom of reserved area
+ */
+ulong board_init_f_alloc_reserve(ulong top);
+
+/**
+ * board_init_f_init_reserve - initialize the reserved area(s)
+ *
+ * This function is called once the C runtime has allocated the reserved
+ * area on the stack. It must initialize the GD at the base of that area.
+ *
+ * @base: top from which reservation was done
+ */
+void board_init_f_init_reserve(ulong base);
+
+/**
+ * arch_setup_gd() - Set up the global_data pointer
+ *
+ * This pointer is special in some architectures and cannot easily be assigned
+ * to. For example on x86 it is implemented by adding a specific record to its
+ * Global Descriptor Table! So we we provide a function to carry out this task.
+ * For most architectures this can simply be:
+ *
+ * gd = gd_ptr;
+ *
+ * @gd_ptr: Pointer to global data
+ */
+void arch_setup_gd(gd_t *gd_ptr);
+
+/* common/board_r.c */
+void board_init_r(gd_t *id, ulong dest_addr) __attribute__ ((noreturn));
+
+int cpu_init_r(void);
+int last_stage_init(void);
+int mac_read_from_eeprom(void);
+int set_cpu_clk_info(void);
+int update_flash_size(int flash_size);
+int arch_early_init_r(void);
+void pci_init(void);
+int misc_init_r(void);
+#if defined(CONFIG_VID)
+int init_func_vid(void);
+#endif
+
+/* common/board_info.c */
+int checkboard(void);
+int show_board_info(void);
+
+#endif /* __ASSEMBLY__ */
+/* Put only stuff here that the assembler can digest */
+
+#endif /* __INIT_H_ */
diff --git a/include/init_helpers.h b/include/init_helpers.h
deleted file mode 100644
index 3efcfdd..0000000
--- a/include/init_helpers.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * (C) Copyright 2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _INIT_HELPERS_H_
-#define _INIT_HELPERS_H_
-
-/**
- * init_cache_f_r() - Turn on the cache in preparation for relocation
- *
- * @return 0 if OK, -ve on error
- */
-int init_cache_f_r(void);
-
-#endif /* _INIT_HELPERS_H_ */
diff --git a/include/pci.h b/include/pci.h
index 7adc043..31dc760 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -585,8 +585,6 @@
/* Used by auto config */
struct pci_region *pci_mem, *pci_io, *pci_prefetch;
- /* Used by ppc405 autoconfig*/
- struct pci_region *pci_fb;
#ifndef CONFIG_DM_PCI
int current_busno;
diff --git a/include/power/stpmu1.h b/include/power/stpmu1.h
new file mode 100644
index 0000000..697e245
--- /dev/null
+++ b/include/power/stpmu1.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#ifndef __PMIC_STPMU1_H_
+#define __PMIC_STPMU1_H_
+
+#define STPMU1_MASK_RESET_BUCK 0x18
+#define STPMU1_BUCKX_CTRL_REG(buck) (0x20 + (buck))
+#define STPMU1_VREF_CTRL_REG 0x24
+#define STPMU1_LDOX_CTRL_REG(ldo) (0x25 + (ldo))
+#define STPMU1_USB_CTRL_REG 0x40
+#define STPMU1_NVM_USER_STATUS_REG 0xb8
+#define STPMU1_NVM_USER_CONTROL_REG 0xb9
+
+#define STPMU1_MASK_RESET_BUCK3 BIT(2)
+
+#define STPMU1_BUCK_EN BIT(0)
+#define STPMU1_BUCK_MODE BIT(1)
+#define STPMU1_BUCK_OUTPUT_MASK GENMASK(7, 2)
+#define STPMU1_BUCK_OUTPUT_SHIFT 2
+#define STPMU1_BUCK2_1200000V (24 << STPMU1_BUCK_OUTPUT_SHIFT)
+#define STPMU1_BUCK2_1350000V (30 << STPMU1_BUCK_OUTPUT_SHIFT)
+#define STPMU1_BUCK3_1800000V (39 << STPMU1_BUCK_OUTPUT_SHIFT)
+
+#define STPMU1_VREF_EN BIT(0)
+
+#define STPMU1_LDO_EN BIT(0)
+#define STPMU1_LDO12356_OUTPUT_MASK GENMASK(6, 2)
+#define STPMU1_LDO12356_OUTPUT_SHIFT 2
+#define STPMU1_LDO3_MODE BIT(7)
+#define STPMU1_LDO3_DDR_SEL 31
+#define STPMU1_LDO3_1800000 (9 << STPMU1_LDO12356_OUTPUT_SHIFT)
+#define STPMU1_LDO4_UV 3300000
+
+#define STPMU1_USB_BOOST_EN BIT(0)
+#define STPMU1_USB_PWR_SW_EN GENMASK(2, 1)
+
+#define STPMU1_NVM_USER_CONTROL_PROGRAM BIT(0)
+#define STPMU1_NVM_USER_CONTROL_READ BIT(1)
+
+#define STPMU1_NVM_USER_STATUS_BUSY BIT(0)
+#define STPMU1_NVM_USER_STATUS_ERROR BIT(1)
+
+#define STPMU1_DEFAULT_START_UP_DELAY_MS 1
+#define STPMU1_USB_BOOST_START_UP_DELAY_MS 10
+
+enum {
+ STPMU1_BUCK1,
+ STPMU1_BUCK2,
+ STPMU1_BUCK3,
+ STPMU1_BUCK4,
+ STPMU1_MAX_BUCK,
+};
+
+enum {
+ STPMU1_BUCK_MODE_HP,
+ STPMU1_BUCK_MODE_LP,
+};
+
+enum {
+ STPMU1_LDO1,
+ STPMU1_LDO2,
+ STPMU1_LDO3,
+ STPMU1_LDO4,
+ STPMU1_LDO5,
+ STPMU1_LDO6,
+ STPMU1_MAX_LDO,
+};
+
+enum {
+ STPMU1_LDO_MODE_NORMAL,
+ STPMU1_LDO_MODE_BYPASS,
+ STPMU1_LDO_MODE_SINK_SOURCE,
+};
+
+enum {
+ STPMU1_PWR_SW1,
+ STPMU1_PWR_SW2,
+ STPMU1_MAX_PWR_SW,
+};
+
+#endif
diff --git a/include/st_logo_data.h b/include/st_logo_data.h
new file mode 100644
index 0000000..4d3a26e
--- /dev/null
+++ b/include/st_logo_data.h
@@ -0,0 +1,3267 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
+ * Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/*
+ * file generated from picture
+ * tools/logos/stmicroelectronics_uboot_logo_8bit_rle.bmp
+ */
+
+unsigned char stmicroelectronics_uboot_logo_8bit_rle[] = {
+0x42, 0x4d, 0x5c, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7a, 0x04,
+0x00, 0x00, 0x6c, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x60, 0x01,
+0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0xe2, 0x93,
+0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x01,
+0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x42, 0x47, 0x52, 0x73, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0xff, 0xff, 0xff, 0x00, 0xae, 0x82, 0x3a, 0x00, 0xa5, 0x7b,
+0x37, 0x00, 0xfe, 0xfe, 0xfe, 0x00, 0xac, 0x80, 0x39, 0x00, 0x4e, 0x1b,
+0x02, 0x00, 0xb7, 0x88, 0x3b, 0x00, 0x4f, 0x1c, 0x02, 0x00, 0xb3, 0x85,
+0x3a, 0x00, 0xe1, 0xaa, 0x35, 0x00, 0x86, 0x62, 0x1f, 0x00, 0x65, 0x4a,
+0x13, 0x00, 0xa9, 0x7e, 0x38, 0x00, 0xff, 0xfe, 0xff, 0x00, 0x77, 0x55,
+0x13, 0x00, 0xbe, 0x91, 0x47, 0x00, 0xbc, 0x8d, 0x3d, 0x00, 0xfe, 0xfd,
+0xfd, 0x00, 0xa3, 0x7a, 0x38, 0x00, 0xbd, 0x8e, 0x42, 0x00, 0xa7, 0x7d,
+0x39, 0x00, 0x72, 0x52, 0x14, 0x00, 0xbc, 0x8d, 0x40, 0x00, 0x84, 0x60,
+0x1e, 0x00, 0xba, 0x8a, 0x3c, 0x00, 0x75, 0x53, 0x13, 0x00, 0x87, 0x62,
+0x11, 0x00, 0x85, 0x60, 0x10, 0x00, 0x7e, 0x5b, 0x12, 0x00, 0xb4, 0x86,
+0x3a, 0x00, 0x8c, 0x6a, 0x35, 0x00, 0xb1, 0x84, 0x3b, 0x00, 0xaa, 0x7f,
+0x3a, 0x00, 0xbc, 0x8c, 0x3c, 0x00, 0x85, 0x64, 0x34, 0x00, 0xb9, 0x89,
+0x3b, 0x00, 0x93, 0x69, 0x0e, 0x00, 0x8d, 0x65, 0x0e, 0x00, 0xfd, 0xfd,
+0xfc, 0x00, 0xa0, 0x78, 0x37, 0x00, 0x81, 0x5d, 0x12, 0x00, 0x9e, 0x76,
+0x36, 0x00, 0xbe, 0x90, 0x45, 0x00, 0x94, 0x6a, 0x0b, 0x00, 0x8b, 0x64,
+0x10, 0x00, 0x68, 0x4c, 0x14, 0x00, 0x8b, 0x69, 0x35, 0x00, 0x82, 0x5e,
+0x11, 0x00, 0x90, 0x6c, 0x35, 0x00, 0x89, 0x63, 0x0f, 0x00, 0xaf, 0x83,
+0x39, 0x00, 0xa2, 0x75, 0x06, 0x00, 0x96, 0x6b, 0x0d, 0x00, 0x7b, 0x59,
+0x12, 0x00, 0x9c, 0x70, 0x08, 0x00, 0x99, 0x73, 0x37, 0x00, 0xb0, 0x83,
+0x39, 0x00, 0x84, 0x60, 0x11, 0x00, 0x80, 0x5c, 0x14, 0x00, 0x91, 0x68,
+0x0c, 0x00, 0x6a, 0x4d, 0x14, 0x00, 0xc3, 0x99, 0x54, 0x00, 0x92, 0x6e,
+0x36, 0x00, 0x9a, 0x6e, 0x0b, 0x00, 0x8a, 0x68, 0x34, 0x00, 0xc0, 0x94,
+0x4b, 0x00, 0x98, 0x6c, 0x09, 0x00, 0x8f, 0x67, 0x0f, 0x00, 0x82, 0x62,
+0x34, 0x00, 0x7d, 0x5a, 0x15, 0x00, 0xc5, 0x9f, 0x5f, 0x00, 0xbb, 0x8b,
+0x3b, 0x00, 0xc8, 0xa7, 0x6a, 0x00, 0xc0, 0x95, 0x4e, 0x00, 0x87, 0x66,
+0x34, 0x00, 0x9f, 0x72, 0x06, 0x00, 0xbf, 0x93, 0x49, 0x00, 0xfd, 0xfb,
+0xfc, 0x00, 0xc7, 0xa4, 0x66, 0x00, 0x7a, 0x57, 0x13, 0x00, 0xc4, 0x9d,
+0x5a, 0x00, 0x83, 0x5f, 0x13, 0x00, 0x9c, 0x75, 0x36, 0x00, 0x7f, 0x60,
+0x32, 0x00, 0xb5, 0x87, 0x3c, 0x00, 0xc3, 0x9b, 0x57, 0x00, 0xc8, 0xa5,
+0x69, 0x00, 0x72, 0x55, 0x25, 0x00, 0xb9, 0x8a, 0x3a, 0x00, 0x94, 0x70,
+0x36, 0x00, 0xa2, 0x79, 0x36, 0x00, 0x7f, 0x5c, 0x12, 0x00, 0x97, 0x72,
+0x37, 0x00, 0x6c, 0x4e, 0x14, 0x00, 0xc5, 0x9e, 0x5d, 0x00, 0xca, 0xa9,
+0x6c, 0x00, 0xc5, 0xa3, 0x64, 0x00, 0x9e, 0x72, 0x0b, 0x00, 0xad, 0x81,
+0x3a, 0x00, 0x8e, 0x6b, 0x36, 0x00, 0xc6, 0xa1, 0x62, 0x00, 0x7c, 0x5f,
+0x31, 0x00, 0x6f, 0x50, 0x14, 0x00, 0xc1, 0x96, 0x50, 0x00, 0xd9, 0xc4,
+0x9f, 0x00, 0xcd, 0xbe, 0xa9, 0x00, 0xaa, 0x98, 0x7f, 0x00, 0xf6, 0xf3,
+0xf1, 0x00, 0xb9, 0x9b, 0x62, 0x00, 0x6a, 0x4c, 0x19, 0x00, 0x76, 0x59,
+0x29, 0x00, 0x79, 0x57, 0x15, 0x00, 0x6e, 0x4f, 0x13, 0x00, 0xfb, 0xf9,
+0xf9, 0x00, 0xae, 0x8d, 0x53, 0x00, 0x78, 0x5c, 0x2e, 0x00, 0xb2, 0x91,
+0x55, 0x00, 0xe8, 0xe1, 0xdc, 0x00, 0x8b, 0x69, 0x2e, 0x00, 0xc0, 0x9f,
+0x62, 0x00, 0xc1, 0x97, 0x52, 0x00, 0x52, 0x20, 0x06, 0x00, 0xbe, 0x9c,
+0x60, 0x00, 0xa1, 0x79, 0x38, 0x00, 0xed, 0xe8, 0xe5, 0x00, 0xdc, 0xc8,
+0xa6, 0x00, 0xd6, 0xca, 0xb9, 0x00, 0x80, 0x5e, 0x1d, 0x00, 0xb6, 0x95,
+0x58, 0x00, 0xb5, 0x97, 0x60, 0x00, 0x92, 0x75, 0x41, 0x00, 0x6f, 0x51,
+0x1d, 0x00, 0xc9, 0xba, 0xb2, 0x00, 0xa2, 0x88, 0x7b, 0x00, 0x82, 0x5e,
+0x1a, 0x00, 0x89, 0x67, 0x56, 0x00, 0xb0, 0x93, 0x5d, 0x00, 0x67, 0x4a,
+0x00, 0x00, 0xad, 0x9c, 0x81, 0x00, 0xd1, 0xbc, 0x9a, 0x00, 0x84, 0x64,
+0x2c, 0x00, 0x6e, 0x53, 0x25, 0x00, 0xf2, 0xee, 0xeb, 0x00, 0xbe, 0xa0,
+0x69, 0x00, 0xd5, 0xbf, 0x9b, 0x00, 0xba, 0x99, 0x5c, 0x00, 0x5a, 0x2a,
+0x12, 0x00, 0x7d, 0x5e, 0x29, 0x00, 0xbc, 0xa9, 0x9f, 0x00, 0x56, 0x24,
+0x0b, 0x00, 0xd0, 0xc2, 0xba, 0x00, 0x64, 0x37, 0x21, 0x00, 0x6a, 0x3f,
+0x29, 0x00, 0xd6, 0xcb, 0xc4, 0x00, 0xe4, 0xdc, 0xd7, 0x00, 0x6f, 0x45,
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+0x01, 0x67, 0x01, 0x49, 0x03, 0x67, 0x04, 0x78, 0x06, 0x3d, 0x06, 0x55,
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+0x78, 0x3d, 0x3d, 0x00, 0x03, 0x78, 0x03, 0x67, 0x04, 0x49, 0x05, 0x41,
+0x01, 0x4c, 0x01, 0x4c, 0x06, 0x0f, 0x03, 0x2a, 0x05, 0x13, 0x03, 0x16,
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+0x01, 0x23, 0x03, 0x06, 0x03, 0x54, 0x01, 0x1d, 0x01, 0x1d, 0x04, 0x08,
+0x00, 0x05, 0x1f, 0x38, 0x38, 0x32, 0x32, 0x00, 0x03, 0x01, 0x01, 0x62,
+0x03, 0x04, 0x03, 0x20, 0x03, 0x0c, 0x04, 0x14, 0x00, 0x0a, 0x02, 0x5a,
+0xaa, 0x91, 0x6c, 0x6c, 0x81, 0xd9, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00,
+0x87, 0x00, 0x00, 0x05, 0xb2, 0xea, 0xa8, 0xb4, 0xb4, 0x00, 0x03, 0xaf,
+0x01, 0xa8, 0x03, 0xaf, 0x00, 0x04, 0xb4, 0xb4, 0x12, 0x7b, 0x03, 0x5a,
+0x01, 0x02, 0x01, 0x12, 0x04, 0x02, 0x01, 0x14, 0x01, 0x14, 0x04, 0x0c,
+0x01, 0x20, 0x01, 0x20, 0x04, 0x04, 0x03, 0x01, 0x00, 0x05, 0x32, 0x32,
+0x38, 0x38, 0x1f, 0x00, 0x05, 0x08, 0x00, 0x03, 0x1d, 0x54, 0x1d, 0x00,
+0x03, 0x06, 0x03, 0x23, 0x01, 0x18, 0x01, 0x18, 0x03, 0x47, 0x01, 0x21,
+0x01, 0x47, 0x04, 0x21, 0x00, 0x04, 0x10, 0x10, 0x16, 0x16, 0x04, 0x13,
+0x04, 0x2a, 0x05, 0x0f, 0x01, 0x4c, 0x01, 0x4c, 0x05, 0x41, 0x04, 0x49,
+0x04, 0x67, 0x01, 0x78, 0x01, 0x78, 0x08, 0x3d, 0x05, 0x55, 0x05, 0x50,
+0x04, 0x5e, 0x07, 0x46, 0x04, 0x64, 0x08, 0x4e, 0x03, 0x56, 0x13, 0x48,
+0x06, 0x56, 0x06, 0x4e, 0x01, 0x64, 0x01, 0x4e, 0x04, 0x64, 0x07, 0x46,
+0x05, 0x5e, 0x04, 0x50, 0x04, 0x55, 0x01, 0x3d, 0x01, 0x55, 0x03, 0x3d,
+0x06, 0x78, 0x04, 0x67, 0x01, 0x49, 0x01, 0x49, 0x05, 0x41, 0x03, 0x4c,
+0x05, 0x0f, 0x04, 0x2a, 0x03, 0x13, 0x04, 0x16, 0x00, 0x04, 0x10, 0x10,
+0x21, 0x21, 0x05, 0x47, 0x01, 0x58, 0x01, 0x58, 0x03, 0x23, 0x04, 0x06,
+0x04, 0x1d, 0x04, 0x08, 0x03, 0x38, 0x00, 0x03, 0x32, 0x01, 0x01, 0x00,
+0x05, 0x04, 0x06, 0x0c, 0x07, 0x02, 0x00, 0x08, 0x5a, 0x5a, 0x74, 0x8f,
+0x8f, 0x80, 0xd0, 0x4d, 0x29, 0x00, 0x00, 0x00, 0x85, 0x00, 0x00, 0x07,
+0x03, 0x00, 0x00, 0x0d, 0x75, 0x8b, 0x88, 0x00, 0x04, 0xaf, 0x06, 0xa8,
+0x03, 0xaf, 0x03, 0xaa, 0x03, 0x14, 0x0c, 0xaa, 0x01, 0x62, 0x06, 0x01,
+0x07, 0x1f, 0x06, 0x54, 0x01, 0x06, 0x04, 0xb7, 0x03, 0x18, 0x03, 0x16,
+0x01, 0x10, 0x03, 0x16, 0x04, 0xf3, 0x00, 0x04, 0x13, 0xf3, 0xf3, 0x2a,
+0x08, 0x0f, 0x00, 0x05, 0x4c, 0x4c, 0xfb, 0xfb, 0x41, 0x00, 0x06, 0x49,
+0x01, 0x67, 0x01, 0x67, 0x09, 0x78, 0x03, 0x3d, 0x07, 0x55, 0x05, 0x50,
+0x06, 0x5e, 0x06, 0x46, 0x03, 0x64, 0x05, 0x60, 0x07, 0x4e, 0x10, 0x56,
+0x04, 0x4e, 0x00, 0x04, 0x60, 0x60, 0x4e, 0x4e, 0x04, 0x60, 0x04, 0x64,
+0x0a, 0x46, 0x01, 0x5e, 0x01, 0x5e, 0x05, 0x50, 0x07, 0x55, 0x03, 0x3d,
+0x00, 0x03, 0x78, 0x3d, 0x3d, 0x00, 0x07, 0x78, 0x01, 0x67, 0x01, 0x67,
+0x06, 0x49, 0x01, 0x41, 0x07, 0x4c, 0x05, 0x0f, 0x03, 0x2a, 0x06, 0x13,
+0x06, 0x16, 0x00, 0x03, 0xb7, 0xb7, 0x16, 0x00, 0x08, 0xb7, 0x06, 0x54,
+0x08, 0x1f, 0x04, 0x01, 0x00, 0x04, 0x62, 0xaa, 0x62, 0xaa, 0x03, 0x20,
+0x03, 0xaa, 0x00, 0x0b, 0x14, 0x14, 0x02, 0xf8, 0x8f, 0xcc, 0x8f, 0xcc,
+0xe7, 0x00, 0x03, 0x00, 0x27, 0x00, 0x00, 0x00, 0x86, 0x00, 0x01, 0x0d,
+0x01, 0x11, 0x03, 0x00, 0x00, 0x05, 0x6b, 0x7e, 0xcf, 0x88, 0xa8, 0x00,
+0x03, 0xaf, 0x03, 0xa8, 0x03, 0x72, 0x06, 0xa8, 0x00, 0x06, 0x72, 0xa8,
+0xa8, 0x72, 0x72, 0xa8, 0x23, 0x72, 0x1d, 0x74, 0x13, 0x80, 0x00, 0x04,
+0x81, 0x80, 0x80, 0x81, 0x04, 0x80, 0x1b, 0x81, 0x00, 0x04, 0x91, 0x91,
+0x81, 0x91, 0x34, 0x6c, 0x03, 0x7a, 0x01, 0x6c, 0x22, 0x7a, 0x03, 0x77,
+0x00, 0x03, 0x7a, 0x7a, 0x77, 0x00, 0x03, 0x7a, 0x05, 0x77, 0x01, 0x7a,
+0x2a, 0x77, 0x03, 0xcc, 0x00, 0x04, 0x91, 0xd9, 0x00, 0x03, 0x27, 0x00,
+0x00, 0x00, 0x8e, 0x00, 0x00, 0x0b, 0x8e, 0x7e, 0xea, 0x8f, 0x88, 0xa8,
+0xaf, 0xaf, 0xa8, 0x72, 0x72, 0x00, 0x3d, 0x88, 0x2c, 0x81, 0x01, 0x6c,
+0x09, 0x81, 0x01, 0x6c, 0x03, 0x81, 0x2e, 0x6c, 0x28, 0x8f, 0x1c, 0xcc,
+0x01, 0xa7, 0x03, 0xcc, 0x00, 0x05, 0xa7, 0xcc, 0xa7, 0xa7, 0xcc, 0x00,
+0x14, 0xa7, 0x13, 0x9d, 0x00, 0x07, 0xa7, 0x9d, 0x9d, 0x77, 0xec, 0x00,
+0x03, 0x00, 0x27, 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x08, 0x6b, 0xb2,
+0x7d, 0xd0, 0xea, 0xcc, 0x81, 0x88, 0x12, 0xc1, 0x00, 0x03, 0x72, 0x72,
+0xc1, 0x00, 0x24, 0x72, 0x01, 0x74, 0x03, 0x72, 0x01, 0x74, 0x01, 0x72,
+0x27, 0x74, 0x2c, 0x80, 0x01, 0x91, 0x01, 0x80, 0x23, 0x91, 0x05, 0x7a,
+0x01, 0x91, 0x18, 0x7a, 0x04, 0x77, 0x01, 0x7a, 0x1b, 0x77, 0x01, 0x60,
+0x01, 0x64, 0x24, 0x60, 0x00, 0x05, 0x77, 0xfa, 0x6b, 0x00, 0x0d, 0x00,
+0x27, 0x00, 0x00, 0x00, 0x95, 0x00, 0x00, 0x08, 0x71, 0x7c, 0xe7, 0xec,
+0x7e, 0x7d, 0x68, 0x90, 0x45, 0x8b, 0x00, 0x03, 0x90, 0x90, 0x8b, 0x00,
+0x2b, 0x90, 0x01, 0x68, 0x04, 0x90, 0x4d, 0x68, 0x00, 0x03, 0x7d, 0x7d,
+0x68, 0x00, 0x4f, 0x7d, 0x00, 0x04, 0xd9, 0x8e, 0x00, 0x0d, 0x28, 0x00,
+0x00, 0x00, 0x9d, 0x00, 0xff, 0x0d, 0x18, 0x0d, 0x2c, 0x00, 0x00, 0x00,
+0x95, 0x00, 0x01, 0x0d, 0x03, 0x03, 0x00, 0x03, 0x11, 0x11, 0x0d, 0x00,
+0xff, 0x00, 0x1a, 0x00, 0x01, 0x0d, 0x2a, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x01
+};
+
diff --git a/include/tee/optee.h b/include/tee/optee.h
index 9ab0d08..4b9e94c 100644
--- a/include/tee/optee.h
+++ b/include/tee/optee.h
@@ -10,6 +10,8 @@
#ifndef _OPTEE_H
#define _OPTEE_H
+#include <linux/errno.h>
+
#define OPTEE_MAGIC 0x4554504f
#define OPTEE_VERSION 1
#define OPTEE_ARCH_ARM32 0
@@ -27,4 +29,43 @@
uint32_t paged_size;
};
+static inline uint32_t optee_image_get_entry_point(const image_header_t *hdr)
+{
+ struct optee_header *optee_hdr = (struct optee_header *)(hdr + 1);
+
+ return optee_hdr->init_load_addr_lo;
+}
+
+static inline uint32_t optee_image_get_load_addr(const image_header_t *hdr)
+{
+ return optee_image_get_entry_point(hdr) - sizeof(struct optee_header);
+}
+
+#if defined(CONFIG_OPTEE)
+int optee_verify_image(struct optee_header *hdr, unsigned long tzdram_start,
+ unsigned long tzdram_len, unsigned long image_len);
+#else
+static inline int optee_verify_image(struct optee_header *hdr,
+ unsigned long tzdram_start,
+ unsigned long tzdram_len,
+ unsigned long image_len)
+{
+ return -EPERM;
+}
+
+#endif
+
+#if defined(CONFIG_OPTEE)
+int optee_verify_bootm_image(unsigned long image_addr,
+ unsigned long image_load_addr,
+ unsigned long image_len);
+#else
+static inline int optee_verify_bootm_image(unsigned long image_addr,
+ unsigned long image_load_addr,
+ unsigned long image_len)
+{
+ return -EPERM;
+}
+#endif
+
#endif /* _OPTEE_H */
diff --git a/lib/Kconfig b/lib/Kconfig
index 4fd41c4..a4029a6 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -310,5 +310,6 @@
source lib/efi/Kconfig
source lib/efi_loader/Kconfig
+source lib/optee/Kconfig
endmenu
diff --git a/lib/Makefile b/lib/Makefile
index 0db41c1..35da570 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -18,6 +18,7 @@
obj-$(CONFIG_OF_LIVE) += of_live.o
obj-$(CONFIG_CMD_DHRYSTONE) += dhry/
obj-$(CONFIG_ARCH_AT91) += at91/
+obj-$(CONFIG_OPTEE) += optee/
obj-$(CONFIG_AES) += aes.o
obj-y += charset.o
diff --git a/lib/optee/Kconfig b/lib/optee/Kconfig
new file mode 100644
index 0000000..1e5ab45
--- /dev/null
+++ b/lib/optee/Kconfig
@@ -0,0 +1,39 @@
+config OPTEE
+ bool "Support OPTEE images"
+ help
+ U-Boot can be configured to boot OPTEE images.
+ Selecting this option will enable shared OPTEE library code and
+ enable an OPTEE specific bootm command that will perform additional
+ OPTEE specific checks before booting an OPTEE image created with
+ mkimage.
+
+config OPTEE_LOAD_ADDR
+ hex "OPTEE load address"
+ default 0x00000000
+ help
+ The load address of the bootable OPTEE binary.
+
+config OPTEE_TZDRAM_SIZE
+ hex "Amount of Trust-Zone RAM for the OPTEE image"
+ depends on OPTEE
+ default 0x3000000
+ help
+ The size of pre-allocated Trust Zone DRAM to allocate for the OPTEE
+ runtime.
+
+config OPTEE_TZDRAM_BASE
+ hex "Base address of Trust-Zone RAM for the OPTEE image"
+ depends on OPTEE
+ default 0x9d000000
+ help
+ The base address of pre-allocated Trust Zone DRAM for
+ the OPTEE runtime.
+
+config BOOTM_OPTEE
+ bool "Support OPTEE bootm command"
+ select BOOTM_LINUX
+ default n
+ help
+ Select this command to enable chain-loading of a Linux kernel
+ via an OPTEE firmware.
+ The bootflow is BootROM -> u-boot -> OPTEE -> Linux in this case.
diff --git a/lib/optee/Makefile b/lib/optee/Makefile
new file mode 100644
index 0000000..03e832f
--- /dev/null
+++ b/lib/optee/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2017 Linaro
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_OPTEE) += optee.o
diff --git a/lib/optee/optee.c b/lib/optee/optee.c
new file mode 100644
index 0000000..78a15e8
--- /dev/null
+++ b/lib/optee/optee.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2017 Linaro
+ * Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <tee/optee.h>
+
+#define optee_hdr_err_msg \
+ "OPTEE verification error:" \
+ "\n\thdr=%p image=0x%08lx magic=0x%08x tzdram 0x%08lx-0x%08lx " \
+ "\n\theader lo=0x%08x hi=0x%08x size=0x%08lx arch=0x%08x" \
+ "\n\tuimage params 0x%08lx-0x%08lx\n"
+
+int optee_verify_image(struct optee_header *hdr, unsigned long tzdram_start,
+ unsigned long tzdram_len, unsigned long image_len)
+{
+ unsigned long tzdram_end = tzdram_start + tzdram_len;
+ uint32_t tee_file_size;
+
+ tee_file_size = hdr->init_size + hdr->paged_size +
+ sizeof(struct optee_header);
+
+ if (hdr->magic != OPTEE_MAGIC ||
+ hdr->version != OPTEE_VERSION ||
+ hdr->init_load_addr_hi > tzdram_end ||
+ hdr->init_load_addr_lo < tzdram_start ||
+ tee_file_size > tzdram_len ||
+ tee_file_size != image_len ||
+ (hdr->init_load_addr_lo + tee_file_size) > tzdram_end) {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int optee_verify_bootm_image(unsigned long image_addr,
+ unsigned long image_load_addr,
+ unsigned long image_len)
+{
+ struct optee_header *hdr = (struct optee_header *)image_addr;
+ unsigned long tzdram_start = CONFIG_OPTEE_TZDRAM_BASE;
+ unsigned long tzdram_len = CONFIG_OPTEE_TZDRAM_SIZE;
+
+ int ret;
+
+ ret = optee_verify_image(hdr, tzdram_start, tzdram_len, image_len);
+ if (ret)
+ goto error;
+
+ if (image_load_addr + sizeof(*hdr) != hdr->init_load_addr_lo) {
+ ret = -EINVAL;
+ goto error;
+ }
+
+ return ret;
+error:
+ printf(optee_hdr_err_msg, hdr, image_addr, hdr->magic, tzdram_start,
+ tzdram_start + tzdram_len, hdr->init_load_addr_lo,
+ hdr->init_load_addr_hi, image_len, hdr->arch, image_load_addr,
+ image_load_addr + image_len);
+
+ return ret;
+}
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index b0958d7..d6fd150 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -1335,7 +1335,6 @@
CONFIG_MTD_CONCAT
CONFIG_MTD_DEVICE
CONFIG_MTD_ECC_SOFT
-CONFIG_MTD_NAND_ECC_SMC
CONFIG_MTD_NAND_MUSEUM_IDS
CONFIG_MTD_NAND_VERIFY_WRITE
CONFIG_MTD_ONENAND_VERIFY_WRITE
@@ -1416,7 +1415,6 @@
CONFIG_NAND_LPC32XX_SLC
CONFIG_NAND_MODE_REG
CONFIG_NAND_MXC_V1_1
-CONFIG_NAND_NDFC
CONFIG_NAND_OMAP_ECCSCHEME
CONFIG_NAND_OMAP_GPMC_WSCFG
CONFIG_NAND_SECBOOT
diff --git a/tools/Makefile b/tools/Makefile
index f38f68e..55efb74 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -103,6 +103,7 @@
pblimage.o \
pbl_crc32.o \
vybridimage.o \
+ stm32image.o \
$(ROCKCHIP_OBS) \
socfpgaimage.o \
lib/sha1.o \
diff --git a/tools/default_image.c b/tools/default_image.c
index 4e5568e..c67f66b 100644
--- a/tools/default_image.c
+++ b/tools/default_image.c
@@ -18,6 +18,7 @@
#include "mkimage.h"
#include <image.h>
+#include <tee/optee.h>
#include <u-boot/crc.h>
static image_header_t header;
@@ -90,6 +91,8 @@
uint32_t checksum;
time_t time;
uint32_t imagesize;
+ uint32_t ep;
+ uint32_t addr;
image_header_t * hdr = (image_header_t *)ptr;
@@ -99,18 +102,26 @@
sbuf->st_size - sizeof(image_header_t));
time = imagetool_get_source_date(params, sbuf->st_mtime);
+ ep = params->ep;
+ addr = params->addr;
+
if (params->type == IH_TYPE_FIRMWARE_IVT)
/* Add size of CSF minus IVT */
imagesize = sbuf->st_size - sizeof(image_header_t) + 0x1FE0;
else
imagesize = sbuf->st_size - sizeof(image_header_t);
+ if (params->os == IH_OS_TEE) {
+ addr = optee_image_get_load_addr(hdr);
+ ep = optee_image_get_entry_point(hdr);
+ }
+
/* Build new header */
image_set_magic(hdr, IH_MAGIC);
image_set_time(hdr, time);
image_set_size(hdr, imagesize);
- image_set_load(hdr, params->addr);
- image_set_ep(hdr, params->ep);
+ image_set_load(hdr, addr);
+ image_set_ep(hdr, ep);
image_set_dcrc(hdr, checksum);
image_set_os(hdr, params->os);
image_set_arch(hdr, params->arch);
diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 0e3e343..77eac3d 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -14,6 +14,7 @@
#include <errno.h>
#include <env_flags.h>
#include <fcntl.h>
+#include <libgen.h>
#include <linux/fs.h>
#include <linux/stringify.h>
#include <ctype.h>
@@ -64,14 +65,14 @@
int is_ubi; /* set if we use UBI volume */
};
-static struct envdev_s envdevices[2] =
-{
+static struct envdev_s envdevices[2] = {
{
.mtd_type = MTD_ABSENT,
}, {
.mtd_type = MTD_ABSENT,
},
};
+
static int dev_current;
#define DEVNAME(i) envdevices[(i)].devname
@@ -88,14 +89,14 @@
#define ENV_SIZE usable_envsize
struct env_image_single {
- uint32_t crc; /* CRC32 over data bytes */
- char data[];
+ uint32_t crc; /* CRC32 over data bytes */
+ char data[];
};
struct env_image_redundant {
- uint32_t crc; /* CRC32 over data bytes */
- unsigned char flags; /* active or obsolete */
- char data[];
+ uint32_t crc; /* CRC32 over data bytes */
+ unsigned char flags; /* active or obsolete */
+ char data[];
};
enum flag_scheme {
@@ -105,18 +106,18 @@
};
struct environment {
- void *image;
- uint32_t *crc;
- unsigned char *flags;
- char *data;
- enum flag_scheme flag_scheme;
+ void *image;
+ uint32_t *crc;
+ unsigned char *flags;
+ char *data;
+ enum flag_scheme flag_scheme;
};
static struct environment environment = {
.flag_scheme = FLAG_NONE,
};
-static int HaveRedundEnv = 0;
+static int have_redund_env;
static unsigned char active_flag = 1;
/* obsolete_flag must be 0 to efficiently set it on NOR flash without erasing */
@@ -347,11 +348,11 @@
return 0;
}
-static int flash_io (int mode);
+static int flash_io(int mode);
static int parse_config(struct env_opts *opts);
#if defined(CONFIG_FILE)
-static int get_config (char *);
+static int get_config(char *);
#endif
static char *skip_chars(char *s)
@@ -394,7 +395,7 @@
* Search the environment for a variable.
* Return the value, if found, or NULL, if not found.
*/
-char *fw_getenv (char *name)
+char *fw_getenv(char *name)
{
char *env, *nxt;
@@ -403,12 +404,12 @@
for (nxt = env; *nxt; ++nxt) {
if (nxt >= &environment.data[ENV_SIZE]) {
- fprintf (stderr, "## Error: "
+ fprintf(stderr, "## Error: "
"environment not terminated\n");
return NULL;
}
}
- val = envmatch (name, env);
+ val = envmatch(name, env);
if (!val)
continue;
return val;
@@ -462,18 +463,18 @@
if (fw_env_open(opts))
return -1;
- if (argc == 0) { /* Print all env variables */
+ if (argc == 0) { /* Print all env variables */
char *env, *nxt;
for (env = environment.data; *env; env = nxt + 1) {
for (nxt = env; *nxt; ++nxt) {
if (nxt >= &environment.data[ENV_SIZE]) {
- fprintf (stderr, "## Error: "
+ fprintf(stderr, "## Error: "
"environment not terminated\n");
return -1;
}
}
- printf ("%s\n", env);
+ printf("%s\n", env);
}
fw_env_close(opts);
return 0;
@@ -485,7 +486,7 @@
val = fw_getenv(name);
if (!val) {
- fprintf (stderr, "## Error: \"%s\" not defined\n", name);
+ fprintf(stderr, "## Error: \"%s\" not defined\n", name);
rc = -1;
continue;
}
@@ -515,15 +516,13 @@
/* write environment back to flash */
if (flash_io(O_RDWR)) {
- fprintf(stderr,
- "Error: can't write fw_env to flash\n");
- return -1;
+ fprintf(stderr, "Error: can't write fw_env to flash\n");
+ return -1;
}
return 0;
}
-
/*
* Set/Clear a single variable in the environment.
* This is called in sequence to update the environment
@@ -548,7 +547,8 @@
return -1;
}
}
- if ((oldval = envmatch (name, env)) != NULL)
+ oldval = envmatch(name, env);
+ if (oldval)
break;
}
@@ -571,7 +571,7 @@
errno = EROFS;
return -1;
} else if (env_flags_validate_varaccess(name,
- ENV_FLAGS_VARACCESS_PREVENT_NONDEF_OVERWR)) {
+ ENV_FLAGS_VARACCESS_PREVENT_NONDEF_OVERWR)) {
const char *defval = fw_getdefenv(name);
if (defval == NULL)
@@ -615,21 +615,21 @@
/*
* Append new definition at the end
*/
- for (env = environment.data; *env || *(env + 1); ++env);
+ for (env = environment.data; *env || *(env + 1); ++env)
+ ;
if (env > environment.data)
++env;
/*
* Overflow when:
* "name" + "=" + "val" +"\0\0" > CUR_ENVSIZE - (env-environment)
*/
- len = strlen (name) + 2;
+ len = strlen(name) + 2;
/* add '=' for first arg, ' ' for all others */
len += strlen(value) + 1;
if (len > (&environment.data[ENV_SIZE] - env)) {
- fprintf (stderr,
- "Error: environment overflow, \"%s\" deleted\n",
- name);
+ fprintf(stderr,
+ "Error: environment overflow, \"%s\" deleted\n", name);
return -1;
}
@@ -759,7 +759,7 @@
fp = fopen(fname, "r");
if (fp == NULL) {
fprintf(stderr, "I cannot open %s for reading\n",
- fname);
+ fname);
return -1;
}
}
@@ -774,7 +774,7 @@
*/
if (dump[len - 1] != '\n') {
fprintf(stderr,
- "Line %d not corrected terminated or too long\n",
+ "Line %d not corrected terminated or too long\n",
lineno);
ret = -1;
break;
@@ -807,7 +807,6 @@
else
val = NULL;
}
-
#ifdef DEBUG
fprintf(stderr, "Setting %s : %s\n",
name, val ? val : " removed");
@@ -824,7 +823,7 @@
*/
if (fw_env_write(name, val)) {
fprintf(stderr,
- "fw_env_write returns with error : %s\n",
+ "fw_env_write returns with error : %s\n",
strerror(errno));
ret = -1;
break;
@@ -867,13 +866,13 @@
int badblock = ioctl(fd, MEMGETBADBLOCK, &blockstart);
if (badblock < 0) {
- perror ("Cannot read bad block mark");
+ perror("Cannot read bad block mark");
return badblock;
}
if (badblock) {
#ifdef DEBUG
- fprintf (stderr, "Bad block at 0x%llx, skipping\n",
+ fprintf(stderr, "Bad block at 0x%llx, skipping\n",
(unsigned long long)blockstart);
#endif
return badblock;
@@ -888,8 +887,8 @@
* bad blocks but makes sure it stays within ENVSECTORS (dev) starting from
* the DEVOFFSET (dev) block. On NOR the loop is only run once.
*/
-static int flash_read_buf (int dev, int fd, void *buf, size_t count,
- off_t offset)
+static int flash_read_buf(int dev, int fd, void *buf, size_t count,
+ off_t offset)
{
size_t blocklen; /* erase / write length - one block on NAND,
0 on NOR */
@@ -901,7 +900,7 @@
MEMGETBADBLOCK needs 64 bits */
int rc;
- blockstart = (offset / DEVESIZE (dev)) * DEVESIZE (dev);
+ blockstart = (offset / DEVESIZE(dev)) * DEVESIZE(dev);
/* Offset inside a block */
block_seek = offset - blockstart;
@@ -911,7 +910,7 @@
* NAND: calculate which blocks we are reading. We have
* to read one block at a time to skip bad blocks.
*/
- blocklen = DEVESIZE (dev);
+ blocklen = DEVESIZE(dev);
/* Limit to one block for the first read */
if (readlen > blocklen - block_seek)
@@ -923,17 +922,16 @@
/* This only runs once on NOR flash */
while (processed < count) {
rc = flash_bad_block(fd, DEVTYPE(dev), blockstart);
- if (rc < 0) /* block test failed */
+ if (rc < 0) /* block test failed */
return -1;
if (blockstart + block_seek + readlen > environment_end(dev)) {
/* End of range is reached */
- fprintf (stderr,
- "Too few good blocks within range\n");
+ fprintf(stderr, "Too few good blocks within range\n");
return -1;
}
- if (rc) { /* block is bad */
+ if (rc) { /* block is bad */
blockstart += blocklen;
continue;
}
@@ -942,21 +940,21 @@
* If a block is bad, we retry in the next block at the same
* offset - see env/nand.c::writeenv()
*/
- lseek (fd, blockstart + block_seek, SEEK_SET);
+ lseek(fd, blockstart + block_seek, SEEK_SET);
- rc = read (fd, buf + processed, readlen);
+ rc = read(fd, buf + processed, readlen);
if (rc != readlen) {
- fprintf (stderr, "Read error on %s: %s\n",
- DEVNAME (dev), strerror (errno));
+ fprintf(stderr, "Read error on %s: %s\n",
+ DEVNAME(dev), strerror(errno));
return -1;
}
#ifdef DEBUG
fprintf(stderr, "Read 0x%x bytes at 0x%llx on %s\n",
- rc, (unsigned long long) blockstart + block_seek,
+ rc, (unsigned long long)blockstart + block_seek,
DEVNAME(dev));
#endif
processed += readlen;
- readlen = min (blocklen, count - processed);
+ readlen = min(blocklen, count - processed);
block_seek = 0;
blockstart += blocklen;
}
@@ -1018,7 +1016,7 @@
* to the end of the block
*/
write_total = ((block_seek + count + blocklen - 1) /
- blocklen) * blocklen;
+ blocklen) * blocklen;
}
/*
@@ -1027,11 +1025,11 @@
* block back again.
*/
if (write_total > count) {
- data = malloc (erase_len);
+ data = malloc(erase_len);
if (!data) {
- fprintf (stderr,
- "Cannot malloc %zu bytes: %s\n",
- erase_len, strerror (errno));
+ fprintf(stderr,
+ "Cannot malloc %zu bytes: %s\n",
+ erase_len, strerror(errno));
return -1;
}
@@ -1047,13 +1045,13 @@
if (block_seek != 0)
fprintf(stderr, " and ");
fprintf(stderr, "0x%lx - 0x%lx",
- (unsigned long) block_seek + count,
- (unsigned long) write_total - 1);
+ (unsigned long)block_seek + count,
+ (unsigned long)write_total - 1);
}
fprintf(stderr, "\n");
#endif
/* Overwrite the old environment */
- memcpy (data + block_seek, buf, count);
+ memcpy(data + block_seek, buf, count);
} else {
/*
* We get here, iff offset is block-aligned and count is a
@@ -1077,15 +1075,15 @@
/* This only runs once on NOR flash and SPI-dataflash */
while (processed < write_total) {
rc = flash_bad_block(fd, DEVTYPE(dev), blockstart);
- if (rc < 0) /* block test failed */
+ if (rc < 0) /* block test failed */
return rc;
if (blockstart + erasesize > environment_end(dev)) {
- fprintf (stderr, "End of range reached, aborting\n");
+ fprintf(stderr, "End of range reached, aborting\n");
return -1;
}
- if (rc) { /* block is bad */
+ if (rc) { /* block is bad */
blockstart += blocklen;
continue;
}
@@ -1103,34 +1101,33 @@
}
}
- if (lseek (fd, blockstart, SEEK_SET) == -1) {
- fprintf (stderr,
- "Seek error on %s: %s\n",
- DEVNAME (dev), strerror (errno));
+ if (lseek(fd, blockstart, SEEK_SET) == -1) {
+ fprintf(stderr,
+ "Seek error on %s: %s\n",
+ DEVNAME(dev), strerror(errno));
return -1;
}
-
#ifdef DEBUG
fprintf(stderr, "Write 0x%llx bytes at 0x%llx\n",
- (unsigned long long) erasesize,
- (unsigned long long) blockstart);
+ (unsigned long long)erasesize,
+ (unsigned long long)blockstart);
#endif
- if (write (fd, data + processed, erasesize) != erasesize) {
- fprintf (stderr, "Write error on %s: %s\n",
- DEVNAME (dev), strerror (errno));
+ if (write(fd, data + processed, erasesize) != erasesize) {
+ fprintf(stderr, "Write error on %s: %s\n",
+ DEVNAME(dev), strerror(errno));
return -1;
}
if (DEVTYPE(dev) != MTD_ABSENT)
ioctl(fd, MEMLOCK, &erase);
- processed += erasesize;
+ processed += erasesize;
block_seek = 0;
blockstart += erasesize;
}
if (write_total > count)
- free (data);
+ free(data);
return processed;
}
@@ -1138,30 +1135,30 @@
/*
* Set obsolete flag at offset - NOR flash only
*/
-static int flash_flag_obsolete (int dev, int fd, off_t offset)
+static int flash_flag_obsolete(int dev, int fd, off_t offset)
{
int rc;
struct erase_info_user erase;
- erase.start = DEVOFFSET (dev);
- erase.length = DEVESIZE (dev);
+ erase.start = DEVOFFSET(dev);
+ erase.length = DEVESIZE(dev);
/* This relies on the fact, that obsolete_flag == 0 */
- rc = lseek (fd, offset, SEEK_SET);
+ rc = lseek(fd, offset, SEEK_SET);
if (rc < 0) {
- fprintf (stderr, "Cannot seek to set the flag on %s \n",
- DEVNAME (dev));
+ fprintf(stderr, "Cannot seek to set the flag on %s\n",
+ DEVNAME(dev));
return rc;
}
- ioctl (fd, MEMUNLOCK, &erase);
- rc = write (fd, &obsolete_flag, sizeof (obsolete_flag));
- ioctl (fd, MEMLOCK, &erase);
+ ioctl(fd, MEMUNLOCK, &erase);
+ rc = write(fd, &obsolete_flag, sizeof(obsolete_flag));
+ ioctl(fd, MEMLOCK, &erase);
if (rc < 0)
- perror ("Could not set obsolete flag");
+ perror("Could not set obsolete flag");
return rc;
}
-static int flash_write (int fd_current, int fd_target, int dev_target)
+static int flash_write(int fd_current, int fd_target, int dev_target)
{
int rc;
@@ -1175,14 +1172,14 @@
*environment.flags = active_flag;
break;
default:
- fprintf (stderr, "Unimplemented flash scheme %u \n",
- environment.flag_scheme);
+ fprintf(stderr, "Unimplemented flash scheme %u\n",
+ environment.flag_scheme);
return -1;
}
#ifdef DEBUG
fprintf(stderr, "Writing new environment at 0x%llx on %s\n",
- DEVOFFSET (dev_target), DEVNAME (dev_target));
+ DEVOFFSET(dev_target), DEVNAME(dev_target));
#endif
if (IS_UBI(dev_target)) {
@@ -1198,20 +1195,20 @@
if (environment.flag_scheme == FLAG_BOOLEAN) {
/* Have to set obsolete flag */
- off_t offset = DEVOFFSET (dev_current) +
- offsetof (struct env_image_redundant, flags);
+ off_t offset = DEVOFFSET(dev_current) +
+ offsetof(struct env_image_redundant, flags);
#ifdef DEBUG
fprintf(stderr,
"Setting obsolete flag in environment at 0x%llx on %s\n",
- DEVOFFSET (dev_current), DEVNAME (dev_current));
+ DEVOFFSET(dev_current), DEVNAME(dev_current));
#endif
- flash_flag_obsolete (dev_current, fd_current, offset);
+ flash_flag_obsolete(dev_current, fd_current, offset);
}
return 0;
}
-static int flash_read (int fd)
+static int flash_read(int fd)
{
int rc;
@@ -1229,72 +1226,153 @@
return 0;
}
-static int flash_io (int mode)
+static int flash_open_tempfile(const char **dname, const char **target_temp)
{
- int fd_current, fd_target, rc, dev_target;
+ char *dup_name = strdup(DEVNAME(dev_current));
+ char *temp_name = NULL;
+ int rc = -1;
- /* dev_current: fd_current, erase_current */
- fd_current = open (DEVNAME (dev_current), mode);
- if (fd_current < 0) {
- fprintf (stderr,
- "Can't open %s: %s\n",
- DEVNAME (dev_current), strerror (errno));
+ if (!dup_name)
return -1;
+
+ *dname = dirname(dup_name);
+ if (!*dname)
+ goto err;
+
+ rc = asprintf(&temp_name, "%s/XXXXXX", *dname);
+ if (rc == -1)
+ goto err;
+
+ rc = mkstemp(temp_name);
+ if (rc == -1) {
+ /* fall back to in place write */
+ fprintf(stderr,
+ "Can't create %s: %s\n", temp_name, strerror(errno));
+ free(temp_name);
+ } else {
+ *target_temp = temp_name;
+ /* deliberately leak dup_name as dname /might/ point into
+ * it and we need it for our caller
+ */
+ dup_name = NULL;
}
- if (mode == O_RDWR) {
- if (HaveRedundEnv) {
- /* switch to next partition for writing */
- dev_target = !dev_current;
- /* dev_target: fd_target, erase_target */
- fd_target = open (DEVNAME (dev_target), mode);
- if (fd_target < 0) {
- fprintf (stderr,
- "Can't open %s: %s\n",
- DEVNAME (dev_target),
- strerror (errno));
- rc = -1;
- goto exit;
- }
- } else {
- dev_target = dev_current;
- fd_target = fd_current;
+err:
+ if (dup_name)
+ free(dup_name);
+
+ return rc;
+}
+
+static int flash_io_write(int fd_current)
+{
+ int fd_target = -1, rc, dev_target;
+ const char *dname, *target_temp = NULL;
+
+ if (have_redund_env) {
+ /* switch to next partition for writing */
+ dev_target = !dev_current;
+ /* dev_target: fd_target, erase_target */
+ fd_target = open(DEVNAME(dev_target), O_RDWR);
+ if (fd_target < 0) {
+ fprintf(stderr,
+ "Can't open %s: %s\n",
+ DEVNAME(dev_target), strerror(errno));
+ rc = -1;
+ goto exit;
}
+ } else {
+ struct stat sb;
+
+ if (fstat(fd_current, &sb) == 0 && S_ISREG(sb.st_mode)) {
+ /* if any part of flash_open_tempfile() fails we fall
+ * back to in-place writes
+ */
+ fd_target = flash_open_tempfile(&dname, &target_temp);
+ }
+ dev_target = dev_current;
+ if (fd_target == -1)
+ fd_target = fd_current;
+ }
- rc = flash_write (fd_current, fd_target, dev_target);
+ rc = flash_write(fd_current, fd_target, dev_target);
- if (fsync(fd_current) &&
+ if (fsync(fd_current) && !(errno == EINVAL || errno == EROFS)) {
+ fprintf(stderr,
+ "fsync failed on %s: %s\n",
+ DEVNAME(dev_current), strerror(errno));
+ }
+
+ if (fd_current != fd_target) {
+ if (fsync(fd_target) &&
!(errno == EINVAL || errno == EROFS)) {
- fprintf (stderr,
- "fsync failed on %s: %s\n",
- DEVNAME (dev_current), strerror (errno));
+ fprintf(stderr,
+ "fsync failed on %s: %s\n",
+ DEVNAME(dev_current), strerror(errno));
}
- if (HaveRedundEnv) {
- if (fsync(fd_target) &&
- !(errno == EINVAL || errno == EROFS)) {
- fprintf (stderr,
- "fsync failed on %s: %s\n",
- DEVNAME (dev_current), strerror (errno));
- }
+ if (close(fd_target)) {
+ fprintf(stderr,
+ "I/O error on %s: %s\n",
+ DEVNAME(dev_target), strerror(errno));
+ rc = -1;
+ }
- if (close (fd_target)) {
- fprintf (stderr,
- "I/O error on %s: %s\n",
- DEVNAME (dev_target),
- strerror (errno));
+ if (target_temp) {
+ int dir_fd;
+
+ dir_fd = open(dname, O_DIRECTORY | O_RDONLY);
+ if (dir_fd == -1)
+ fprintf(stderr,
+ "Can't open %s: %s\n",
+ dname, strerror(errno));
+
+ if (rename(target_temp, DEVNAME(dev_target))) {
+ fprintf(stderr,
+ "rename failed %s => %s: %s\n",
+ target_temp, DEVNAME(dev_target),
+ strerror(errno));
rc = -1;
}
+
+ if (dir_fd != -1 && fsync(dir_fd))
+ fprintf(stderr,
+ "fsync failed on %s: %s\n",
+ dname, strerror(errno));
+
+ if (dir_fd != -1 && close(dir_fd))
+ fprintf(stderr,
+ "I/O error on %s: %s\n",
+ dname, strerror(errno));
}
+ }
+ exit:
+ return rc;
+}
+
+static int flash_io(int mode)
+{
+ int fd_current, rc;
+
+ /* dev_current: fd_current, erase_current */
+ fd_current = open(DEVNAME(dev_current), mode);
+ if (fd_current < 0) {
+ fprintf(stderr,
+ "Can't open %s: %s\n",
+ DEVNAME(dev_current), strerror(errno));
+ return -1;
+ }
+
+ if (mode == O_RDWR) {
+ rc = flash_io_write(fd_current);
} else {
- rc = flash_read (fd_current);
+ rc = flash_read(fd_current);
}
-exit:
- if (close (fd_current)) {
- fprintf (stderr,
- "I/O error on %s: %s\n",
- DEVNAME (dev_current), strerror (errno));
+ if (close(fd_current)) {
+ fprintf(stderr,
+ "I/O error on %s: %s\n",
+ DEVNAME(dev_current), strerror(errno));
return -1;
}
@@ -1322,7 +1400,7 @@
if (!opts)
opts = &default_opts;
- if (parse_config(opts)) /* should fill envdevices */
+ if (parse_config(opts)) /* should fill envdevices */
return -EINVAL;
addr0 = calloc(1, CUR_ENVSIZE);
@@ -1337,16 +1415,16 @@
/* read environment from FLASH to local buffer */
environment.image = addr0;
- if (HaveRedundEnv) {
+ if (have_redund_env) {
redundant = addr0;
- environment.crc = &redundant->crc;
- environment.flags = &redundant->flags;
- environment.data = redundant->data;
+ environment.crc = &redundant->crc;
+ environment.flags = &redundant->flags;
+ environment.data = redundant->data;
} else {
single = addr0;
- environment.crc = &single->crc;
- environment.flags = NULL;
- environment.data = single->data;
+ environment.crc = &single->crc;
+ environment.flags = NULL;
+ environment.data = single->data;
}
dev_current = 0;
@@ -1355,14 +1433,15 @@
goto open_cleanup;
}
- crc0 = crc32 (0, (uint8_t *) environment.data, ENV_SIZE);
+ crc0 = crc32(0, (uint8_t *)environment.data, ENV_SIZE);
crc0_ok = (crc0 == *environment.crc);
- if (!HaveRedundEnv) {
+ if (!have_redund_env) {
if (!crc0_ok) {
- fprintf (stderr,
+ fprintf(stderr,
"Warning: Bad CRC, using default environment\n");
- memcpy(environment.data, default_environment, sizeof default_environment);
+ memcpy(environment.data, default_environment,
+ sizeof(default_environment));
}
} else {
flag0 = *environment.flags;
@@ -1406,12 +1485,12 @@
IS_UBI(dev_current) == IS_UBI(!dev_current)) {
environment.flag_scheme = FLAG_INCREMENTAL;
} else {
- fprintf (stderr, "Incompatible flash types!\n");
+ fprintf(stderr, "Incompatible flash types!\n");
ret = -EINVAL;
goto open_cleanup;
}
- crc1 = crc32 (0, (uint8_t *) redundant->data, ENV_SIZE);
+ crc1 = crc32(0, (uint8_t *)redundant->data, ENV_SIZE);
crc1_ok = (crc1 == redundant->crc);
flag1 = redundant->flags;
@@ -1421,10 +1500,10 @@
} else if (!crc0_ok && crc1_ok) {
dev_current = 1;
} else if (!crc0_ok && !crc1_ok) {
- fprintf (stderr,
+ fprintf(stderr,
"Warning: Bad CRC, using default environment\n");
- memcpy (environment.data, default_environment,
- sizeof default_environment);
+ memcpy(environment.data, default_environment,
+ sizeof(default_environment));
dev_current = 0;
} else {
switch (environment.flag_scheme) {
@@ -1451,12 +1530,12 @@
else if ((flag1 == 255 && flag0 == 0) ||
flag0 >= flag1)
dev_current = 0;
- else /* flag1 > flag0 */
+ else /* flag1 > flag0 */
dev_current = 1;
break;
default:
- fprintf (stderr, "Unknown flag scheme %u \n",
- environment.flag_scheme);
+ fprintf(stderr, "Unknown flag scheme %u\n",
+ environment.flag_scheme);
return -1;
}
}
@@ -1467,15 +1546,15 @@
* flags before writing out
*/
if (dev_current) {
- environment.image = addr1;
- environment.crc = &redundant->crc;
- environment.flags = &redundant->flags;
- environment.data = redundant->data;
- free (addr0);
+ environment.image = addr1;
+ environment.crc = &redundant->crc;
+ environment.flags = &redundant->flags;
+ environment.data = redundant->data;
+ free(addr0);
} else {
- environment.image = addr0;
+ environment.image = addr0;
/* Other pointers are already set */
- free (addr1);
+ free(addr1);
}
#ifdef DEBUG
fprintf(stderr, "Selected env in %s\n", DEVNAME(dev_current));
@@ -1483,7 +1562,7 @@
}
return 0;
-open_cleanup:
+ open_cleanup:
if (addr0)
free(addr0);
@@ -1518,15 +1597,13 @@
fd = open(DEVNAME(dev), O_RDONLY);
if (fd < 0) {
fprintf(stderr,
- "Cannot open %s: %s\n",
- DEVNAME(dev), strerror(errno));
+ "Cannot open %s: %s\n", DEVNAME(dev), strerror(errno));
return -1;
}
rc = fstat(fd, &st);
if (rc < 0) {
- fprintf(stderr, "Cannot stat the file %s\n",
- DEVNAME(dev));
+ fprintf(stderr, "Cannot stat the file %s\n", DEVNAME(dev));
goto err;
}
@@ -1571,14 +1648,16 @@
if (DEVOFFSET(dev) < 0) {
rc = ioctl(fd, BLKGETSIZE64, &size);
if (rc < 0) {
- fprintf(stderr, "Could not get block device size on %s\n",
+ fprintf(stderr,
+ "Could not get block device size on %s\n",
DEVNAME(dev));
goto err;
}
DEVOFFSET(dev) = DEVOFFSET(dev) + size;
#ifdef DEBUG
- fprintf(stderr, "Calculated device offset 0x%llx on %s\n",
+ fprintf(stderr,
+ "Calculated device offset 0x%llx on %s\n",
DEVOFFSET(dev), DEVNAME(dev));
#endif
}
@@ -1589,18 +1668,20 @@
ENVSECTORS(dev) = DIV_ROUND_UP(ENVSIZE(dev), DEVESIZE(dev));
if (DEVOFFSET(dev) % DEVESIZE(dev) != 0) {
- fprintf(stderr, "Environment does not start on (erase) block boundary\n");
+ fprintf(stderr,
+ "Environment does not start on (erase) block boundary\n");
errno = EINVAL;
return -1;
}
if (ENVSIZE(dev) > ENVSECTORS(dev) * DEVESIZE(dev)) {
- fprintf(stderr, "Environment does not fit into available sectors\n");
+ fprintf(stderr,
+ "Environment does not fit into available sectors\n");
errno = EINVAL;
return -1;
}
-err:
+ err:
close(fd);
return rc;
}
@@ -1620,42 +1701,42 @@
return -1;
}
#else
- DEVNAME (0) = DEVICE1_NAME;
- DEVOFFSET (0) = DEVICE1_OFFSET;
- ENVSIZE (0) = ENV1_SIZE;
+ DEVNAME(0) = DEVICE1_NAME;
+ DEVOFFSET(0) = DEVICE1_OFFSET;
+ ENVSIZE(0) = ENV1_SIZE;
/* Set defaults for DEVESIZE, ENVSECTORS later once we
* know DEVTYPE
*/
#ifdef DEVICE1_ESIZE
- DEVESIZE (0) = DEVICE1_ESIZE;
+ DEVESIZE(0) = DEVICE1_ESIZE;
#endif
#ifdef DEVICE1_ENVSECTORS
- ENVSECTORS (0) = DEVICE1_ENVSECTORS;
+ ENVSECTORS(0) = DEVICE1_ENVSECTORS;
#endif
#ifdef HAVE_REDUND
- DEVNAME (1) = DEVICE2_NAME;
- DEVOFFSET (1) = DEVICE2_OFFSET;
- ENVSIZE (1) = ENV2_SIZE;
+ DEVNAME(1) = DEVICE2_NAME;
+ DEVOFFSET(1) = DEVICE2_OFFSET;
+ ENVSIZE(1) = ENV2_SIZE;
/* Set defaults for DEVESIZE, ENVSECTORS later once we
* know DEVTYPE
*/
#ifdef DEVICE2_ESIZE
- DEVESIZE (1) = DEVICE2_ESIZE;
+ DEVESIZE(1) = DEVICE2_ESIZE;
#endif
#ifdef DEVICE2_ENVSECTORS
- ENVSECTORS (1) = DEVICE2_ENVSECTORS;
+ ENVSECTORS(1) = DEVICE2_ENVSECTORS;
#endif
- HaveRedundEnv = 1;
+ have_redund_env = 1;
#endif
#endif
rc = check_device_config(0);
if (rc < 0)
return rc;
- if (HaveRedundEnv) {
+ if (have_redund_env) {
rc = check_device_config(1);
if (rc < 0)
return rc;
@@ -1668,14 +1749,14 @@
}
usable_envsize = CUR_ENVSIZE - sizeof(uint32_t);
- if (HaveRedundEnv)
+ if (have_redund_env)
usable_envsize -= sizeof(char);
return 0;
}
#if defined(CONFIG_FILE)
-static int get_config (char *fname)
+static int get_config(char *fname)
{
FILE *fp;
int i = 0;
@@ -1683,11 +1764,11 @@
char dump[128];
char *devname;
- fp = fopen (fname, "r");
+ fp = fopen(fname, "r");
if (fp == NULL)
return -1;
- while (i < 2 && fgets (dump, sizeof (dump), fp)) {
+ while (i < 2 && fgets(dump, sizeof(dump), fp)) {
/* Skip incomplete conversions and comment strings */
if (dump[0] == '#')
continue;
@@ -1695,9 +1776,7 @@
rc = sscanf(dump, "%ms %lli %lx %lx %lx",
&devname,
&DEVOFFSET(i),
- &ENVSIZE(i),
- &DEVESIZE(i),
- &ENVSECTORS(i));
+ &ENVSIZE(i), &DEVESIZE(i), &ENVSECTORS(i));
if (rc < 3)
continue;
@@ -1710,10 +1789,10 @@
i++;
}
- fclose (fp);
+ fclose(fp);
- HaveRedundEnv = i - 1;
- if (!i) { /* No valid entries found */
+ have_redund_env = i - 1;
+ if (!i) { /* No valid entries found */
errno = EINVAL;
return -1;
} else
diff --git a/tools/stm32image.c b/tools/stm32image.c
new file mode 100644
index 0000000..437e384
--- /dev/null
+++ b/tools/stm32image.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <image.h>
+#include "imagetool.h"
+
+/* magic ='S' 'T' 'M' 0x32 */
+#define HEADER_MAGIC be32_to_cpu(0x53544D32)
+#define VER_MAJOR_IDX 2
+#define VER_MINOR_IDX 1
+#define VER_VARIANT_IDX 0
+#define HEADER_VERSION_V1 0x1
+/* default option : bit0 => no signature */
+#define HEADER_DEFAULT_OPTION (cpu_to_le32(0x00000001))
+
+struct stm32_header {
+ uint32_t magic_number;
+ uint32_t image_signature[64 / 4];
+ uint32_t image_checksum;
+ uint8_t header_version[4];
+ uint32_t image_length;
+ uint32_t image_entry_point;
+ uint32_t reserved1;
+ uint32_t load_address;
+ uint32_t reserved2;
+ uint32_t version_number;
+ uint32_t option_flags;
+ uint32_t ecdsa_algorithm;
+ uint32_t ecdsa_public_key[64 / 4];
+ uint32_t padding[84 / 4];
+};
+
+static struct stm32_header stm32image_header;
+
+static void stm32image_default_header(struct stm32_header *ptr)
+{
+ if (!ptr)
+ return;
+
+ ptr->magic_number = HEADER_MAGIC;
+ ptr->header_version[VER_MAJOR_IDX] = HEADER_VERSION_V1;
+ ptr->option_flags = HEADER_DEFAULT_OPTION;
+ ptr->ecdsa_algorithm = 1;
+}
+
+static uint32_t stm32image_checksum(void *start, uint32_t len)
+{
+ uint32_t csum = 0;
+ uint32_t hdr_len = sizeof(struct stm32_header);
+ uint8_t *p;
+
+ if (len < hdr_len)
+ return 0;
+
+ p = start + hdr_len;
+ len -= hdr_len;
+
+ while (len > 0) {
+ csum += *p;
+ p++;
+ len--;
+ }
+
+ return csum;
+}
+
+static int stm32image_check_image_types(uint8_t type)
+{
+ if (type == IH_TYPE_STM32IMAGE)
+ return EXIT_SUCCESS;
+ return EXIT_FAILURE;
+}
+
+static int stm32image_verify_header(unsigned char *ptr, int image_size,
+ struct image_tool_params *params)
+{
+ struct stm32_header *stm32hdr = (struct stm32_header *)ptr;
+ int i;
+
+ if (image_size < sizeof(struct stm32_header))
+ return -1;
+ if (stm32hdr->magic_number != HEADER_MAGIC)
+ return -1;
+ if (stm32hdr->header_version[VER_MAJOR_IDX] != HEADER_VERSION_V1)
+ return -1;
+ if (stm32hdr->reserved1 || stm32hdr->reserved2)
+ return -1;
+ for (i = 0; i < (sizeof(stm32hdr->padding) / 4); i++) {
+ if (stm32hdr->padding[i] != 0)
+ return -1;
+ }
+
+ return 0;
+}
+
+static void stm32image_print_header(const void *ptr)
+{
+ struct stm32_header *stm32hdr = (struct stm32_header *)ptr;
+
+ printf("Image Type : STMicroelectronics STM32 V%d.%d\n",
+ stm32hdr->header_version[VER_MAJOR_IDX],
+ stm32hdr->header_version[VER_MINOR_IDX]);
+ printf("Image Size : %lu bytes\n",
+ (unsigned long)le32_to_cpu(stm32hdr->image_length));
+ printf("Image Load : 0x%08x\n",
+ le32_to_cpu(stm32hdr->load_address));
+ printf("Entry Point : 0x%08x\n",
+ le32_to_cpu(stm32hdr->image_entry_point));
+ printf("Checksum : 0x%08x\n",
+ le32_to_cpu(stm32hdr->image_checksum));
+ printf("Option : 0x%08x\n",
+ le32_to_cpu(stm32hdr->option_flags));
+}
+
+static void stm32image_set_header(void *ptr, struct stat *sbuf, int ifd,
+ struct image_tool_params *params)
+{
+ struct stm32_header *stm32hdr = (struct stm32_header *)ptr;
+
+ stm32image_default_header(stm32hdr);
+
+ stm32hdr->load_address = cpu_to_le32(params->addr);
+ stm32hdr->image_entry_point = cpu_to_le32(params->ep);
+ stm32hdr->image_length = cpu_to_le32((uint32_t)sbuf->st_size -
+ sizeof(struct stm32_header));
+ stm32hdr->image_checksum = stm32image_checksum(ptr, sbuf->st_size);
+}
+
+/*
+ * stm32image parameters
+ */
+U_BOOT_IMAGE_TYPE(
+ stm32image,
+ "STMicroelectronics STM32MP Image support",
+ sizeof(struct stm32_header),
+ (void *)&stm32image_header,
+ NULL,
+ stm32image_verify_header,
+ stm32image_print_header,
+ stm32image_set_header,
+ NULL,
+ stm32image_check_image_types,
+ NULL,
+ NULL
+);