tree 62125bde75ee5fcda1387f6f2bd9b7ceb9f0d187
parent e4361e9258b8d6808d201005e3ab59d767222c14
author Lokesh Vutla <lokeshvutla@ti.com> 1386842696 +0530
committer Tom Rini <trini@ti.com> 1386888219 -0500

ARM: DRA7xx: Change clk divider setting

Commit "armv7: hw_data: change clock divider setting"
updates the setting for m6 divider for 20MHz sys_clk frequency.
But missed to update for other sys_clk frequencies. Doing the same.

Reported-by: Rajendran, Vinothkumar <vinothr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>