ARM: OMAP4+: emif: Detect SDRAM from SDRAM config register
Now SDRAM initialization is done on the basis of omap revision.
Instead this should be done on basis of SDRAM type read from
EMIF_SDRAM_CONFIG register. This will be helpful to avoid
unnessecary cpu checks for new boards
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c
index eecfbad..1f33692 100644
--- a/arch/arm/cpu/armv7/omap5/clocks.c
+++ b/arch/arm/cpu/armv7/omap5/clocks.c
@@ -36,6 +36,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/utils.h>
#include <asm/omap_gpio.h>
+#include <asm/emif.h>
#ifndef CONFIG_SPL_BUILD
/*
@@ -279,7 +280,7 @@
do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu);
do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm);
- if (omap_revision() == OMAP5432_ES1_0) {
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
/* Configure LDO SRAM "magic" bits */
writel(2, &prcm->prm_sldo_core_setup);
writel(2, &prcm->prm_sldo_mpu_setup);
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index d0c3ff7..4def422 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -191,7 +191,7 @@
(sc_fast << 17) | (sc_fast << 14);
writel(io_settings, &(ioregs_base->control_smart3io_padconf_1));
- if (omap_revision() <= OMAP5430_ES1_0)
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
io_settings_lpddr2();
else
io_settings_ddr3();