Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
diff --git a/MAINTAINERS b/MAINTAINERS
index d6b1bc9..4597798 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -556,7 +556,7 @@
Dirk Behme <dirk.behme@gmail.com>
- omap3_beagle ARM CORTEX-A8 (OMAP3530 SoC)
+ omap3_beagle ARM ARMV7 (OMAP3530 SoC)
Eric Benard <eric@eukrea.com>
@@ -622,11 +622,11 @@
Vaibhav Hiremath <hvaibhav@ti.com>
- am3517_evm ARM CORTEX-A8 (AM35x SoC)
+ am3517_evm ARM ARMV7 (AM35x SoC)
Grazvydas Ignotas <notasas@gmail.com>
- omap3_pandora ARM CORTEX-A8 (OMAP3xx SoC)
+ omap3_pandora ARM ARMV7 (OMAP3xx SoC)
Gary Jennejohn <garyj@denx.de>
@@ -656,12 +656,12 @@
Minkyu Kang <mk7.kang@samsung.com>
- s5p_goni ARM CORTEX-A8 (S5PC110 SoC)
- SMDKC100 ARM CORTEX-A8 (S5PC100 SoC)
+ s5p_goni ARM ARMV7 (S5PC110 SoC)
+ SMDKC100 ARM ARMV7 (S5PC100 SoC)
Frederik Kriewitz <frederik@kriewitz.eu>
- devkit8000 ARM CORTEX-A8 (OMAP3530 SoC)
+ devkit8000 ARM ARMV7 (OMAP3530 SoC)
Sergey Kubushyn <ksi@koi8.net>
@@ -686,8 +686,8 @@
Nishanth Menon <nm@ti.com>
- omap3_sdp3430 ARM CORTEX-A8 (OMAP3xx SoC)
- omap3_zoom1 ARM CORTEX-A8 (OMAP3xx SoC)
+ omap3_sdp3430 ARM ARMV7 (OMAP3xx SoC)
+ omap3_zoom1 ARM ARMV7 (OMAP3xx SoC)
David Müller <d.mueller@elsoft.ch>
@@ -725,7 +725,7 @@
Manikandan Pillai <mani.pillai@ti.com>
- omap3_evm ARM CORTEX-A8 (OMAP3xx SoC)
+ omap3_evm ARM ARMV7 (OMAP3xx SoC)
Stelian Pop <stelian.pop@leadtechdesign.com>
@@ -737,7 +737,7 @@
Tom Rix <Tom.Rix@windriver.com>
- omap3_zoom2 ARM CORTEX-A8 (OMAP3xx SoC)
+ omap3_zoom2 ARM ARMV7 (OMAP3xx SoC)
John Rigby <jcrigby@gmail.com>
@@ -756,7 +756,9 @@
Steve Sakoman <sakoman@gmail.com>
- omap3_overo ARM CORTEX-A8 (OMAP3xx SoC)
+ omap3_overo ARM ARMV7 (OMAP3xx SoC)
+ omap4_panda ARM ARMV7 (OMAP4xx SoC)
+ omap4_sdp4430 ARM ARMV7 (OMAP4xx SoC)
Jens Scharsig <esw@bus-elektronik.de>
diff --git a/MAKEALL b/MAKEALL
index 6fddc61..83cee9d 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -647,9 +647,9 @@
"
#########################################################################
-## ARM Cortex-A8 Systems
+## ARMV7 Systems
#########################################################################
-LIST_ARM_CORTEX_A8=" \
+LIST_ARMV7=" \
am3517_evm \
devkit8000 \
mx51evk \
@@ -660,6 +660,8 @@
omap3_sdp3430 \
omap3_zoom1 \
omap3_zoom2 \
+ omap4_panda \
+ omap4_sdp4430 \
s5p_goni \
smdkc100 \
"
@@ -705,6 +707,7 @@
LIST_pxa=" \
cerf250 \
+ colibri_pxa270 \
cradle \
csb226 \
delta \
@@ -714,10 +717,13 @@
polaris \
pxa255_idp \
trizepsiv \
+ vpac270_nor \
+ vpac270_onenand \
wepep250 \
xaeniax \
xm250 \
xsengine \
+ zipitz2 \
zylonite \
"
@@ -742,7 +748,7 @@
${LIST_ARM9} \
${LIST_ARM10} \
${LIST_ARM11} \
- ${LIST_ARM_CORTEX_A8} \
+ ${LIST_ARMV7} \
${LIST_at91} \
${LIST_pxa} \
${LIST_ixp} \
@@ -1006,7 +1012,7 @@
for arg in $@
do
case "$arg" in
- arm|SA|ARM7|ARM9|ARM10|ARM11|ARM_CORTEX_A8|at91|ixp|pxa \
+ arm|SA|ARM7|ARM9|ARM10|ARM11|ARMV7|at91|ixp|pxa \
|avr32 \
|blackfin \
|coldfire \
diff --git a/Makefile b/Makefile
index cd83ba7..9cea069 100644
--- a/Makefile
+++ b/Makefile
@@ -246,6 +246,13 @@
LIBS += api/libapi.a
LIBS += post/libpost.a
+ifeq ($(SOC),omap3)
+LIBS += $(CPUDIR)/omap-common/libomap-common.a
+endif
+ifeq ($(SOC),omap4)
+LIBS += $(CPUDIR)/omap-common/libomap-common.a
+endif
+
LIBS := $(addprefix $(obj),$(LIBS))
.PHONY : $(LIBS) $(TIMESTAMP_FILE) $(VERSION_FILE)
@@ -2172,6 +2179,15 @@
fi;
@$(MKCONFIG) -n $@ -a trizepsiv arm pxa trizepsiv
+vpac270_nor_config \
+vpac270_onenand_config : unconfig
+ @mkdir -p $(obj)include
+ @if [ "$(findstring onenand,$@)" ] ; then \
+ echo "#define CONFIG_ONENAND_U_BOOT" \
+ >>$(obj)include/config.h ; \
+ fi;
+ @$(MKCONFIG) -n $@ -a vpac270 arm pxa vpac270
+
#########################################################################
## ARM1136 Systems
#########################################################################
diff --git a/arch/arm/cpu/arm_cortexa8/Makefile b/arch/arm/cpu/armv7/Makefile
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/Makefile
rename to arch/arm/cpu/armv7/Makefile
diff --git a/arch/arm/cpu/arm_cortexa8/config.mk b/arch/arm/cpu/armv7/config.mk
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/config.mk
rename to arch/arm/cpu/armv7/config.mk
diff --git a/arch/arm/cpu/arm_cortexa8/cpu.c b/arch/arm/cpu/armv7/cpu.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/cpu.c
rename to arch/arm/cpu/armv7/cpu.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/Makefile b/arch/arm/cpu/armv7/mx51/Makefile
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/Makefile
rename to arch/arm/cpu/armv7/mx51/Makefile
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/clock.c b/arch/arm/cpu/armv7/mx51/clock.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/clock.c
rename to arch/arm/cpu/armv7/mx51/clock.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/iomux.c b/arch/arm/cpu/armv7/mx51/iomux.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/iomux.c
rename to arch/arm/cpu/armv7/mx51/iomux.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S b/arch/arm/cpu/armv7/mx51/lowlevel_init.S
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S
rename to arch/arm/cpu/armv7/mx51/lowlevel_init.S
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/soc.c b/arch/arm/cpu/armv7/mx51/soc.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/soc.c
rename to arch/arm/cpu/armv7/mx51/soc.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/speed.c b/arch/arm/cpu/armv7/mx51/speed.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/speed.c
rename to arch/arm/cpu/armv7/mx51/speed.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/timer.c b/arch/arm/cpu/armv7/mx51/timer.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/mx51/timer.c
rename to arch/arm/cpu/armv7/mx51/timer.c
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds b/arch/arm/cpu/armv7/mx51/u-boot.lds
similarity index 97%
rename from arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds
rename to arch/arm/cpu/armv7/mx51/u-boot.lds
index 2953b93..d66434c 100644
--- a/arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds
+++ b/arch/arm/cpu/armv7/mx51/u-boot.lds
@@ -36,7 +36,7 @@
. = ALIGN(4);
.text :
{
- arch/arm/cpu/arm_cortexa8/start.o
+ arch/arm/cpu/armv7/start.o
*(.text)
}
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
similarity index 77%
copy from arch/arm/cpu/arm_cortexa8/omap3/Makefile
copy to arch/arm/cpu/armv7/omap-common/Makefile
index 7d63c6b..3a4a304 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -23,27 +23,15 @@
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)libomap-common.a
-SOBJS := lowlevel_init.o
-SOBJS += cache.o
-SOBJS += reset.o
-
-COBJS += board.o
-COBJS += clock.o
-COBJS += gpio.o
-COBJS += mem.o
-COBJS += syslib.o
-COBJS += sys_info.o
-COBJS += timer.o
-
-COBJS-$(CONFIG_EMIF4) += emif4.o
-COBJS-$(CONFIG_SDRC) += sdrc.o
+SOBJS := reset.o
+COBJS := timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-all: $(obj).depend $(LIB)
+all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
diff --git a/arch/arm/cpu/arm_cortexa8/config.mk b/arch/arm/cpu/armv7/omap-common/config.mk
similarity index 100%
copy from arch/arm/cpu/arm_cortexa8/config.mk
copy to arch/arm/cpu/armv7/omap-common/config.mk
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/reset.S b/arch/arm/cpu/armv7/omap-common/reset.S
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/reset.S
rename to arch/arm/cpu/armv7/omap-common/reset.S
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c
similarity index 95%
rename from arch/arm/cpu/arm_cortexa8/omap3/timer.c
rename to arch/arm/cpu/armv7/omap-common/timer.c
index 401bfe6..69e285f 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/timer.c
+++ b/arch/arm/cpu/armv7/omap-common/timer.c
@@ -84,6 +84,11 @@
/* delay x useconds */
void __udelay(unsigned long usec)
{
+#if defined(CONFIG_OMAP44XX)
+ /* TODO temporary hack until OMAP4 clock setup routines are present */
+ if (usec > 1000)
+ usec = usec/1000;
+#endif
long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
unsigned long now, last = readl(&timer_base->tcrr);
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile
similarity index 97%
rename from arch/arm/cpu/arm_cortexa8/omap3/Makefile
rename to arch/arm/cpu/armv7/omap3/Makefile
index 7d63c6b..79ae267 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
+++ b/arch/arm/cpu/armv7/omap3/Makefile
@@ -27,7 +27,6 @@
SOBJS := lowlevel_init.o
SOBJS += cache.o
-SOBJS += reset.o
COBJS += board.o
COBJS += clock.o
@@ -35,7 +34,6 @@
COBJS += mem.o
COBJS += syslib.o
COBJS += sys_info.o
-COBJS += timer.o
COBJS-$(CONFIG_EMIF4) += emif4.o
COBJS-$(CONFIG_SDRC) += sdrc.o
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/board.c
rename to arch/arm/cpu/armv7/omap3/board.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/cache.S b/arch/arm/cpu/armv7/omap3/cache.S
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/cache.S
rename to arch/arm/cpu/armv7/omap3/cache.S
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/clock.c
rename to arch/arm/cpu/armv7/omap3/clock.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/emif4.c b/arch/arm/cpu/armv7/omap3/emif4.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/emif4.c
rename to arch/arm/cpu/armv7/omap3/emif4.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/gpio.c b/arch/arm/cpu/armv7/omap3/gpio.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/gpio.c
rename to arch/arm/cpu/armv7/omap3/gpio.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/lowlevel_init.S
rename to arch/arm/cpu/armv7/omap3/lowlevel_init.S
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/mem.c
rename to arch/arm/cpu/armv7/omap3/mem.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/sdrc.c
rename to arch/arm/cpu/armv7/omap3/sdrc.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/sys_info.c
rename to arch/arm/cpu/armv7/omap3/sys_info.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/syslib.c b/arch/arm/cpu/armv7/omap3/syslib.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/omap3/syslib.c
rename to arch/arm/cpu/armv7/omap3/syslib.c
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
similarity index 81%
copy from arch/arm/cpu/arm_cortexa8/omap3/Makefile
copy to arch/arm/cpu/armv7/omap4/Makefile
index 7d63c6b..ecf64f9 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -25,23 +25,13 @@
LIB = $(obj)lib$(SOC).a
-SOBJS := lowlevel_init.o
-SOBJS += cache.o
-SOBJS += reset.o
+SOBJS += lowlevel_init.o
COBJS += board.o
-COBJS += clock.o
-COBJS += gpio.o
-COBJS += mem.o
-COBJS += syslib.o
COBJS += sys_info.o
-COBJS += timer.o
-
-COBJS-$(CONFIG_EMIF4) += emif4.o
-COBJS-$(CONFIG_SDRC) += sdrc.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
all: $(obj).depend $(LIB)
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
new file mode 100644
index 0000000..5bf7173
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -0,0 +1,90 @@
+/*
+ *
+ * Common functions for OMAP4 based boards
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+
+/*
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called path is with SRAM stack.
+ */
+void s_init(void)
+{
+ watchdog_init();
+}
+
+/*
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ */
+void wait_for_command_complete(struct watchdog *wd_base)
+{
+ int pending = 1;
+ do {
+ pending = readl(&wd_base->wwps);
+ } while (pending);
+}
+
+/*
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ */
+void watchdog_init(void)
+{
+ struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
+
+ writel(WD_UNLOCK1, &wd2_base->wspr);
+ wait_for_command_complete(wd2_base);
+ writel(WD_UNLOCK2, &wd2_base->wspr);
+}
+
+/*
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = 0x80000000;
+ gd->bd->bi_dram[0].size = 512 << 20;
+ return 0;
+}
+
+/*
+ * Print board information
+ */
+int checkboard(void)
+{
+ puts(sysinfo.board_string);
+ return 0;
+}
+
diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
new file mode 100644
index 0000000..9a181eb
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S
@@ -0,0 +1,48 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/omap4.h>
+
+.globl lowlevel_init
+lowlevel_init:
+ /*
+ * Setup a temporary stack
+ */
+ ldr sp, =LOW_LEVEL_SRAM_STACK
+
+ /*
+ * Save the old lr(passed in ip) and the current lr to stack
+ */
+ push {ip, lr}
+
+ /*
+ * go setup pll, mux, memory
+ */
+ bl s_init
+ pop {ip, pc}
+
diff --git a/arch/arm/cpu/armv7/omap4/sys_info.c b/arch/arm/cpu/armv7/omap4/sys_info.c
new file mode 100644
index 0000000..3b73191
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/sys_info.c
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+/*
+ * get_device_type(): tell if GP/HS/EMU/TST
+ */
+u32 get_device_type(void)
+{
+ return 0;
+}
+
+/*
+ * get_board_rev() - get board revision
+ */
+u32 get_board_rev(void)
+{
+ return 0x20;
+}
+
+/*
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+
+ puts("CPU : OMAP4430\n");
+
+ return 0;
+}
+
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/Makefile b/arch/arm/cpu/armv7/s5pc1xx/Makefile
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/Makefile
rename to arch/arm/cpu/armv7/s5pc1xx/Makefile
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/cache.S b/arch/arm/cpu/armv7/s5pc1xx/cache.S
similarity index 98%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/cache.S
rename to arch/arm/cpu/armv7/s5pc1xx/cache.S
index 906118d..7734b32 100644
--- a/arch/arm/cpu/arm_cortexa8/s5pc1xx/cache.S
+++ b/arch/arm/cpu/armv7/s5pc1xx/cache.S
@@ -2,7 +2,7 @@
* Copyright (C) 2009 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
*
- * based on arch/arm/cpu/arm_cortexa8/omap3/cache.S
+ * based on arch/arm/cpu/armv7/omap3/cache.S
*
* See file CREDITS for list of people who contributed to this
* project.
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/clock.c b/arch/arm/cpu/armv7/s5pc1xx/clock.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/clock.c
rename to arch/arm/cpu/armv7/s5pc1xx/clock.c
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/cpu_info.c b/arch/arm/cpu/armv7/s5pc1xx/cpu_info.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/cpu_info.c
rename to arch/arm/cpu/armv7/s5pc1xx/cpu_info.c
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/reset.S b/arch/arm/cpu/armv7/s5pc1xx/reset.S
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/reset.S
rename to arch/arm/cpu/armv7/s5pc1xx/reset.S
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/sromc.c b/arch/arm/cpu/armv7/s5pc1xx/sromc.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/sromc.c
rename to arch/arm/cpu/armv7/s5pc1xx/sromc.c
diff --git a/arch/arm/cpu/arm_cortexa8/s5pc1xx/timer.c b/arch/arm/cpu/armv7/s5pc1xx/timer.c
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/s5pc1xx/timer.c
rename to arch/arm/cpu/armv7/s5pc1xx/timer.c
diff --git a/arch/arm/cpu/arm_cortexa8/start.S b/arch/arm/cpu/armv7/start.S
similarity index 100%
rename from arch/arm/cpu/arm_cortexa8/start.S
rename to arch/arm/cpu/armv7/start.S
diff --git a/arch/arm/cpu/arm_cortexa8/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
similarity index 96%
rename from arch/arm/cpu/arm_cortexa8/u-boot.lds
rename to arch/arm/cpu/armv7/u-boot.lds
index 820e3a1..9e5b5a9 100644
--- a/arch/arm/cpu/arm_cortexa8/u-boot.lds
+++ b/arch/arm/cpu/armv7/u-boot.lds
@@ -34,7 +34,7 @@
. = ALIGN(4);
.text :
{
- arch/arm/cpu/arm_cortexa8/start.o (.text)
+ arch/arm/cpu/armv7/start.o (.text)
*(.text)
}
diff --git a/arch/arm/cpu/pxa/pxafb.c b/arch/arm/cpu/pxa/pxafb.c
index d56c5f0..524a03b 100644
--- a/arch/arm/cpu/pxa/pxafb.c
+++ b/arch/arm/cpu/pxa/pxafb.c
@@ -112,6 +112,39 @@
vl_efw: 0,
};
#endif /* CONFIG_SHARP_LM8V31 */
+/*----------------------------------------------------------------------*/
+#ifdef CONFIG_VOIPAC_LCD
+
+# define LCD_BPP LCD_COLOR8
+# define LCD_INVERT_COLORS
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0 0x043008f8
+# define REG_LCCR3 0x0340FF08
+
+vidinfo_t panel_info = {
+ vl_col: 640,
+ vl_row: 480,
+ vl_width: 157,
+ vl_height: 118,
+ vl_clkp: CONFIG_SYS_HIGH,
+ vl_oep: CONFIG_SYS_HIGH,
+ vl_hsp: CONFIG_SYS_HIGH,
+ vl_vsp: CONFIG_SYS_HIGH,
+ vl_dp: CONFIG_SYS_HIGH,
+ vl_bpix: LCD_BPP,
+ vl_lbw: 0,
+ vl_splt: 1,
+ vl_clor: 1,
+ vl_tft: 1,
+ vl_hpw: 32,
+ vl_blw: 144,
+ vl_elw: 32,
+ vl_vpw: 2,
+ vl_bfw: 13,
+ vl_efw: 30,
+};
+#endif /* CONFIG_VOIPAC_LCD */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_HITACHI_SX14
@@ -147,6 +180,40 @@
#endif /* CONFIG_HITACHI_SX14 */
/*----------------------------------------------------------------------*/
+#ifdef CONFIG_LMS283GF05
+
+# define LCD_BPP LCD_COLOR8
+//# define LCD_INVERT_COLORS
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0 0x043008f8
+# define REG_LCCR3 0x03b00009
+
+vidinfo_t panel_info = {
+ vl_col: 240,
+ vl_row: 320,
+ vl_width: 240,
+ vl_height: 320,
+ vl_clkp: CONFIG_SYS_HIGH,
+ vl_oep: CONFIG_SYS_LOW,
+ vl_hsp: CONFIG_SYS_LOW,
+ vl_vsp: CONFIG_SYS_LOW,
+ vl_dp: CONFIG_SYS_HIGH,
+ vl_bpix: LCD_BPP,
+ vl_lbw: 0,
+ vl_splt: 1,
+ vl_clor: 1,
+ vl_tft: 1,
+ vl_hpw: 4,
+ vl_blw: 4,
+ vl_elw: 8,
+ vl_vpw: 4,
+ vl_bfw: 4,
+ vl_efw: 8,
+};
+#endif /* CONFIG_LMS283GF05 */
+
+/*----------------------------------------------------------------------*/
#if LCD_BPP == LCD_COLOR8
void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
@@ -292,7 +359,9 @@
return 0;
}
-
+#ifdef CONFIG_CPU_MONAHANS
+static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
+#else
static void pxafb_setup_gpio (vidinfo_t *vid)
{
u_long lccr0;
@@ -349,6 +418,7 @@
printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
}
}
+#endif
static void pxafb_enable_controller (vidinfo_t *vid)
{
@@ -363,7 +433,11 @@
FDADR1 = vid->pxa.fdadr1;
LCCR0 |= LCCR0_ENB;
+#ifdef CONFIG_CPU_MONAHANS
+ CKENA |= CKENA_1_LCD;
+#else
CKEN |= CKEN16_LCD;
+#endif
debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0);
debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1);
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index e07c8c2..8010b0e 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -34,6 +34,25 @@
.globl _start
_start: b reset
+#ifdef CONFIG_PRELOADER
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+ ldr pc, _hang
+
+_hang:
+ .word do_hang
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678
+ .word 0x12345678 /* now 16*4=64 */
+#else
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
@@ -49,6 +68,7 @@
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
+#endif /* CONFIG_PRELOADER */
.balignl 16,0xdeadbeef
@@ -117,8 +137,10 @@
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
+#ifndef CONFIG_PRELOADER
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
+#endif
ldr r2, _armboot_start
ldr r3, _bss_start
@@ -135,28 +157,37 @@
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
+#ifdef CONFIG_PRELOADER
+ sub sp, r0, #128 /* leave 32 words for abort-stack */
+#else
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif /* CONFIG_USE_IRQ */
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
+#endif
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
+#ifndef CONFIG_PRELOADER
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
ble clbss_l
+#endif
ldr pc, _start_armboot
+#ifdef CONFIG_ONENAND_IPL
+_start_armboot: .word start_oneboot
+#else
_start_armboot: .word start_armboot
-
+#endif
/****************************************************************************/
/* */
@@ -296,7 +327,7 @@
*/
mov pc, lr
-
+#ifndef CONFIG_PRELOADER
/****************************************************************************/
/* */
/* Interrupt handling */
@@ -394,6 +425,7 @@
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
+#endif /* CONFIG_PRELOADER */
/****************************************************************************/
@@ -402,6 +434,12 @@
/* */
/****************************************************************************/
+#ifdef CONFIG_PRELOADER
+ .align 5
+do_hang:
+ ldr sp, _TEXT_BASE /* use 32 words abort stack */
+ bl hang /* hang and never return */
+#else /* !CONFIG_PRELOADER */
.align 5
undefined_instruction:
get_bad_stack
@@ -461,7 +499,7 @@
get_bad_stack
bad_save_user_regs
bl do_fiq
-
+#endif /* CONFIG_PRELOADER */
#endif /* CONFIG_USE_IRQ */
/****************************************************************************/
diff --git a/arch/arm/include/asm/arch-mx51/asm-offsets.h b/arch/arm/include/asm/arch-mx51/asm-offsets.h
index fbba412..afd2728 100644
--- a/arch/arm/include/asm/arch-mx51/asm-offsets.h
+++ b/arch/arm/include/asm/arch-mx51/asm-offsets.h
@@ -1,5 +1,5 @@
/*
- * needed for arch/arm/cpu/arm_cortexa8/mx51/lowlevel_init.S
+ * needed for arch/arm/cpu/armv7/mx51/lowlevel_init.S
*
* These should be auto-generated
*/
diff --git a/arch/arm/include/asm/arch-omap3/i2c.h b/arch/arm/include/asm/arch-omap3/i2c.h
index 490e03b..7a4a73a 100644
--- a/arch/arm/include/asm/arch-omap3/i2c.h
+++ b/arch/arm/include/asm/arch-omap3/i2c.h
@@ -20,9 +20,10 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#ifndef _I2C_H_
-#define _I2C_H_
+#ifndef _OMAP3_I2C_H_
+#define _OMAP3_I2C_H_
+#define I2C_BUS_MAX 3
#define I2C_DEFAULT_BASE I2C_BASE1
struct i2c {
@@ -58,146 +59,4 @@
unsigned short res15;
};
-#define I2C_BUS_MAX 3
-
-/* I2C masks */
-
-/* I2C Interrupt Enable Register (I2C_IE): */
-#define I2C_IE_GC_IE (1 << 5)
-#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
-#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
-#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
-#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
-#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
-
-/* I2C Status Register (I2C_STAT): */
-
-#define I2C_STAT_SBD (1 << 15) /* Single byte data */
-#define I2C_STAT_BB (1 << 12) /* Bus busy */
-#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
-#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
-#define I2C_STAT_AAS (1 << 9) /* Address as slave */
-#define I2C_STAT_GC (1 << 5)
-#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
-#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
-#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
-#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
-#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
-
-/* I2C Interrupt Code Register (I2C_INTCODE): */
-
-#define I2C_INTCODE_MASK 7
-#define I2C_INTCODE_NONE 0
-#define I2C_INTCODE_AL 1 /* Arbitration lost */
-#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
-#define I2C_INTCODE_ARDY 3 /* Register access ready */
-#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
-#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
-
-/* I2C Buffer Configuration Register (I2C_BUF): */
-
-#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */
-#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */
-
-/* I2C Configuration Register (I2C_CON): */
-
-#define I2C_CON_EN (1 << 15) /* I2C module enable */
-#define I2C_CON_BE (1 << 14) /* Big endian mode */
-#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */
-#define I2C_CON_MST (1 << 10) /* Master/slave mode */
-#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */
- /* (master mode only) */
-#define I2C_CON_XA (1 << 8) /* Expand address */
-#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */
-#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */
-
-/* I2C System Test Register (I2C_SYSTEST): */
-
-#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
-#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */
-#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
-#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
-#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */
-#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */
-#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */
-#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */
-
-#define I2C_SCLL_SCLL 0
-#define I2C_SCLL_SCLL_M 0xFF
-#define I2C_SCLL_HSSCLL 8
-#define I2C_SCLH_HSSCLL_M 0xFF
-#define I2C_SCLH_SCLH 0
-#define I2C_SCLH_SCLH_M 0xFF
-#define I2C_SCLH_HSSCLH 8
-#define I2C_SCLH_HSSCLH_M 0xFF
-
-#define OMAP_I2C_STANDARD 100000
-#define OMAP_I2C_FAST_MODE 400000
-#define OMAP_I2C_HIGH_SPEED 3400000
-
-#define SYSTEM_CLOCK_12 12000000
-#define SYSTEM_CLOCK_13 13000000
-#define SYSTEM_CLOCK_192 19200000
-#define SYSTEM_CLOCK_96 96000000
-
-/* Use the reference value of 96MHz if not explicitly set by the board */
-#ifndef I2C_IP_CLK
-#define I2C_IP_CLK SYSTEM_CLOCK_96
-#endif
-
-/*
- * The reference minimum clock for high speed is 19.2MHz.
- * The linux 2.6.30 kernel uses this value.
- * The reference minimum clock for fast mode is 9.6MHz
- * The reference minimum clock for standard mode is 4MHz
- * In TRM, the value of 12MHz is used.
- */
-#ifndef I2C_INTERNAL_SAMPLING_CLK
-#define I2C_INTERNAL_SAMPLING_CLK 19200000
-#endif
-
-/*
- * The equation for the low and high time is
- * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
- * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
- *
- * If the duty cycle is 50%
- *
- * tlow = scll + scll_trim = sampling clock / (2 * speed)
- * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
- *
- * In TRM
- * scll_trim = 7
- * sclh_trim = 5
- *
- * The linux 2.6.30 kernel uses
- * scll_trim = 6
- * sclh_trim = 6
- *
- * These are the trim values for standard and fast speed
- */
-#ifndef I2C_FASTSPEED_SCLL_TRIM
-#define I2C_FASTSPEED_SCLL_TRIM 6
-#endif
-#ifndef I2C_FASTSPEED_SCLH_TRIM
-#define I2C_FASTSPEED_SCLH_TRIM 6
-#endif
-
-/* These are the trim values for high speed */
-#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
-#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
-#endif
-#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
-#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
-#endif
-#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
-#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
-#endif
-#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
-#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
-#endif
-
-#define I2C_PSC_MAX 0x0f
-#define I2C_PSC_MIN 0x00
-
-#endif /* _I2C_H_ */
+#endif /* _OMAP3_I2C_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
index aa751c9..43dd705 100644
--- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
@@ -29,13 +29,20 @@
#define T2_BASE 0x48002000
typedef struct t2 {
- unsigned char res1[0x274];
+ unsigned char res1[0x274]; /* 0x000 */
unsigned int devconf0; /* 0x274 */
- unsigned char res2[0x2A8];
+ unsigned char res2[0x060]; /* 0x278 */
+ unsigned int devconf1; /* 0x2D8 */
+ unsigned char res3[0x244]; /* 0x2DC */
unsigned int pbias_lite; /* 0x520 */
} t2_t;
#define MMCSDIO1ADPCLKISEL (1 << 24)
+#define MMCSDIO2ADPCLKISEL (1 << 6)
+
+#define EN_MMC1 (1 << 24)
+#define EN_MMC2 (1 << 25)
+#define EN_MMC3 (1 << 30)
#define PBIASLITEPWRDNZ0 (1 << 1)
#define PBIASSPEEDCTRL0 (1 << 2)
@@ -44,7 +51,9 @@
/*
* OMAP HSMMC register definitions
*/
-#define OMAP_HSMMC_BASE 0x4809C000
+#define OMAP_HSMMC1_BASE 0x4809C000
+#define OMAP_HSMMC2_BASE 0x480B4000
+#define OMAP_HSMMC3_BASE 0x480AD000
typedef struct hsmmc {
unsigned char res1[0x10];
diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h
new file mode 100644
index 0000000..7d8aa20
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/cpu.h
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2006-2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct gptimer {
+ u32 tidr; /* 0x00 r */
+ u8 res[0xc];
+ u32 tiocp_cfg; /* 0x10 rw */
+ u32 tistat; /* 0x14 r */
+ u32 tisr; /* 0x18 rw */
+ u32 tier; /* 0x1c rw */
+ u32 twer; /* 0x20 rw */
+ u32 tclr; /* 0x24 rw */
+ u32 tcrr; /* 0x28 rw */
+ u32 tldr; /* 0x2c rw */
+ u32 ttgr; /* 0x30 rw */
+ u32 twpc; /* 0x34 r */
+ u32 tmar; /* 0x38 rw */
+ u32 tcar1; /* 0x3c r */
+ u32 tcicr; /* 0x40 rw */
+ u32 tcar2; /* 0x44 r */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* enable sys_clk NO-prescale /1 */
+#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
+
+/* Watchdog */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct watchdog {
+ u8 res1[0x34];
+ u32 wwps; /* 0x34 r */
+ u8 res2[0x10];
+ u32 wspr; /* 0x48 rw */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define WD_UNLOCK1 0xAAAA
+#define WD_UNLOCK2 0x5555
+
+#define SYSCLKDIV_1 (0x1 << 6)
+#define SYSCLKDIV_2 (0x1 << 7)
+
+#define CLKSEL_GPT1 (0x1 << 0)
+
+#define EN_GPT1 (0x1 << 0)
+#define EN_32KSYNC (0x1 << 2)
+
+#define ST_WDT2 (0x1 << 5)
+
+#define RESETDONE (0x1 << 0)
+
+#define TCLR_ST (0x1 << 0)
+#define TCLR_AR (0x1 << 1)
+#define TCLR_PRE (0x1 << 5)
+
+/* I2C base */
+#define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000)
+#define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000)
+#define I2C_BASE3 (OMAP44XX_L4_PER_BASE + 0x60000)
+
+#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-omap4/i2c.h b/arch/arm/include/asm/arch-omap4/i2c.h
new file mode 100644
index 0000000..a91b4c2
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/i2c.h
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2004-2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP4_I2C_H_
+#define _OMAP4_I2C_H_
+
+#define I2C_BUS_MAX 3
+#define I2C_DEFAULT_BASE I2C_BASE1
+
+struct i2c {
+ unsigned short revnb_lo; /* 0x00 */
+ unsigned short res1;
+ unsigned short revnb_hi; /* 0x04 */
+ unsigned short res2[13];
+ unsigned short sysc; /* 0x20 */
+ unsigned short res3;
+ unsigned short irqstatus_raw; /* 0x24 */
+ unsigned short res4;
+ unsigned short stat; /* 0x28 */
+ unsigned short res5;
+ unsigned short ie; /* 0x2C */
+ unsigned short res6;
+ unsigned short irqenable_clr; /* 0x30 */
+ unsigned short res7;
+ unsigned short iv; /* 0x34 */
+ unsigned short res8[45];
+ unsigned short syss; /* 0x90 */
+ unsigned short res9;
+ unsigned short buf; /* 0x94 */
+ unsigned short res10;
+ unsigned short cnt; /* 0x98 */
+ unsigned short res11;
+ unsigned short data; /* 0x9C */
+ unsigned short res13;
+ unsigned short res14; /* 0xA0 */
+ unsigned short res15;
+ unsigned short con; /* 0xA4 */
+ unsigned short res16;
+ unsigned short oa; /* 0xA8 */
+ unsigned short res17;
+ unsigned short sa; /* 0xAC */
+ unsigned short res18;
+ unsigned short psc; /* 0xB0 */
+ unsigned short res19;
+ unsigned short scll; /* 0xB4 */
+ unsigned short res20;
+ unsigned short sclh; /* 0xB8 */
+ unsigned short res21;
+ unsigned short systest; /* 0xBC */
+ unsigned short res22;
+ unsigned short bufstat; /* 0xC0 */
+ unsigned short res23;
+};
+
+#endif /* _OMAP4_I2C_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
new file mode 100644
index 0000000..e5d8b53
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+/*
+ * OMAP HSMMC register definitions
+ */
+
+#define OMAP_HSMMC1_BASE 0x4809C100
+#define OMAP_HSMMC2_BASE 0x480B4100
+#define OMAP_HSMMC3_BASE 0x480AD100
+
+typedef struct hsmmc {
+ unsigned char res1[0x10];
+ unsigned int sysconfig; /* 0x10 */
+ unsigned int sysstatus; /* 0x14 */
+ unsigned char res2[0x14];
+ unsigned int con; /* 0x2C */
+ unsigned char res3[0xD4];
+ unsigned int blk; /* 0x104 */
+ unsigned int arg; /* 0x108 */
+ unsigned int cmd; /* 0x10C */
+ unsigned int rsp10; /* 0x110 */
+ unsigned int rsp32; /* 0x114 */
+ unsigned int rsp54; /* 0x118 */
+ unsigned int rsp76; /* 0x11C */
+ unsigned int data; /* 0x120 */
+ unsigned int pstate; /* 0x124 */
+ unsigned int hctl; /* 0x128 */
+ unsigned int sysctl; /* 0x12C */
+ unsigned int stat; /* 0x130 */
+ unsigned int ie; /* 0x134 */
+ unsigned char res4[0x8];
+ unsigned int capa; /* 0x140 */
+} hsmmc_t;
+
+/*
+ * OMAP HS MMC Bit definitions
+ */
+#define MMC_SOFTRESET (0x1 << 1)
+#define RESETDONE (0x1 << 0)
+#define NOOPENDRAIN (0x0 << 0)
+#define OPENDRAIN (0x1 << 0)
+#define OD (0x1 << 0)
+#define INIT_NOINIT (0x0 << 1)
+#define INIT_INITSTREAM (0x1 << 1)
+#define HR_NOHOSTRESP (0x0 << 2)
+#define STR_BLOCK (0x0 << 3)
+#define MODE_FUNC (0x0 << 4)
+#define DW8_1_4BITMODE (0x0 << 5)
+#define MIT_CTO (0x0 << 6)
+#define CDP_ACTIVEHIGH (0x0 << 7)
+#define WPP_ACTIVEHIGH (0x0 << 8)
+#define RESERVED_MASK (0x3 << 9)
+#define CTPL_MMC_SD (0x0 << 11)
+#define BLEN_512BYTESLEN (0x200 << 0)
+#define NBLK_STPCNT (0x0 << 16)
+#define DE_DISABLE (0x0 << 0)
+#define BCE_DISABLE (0x0 << 1)
+#define ACEN_DISABLE (0x0 << 2)
+#define DDIR_OFFSET (4)
+#define DDIR_MASK (0x1 << 4)
+#define DDIR_WRITE (0x0 << 4)
+#define DDIR_READ (0x1 << 4)
+#define MSBS_SGLEBLK (0x0 << 5)
+#define RSP_TYPE_OFFSET (16)
+#define RSP_TYPE_MASK (0x3 << 16)
+#define RSP_TYPE_NORSP (0x0 << 16)
+#define RSP_TYPE_LGHT136 (0x1 << 16)
+#define RSP_TYPE_LGHT48 (0x2 << 16)
+#define RSP_TYPE_LGHT48B (0x3 << 16)
+#define CCCE_NOCHECK (0x0 << 19)
+#define CCCE_CHECK (0x1 << 19)
+#define CICE_NOCHECK (0x0 << 20)
+#define CICE_CHECK (0x1 << 20)
+#define DP_OFFSET (21)
+#define DP_MASK (0x1 << 21)
+#define DP_NO_DATA (0x0 << 21)
+#define DP_DATA (0x1 << 21)
+#define CMD_TYPE_NORMAL (0x0 << 22)
+#define INDEX_OFFSET (24)
+#define INDEX_MASK (0x3f << 24)
+#define INDEX(i) (i << 24)
+#define DATI_MASK (0x1 << 1)
+#define DATI_CMDDIS (0x1 << 1)
+#define DTW_1_BITMODE (0x0 << 1)
+#define DTW_4_BITMODE (0x1 << 1)
+#define SDBP_PWROFF (0x0 << 8)
+#define SDBP_PWRON (0x1 << 8)
+#define SDVS_1V8 (0x5 << 9)
+#define SDVS_3V0 (0x6 << 9)
+#define ICE_MASK (0x1 << 0)
+#define ICE_STOP (0x0 << 0)
+#define ICS_MASK (0x1 << 1)
+#define ICS_NOTREADY (0x0 << 1)
+#define ICE_OSCILLATE (0x1 << 0)
+#define CEN_MASK (0x1 << 2)
+#define CEN_DISABLE (0x0 << 2)
+#define CEN_ENABLE (0x1 << 2)
+#define CLKD_OFFSET (6)
+#define CLKD_MASK (0x3FF << 6)
+#define DTO_MASK (0xF << 16)
+#define DTO_15THDTO (0xE << 16)
+#define SOFTRESETALL (0x1 << 24)
+#define CC_MASK (0x1 << 0)
+#define TC_MASK (0x1 << 1)
+#define BWR_MASK (0x1 << 4)
+#define BRR_MASK (0x1 << 5)
+#define ERRI_MASK (0x1 << 15)
+#define IE_CC (0x01 << 0)
+#define IE_TC (0x01 << 1)
+#define IE_BWR (0x01 << 4)
+#define IE_BRR (0x01 << 5)
+#define IE_CTO (0x01 << 16)
+#define IE_CCRC (0x01 << 17)
+#define IE_CEB (0x01 << 18)
+#define IE_CIE (0x01 << 19)
+#define IE_DTO (0x01 << 20)
+#define IE_DCRC (0x01 << 21)
+#define IE_DEB (0x01 << 22)
+#define IE_CERR (0x01 << 28)
+#define IE_BADA (0x01 << 29)
+
+#define VS30_3V0SUP (1 << 25)
+#define VS18_1V8SUP (1 << 26)
+
+/* Driver definitions */
+#define MMCSD_SECTOR_SIZE 512
+#define MMC_CARD 0
+#define SD_CARD 1
+#define BYTE_MODE 0
+#define SECTOR_MODE 1
+#define CLK_INITSEQ 0
+#define CLK_400KHZ 1
+#define CLK_MISC 2
+
+typedef struct {
+ unsigned int card_type;
+ unsigned int version;
+ unsigned int mode;
+ unsigned int size;
+ unsigned int RCA;
+} mmc_card_data;
+
+#define mmc_reg_out(addr, mask, val)\
+ writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
+
+#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
new file mode 100644
index 0000000..d123d6a
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Authors:
+ * Aneesh V <aneesh@ti.com>
+ *
+ * Derived from OMAP3 work by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAP4_H_
+#define _OMAP4_H_
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+/*
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP44XX_L4_CORE_BASE 0x4A000000
+#define OMAP44XX_L4_WKUP_BASE 0x4A300000
+#define OMAP44XX_L4_PER_BASE 0x48000000
+
+/* CONTROL */
+#define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000)
+
+/* UART */
+#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
+#define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000)
+#define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000)
+
+/* General Purpose Timers */
+#define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000)
+#define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000)
+#define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000)
+
+/* Watchdog Timer2 - MPU watchdog */
+#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000)
+
+/* 32KTIMER */
+#define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
+
+/* GPMC */
+#define GPMC_BASE 0x50000000
+
+/*
+ * Hardware Register Details
+ */
+
+/* Watchdog Timer */
+#define WD_UNLOCK1 0xAAAA
+#define WD_UNLOCK2 0x5555
+
+/* GP Timer */
+#define TCLR_ST (0x1 << 0)
+#define TCLR_AR (0x1 << 1)
+#define TCLR_PRE (0x1 << 5)
+
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE 0x4A306000
+#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL PRM_DEVICE_BASE
+
+#ifndef __ASSEMBLY__
+
+struct s32ktimer {
+ unsigned char res[0x10];
+ unsigned int s32k_cr; /* 0x10 */
+};
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Non-secure SRAM Addresses
+ * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
+ * at 0x40304000(EMU base) so that our code works for both EMU and GP
+ */
+#define NON_SECURE_SRAM_START 0x40304000
+#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_ROM_VECT_BASE 0x4030D000
+/* Temporary SRAM stack used while low level init is done */
+#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
+
+/*
+ * OMAP4 real hardware:
+ * TODO: Change this to the IDCODE in the hw regsiter
+ */
+#define CPU_OMAP4430_ES10 1
+#define CPU_OMAP4430_ES20 2
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
new file mode 100644
index 0000000..6f4d3d5
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#include <asm/arch/omap4.h>
+#include <asm/io.h>
+
+struct omap_sysinfo {
+ char *board_string;
+};
+
+void watchdog_init(void);
+u32 get_device_type(void);
+void invalidate_dcache(u32);
+
+extern const struct omap_sysinfo sysinfo;
+
+#endif
diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h
new file mode 100644
index 0000000..035a57e
--- /dev/null
+++ b/arch/arm/include/asm/arch-pxa/macro.h
@@ -0,0 +1,324 @@
+/*
+ * arch/arm/include/asm/arch-pxa/macro.h
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_PXA_MACRO_H__
+#define __ASM_ARCH_PXA_MACRO_H__
+#ifdef __ASSEMBLY__
+
+#include <asm/macro.h>
+#include <asm/arch/pxa-regs.h>
+
+/*
+ * This macro performs a 32bit write to a memory location and makes sure the
+ * write operation really happened by performing a read back.
+ *
+ * Clobbered regs: r4, r5
+ */
+.macro write32rb addr, data
+ ldr r4, =\addr
+ ldr r5, =\data
+ str r5, [r4]
+ ldr r5, [r4]
+.endm
+
+/*
+ * This macro waits according to OSCR incrementation
+ *
+ * Clobbered regs: r4, r5, r6
+ */
+.macro pxa_wait_ticks ticks
+ ldr r4, =OSCR
+ mov r5, #0
+ str r5, [r4]
+ ldr r5, =\ticks
+1:
+ ldr r6, [r4]
+ cmp r5, r6
+ bgt 1b
+.endm
+
+/*
+ * This macro sets up the GPIO pins of the PXA2xx/PXA3xx CPU
+ *
+ * Clobbered regs: r4, r5
+ */
+.macro pxa_gpio_setup
+ write32 GPSR0, CONFIG_SYS_GPSR0_VAL
+ write32 GPSR1, CONFIG_SYS_GPSR1_VAL
+ write32 GPSR2, CONFIG_SYS_GPSR2_VAL
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ write32 GPSR3, CONFIG_SYS_GPSR3_VAL
+#endif
+
+ write32 GPCR0, CONFIG_SYS_GPCR0_VAL
+ write32 GPCR1, CONFIG_SYS_GPCR1_VAL
+ write32 GPCR2, CONFIG_SYS_GPCR2_VAL
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ write32 GPCR3, CONFIG_SYS_GPCR3_VAL
+#endif
+
+ write32 GPDR0, CONFIG_SYS_GPDR0_VAL
+ write32 GPDR1, CONFIG_SYS_GPDR1_VAL
+ write32 GPDR2, CONFIG_SYS_GPDR2_VAL
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ write32 GPDR3, CONFIG_SYS_GPDR3_VAL
+#endif
+
+ write32 GAFR0_L, CONFIG_SYS_GAFR0_L_VAL
+ write32 GAFR0_U, CONFIG_SYS_GAFR0_U_VAL
+ write32 GAFR1_L, CONFIG_SYS_GAFR1_L_VAL
+ write32 GAFR1_U, CONFIG_SYS_GAFR1_U_VAL
+ write32 GAFR2_L, CONFIG_SYS_GAFR2_L_VAL
+ write32 GAFR2_U, CONFIG_SYS_GAFR2_U_VAL
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ write32 GAFR3_L, CONFIG_SYS_GAFR3_L_VAL
+ write32 GAFR3_U, CONFIG_SYS_GAFR3_U_VAL
+#endif
+
+ write32 PSSR, CONFIG_SYS_PSSR_VAL
+.endm
+
+/*
+ * This macro sets up the Memory controller of the PXA2xx CPU
+ *
+ * Clobbered regs: r3, r4, r5
+ */
+.macro pxa_mem_setup
+ /* This comes handy when setting MDREFR */
+ ldr r3, =MEMC_BASE
+
+ /*
+ * 1) Initialize Asynchronous static memory controller
+ */
+
+ /* MSC0: nCS(0,1) */
+ write32rb (MEMC_BASE + MSC0_OFFSET), CONFIG_SYS_MSC0_VAL
+ /* MSC1: nCS(2,3) */
+ write32rb (MEMC_BASE + MSC1_OFFSET), CONFIG_SYS_MSC1_VAL
+ /* MSC2: nCS(4,5) */
+ write32rb (MEMC_BASE + MSC2_OFFSET), CONFIG_SYS_MSC2_VAL
+
+ /*
+ * 2) Initialize Card Interface
+ */
+
+ /* MECR: Memory Expansion Card Register */
+ write32rb (MEMC_BASE + MECR_OFFSET), CONFIG_SYS_MECR_VAL
+ /* MCMEM0: Card Interface slot 0 timing */
+ write32rb (MEMC_BASE + MCMEM0_OFFSET), CONFIG_SYS_MCMEM0_VAL
+ /* MCMEM1: Card Interface slot 1 timing */
+ write32rb (MEMC_BASE + MCMEM1_OFFSET), CONFIG_SYS_MCMEM1_VAL
+ /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+ write32rb (MEMC_BASE + MCATT0_OFFSET), CONFIG_SYS_MCATT0_VAL
+ /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+ write32rb (MEMC_BASE + MCATT1_OFFSET), CONFIG_SYS_MCATT1_VAL
+ /* MCIO0: Card Interface I/O Space Timing, slot 0 */
+ write32rb (MEMC_BASE + MCIO0_OFFSET), CONFIG_SYS_MCIO0_VAL
+ /* MCIO1: Card Interface I/O Space Timing, slot 1 */
+ write32rb (MEMC_BASE + MCIO1_OFFSET), CONFIG_SYS_MCIO1_VAL
+
+ /*
+ * 3) Configure Fly-By DMA register
+ */
+
+ write32rb (MEMC_BASE + FLYCNFG_OFFSET), CONFIG_SYS_FLYCNFG_VAL
+
+ /*
+ * 4) Initialize Timing for Sync Memory (SDCLK0)
+ */
+
+ /*
+ * Before accessing MDREFR we need a valid DRI field, so we set
+ * this to power on defaults + DRI field.
+ */
+ ldr r5, [r3, #MDREFR_OFFSET]
+ bic r5, r5, #0x0ff
+ bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */
+
+ ldr r4, =CONFIG_SYS_MDREFR_VAL
+ mov r6, r4
+ lsl r4, #20
+ lsr r4, #20 /* Get a valid DRI field */
+
+ orr r5, r5, r4 /* MDREFR user config with correct DRI */
+
+ orr r5, #MDREFR_K0RUN
+ orr r5, #MDREFR_SLFRSH
+ bic r5, #MDREFR_APD
+ bic r5, #MDREFR_E1PIN
+
+ str r5, [r3, #MDREFR_OFFSET]
+ ldr r4, [r3, #MDREFR_OFFSET]
+
+ /*
+ * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
+ */
+
+ /* Initialize SXCNFG register. Assert the enable bits.
+ *
+ * Write SXMRS to cause an MRS command to all enabled banks of
+ * synchronous static memory. Note that SXLCR need not be written
+ * at this time.
+ */
+ write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL
+
+ /*
+ * 6) Initialize SDRAM
+ */
+
+ bic r6, #MDREFR_SLFRSH
+ str r6, [r3, #MDREFR_OFFSET]
+ ldr r4, [r3, #MDREFR_OFFSET]
+
+ orr r6, #MDREFR_E1PIN
+ str r6, [r3, #MDREFR_OFFSET]
+ ldr r4, [r3, #MDREFR_OFFSET]
+
+ /*
+ * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
+ * but not enable each SDRAM partition pair.
+ */
+
+ /* Fetch platform value of MDCNFG */
+ ldr r4, =CONFIG_SYS_MDCNFG_VAL
+ /* Disable all sdram banks */
+ bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
+ bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
+ /* Write initial value of MDCNFG, w/o enabling sdram banks */
+ str r4, [r3, #MDCNFG_OFFSET]
+ ldr r4, [r3, #MDCNFG_OFFSET]
+
+ /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
+ pxa_wait_ticks 0x300
+
+ /*
+ * 8) Trigger a number (usually 8) refresh cycles by attempting
+ * non-burst read or write accesses to disabled SDRAM, as commonly
+ * specified in the power up sequence documented in SDRAM data
+ * sheets. The address(es) used for this purpose must not be
+ * cacheable.
+ */
+
+ ldr r4, =CONFIG_SYS_DRAM_BASE
+.rept 9
+ str r5, [r4]
+.endr
+
+ /*
+ * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
+ */
+
+ ldr r5, =CONFIG_SYS_MDCNFG_VAL
+ ldr r4, =(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3)
+ and r5, r5, r4
+ ldr r4, [r3, #MDCNFG_OFFSET]
+ orr r4, r4, r5
+ str r4, [r3, #MDCNFG_OFFSET]
+ ldr r4, [r3, #MDCNFG_OFFSET]
+
+ /*
+ * 10) Write MDMRS.
+ */
+
+ ldr r4, =CONFIG_SYS_MDMRS_VAL
+ str r4, [r3, #MDMRS_OFFSET]
+ ldr r4, [r3, #MDMRS_OFFSET]
+
+ /*
+ * 11) Enable APD
+ */
+
+ ldr r4, [r3, #MDREFR_OFFSET]
+ and r6, r6, #MDREFR_APD
+ orr r4, r4, r6
+ str r4, [r3, #MDREFR_OFFSET]
+ ldr r4, [r3, #MDREFR_OFFSET]
+.endm
+
+/*
+ * This macro tests if the CPU woke up from sleep and eventually resumes
+ *
+ * Clobbered regs: r4, r5
+ */
+.macro pxa_wakeup
+ ldr r4, =RCSR
+ ldr r5, [r4]
+ and r5, r5, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
+ str r5, [r4]
+ teq r5, #RCSR_SMR
+
+ bne pxa_wakeup_exit
+
+ ldr r4, =PSSR
+ mov r5, #PSSR_PH
+ str r5, [r4]
+
+ ldr r4, =PSPR
+ ldr pc, [r4]
+pxa_wakeup_exit:
+.endm
+
+/*
+ * This macro disables all interupts on PXA2xx/PXA3xx CPU
+ *
+ * Clobbered regs: r4, r5
+ */
+.macro pxa_intr_setup
+ write32 ICLR, 0
+ write32 ICMR, 0
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ write32 ICLR2, 0
+ write32 ICMR2, 0
+#endif
+.endm
+
+/*
+ * This macro configures clock on PXA2xx/PXA3xx CPU
+ *
+ * Clobbered regs: r4, r5
+ */
+.macro pxa_clock_setup
+ /* Disable the peripheral clocks, and set the core clock frequency */
+
+ /* Turn Off ALL on-chip peripheral clocks for re-configuration */
+ write32 CKEN, CONFIG_SYS_CKEN
+
+ /* Write CCCR */
+ write32 CCCR, CONFIG_SYS_CCCR
+
+#ifdef CONFIG_RTC
+ /* enable the 32Khz oscillator for RTC and PowerManager */
+ write32 OSCC, #OSCC_OON
+ ldr r4, =OSCC
+
+ /* Spin here until OSCC.OOK get set, meaning the PLL has settled. */
+2:
+ ldr r5, [r4]
+ ands r5, r5, #1
+ beq 2b
+#endif
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_PXA_MACRO_H__ */
diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h
index cd7b7f9..d442fb0 100644
--- a/arch/arm/include/asm/arch-pxa/pxa-regs.h
+++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h
@@ -1132,10 +1132,18 @@
#define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */
#define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */
-#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */
+#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1 Control Register */
#define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */
#define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */
+#define PWM_CTRL2 __REG(0x40B00010) /* PWM 2 Control Register */
+#define PWM_PWDUTY2 __REG(0x40B00014) /* PWM 2 Duty Cycle Register */
+#define PWM_PERVAL2 __REG(0x40B00018) /* PWM 2 Period Control Register */
+
+#define PWM_CTRL3 __REG(0x40C00010) /* PWM 3 Control Register */
+#define PWM_PWDUTY3 __REG(0x40C00014) /* PWM 3 Duty Cycle Register */
+#define PWM_PERVAL3 __REG(0x40C00018) /* PWM 3 Period Control Register */
+
/*
* Interrupt Controller
*/
diff --git a/board/colibri_pxa270/Makefile b/board/colibri_pxa270/Makefile
new file mode 100644
index 0000000..44d73cc
--- /dev/null
+++ b/board/colibri_pxa270/Makefile
@@ -0,0 +1,45 @@
+#
+# Toradex Colibri PXA270 Support
+#
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := colibri_pxa270.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/colibri_pxa270/colibri_pxa270.c b/board/colibri_pxa270/colibri_pxa270.c
new file mode 100644
index 0000000..d3822f0
--- /dev/null
+++ b/board/colibri_pxa270/colibri_pxa270.c
@@ -0,0 +1,118 @@
+/*
+ * Toradex Colibri PXA270 Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+extern struct serial_device serial_ffuart_device;
+extern struct serial_device serial_btuart_device;
+extern struct serial_device serial_stuart_device;
+
+struct serial_device *default_serial_console (void)
+{
+ return &serial_ffuart_device;
+}
+
+int board_init (void)
+{
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of vpac270 */
+ gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_USB
+int usb_board_init(void)
+{
+ UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+
+ UHCHR |= UHCHR_FSBIR;
+
+ while (UHCHR & UHCHR_FSBIR);
+
+ UHCHR &= ~UHCHR_SSE;
+ UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+
+ /* Clear any OTG Pin Hold */
+ if (PSSR & PSSR_OTGPH)
+ PSSR |= PSSR_OTGPH;
+
+ UHCRHDA &= ~(0x200);
+ UHCRHDA |= 0x100;
+
+ /* Set port power control mask bits, only 3 ports. */
+ UHCRHDB |= (0x7<<17);
+
+ /* enable port 2 */
+ UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
+
+ return 0;
+}
+
+void usb_board_init_fail(void)
+{
+ return;
+}
+
+void usb_board_stop(void)
+{
+ UHCHR |= UHCHR_FHR;
+ udelay(11);
+ UHCHR &= ~UHCHR_FHR;
+
+ UHCCOMS |= 1;
+ udelay(10);
+
+ CKEN &= ~CKEN10_USBHOST;
+
+ return;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+#endif
diff --git a/board/colibri_pxa270/config.mk b/board/colibri_pxa270/config.mk
new file mode 100644
index 0000000..1d650ac
--- /dev/null
+++ b/board/colibri_pxa270/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xa1000000
diff --git a/board/colibri_pxa270/lowlevel_init.S b/board/colibri_pxa270/lowlevel_init.S
new file mode 100644
index 0000000..a43dac2
--- /dev/null
+++ b/board/colibri_pxa270/lowlevel_init.S
@@ -0,0 +1,36 @@
+/*
+ * Toradex Colibri PXA270 Lowlevel Hardware Initialization
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/macro.h>
+
+.globl lowlevel_init
+lowlevel_init:
+ pxa_gpio_setup
+ pxa_wait_ticks 0x8000
+ pxa_mem_setup
+ pxa_wakeup
+ pxa_intr_setup
+ pxa_clock_setup
+
+ mov pc, lr
diff --git a/board/logicpd/zoom2/zoom2.c b/board/logicpd/zoom2/zoom2.c
index 6455d1d..e9f6625 100644
--- a/board/logicpd/zoom2/zoom2.c
+++ b/board/logicpd/zoom2/zoom2.c
@@ -46,7 +46,7 @@
/*
* This the the zoom2, board specific, gpmc configuration for the
* quad uart on the debug board. The more general gpmc configurations
- * are setup at the cpu level in arch/arm/cpu/arm_cortexa8/omap3/mem.c
+ * are setup at the cpu level in arch/arm/cpu/armv7/omap3/mem.c
*
* The details of the setting of the serial gpmc setup are not available.
* The values were provided by another party.
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile b/board/ti/panda/Makefile
similarity index 68%
copy from arch/arm/cpu/arm_cortexa8/omap3/Makefile
copy to board/ti/panda/Makefile
index 7d63c6b..81e5469 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
+++ b/board/ti/panda/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -12,7 +12,7 @@
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
@@ -23,30 +23,21 @@
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(BOARD).a
-SOBJS := lowlevel_init.o
-SOBJS += cache.o
-SOBJS += reset.o
+COBJS := panda.o
-COBJS += board.o
-COBJS += clock.o
-COBJS += gpio.o
-COBJS += mem.o
-COBJS += syslib.o
-COBJS += sys_info.o
-COBJS += timer.o
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
-COBJS-$(CONFIG_EMIF4) += emif4.o
-COBJS-$(CONFIG_SDRC) += sdrc.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
-all: $(obj).depend $(LIB)
+clean:
+ rm -f $(OBJS)
-$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
diff --git a/board/ti/panda/config.mk b/board/ti/panda/config.mk
new file mode 100644
index 0000000..7382263
--- /dev/null
+++ b/board/ti/panda/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2006-2009
+# Texas Instruments Incorporated, <www.ti.com>
+#
+# OMAP 4430 SDP
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# SDRAM Address Space:
+# 8000'0000 - 9fff'ffff (512 MB)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# Let's place u-boot 1MB before the end of SDRAM.
+TEXT_BASE = 0x9ff00000
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
new file mode 100644
index 0000000..46a5d1d
--- /dev/null
+++ b/board/ti/panda/panda.c
@@ -0,0 +1,61 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+ "Board: OMAP4 Panda\n"
+};
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA;
+ gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+/**
+ * @brief misc_init_r - Configure Panda board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+ return 0;
+}
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile b/board/ti/sdp4430/Makefile
similarity index 68%
copy from arch/arm/cpu/arm_cortexa8/omap3/Makefile
copy to board/ti/sdp4430/Makefile
index 7d63c6b..2554c7b 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
+++ b/board/ti/sdp4430/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -12,7 +12,7 @@
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
@@ -23,30 +23,21 @@
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(BOARD).a
-SOBJS := lowlevel_init.o
-SOBJS += cache.o
-SOBJS += reset.o
+COBJS := sdp.o
-COBJS += board.o
-COBJS += clock.o
-COBJS += gpio.o
-COBJS += mem.o
-COBJS += syslib.o
-COBJS += sys_info.o
-COBJS += timer.o
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
-COBJS-$(CONFIG_EMIF4) += emif4.o
-COBJS-$(CONFIG_SDRC) += sdrc.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
-all: $(obj).depend $(LIB)
+clean:
+ rm -f $(OBJS)
-$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
diff --git a/board/ti/sdp4430/config.mk b/board/ti/sdp4430/config.mk
new file mode 100644
index 0000000..7382263
--- /dev/null
+++ b/board/ti/sdp4430/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2006-2009
+# Texas Instruments Incorporated, <www.ti.com>
+#
+# OMAP 4430 SDP
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# SDRAM Address Space:
+# 8000'0000 - 9fff'ffff (512 MB)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# Let's place u-boot 1MB before the end of SDRAM.
+TEXT_BASE = 0x9ff00000
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
new file mode 100644
index 0000000..6ae016c
--- /dev/null
+++ b/board/ti/sdp4430/sdp.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+ "Board: OMAP4430 SDP\n"
+};
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP_4430SDP;
+ gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+/**
+ * @brief misc_init_r - Configure SDP board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+ return 0;
+}
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile b/board/vpac270/Makefile
similarity index 66%
copy from arch/arm/cpu/arm_cortexa8/omap3/Makefile
copy to board/vpac270/Makefile
index 7d63c6b..0f3eacd 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
+++ b/board/vpac270/Makefile
@@ -1,5 +1,6 @@
+
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -23,36 +24,25 @@
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = lib$(BOARD).a
+OBJS := vpac270.o
SOBJS := lowlevel_init.o
-SOBJS += cache.o
-SOBJS += reset.o
-
-COBJS += board.o
-COBJS += clock.o
-COBJS += gpio.o
-COBJS += mem.o
-COBJS += syslib.o
-COBJS += sys_info.o
-COBJS += timer.o
-COBJS-$(CONFIG_EMIF4) += emif4.o
-COBJS-$(CONFIG_SDRC) += sdrc.o
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
+clean:
+ rm -f $(SOBJS) $(OBJS)
-all: $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
#########################################################################
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-sinclude $(obj).depend
+-include .depend
#########################################################################
diff --git a/board/vpac270/config.mk b/board/vpac270/config.mk
new file mode 100644
index 0000000..1d650ac
--- /dev/null
+++ b/board/vpac270/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xa1000000
diff --git a/board/vpac270/lowlevel_init.S b/board/vpac270/lowlevel_init.S
new file mode 100644
index 0000000..ec0d12c
--- /dev/null
+++ b/board/vpac270/lowlevel_init.S
@@ -0,0 +1,40 @@
+/*
+ * Voipac PXA270 Lowlevel Hardware Initialization
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/macro.h>
+
+.globl lowlevel_init
+lowlevel_init:
+ pxa_gpio_setup
+ pxa_wait_ticks 0x8000
+ pxa_mem_setup
+ pxa_wakeup
+ pxa_intr_setup
+ pxa_clock_setup
+
+ mov pc, lr
diff --git a/arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds b/board/vpac270/u-boot.lds
similarity index 76%
copy from arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds
copy to board/vpac270/u-boot.lds
index 2953b93..58c371d 100644
--- a/arch/arm/cpu/arm_cortexa8/mx51/u-boot.lds
+++ b/board/vpac270/u-boot.lds
@@ -1,11 +1,6 @@
/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -17,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -34,9 +29,9 @@
. = 0x00000000;
. = ALIGN(4);
- .text :
+ .text :
{
- arch/arm/cpu/arm_cortexa8/start.o
+ cpu/pxa/start.o (.text)
*(.text)
}
@@ -49,7 +44,6 @@
. = ALIGN(4);
.got : { *(.got) }
- . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c
new file mode 100644
index 0000000..48e93ab
--- /dev/null
+++ b/board/vpac270/vpac270.c
@@ -0,0 +1,127 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+extern struct serial_device serial_ffuart_device;
+extern struct serial_device serial_btuart_device;
+extern struct serial_device serial_stuart_device;
+
+struct serial_device *default_serial_console (void)
+{
+ return &serial_ffuart_device;
+}
+
+int board_init (void)
+{
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of vpac270 */
+ gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+ return 0;
+}
+
+int usb_board_init(void)
+{
+ UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+
+ UHCHR |= UHCHR_FSBIR;
+
+ while (UHCHR & UHCHR_FSBIR);
+
+ UHCHR &= ~UHCHR_SSE;
+ UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+
+ /* Clear any OTG Pin Hold */
+ if (PSSR & PSSR_OTGPH)
+ PSSR |= PSSR_OTGPH;
+
+ UHCRHDA &= ~(0x200);
+ UHCRHDA |= 0x100;
+
+ /* Set port power control mask bits, only 3 ports. */
+ UHCRHDB |= (0x7<<17);
+
+ /* enable port 2 */
+ UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
+
+ return 0;
+}
+
+void usb_board_init_fail(void)
+{
+ return;
+}
+
+void usb_board_stop(void)
+{
+ UHCHR |= UHCHR_FHR;
+ udelay(11);
+ UHCHR &= ~UHCHR_FHR;
+
+ UHCCOMS |= 1;
+ udelay(10);
+
+ CKEN &= ~CKEN10_USBHOST;
+
+ return;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+#endif
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile b/board/zipitz2/Makefile
similarity index 70%
copy from arch/arm/cpu/arm_cortexa8/omap3/Makefile
copy to board/zipitz2/Makefile
index 7d63c6b..2673835 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
+++ b/board/zipitz2/Makefile
@@ -1,6 +1,9 @@
+
+#
+# Copyright (C) 2009
+# Marek Vasut <marek.vasut@gmail.com>
#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Heavily based on pxa255_idp platform
#
# See file CREDITS for list of people who contributed to this
# project.
@@ -23,30 +26,23 @@
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(SOC).a
+LIB = $(obj)lib$(BOARD).a
+COBJS := zipitz2.o
SOBJS := lowlevel_init.o
-SOBJS += cache.o
-SOBJS += reset.o
-
-COBJS += board.o
-COBJS += clock.o
-COBJS += gpio.o
-COBJS += mem.o
-COBJS += syslib.o
-COBJS += sys_info.o
-COBJS += timer.o
-
-COBJS-$(CONFIG_EMIF4) += emif4.o
-COBJS-$(CONFIG_SDRC) += sdrc.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-all: $(obj).depend $(LIB)
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
-$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
diff --git a/board/zipitz2/config.mk b/board/zipitz2/config.mk
new file mode 100644
index 0000000..1d650ac
--- /dev/null
+++ b/board/zipitz2/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xa1000000
diff --git a/board/zipitz2/lowlevel_init.S b/board/zipitz2/lowlevel_init.S
new file mode 100644
index 0000000..82a52e8
--- /dev/null
+++ b/board/zipitz2/lowlevel_init.S
@@ -0,0 +1,40 @@
+/*
+ * Aeronix Zipit Z2 Lowlevel Hardware Initialization
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/macro.h>
+
+.globl lowlevel_init
+lowlevel_init:
+ pxa_gpio_setup
+ pxa_wait_ticks 0x8000
+ pxa_mem_setup
+ pxa_wakeup
+ pxa_intr_setup
+ pxa_clock_setup
+
+ mov pc, lr
diff --git a/arch/arm/cpu/arm_cortexa8/u-boot.lds b/board/zipitz2/u-boot.lds
similarity index 77%
copy from arch/arm/cpu/arm_cortexa8/u-boot.lds
copy to board/zipitz2/u-boot.lds
index 820e3a1..fb4358b 100644
--- a/arch/arm/cpu/arm_cortexa8/u-boot.lds
+++ b/board/zipitz2/u-boot.lds
@@ -1,9 +1,6 @@
/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -15,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -32,10 +29,10 @@
. = 0x00000000;
. = ALIGN(4);
- .text :
+ .text :
{
- arch/arm/cpu/arm_cortexa8/start.o (.text)
- *(.text)
+ cpu/pxa/start.o (.text)
+ *(.text)
}
. = ALIGN(4);
@@ -47,12 +44,13 @@
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
- .bss : { *(.bss) }
+ .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
_end = .;
}
diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c
new file mode 100644
index 0000000..14d1d76
--- /dev/null
+++ b/board/zipitz2/zipitz2.c
@@ -0,0 +1,213 @@
+/*
+ * Copyright (C) 2009
+ * Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Heavily based on pxa255_idp platform
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <serial.h>
+#include <asm/arch/hardware.h>
+#include <spi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_SPI
+void lcd_start(void);
+#else
+inline void lcd_start(void) {};
+#endif
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of Lubbock-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ /* Enable LCD */
+ lcd_start();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setenv("stdout", "serial");
+ setenv("stderr", "serial");
+ return 0;
+}
+
+struct serial_device *default_serial_console (void)
+{
+ return &serial_stuart_device;
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_SPI
+
+struct {
+ unsigned char reg;
+ unsigned short data;
+ unsigned char mdelay;
+} lcd_data[] = {
+ { 0x07, 0x0000, 0 },
+ { 0x13, 0x0000, 10 },
+ { 0x11, 0x3004, 0 },
+ { 0x14, 0x200F, 0 },
+ { 0x10, 0x1a20, 0 },
+ { 0x13, 0x0040, 50 },
+ { 0x13, 0x0060, 0 },
+ { 0x13, 0x0070, 200 },
+ { 0x01, 0x0127, 0 },
+ { 0x02, 0x0700, 0 },
+ { 0x03, 0x1030, 0 },
+ { 0x08, 0x0208, 0 },
+ { 0x0B, 0x0620, 0 },
+ { 0x0C, 0x0110, 0 },
+ { 0x30, 0x0120, 0 },
+ { 0x31, 0x0127, 0 },
+ { 0x32, 0x0000, 0 },
+ { 0x33, 0x0503, 0 },
+ { 0x34, 0x0727, 0 },
+ { 0x35, 0x0124, 0 },
+ { 0x36, 0x0706, 0 },
+ { 0x37, 0x0701, 0 },
+ { 0x38, 0x0F00, 0 },
+ { 0x39, 0x0F00, 0 },
+ { 0x40, 0x0000, 0 },
+ { 0x41, 0x0000, 0 },
+ { 0x42, 0x013f, 0 },
+ { 0x43, 0x0000, 0 },
+ { 0x44, 0x013f, 0 },
+ { 0x45, 0x0000, 0 },
+ { 0x46, 0xef00, 0 },
+ { 0x47, 0x013f, 0 },
+ { 0x48, 0x0000, 0 },
+ { 0x07, 0x0015, 30 },
+ { 0x07, 0x0017, 0 },
+ { 0x20, 0x0000, 0 },
+ { 0x21, 0x0000, 0 },
+ { 0x22, 0x0000, 0 },
+};
+
+void zipitz2_spi_sda(int set)
+{
+ /* GPIO 13 */
+ if (set)
+ GPSR0 = (1 << 13);
+ else
+ GPCR0 = (1 << 13);
+}
+
+void zipitz2_spi_scl(int set)
+{
+ /* GPIO 22 */
+ if (set)
+ GPCR0 = (1 << 22);
+ else
+ GPSR0 = (1 << 22);
+}
+
+unsigned char zipitz2_spi_read(void)
+{
+ /* GPIO 40 */
+ return !!(GPLR1 & (1 << 8));
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ /* Always valid */
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* GPIO 88 low */
+ GPCR2 = (1 << 24);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* GPIO 88 high */
+ GPSR2 = (1 << 24);
+
+}
+
+void lcd_start(void)
+{
+ int i;
+ unsigned char reg[3] = { 0x74, 0x00, 0 };
+ unsigned char data[3] = { 0x76, 0, 0 };
+ unsigned char dummy[3] = { 0, 0, 0 };
+
+ /* PWM2 AF */
+ GAFR0_L |= 0x00800000;
+ /* Enable clock to all PWM */
+ CKEN |= 0x3;
+ /* Configure PWM2 */
+ PWM_CTRL2 = 0x4f;
+ PWM_PWDUTY2 = 0x2ff;
+ PWM_PERVAL2 = 792;
+
+ /* Toggle the reset pin to reset the LCD */
+ GPSR0 = (1 << 19);
+ udelay(100000);
+ GPCR0 = (1 << 19);
+ udelay(20000);
+ GPSR0 = (1 << 19);
+ udelay(20000);
+
+ /* Program the LCD init sequence */
+ for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) {
+ reg[0] = 0x74;
+ reg[1] = 0x0;
+ reg[2] = lcd_data[i].reg;
+ spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
+
+ data[0] = 0x76;
+ data[1] = lcd_data[i].data >> 8;
+ data[2] = lcd_data[i].data & 0xff;
+ spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
+
+ if (lcd_data[i].mdelay)
+ udelay(lcd_data[i].mdelay * 1000);
+ }
+
+ GPSR0 = (1 << 11);
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index 30b4137..8aab169 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -45,13 +45,14 @@
pm9263 arm arm926ejs - ronetix at91
suen3 arm arm926ejs km_arm keymile kirkwood
rd6281a arm arm926ejs - Marvell kirkwood
-mx51evk arm arm_cortexa8 mx51evk freescale mx51
+mx51evk arm armv7 mx51evk freescale mx51
actux1 arm ixp
actux2 arm ixp
actux3 arm ixp
actux4 arm ixp
ixdp425 arm ixp
cerf250 arm pxa
+colibri_pxa270 arm pxa
cradle arm pxa
csb226 arm pxa
delta arm pxa
@@ -61,6 +62,7 @@
pleb2 arm pxa
xaeniax arm pxa
xm250 arm pxa
+zipitz2 arm pxa
B2 arm s3c44b0 - dave
assabet arm sa1100
dnp1110 arm sa1100
@@ -253,17 +255,19 @@
magnesium arm arm926ejs imx27lite logicpd mx27
omap5912osk arm arm926ejs - ti omap
edminiv2 arm arm926ejs - LaCie orion5x
-omap3_overo arm arm_cortexa8 overo - omap3
-omap3_pandora arm arm_cortexa8 pandora - omap3
-omap3_zoom1 arm arm_cortexa8 zoom1 logicpd omap3
-omap3_zoom2 arm arm_cortexa8 zoom2 logicpd omap3
-omap3_beagle arm arm_cortexa8 beagle ti omap3
-omap3_evm arm arm_cortexa8 evm ti omap3
-omap3_sdp3430 arm arm_cortexa8 sdp3430 ti omap3
-am3517_evm arm arm_cortexa8 am3517evm logicpd omap3
-devkit8000 arm arm_cortexa8 devkit8000 timll omap3
-s5p_goni arm arm_cortexa8 goni samsung s5pc1xx
-smdkc100 arm arm_cortexa8 smdkc100 samsung s5pc1xx
+omap3_overo arm armv7 overo - omap3
+omap3_pandora arm armv7 pandora - omap3
+omap3_zoom1 arm armv7 zoom1 logicpd omap3
+omap3_zoom2 arm armv7 zoom2 logicpd omap3
+omap3_beagle arm armv7 beagle ti omap3
+omap3_evm arm armv7 evm ti omap3
+omap3_sdp3430 arm armv7 sdp3430 ti omap3
+omap4_panda arm armv7 panda ti omap4
+omap4_sdp4430 arm armv7 sdp4430 ti omap4
+am3517_evm arm armv7 am3517evm logicpd omap3
+devkit8000 arm armv7 devkit8000 timll omap3
+s5p_goni arm armv7 goni samsung s5pc1xx
+smdkc100 arm armv7 smdkc100 samsung s5pc1xx
ixdpg425 arm ixp
lpd7a400 arm lh7a40x lpd7a40x
lpd7a404 arm lh7a40x lpd7a40x
diff --git a/common/lcd.c b/common/lcd.c
index 93ddedf..d854c21 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -41,7 +41,7 @@
#include <lcd.h>
#include <watchdog.h>
-#if defined(CONFIG_PXA250)
+#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
#include <asm/byteorder.h>
#endif
@@ -503,7 +503,7 @@
uchar *bmap;
uchar *fb;
ushort *fb16;
-#if defined(CONFIG_PXA250)
+#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
struct pxafb_info *fbi = &panel_info.pxa;
#elif defined(CONFIG_MPC823)
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
@@ -519,7 +519,7 @@
if (NBITS(panel_info.vl_bpix) < 12) {
/* Leave room for default color map */
-#if defined(CONFIG_PXA250)
+#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
cmap = (ushort *)fbi->palette;
#elif defined(CONFIG_MPC823)
cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]);
@@ -615,7 +615,7 @@
unsigned long pwidth = panel_info.vl_col;
unsigned colors, bpix, bmp_bpix;
unsigned long compression;
-#if defined(CONFIG_PXA250)
+#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
struct pxafb_info *fbi = &panel_info.pxa;
#elif defined(CONFIG_MPC823)
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
@@ -656,7 +656,7 @@
#if !defined(CONFIG_MCC200)
/* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */
if (bmp_bpix == 8) {
-#if defined(CONFIG_PXA250)
+#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
cmap = (ushort *)fbi->palette;
#elif defined(CONFIG_MPC823)
cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
@@ -745,7 +745,7 @@
WATCHDOG_RESET();
for (j = 0; j < width; j++) {
if (bpix != 16) {
-#if defined(CONFIG_PXA250) || defined(CONFIG_ATMEL_LCD)
+#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS || defined(CONFIG_ATMEL_LCD)
*(fb++) = *(bmap++);
#elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
*(fb++) = 255 - *(bmap++);
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index ff18991..3256133 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -25,6 +25,8 @@
#include <asm/arch/i2c.h>
#include <asm/io.h>
+#include "omap24xx_i2c.h"
+
static void wait_for_bb (void);
static u16 wait_for_pin (void);
static void flush_fifo(void);
@@ -176,7 +178,8 @@
status = wait_for_pin ();
if (status & I2C_STAT_RRDY) {
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
+ defined(CONFIG_OMAP44XX)
*value = readb (&i2c_base->data);
#else
*value = readw (&i2c_base->data);
@@ -221,7 +224,8 @@
status = wait_for_pin ();
if (status & I2C_STAT_XRDY) {
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
+ defined(CONFIG_OMAP44XX)
/* send out 1 byte */
writeb (regoffset, &i2c_base->data);
writew (I2C_STAT_XRDY, &i2c_base->stat);
@@ -274,7 +278,8 @@
while(1){
stat = readw(&i2c_base->stat);
if(stat == I2C_STAT_RRDY){
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
+ defined(CONFIG_OMAP44XX)
readb(&i2c_base->data);
#else
readw(&i2c_base->data);
@@ -435,3 +440,9 @@
return 0;
}
+
+int i2c_get_bus_num(void)
+{
+ return (int) current_bus;
+}
+
diff --git a/drivers/i2c/omap24xx_i2c.h b/drivers/i2c/omap24xx_i2c.h
new file mode 100644
index 0000000..92a3416
--- /dev/null
+++ b/drivers/i2c/omap24xx_i2c.h
@@ -0,0 +1,166 @@
+/*
+ * (C) Copyright 2004-2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP24XX_I2C_H_
+#define _OMAP24XX_I2C_H_
+
+/* I2C masks */
+
+/* I2C Interrupt Enable Register (I2C_IE): */
+#define I2C_IE_GC_IE (1 << 5)
+#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
+#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
+#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
+#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
+#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
+
+/* I2C Status Register (I2C_STAT): */
+
+#define I2C_STAT_SBD (1 << 15) /* Single byte data */
+#define I2C_STAT_BB (1 << 12) /* Bus busy */
+#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
+#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
+#define I2C_STAT_AAS (1 << 9) /* Address as slave */
+#define I2C_STAT_GC (1 << 5)
+#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
+#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
+#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
+#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
+#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
+
+/* I2C Interrupt Code Register (I2C_INTCODE): */
+
+#define I2C_INTCODE_MASK 7
+#define I2C_INTCODE_NONE 0
+#define I2C_INTCODE_AL 1 /* Arbitration lost */
+#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
+#define I2C_INTCODE_ARDY 3 /* Register access ready */
+#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
+#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
+
+/* I2C Buffer Configuration Register (I2C_BUF): */
+
+#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */
+#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */
+
+/* I2C Configuration Register (I2C_CON): */
+
+#define I2C_CON_EN (1 << 15) /* I2C module enable */
+#define I2C_CON_BE (1 << 14) /* Big endian mode */
+#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */
+#define I2C_CON_MST (1 << 10) /* Master/slave mode */
+#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */
+ /* (master mode only) */
+#define I2C_CON_XA (1 << 8) /* Expand address */
+#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */
+#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */
+
+/* I2C System Test Register (I2C_SYSTEST): */
+
+#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
+#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */
+#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
+#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
+#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */
+#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */
+#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */
+#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */
+
+#define I2C_SCLL_SCLL 0
+#define I2C_SCLL_SCLL_M 0xFF
+#define I2C_SCLL_HSSCLL 8
+#define I2C_SCLH_HSSCLL_M 0xFF
+#define I2C_SCLH_SCLH 0
+#define I2C_SCLH_SCLH_M 0xFF
+#define I2C_SCLH_HSSCLH 8
+#define I2C_SCLH_HSSCLH_M 0xFF
+
+#define OMAP_I2C_STANDARD 100000
+#define OMAP_I2C_FAST_MODE 400000
+#define OMAP_I2C_HIGH_SPEED 3400000
+
+#define SYSTEM_CLOCK_12 12000000
+#define SYSTEM_CLOCK_13 13000000
+#define SYSTEM_CLOCK_192 19200000
+#define SYSTEM_CLOCK_96 96000000
+
+/* Use the reference value of 96MHz if not explicitly set by the board */
+#ifndef I2C_IP_CLK
+#define I2C_IP_CLK SYSTEM_CLOCK_96
+#endif
+
+/*
+ * The reference minimum clock for high speed is 19.2MHz.
+ * The linux 2.6.30 kernel uses this value.
+ * The reference minimum clock for fast mode is 9.6MHz
+ * The reference minimum clock for standard mode is 4MHz
+ * In TRM, the value of 12MHz is used.
+ */
+#ifndef I2C_INTERNAL_SAMPLING_CLK
+#define I2C_INTERNAL_SAMPLING_CLK 19200000
+#endif
+
+/*
+ * The equation for the low and high time is
+ * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
+ * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
+ *
+ * If the duty cycle is 50%
+ *
+ * tlow = scll + scll_trim = sampling clock / (2 * speed)
+ * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
+ *
+ * In TRM
+ * scll_trim = 7
+ * sclh_trim = 5
+ *
+ * The linux 2.6.30 kernel uses
+ * scll_trim = 6
+ * sclh_trim = 6
+ *
+ * These are the trim values for standard and fast speed
+ */
+#ifndef I2C_FASTSPEED_SCLL_TRIM
+#define I2C_FASTSPEED_SCLL_TRIM 6
+#endif
+#ifndef I2C_FASTSPEED_SCLH_TRIM
+#define I2C_FASTSPEED_SCLH_TRIM 6
+#endif
+
+/* These are the trim values for high speed */
+#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
+#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
+#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
+#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
+#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM
+#endif
+
+#define I2C_PSC_MAX 0x0f
+#define I2C_PSC_MIN 0x00
+
+#endif /* _OMAP24XX_I2C_H_ */
diff --git a/drivers/mmc/omap3_mmc.c b/drivers/mmc/omap3_mmc.c
index 96c0e65..9506cca 100644
--- a/drivers/mmc/omap3_mmc.c
+++ b/drivers/mmc/omap3_mmc.c
@@ -30,7 +30,8 @@
#include <i2c.h>
#include <twl4030.h>
#include <asm/io.h>
-#include <asm/arch/mmc.h>
+
+#include "omap3_mmc.h"
const unsigned short mmc_transspeed_val[15][4] = {
{CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)},
@@ -52,7 +53,27 @@
mmc_card_data cur_card_data;
static block_dev_desc_t mmc_blk_dev;
-static hsmmc_t *mmc_base = (hsmmc_t *)OMAP_HSMMC_BASE;
+static hsmmc_t *mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE;
+
+int mmc_set_dev(int dev_num)
+{
+ switch (dev_num) {
+ case 1:
+ mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE;
+ break;
+ case 2:
+ mmc_base = (hsmmc_t *)OMAP_HSMMC2_BASE;
+ break;
+ case 3:
+ mmc_base = (hsmmc_t *)OMAP_HSMMC3_BASE;
+ break;
+ default:
+ mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE;
+ return 1;
+ }
+
+ return 0;
+}
block_dev_desc_t *mmc_get_dev(int dev)
{
@@ -61,12 +82,14 @@
unsigned char mmc_board_init(void)
{
- t2_t *t2_base = (t2_t *)T2_BASE;
-
#if defined(CONFIG_TWL4030_POWER)
twl4030_power_mmc_init();
#endif
+#if defined(CONFIG_OMAP34XX)
+ t2_t *t2_base = (t2_t *)T2_BASE;
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+
writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
&t2_base->pbias_lite);
@@ -74,6 +97,20 @@
writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
&t2_base->devconf0);
+ writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
+ &t2_base->devconf1);
+
+ writel(readl(&prcm_base->fclken1_core) |
+ EN_MMC1 | EN_MMC2 | EN_MMC3,
+ &prcm_base->fclken1_core);
+
+ writel(readl(&prcm_base->iclken1_core) |
+ EN_MMC1 | EN_MMC2 | EN_MMC3,
+ &prcm_base->iclken1_core);
+#endif
+
+/* TODO add appropriate OMAP4 init */
+
return 1;
}
@@ -512,8 +549,11 @@
return 1;
}
-int mmc_legacy_init(int verbose)
+int mmc_legacy_init(int dev)
{
+ if (mmc_set_dev(dev) != 0)
+ return 1;
+
if (configure_mmc(&cur_card_data) != 1)
return 1;
diff --git a/arch/arm/include/asm/arch-omap3/mmc.h b/drivers/mmc/omap3_mmc.h
similarity index 98%
rename from arch/arm/include/asm/arch-omap3/mmc.h
rename to drivers/mmc/omap3_mmc.h
index 196ffdc..cbb3dc3 100644
--- a/arch/arm/include/asm/arch-omap3/mmc.h
+++ b/drivers/mmc/omap3_mmc.h
@@ -25,7 +25,7 @@
#ifndef MMC_H
#define MMC_H
-#include "mmc_host_def.h"
+#include <asm/arch/mmc_host_def.h>
/* Responses */
#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 4518ecb..13aca52 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -173,7 +173,7 @@
}
static int davinci_spi_write(struct spi_slave *slave, unsigned int len,
- const u8 *txp, unsigned long flags)
+ const u8 *txp, unsigned long flags)
{
struct davinci_spi_slave *ds = to_davinci_spi(slave);
unsigned int data1_reg_val;
@@ -237,7 +237,7 @@
#endif
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
+ const void *dout, void *din, unsigned long flags)
{
unsigned int len;
@@ -266,6 +266,10 @@
#ifndef CONFIG_SPI_HALF_DUPLEX
else
return davinci_spi_read_write(slave, len, din, dout, flags);
+#else
+ printf("SPI full duplex transaction requested with "
+ "CONFIG_SPI_HALF_DUPLEX defined.\n");
+ flags |= SPI_XFER_END;
#endif
out:
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 513d005..10af21b 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -28,7 +28,7 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
new file mode 100644
index 0000000..277ff67
--- /dev/null
+++ b/include/configs/colibri_pxa270.h
@@ -0,0 +1,278 @@
+/*
+ * Toradex Colibri PXA270 configuration file
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
+#define CONFIG_VPAC270 1 /* Toradex Colibri PXA270 board */
+
+#undef BOARD_LATE_INIT
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+#undef CONFIG_USE_IRQ
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_SIZE 0x4000
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+#define CONFIG_ENV_OVERWRITE /* override default environment */
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc init && fatload mmc 0 0xa0000000 uImage; then " \
+ "bootm 0xa0000000; " \
+ "fi; " \
+ "if usb reset && fatload usb 0 0xa0000000 uImage; then " \
+ "bootm 0xa0000000; " \
+ "fi; " \
+ "bootm 0x80000;"
+#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200"
+#define CONFIG_TIMESTAMP
+#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+#define CONFIG_LZMA /* LZMA compression support */
+
+/*
+ * Serial Console Configuration
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_FFUART 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FLASH
+
+/*
+ * Networking Configuration
+ * chip on the Voipac PXA270 board
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DM9000_BASE 0x08000000
+#define DM9000_IO (CONFIG_DM9000_BASE)
+#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
+#define CONFIG_NET_RETRY_COUNT 10
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#endif
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_PXA_MMC
+#define CONFIG_SYS_MMC_BASE 0xF0000000
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * KGDB
+ */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
+#else
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#endif
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_DEVICE_NULLDEV 1
+
+/*
+ * Clock Configuration
+ */
+#undef CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
+#define CONFIG_SYS_CPUSPEED 0x290 /* 520 MHz */
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * DRAM Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+
+#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
+#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR (0xa1000000)
+
+/*
+ * NOR FLASH
+ */
+#ifdef CONFIG_CMD_FLASH
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER 1
+
+#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+#define CONFIG_SYS_FLASH_PROTECTION 1
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+
+#else /* No flash */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE 0x000000
+#define CONFIG_SYS_MONITOR_LEN 0x40000
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE 0x40000
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GPSR0_VAL 0x00000000
+#define CONFIG_SYS_GPSR1_VAL 0x00020000
+#define CONFIG_SYS_GPSR2_VAL 0x0002C000
+#define CONFIG_SYS_GPSR3_VAL 0x00000000
+
+#define CONFIG_SYS_GPCR0_VAL 0x00000000
+#define CONFIG_SYS_GPCR1_VAL 0x00000000
+#define CONFIG_SYS_GPCR2_VAL 0x00000000
+#define CONFIG_SYS_GPCR3_VAL 0x00000000
+
+#define CONFIG_SYS_GPDR0_VAL 0x08000000
+#define CONFIG_SYS_GPDR1_VAL 0x0002A981
+#define CONFIG_SYS_GPDR2_VAL 0x0202FC00
+#define CONFIG_SYS_GPDR3_VAL 0x00000000
+
+#define CONFIG_SYS_GAFR0_L_VAL 0x00100000
+#define CONFIG_SYS_GAFR0_U_VAL 0x00C00010
+#define CONFIG_SYS_GAFR1_L_VAL 0x999A901A
+#define CONFIG_SYS_GAFR1_U_VAL 0xAAA00008
+#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA
+#define CONFIG_SYS_GAFR2_U_VAL 0x0109A000
+#define CONFIG_SYS_GAFR3_L_VAL 0x54000300
+#define CONFIG_SYS_GAFR3_U_VAL 0x00024001
+
+#define CONFIG_SYS_PSSR_VAL 0x30
+
+/*
+ * Clock settings
+ */
+#define CONFIG_SYS_CKEN 0x00500240
+#define CONFIG_SYS_CCCR 0x02000290
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL 0x000095f2
+#define CONFIG_SYS_MSC1_VAL 0x00007ff4
+#define CONFIG_SYS_MSC2_VAL 0x00000000
+#define CONFIG_SYS_MDCNFG_VAL 0x08000ac9
+#define CONFIG_SYS_MDREFR_VAL 0x2013e01e
+#define CONFIG_SYS_MDMRS_VAL 0x00320032
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CONFIG_SYS_MECR_VAL 0x00000001
+#define CONFIG_SYS_MCMEM0_VAL 0x00014307
+#define CONFIG_SYS_MCMEM1_VAL 0x00014307
+#define CONFIG_SYS_MCATT0_VAL 0x0001c787
+#define CONFIG_SYS_MCATT1_VAL 0x0001c787
+#define CONFIG_SYS_MCIO0_VAL 0x0001430f
+#define CONFIG_SYS_MCIO1_VAL 0x0001430f
+
+/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "tdex270"
+#define CONFIG_USB_STORAGE
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 1076de6..2815771 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -32,7 +32,7 @@
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index e018b21..ae5a791 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -31,7 +31,7 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index af7c65a..c4aa220 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -36,7 +36,7 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index b441831..3a3b389 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -23,7 +23,7 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 9eba003..3308ace 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -26,7 +26,7 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
index d4482d3..5439aa3 100644
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -36,7 +36,7 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 1e88dc0..f612e0f 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -32,7 +32,7 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index be9daf4..aaf929e 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -33,7 +33,7 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
new file mode 100644
index 0000000..b1e40a3
--- /dev/null
+++ b/include/configs/omap4_panda.h
@@ -0,0 +1,220 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated.
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * Configuration settings for the TI OMAP4 Panda board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP44XX 1 /* which is a 44XX */
+#define CONFIG_OMAP4430 1 /* which is in a 4430 */
+#define CONFIG_PANDA 1 /* working with Panda */
+
+/* Get CPU defs */
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap4.h>
+
+/* Display CPU and Board Info */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_L2_OFF 1
+
+/* Clock Defines */
+#define V_OSCK 38400000 /* Clock output from T2 */
+#define V_SCLK V_OSCK
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/*
+ * Size of malloc() pool
+ * Total Size Environment - 256k
+ * Malloc - add 256k
+ */
+#define CONFIG_ENV_SIZE (256 << 10)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
+ /* initial data */
+/* Vector Base */
+#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * serial port - NS16550 compatible
+ */
+#define V_NS16550_CLK 48000000
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 UART3_BASE
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+
+/* I2C */
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+/* MMC */
+#define CONFIG_MMC 1
+#define CONFIG_OMAP3_MMC 1
+#define CONFIG_SYS_MMC_SET_DEV 1
+#define CONFIG_DOS_PARTITION 1
+
+/* Flash */
+#define CONFIG_SYS_NO_FLASH 1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+/* Enabled commands */
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+
+/* Disabled commands */
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+/*
+ * Enabling relocation of u-boot by default
+ * Relocation can be skipped if u-boot is copied to the TEXT_BASE
+ */
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Environment setup
+ */
+
+/* allow overwriting serial config and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "console=ttyS2,115200n8\0" \
+ "mmcdev=1\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc${mmcdev} ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc init ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run nandboot; " \
+ "fi; " \
+ "fi; " \
+ "fi"
+
+#define CONFIG_AUTO_COMPLETE 1
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "Panda # "
+#define CONFIG_SYS_CBSIZE 256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+/*
+ * memtest setup
+ */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+
+/* Use General purpose timer 1 */
+#define CONFIG_SYS_TIMERBASE GPT1_BASE
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
+#endif
+
+/*
+ * SDRAM Memory Map
+ * Even though we use two CS all the memory
+ * is mapped to one contiguous block
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
new file mode 100644
index 0000000..8121554
--- /dev/null
+++ b/include/configs/omap4_sdp4430.h
@@ -0,0 +1,221 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated.
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * Configuration settings for the TI SDP4430 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP44XX 1 /* which is a 44XX */
+#define CONFIG_OMAP4430 1 /* which is in a 4430 */
+#define CONFIG_4430SDP 1 /* working with SDP */
+
+/* Get CPU defs */
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap4.h>
+
+/* Display CPU and Board Info */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_L2_OFF 1
+
+/* Clock Defines */
+#define V_OSCK 38400000 /* Clock output from T2 */
+#define V_SCLK V_OSCK
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/*
+ * Size of malloc() pool
+ * Total Size Environment - 256k
+ * Malloc - add 256k
+ */
+#define CONFIG_ENV_SIZE (256 << 10)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
+ /* initial data */
+/* Vector Base */
+#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * serial port - NS16550 compatible
+ */
+#define V_NS16550_CLK 48000000
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 UART3_BASE
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+
+/* I2C */
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+/* MMC */
+#define CONFIG_MMC 1
+#define CONFIG_OMAP3_MMC 1
+#define CONFIG_SYS_MMC_SET_DEV 1
+#define CONFIG_DOS_PARTITION 1
+
+/* Flash */
+#define CONFIG_SYS_NO_FLASH 1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+/* Enabled commands */
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+
+/* Disabled commands */
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+/*
+ * Enabling relocation of u-boot by default
+ * Relocation can be skipped if u-boot is copied to the TEXT_BASE
+ */
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Environment setup
+ */
+
+/* allow overwriting serial config and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "console=ttyS2,115200n8\0" \
+ "mmcdev=1\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc${mmcdev} ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc init ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run nandboot; " \
+ "fi; " \
+ "fi; " \
+ "fi"
+
+#define CONFIG_AUTO_COMPLETE 1
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "OMAP4430 SDP # "
+#define CONFIG_SYS_CBSIZE 256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+/*
+ * memtest setup
+ */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+
+/* Use General purpose timer 1 */
+#define CONFIG_SYS_TIMERBASE GPT1_BASE
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
+#endif
+
+/*
+ * SDRAM Memory Map
+ * Even though we use two CS all the memory
+ * is mapped to one contiguous block
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 171ec94..ff0dbd3 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -28,7 +28,7 @@
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
#define CONFIG_S5PC1XX 1 /* which is in a S5PC1XX Family */
#define CONFIG_S5PC110 1 /* which is in a S5PC110 */
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index 09bce6d..76a47c4 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -32,7 +32,7 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
#define CONFIG_S5PC1XX 1 /* which is in a S5PC1XX Family */
#define CONFIG_S5PC100 1 /* which is in a S5PC100 */
diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h
new file mode 100644
index 0000000..6d02995
--- /dev/null
+++ b/include/configs/vpac270.h
@@ -0,0 +1,323 @@
+/*
+ * Voipac PXA270 configuration file
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
+#define CONFIG_VPAC270 1 /* Voipac PXA270 board */
+
+#undef BOARD_LATE_INIT
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+#undef CONFIG_USE_IRQ
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_SIZE 0x4000
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+#define CONFIG_ENV_OVERWRITE /* override default environment */
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc init && fatload mmc 0 0xa4000000 uImage; then " \
+ "bootm 0xa4000000; " \
+ "fi; " \
+ "if usb reset && fatload usb 0 0xa4000000 uImage; then " \
+ "bootm 0xa4000000; " \
+ "fi; " \
+ "bootm 0x40000;"
+#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200"
+#define CONFIG_TIMESTAMP
+#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+#define CONFIG_LZMA /* LZMA compression support */
+
+/*
+ * Serial Console Configuration
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_FFUART 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_USB
+#undef CONFIG_LCD
+#define CONFIG_CMD_IDE
+
+#ifdef CONFIG_ONENAND_U_BOOT
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_ONENAND
+#else
+#define CONFIG_CMD_FLASH
+#undef CONFIG_CMD_ONENAND
+#endif
+
+/*
+ * Networking Configuration
+ * chip on the Voipac PXA270 board
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */
+#define DM9000_IO (CONFIG_DM9000_BASE)
+#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
+#define CONFIG_NET_RETRY_COUNT 10
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#endif
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_PXA_MMC
+#define CONFIG_SYS_MMC_BASE 0xF0000000
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * KGDB
+ */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
+#else
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#endif
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_DEVICE_NULLDEV 1
+
+/*
+ * Clock Configuration
+ */
+#undef CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
+#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * DRAM Map
+ */
+#define CONFIG_NR_DRAM_BANKS 2 /* We have 2 banks of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+#define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
+
+#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
+#define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR (0x5c000000)
+
+/*
+ * NOR FLASH
+ */
+#if defined(CONFIG_CMD_FLASH) /* NOR */
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER 1
+
+#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+#define CONFIG_SYS_FLASH_PROTECTION 1
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+
+#elif defined(CONFIG_CMD_ONENAND) /* OneNAND */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_ONENAND_BASE 0x00000000
+#define CONFIG_ENV_IS_IN_ONENAND 1
+
+#else /* No flash */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE 0x000000
+#define CONFIG_SYS_MONITOR_LEN 0x40000
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE 0x40000
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+/*
+ * IDE
+ */
+#ifdef CONFIG_CMD_IDE
+#define CONFIG_LBA48
+#undef CONFIG_IDE_LED
+#undef CONFIG_IDE_RESET
+
+#define CONFIG_SYS_IDE_MAXBUS 1
+#define CONFIG_SYS_IDE_MAXDEVICE 1
+
+#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
+
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x120
+#define CONFIG_SYS_ATA_REG_OFFSET 0x120
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x120
+
+#define CONFIG_SYS_ATA_STRIDE 2
+#endif
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GPSR0_VAL 0x01308800
+#define CONFIG_SYS_GPSR1_VAL 0x00cf0000
+#define CONFIG_SYS_GPSR2_VAL 0x922ac000
+#define CONFIG_SYS_GPSR3_VAL 0x0161e800
+
+#define CONFIG_SYS_GPCR0_VAL 0x00010000
+#define CONFIG_SYS_GPCR1_VAL 0x0
+#define CONFIG_SYS_GPCR2_VAL 0x0
+#define CONFIG_SYS_GPCR3_VAL 0x0
+
+#define CONFIG_SYS_GPDR0_VAL 0xcbb18800
+#define CONFIG_SYS_GPDR1_VAL 0xfccfa981
+#define CONFIG_SYS_GPDR2_VAL 0x922affff
+#define CONFIG_SYS_GPDR3_VAL 0x0161e904
+
+#define CONFIG_SYS_GAFR0_L_VAL 0x00100000
+#define CONFIG_SYS_GAFR0_U_VAL 0xa5da8510
+#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
+#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a0aa
+#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL 0x4109a401
+#define CONFIG_SYS_GAFR3_L_VAL 0x54010310
+#define CONFIG_SYS_GAFR3_U_VAL 0x00025401
+
+#define CONFIG_SYS_PSSR_VAL 0x30
+
+/*
+ * Clock settings
+ */
+#define CONFIG_SYS_CKEN 0x00500240
+#define CONFIG_SYS_CCCR 0x02000290
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL 0x3ffc95fa
+#define CONFIG_SYS_MSC1_VAL 0x02ccf974
+#define CONFIG_SYS_MSC2_VAL 0x00000000
+#define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3
+#define CONFIG_SYS_MDREFR_VAL 0x201fe01e
+#define CONFIG_SYS_MDMRS_VAL 0x00000000
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x40044004
+#define CONFIG_SYS_MEM_BUF_IMP 0x0f
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CONFIG_SYS_MECR_VAL 0x00000001
+#define CONFIG_SYS_MCMEM0_VAL 0x00014307
+#define CONFIG_SYS_MCMEM1_VAL 0x00014307
+#define CONFIG_SYS_MCATT0_VAL 0x0001c787
+#define CONFIG_SYS_MCATT1_VAL 0x0001c787
+#define CONFIG_SYS_MCIO0_VAL 0x0001430f
+#define CONFIG_SYS_MCIO1_VAL 0x0001430f
+
+/*
+ * LCD
+ */
+#ifdef CONFIG_LCD
+#define CONFIG_VOIPAC_LCD
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "vpac270"
+#define CONFIG_USB_STORAGE
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
new file mode 100644
index 0000000..a5a873b
--- /dev/null
+++ b/include/configs/zipitz2.h
@@ -0,0 +1,259 @@
+/*
+ * Aeronix Zipit Z2 configuration file
+ *
+ * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
+#define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */
+
+#undef BOARD_LATE_INIT
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+#undef CONFIG_USE_IRQ
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR 0x40000
+#define CONFIG_ENV_SIZE 0x20000
+
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_STACKSIZE)
+#define CONFIG_SYS_GBL_DATA_SIZE 512
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \
+ "source 0xa0000000; " \
+ "else " \
+ "bootm 0x60000; " \
+ "fi; "
+#define CONFIG_BOOTARGS \
+ "console=tty0 console=ttyS2,115200 fbcon=rotate:3"
+#define CONFIG_TIMESTAMP
+#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+#define CONFIG_LZMA /* LZMA compression support */
+
+/*
+ * Serial Console Configuration
+ * STUART - the lower serial port on Colibri board
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_STUART 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_NET
+#define CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_SPI
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_PXA_MMC
+#define CONFIG_SYS_MMC_BASE 0xF0000000
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * SPI and LCD
+ */
+#ifdef CONFIG_CMD_SPI
+#define CONFIG_SOFT_SPI
+#define CONFIG_LCD
+#define CONFIG_LMS283GF05
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CMD_BMP
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
+#undef SPI_INIT
+
+#define SPI_DELAY udelay(10)
+#define SPI_SDA(val) zipitz2_spi_sda(val)
+#define SPI_SCL(val) zipitz2_spi_scl(val)
+#define SPI_READ zipitz2_spi_read()
+#ifndef __ASSEMBLY__
+void zipitz2_spi_sda(int);
+void zipitz2_spi_scl(int);
+unsigned char zipitz2_spi_read(void);
+#endif
+#endif
+
+/*
+ * KGDB
+ */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
+#else
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#endif
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_DEVICE_NULLDEV 1
+
+/*
+ * Clock Configuration
+ */
+#undef CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
+#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * DRAM Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
+
+#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
+#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
+
+/*
+ * NOR FLASH
+ */
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
+#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+
+#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_PROTECTION
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GAFR0_L_VAL 0x02000140
+#define CONFIG_SYS_GAFR0_U_VAL 0x59188000
+#define CONFIG_SYS_GAFR1_L_VAL 0x63900002
+#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950
+#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL 0x29000308
+#define CONFIG_SYS_GAFR3_L_VAL 0x54000000
+#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5
+#define CONFIG_SYS_GPCR0_VAL 0x00000000
+#define CONFIG_SYS_GPCR1_VAL 0x00000020
+#define CONFIG_SYS_GPCR2_VAL 0x00000000
+#define CONFIG_SYS_GPCR3_VAL 0x00000000
+#define CONFIG_SYS_GPDR0_VAL 0xdafcee00
+#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab
+#define CONFIG_SYS_GPDR2_VAL 0x8fe1ffff
+#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a
+#define CONFIG_SYS_GPSR0_VAL 0x06080400
+#define CONFIG_SYS_GPSR1_VAL 0x007f0000
+#define CONFIG_SYS_GPSR2_VAL 0x032a0000
+#define CONFIG_SYS_GPSR3_VAL 0x00000180
+
+#define CONFIG_SYS_PSSR_VAL 0x30
+
+/*
+ * Clock settings
+ */
+#define CONFIG_SYS_CKEN 0x00511220
+#define CONFIG_SYS_CCCR 0x00000190
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8
+#define CONFIG_SYS_MSC1_VAL 0x0000ccd1
+#define CONFIG_SYS_MSC2_VAL 0x0000b884
+#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9
+#define CONFIG_SYS_MDREFR_VAL 0x2011a01e
+#define CONFIG_SYS_MDMRS_VAL 0x00000000
+#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
+#define CONFIG_SYS_SXCNFG_VAL 0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CONFIG_SYS_MECR_VAL 0x00000001
+#define CONFIG_SYS_MCMEM0_VAL 0x00014307
+#define CONFIG_SYS_MCMEM1_VAL 0x00014307
+#define CONFIG_SYS_MCATT0_VAL 0x0001c787
+#define CONFIG_SYS_MCATT1_VAL 0x0001c787
+#define CONFIG_SYS_MCIO0_VAL 0x0001430f
+#define CONFIG_SYS_MCIO1_VAL 0x0001430f
+
+#endif /* __CONFIG_H */
diff --git a/include/lcd.h b/include/lcd.h
index 1f85daa..cd9d49d 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -87,7 +87,7 @@
u_char vl_wbf; /* Wait between frames */
} vidinfo_t;
-#elif defined CONFIG_PXA250
+#elif defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
/*
* PXA LCD DMA descriptor
*/
diff --git a/include/mmc.h b/include/mmc.h
index 8973bc7..fcb237e 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -271,6 +271,7 @@
int mmc_init(struct mmc *mmc);
int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
struct mmc *find_mmc_device(int dev_num);
+int mmc_set_dev(int dev_num);
void print_mmc_devices(char separator);
int board_mmc_getcd(u8 *cd, struct mmc *mmc);
diff --git a/onenand_ipl/board/vpac270/Makefile b/onenand_ipl/board/vpac270/Makefile
new file mode 100644
index 0000000..22d0410
--- /dev/null
+++ b/onenand_ipl/board/vpac270/Makefile
@@ -0,0 +1,83 @@
+IPL =onenand_ipl
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds
+LDFLAGS = -Bstatic -T $(onenandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
+CFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
+OBJCFLAGS += --gap-fill=0x00
+
+SOBJS := lowlevel_init.o
+SOBJS += start.o
+COBJS := vpac270.o
+COBJS += onenand_read.o
+COBJS += onenand_boot.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(OBJTREE)/onenand_ipl/board/$(BOARDDIR)
+
+onenandobj := $(OBJTREE)/onenand_ipl/
+
+ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin
+
+all: $(obj).depend $(ALL)
+
+$(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x5c040400 -O binary $< $@
+
+$(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(onenandobj)onenand-ipl: $(OBJS) $(onenandobj)u-boot.lds
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+ -Map $@.map -o $@
+
+$(onenandobj)u-boot.lds: $(LDSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+
+# create symbolic links from common files
+
+# from cpu directory
+$(obj)start.S:
+ @rm -f $@
+ ln -s $(SRCTREE)/$(CPUDIR)/start.S $@
+
+# from onenand_ipl directory
+$(obj)onenand_ipl.h:
+ @rm -f $@
+ ln -s $(SRCTREE)/onenand_ipl/onenand_ipl.h $@
+
+$(obj)onenand_boot.c: $(obj)onenand_ipl.h
+ @rm -f $@
+ ln -s $(SRCTREE)/onenand_ipl/onenand_boot.c $@
+
+$(obj)onenand_read.c: $(obj)onenand_ipl.h
+ @rm -f $@
+ ln -s $(SRCTREE)/onenand_ipl/onenand_read.c $@
+
+ifneq ($(OBJTREE), $(SRCTREE))
+$(obj)vpac270.c:
+ @rm -f $@
+ ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/vpac270.c $@
+
+$(obj)lowlevel_init.S:
+ @rm -f $@
+ ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/lowlevel_init.S $@
+endif
+
+#########################################################################
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)$.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/onenand_ipl/board/vpac270/config.mk b/onenand_ipl/board/vpac270/config.mk
new file mode 100644
index 0000000..f071dea
--- /dev/null
+++ b/onenand_ipl/board/vpac270/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x5c03fc00
diff --git a/onenand_ipl/board/vpac270/lowlevel_init.S b/onenand_ipl/board/vpac270/lowlevel_init.S
new file mode 100644
index 0000000..e79d8dd
--- /dev/null
+++ b/onenand_ipl/board/vpac270/lowlevel_init.S
@@ -0,0 +1,34 @@
+/*
+ * Voipac PXA270 Lowlevel Hardware Initialization
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/macro.h>
+
+.globl lowlevel_init
+lowlevel_init:
+ pxa_clock_setup
+ mov pc, lr
diff --git a/arch/arm/cpu/arm_cortexa8/u-boot.lds b/onenand_ipl/board/vpac270/u-boot.onenand.lds
similarity index 72%
copy from arch/arm/cpu/arm_cortexa8/u-boot.lds
copy to onenand_ipl/board/vpac270/u-boot.onenand.lds
index 820e3a1..b2e7557 100644
--- a/arch/arm/cpu/arm_cortexa8/u-boot.lds
+++ b/onenand_ipl/board/vpac270/u-boot.onenand.lds
@@ -1,9 +1,6 @@
/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -15,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -32,10 +29,10 @@
. = 0x00000000;
. = ALIGN(4);
- .text :
+ .text :
{
- arch/arm/cpu/arm_cortexa8/start.o (.text)
- *(.text)
+ start.o (.text)
+ *(.text)
}
. = ALIGN(4);
@@ -47,12 +44,8 @@
. = ALIGN(4);
.got : { *(.got) }
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
. = ALIGN(4);
__bss_start = .;
- .bss : { *(.bss) }
+ .bss : { *(.bss) . = ALIGN(4); }
_end = .;
}
diff --git a/onenand_ipl/board/vpac270/vpac270.c b/onenand_ipl/board/vpac270/vpac270.c
new file mode 100644
index 0000000..a1eb331
--- /dev/null
+++ b/onenand_ipl/board/vpac270/vpac270.c
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+int board_init (void)
+{
+ return 0;
+}
+
+int s_init(int skip)
+{
+ return 0;
+}