Merge git://git.denx.de/u-boot-uniphier
diff --git a/MAINTAINERS b/MAINTAINERS
index 9fd9116..f7e6abd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -452,6 +452,7 @@
X86
M: Simon Glass <sjg@chromium.org>
+M: Bin Meng <bmeng.cn@gmail.com>
S: Maintained
T: git git://git.denx.de/u-boot-x86.git
F: arch/x86/
diff --git a/Makefile b/Makefile
index a1a3aea..3d2b66a 100644
--- a/Makefile
+++ b/Makefile
@@ -1232,13 +1232,16 @@
$(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o
$(call if_changed,u-boot-elf)
+ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink)
+
# Rule to link u-boot
# May be overridden by arch/$(ARCH)/config.mk
quiet_cmd_u-boot__ ?= LD $@
cmd_u-boot__ ?= $(LD) $(LDFLAGS) $(LDFLAGS_u-boot) -o $@ \
-T u-boot.lds $(u-boot-init) \
--start-group $(u-boot-main) --end-group \
- $(PLATFORM_LIBS) -Map u-boot.map
+ $(PLATFORM_LIBS) -Map u-boot.map; \
+ $(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
quiet_cmd_smap = GEN common/system_map.o
cmd_smap = \
@@ -1248,7 +1251,7 @@
-c $(srctree)/common/system_map.c -o common/system_map.o
u-boot: $(u-boot-init) $(u-boot-main) u-boot.lds FORCE
- $(call if_changed,u-boot__)
+ +$(call if_changed,u-boot__)
ifeq ($(CONFIG_KALLSYMS),y)
$(call cmd,smap)
$(call cmd,u-boot__) common/system_map.o
diff --git a/arch/arm/dts/meson-gx.dtsi b/arch/arm/dts/meson-gx.dtsi
index c129100..436b875 100644
--- a/arch/arm/dts/meson-gx.dtsi
+++ b/arch/arm/dts/meson-gx.dtsi
@@ -71,6 +71,14 @@
reg = <0x0 0x10000000 0x0 0x200000>;
no-map;
};
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0xbc00000>;
+ alignment = <0x0 0x400000>;
+ linux,cma-default;
+ };
};
cpus {
@@ -233,7 +241,7 @@
};
i2c_A: i2c@8500 {
- compatible = "amlogic,meson-gxbb-i2c";
+ compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
reg = <0x0 0x08500 0x0 0x20>;
interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
@@ -255,6 +263,14 @@
status = "disabled";
};
+ saradc: adc@8680 {
+ compatible = "amlogic,meson-saradc";
+ reg = <0x0 0x8680 0x0 0x34>;
+ #io-channel-cells = <1>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
pwm_ef: pwm@86c0 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
reg = <0x0 0x086c0 0x0 0x10>;
@@ -271,7 +287,7 @@
};
i2c_B: i2c@87c0 {
- compatible = "amlogic,meson-gxbb-i2c";
+ compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
reg = <0x0 0x087c0 0x0 0x20>;
interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
@@ -280,7 +296,7 @@
};
i2c_C: i2c@87e0 {
- compatible = "amlogic,meson-gxbb-i2c";
+ compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
reg = <0x0 0x087e0 0x0 0x20>;
interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
@@ -288,6 +304,14 @@
status = "disabled";
};
+ spifc: spi@8c80 {
+ compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc";
+ reg = <0x0 0x08c80 0x0 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
watchdog@98d0 {
compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
reg = <0x0 0x098d0 0x0 0x10>;
@@ -309,7 +333,7 @@
};
sram: sram@c8000000 {
- compatible = "amlogic,meson-gxbb-sram", "mmio-sram";
+ compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram";
reg = <0x0 0xc8000000 0x0 0x14000>;
#address-cells = <1>;
@@ -317,12 +341,12 @@
ranges = <0 0x0 0xc8000000 0x14000>;
cpu_scp_lpri: scp-shmem@0 {
- compatible = "amlogic,meson-gxbb-scp-shmem";
+ compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
reg = <0x13000 0x400>;
};
cpu_scp_hpri: scp-shmem@200 {
- compatible = "amlogic,meson-gxbb-scp-shmem";
+ compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
reg = <0x13400 0x400>;
};
};
@@ -334,6 +358,13 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
+ clkc_AO: clock-controller@040 {
+ compatible = "amlogic,gx-aoclkc", "amlogic,gxbb-aoclkc";
+ reg = <0x0 0x00040 0x0 0x4>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
uart_AO: serial@4c0 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x004c0 0x0 0x14>;
@@ -350,8 +381,24 @@
status = "disabled";
};
+ i2c_AO: i2c@500 {
+ compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
+ reg = <0x0 0x500 0x0 0x20>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pwm_AO_ab: pwm@550 {
+ compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
+ reg = <0x0 0x00550 0x0 0x10>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
ir: ir@580 {
- compatible = "amlogic,meson-gxbb-ir";
+ compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
reg = <0x0 0x00580 0x0 0x40>;
interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
@@ -365,13 +412,12 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
- rng {
+ hwrng: rng {
compatible = "amlogic,meson-rng";
reg = <0x0 0x0 0x0 0x4>;
};
};
-
hiubus: hiubus@c883c000 {
compatible = "simple-bus";
reg = <0x0 0xc883c000 0x0 0x2000>;
@@ -395,7 +441,6 @@
0x0 0xc8834540 0x0 0x4>;
interrupts = <0 8 1>;
interrupt-names = "macirq";
- phy-mode = "rgmii";
status = "disabled";
};
@@ -442,6 +487,38 @@
cvbs_vdac_port: port@0 {
reg = <0>;
};
+
+ /* HDMI-TX output port */
+ hdmi_tx_port: port@1 {
+ reg = <1>;
+
+ hdmi_tx_out: endpoint {
+ remote-endpoint = <&hdmi_tx_in>;
+ };
+ };
+ };
+
+ hdmi_tx: hdmi-tx@c883a000 {
+ compatible = "amlogic,meson-gx-dw-hdmi";
+ reg = <0x0 0xc883a000 0x0 0x1c>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ /* VPU VENC Input */
+ hdmi_tx_venc_port: port@0 {
+ reg = <0>;
+
+ hdmi_tx_in: endpoint {
+ remote-endpoint = <&hdmi_tx_out>;
+ };
+ };
+
+ /* TMDS Output */
+ hdmi_tx_tmds_port: port@1 {
+ reg = <1>;
+ };
};
};
};
diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts
index c737183..54a9c6a 100644
--- a/arch/arm/dts/meson-gxbb-odroidc2.dts
+++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
@@ -50,7 +50,7 @@
/ {
compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
model = "Hardkernel ODROID-C2";
-
+
aliases {
serial0 = &uart_AO;
};
@@ -96,7 +96,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- gpio = <&gpio_ao GPIOAO_12 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
@@ -152,6 +152,13 @@
pinctrl-0 = <ð_rgmii_pins>;
pinctrl-names = "default";
phy-handle = <ð_phy0>;
+ phy-mode = "rgmii";
+
+ snps,reset-gpio = <&gpio GPIOZ_14 0>;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-active-low;
+
+ amlogic,tx-delay-ns = <2>;
mdio {
compatible = "snps,dwmac-mdio";
@@ -165,6 +172,57 @@
};
};
+&pinctrl_aobus {
+ gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En",
+ "USB HUB nRESET", "USB OTG Power En",
+ "J7 Header Pin2", "IR In", "J7 Header Pin4",
+ "J7 Header Pin6", "J7 Header Pin5", "J7 Header Pin7",
+ "HDMI CEC", "SYS LED";
+};
+
+&pinctrl_periphs {
+ gpio-line-names = /* Bank GPIOZ */
+ "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
+ "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2",
+ "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
+ "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3",
+ "Eth PHY nRESET", "Eth PHY Intc",
+ /* Bank GPIOH */
+ "HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", "",
+ /* Bank BOOT */
+ "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4",
+ "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk",
+ "eMMC Reset", "eMMC CMD",
+ "", "", "", "", "", "", "",
+ /* Bank CARD */
+ "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
+ "SDCard D3", "SDCard D2", "SDCard Det",
+ /* Bank GPIODV */
+ "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "",
+ "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
+ "PWM D", "PWM B",
+ /* Bank GPIOY */
+ "Revision Bit0", "Revision Bit1", "",
+ "J2 Header Pin35", "", "", "", "J2 Header Pin36",
+ "J2 Header Pin31", "", "", "", "TF VDD En",
+ "J2 Header Pin32", "J2 Header Pin26", "", "",
+ /* Bank GPIOX */
+ "J2 Header Pin29", "J2 Header Pin24",
+ "J2 Header Pin23", "J2 Header Pin22",
+ "J2 Header Pin21", "J2 Header Pin18",
+ "J2 Header Pin33", "J2 Header Pin19",
+ "J2 Header Pin16", "J2 Header Pin15",
+ "J2 Header Pin12", "J2 Header Pin13",
+ "J2 Header Pin8", "J2 Header Pin10",
+ "", "", "", "", "",
+ "J2 Header Pin11", "", "J2 Header Pin7",
+ /* Bank GPIOCLK */
+ "", "", "", "",
+ /* GPIO_TEST_N */
+ "";
+};
+
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
@@ -177,6 +235,21 @@
pinctrl-names = "default";
};
+&gpio_ao {
+ /*
+ * WARNING: The USB Hub on the Odroid-C2 needs a reset signal
+ * to be turned high in order to be detected by the USB Controller
+ * This signal should be handled by a USB specific power sequence
+ * in order to reset the Hub when USB bus is powered down.
+ */
+ usb-hub {
+ gpio-hog;
+ gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-hub-reset";
+ };
+};
+
&usb0_phy {
status = "okay";
phy-supply = <&usb_otg_pwr>;
@@ -194,6 +267,11 @@
status = "okay";
};
+&saradc {
+ status = "okay";
+ vref-supply = <&vcc1v8>;
+};
+
/* SD */
&sd_emmc_b {
status = "okay";
diff --git a/arch/arm/dts/meson-gxbb.dtsi b/arch/arm/dts/meson-gxbb.dtsi
index 39a774a..86105a6 100644
--- a/arch/arm/dts/meson-gxbb.dtsi
+++ b/arch/arm/dts/meson-gxbb.dtsi
@@ -97,17 +97,6 @@
};
};
-&cbus {
- spifc: spi@8c80 {
- compatible = "amlogic,meson-gxbb-spifc";
- reg = <0x0 0x08c80 0x0 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clkc CLKID_SPI>;
- status = "disabled";
- };
-};
-
ðmac {
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
@@ -129,6 +118,7 @@
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_aobus 0 0 14>;
};
uart_ao_a_pins: uart_ao_a {
@@ -203,30 +193,62 @@
function = "pwm_ao_b";
};
};
- };
- clkc_AO: clock-controller@040 {
- compatible = "amlogic,gxbb-aoclkc";
- reg = <0x0 0x00040 0x0 0x4>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
+ i2s_am_clk_pins: i2s_am_clk {
+ mux {
+ groups = "i2s_am_clk";
+ function = "i2s_out_ao";
+ };
+ };
- pwm_ab_AO: pwm@550 {
- compatible = "amlogic,meson-gxbb-pwm";
- reg = <0x0 0x0550 0x0 0x10>;
- #pwm-cells = <3>;
- status = "disabled";
- };
+ i2s_out_ao_clk_pins: i2s_out_ao_clk {
+ mux {
+ groups = "i2s_out_ao_clk";
+ function = "i2s_out_ao";
+ };
+ };
+
+ i2s_out_lr_clk_pins: i2s_out_lr_clk {
+ mux {
+ groups = "i2s_out_lr_clk";
+ function = "i2s_out_ao";
+ };
+ };
+
+ i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
+ mux {
+ groups = "i2s_out_ch01_ao";
+ function = "i2s_out_ao";
+ };
+ };
+
+ i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
+ mux {
+ groups = "i2s_out_ch23_ao";
+ function = "i2s_out_ao";
+ };
+ };
+
+ i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
+ mux {
+ groups = "i2s_out_ch45_ao";
+ function = "i2s_out_ao";
+ };
+ };
+
+ spdif_out_ao_6_pins: spdif_out_ao_6 {
+ mux {
+ groups = "spdif_out_ao_6";
+ function = "spdif_out_ao";
+ };
+ };
- i2c_AO: i2c@500 {
- compatible = "amlogic,meson-gxbb-i2c";
- reg = <0x0 0x500 0x0 0x20>;
- interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc CLKID_AO_I2C>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
+ spdif_out_ao_13_pins: spdif_out_ao_13 {
+ mux {
+ groups = "spdif_out_ao_13";
+ function = "spdif_out_ao";
+ };
+ };
};
};
@@ -245,6 +267,7 @@
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_periphs 0 14 120>;
};
emmc_pins: emmc {
@@ -467,6 +490,34 @@
function = "hdmi_i2c";
};
};
+
+ i2sout_ch23_y_pins: i2sout_ch23_y {
+ mux {
+ groups = "i2sout_ch23_y";
+ function = "i2s_out";
+ };
+ };
+
+ i2sout_ch45_y_pins: i2sout_ch45_y {
+ mux {
+ groups = "i2sout_ch45_y";
+ function = "i2s_out";
+ };
+ };
+
+ i2sout_ch67_y_pins: i2sout_ch67_y {
+ mux {
+ groups = "i2sout_ch67_y";
+ function = "i2s_out";
+ };
+ };
+
+ spdif_out_y_pins: spdif_out_y {
+ mux {
+ groups = "spdif_out_y";
+ function = "spdif_out";
+ };
+ };
};
};
@@ -478,10 +529,51 @@
};
};
+&apb {
+ mali: gpu@c0000 {
+ compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
+ reg = <0x0 0xc0000 0x0 0x40000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp", "gpmmu", "pp", "pmu",
+ "pp0", "ppmmu0", "pp1", "ppmmu1",
+ "pp2", "ppmmu2";
+ clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
+ clock-names = "bus", "core";
+
+ /*
+ * Mali clocking is provided by two identical clock paths
+ * MALI_0 and MALI_1 muxed to a single clock by a glitch
+ * free mux to safely change frequency while running.
+ */
+ assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+ <&clkc CLKID_MALI_0>,
+ <&clkc CLKID_MALI>; /* Glitch free mux */
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+ <0>, /* Do Nothing */
+ <&clkc CLKID_MALI_0>;
+ assigned-clock-rates = <0>, /* Do Nothing */
+ <666666666>,
+ <0>; /* Do Nothing */
+ };
+};
+
&i2c_A {
clocks = <&clkc CLKID_I2C>;
};
+&i2c_AO {
+ clocks = <&clkc CLKID_AO_I2C>;
+};
+
&i2c_B {
clocks = <&clkc CLKID_I2C>;
};
@@ -490,6 +582,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&saradc {
+ compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+};
+
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
@@ -511,6 +613,27 @@
clock-names = "core", "clkin0", "clkin1";
};
+&spifc {
+ clocks = <&clkc CLKID_SPI>;
+};
+
&vpu {
compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
};
+
+&hwrng {
+ clocks = <&clkc CLKID_RNG0>;
+ clock-names = "core";
+};
+
+&hdmi_tx {
+ compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
+ resets = <&reset RESET_HDMITX_CAPB3>,
+ <&reset RESET_HDMI_SYSTEM_RESET>,
+ <&reset RESET_HDMI_TX>;
+ reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
+ clocks = <&clkc CLKID_HDMI_PCLK>,
+ <&clkc CLKID_CLK81>,
+ <&clkc CLKID_GCLK_VENCI_INT0>;
+ clock-names = "isfr", "iahb", "venci";
+};
diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts
index 2c7fa79..c92c2e2 100644
--- a/arch/arm/dts/stm32f746-disco.dts
+++ b/arch/arm/dts/stm32f746-disco.dts
@@ -195,7 +195,6 @@
pinctrl-names = "default";
status = "okay";
- mr-nbanks = <1>;
/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
bank1: bank@0 {
st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_4
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 54f5bc7..783d4e7 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -47,6 +47,8 @@
#include "armv7-m.dtsi"
#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
+#include <dt-bindings/clock/stm32fx-clock.h>
+#include <dt-bindings/mfd/stm32f7-rcc.h>
/ {
clocks {
@@ -74,7 +76,7 @@
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
reg = <0xA0000000 0x1000>;
- clocks = <&rcc 0 64>;
+ clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
u-boot,dm-pre-reloc;
};
@@ -86,14 +88,14 @@
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <92>;
spi-max-frequency = <108000000>;
- clocks = <&rcc 0 65>;
+ clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
status = "disabled";
};
usart1: serial@40011000 {
compatible = "st,stm32f7-usart", "st,stm32f7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
- clocks = <&rcc 0 164>;
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
status = "disabled";
u-boot,dm-pre-reloc;
};
@@ -119,7 +121,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x0 0x400>;
- clocks = <&rcc 0 0>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
u-boot,dm-pre-reloc;
};
@@ -129,7 +131,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x400 0x400>;
- clocks = <&rcc 0 1>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
u-boot,dm-pre-reloc;
};
@@ -140,7 +142,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x800 0x400>;
- clocks = <&rcc 0 2>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
u-boot,dm-pre-reloc;
};
@@ -150,7 +152,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0xc00 0x400>;
- clocks = <&rcc 0 3>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
st,bank-name = "GPIOD";
u-boot,dm-pre-reloc;
};
@@ -160,7 +162,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1000 0x400>;
- clocks = <&rcc 0 4>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
st,bank-name = "GPIOE";
u-boot,dm-pre-reloc;
};
@@ -170,7 +172,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1400 0x400>;
- clocks = <&rcc 0 5>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
st,bank-name = "GPIOF";
u-boot,dm-pre-reloc;
};
@@ -180,7 +182,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1800 0x400>;
- clocks = <&rcc 0 6>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
st,bank-name = "GPIOG";
u-boot,dm-pre-reloc;
};
@@ -190,7 +192,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x1c00 0x400>;
- clocks = <&rcc 0 7>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
st,bank-name = "GPIOH";
u-boot,dm-pre-reloc;
};
@@ -200,7 +202,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2000 0x400>;
- clocks = <&rcc 0 8>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
st,bank-name = "GPIOI";
u-boot,dm-pre-reloc;
};
@@ -210,7 +212,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2400 0x400>;
- clocks = <&rcc 0 9>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
st,bank-name = "GPIOJ";
u-boot,dm-pre-reloc;
};
@@ -220,7 +222,7 @@
#gpio-cells = <2>;
compatible = "st,stm32-gpio";
reg = <0x2800 0x400>;
- clocks = <&rcc 0 10>;
+ clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
st,bank-name = "GPIOK";
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts
index 6591cc8..f34ffcc 100644
--- a/arch/arm/dts/stm32f769-disco.dts
+++ b/arch/arm/dts/stm32f769-disco.dts
@@ -209,7 +209,6 @@
pinctrl-names = "default";
status = "okay";
- mr-nbanks = <1>;
/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
bank1: bank@0 {
st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_32 BANKS_4
diff --git a/arch/arm/include/asm/arch-meson/gpio.h b/arch/arm/include/asm/arch-meson/gpio.h
new file mode 100644
index 0000000..7079ab3
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/gpio.h
@@ -0,0 +1,11 @@
+/*
+ * (C) Copyright 2017 - Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MESON_GPIO_H
+#define __ASM_ARCH_MESON_GPIO_H
+
+
+#endif /* __ASM_ARCH_MESON_GPIO_H */
diff --git a/arch/arm/include/asm/arch-stm32f7/fmc.h b/arch/arm/include/asm/arch-stm32f7/fmc.h
deleted file mode 100644
index 4741e5a..0000000
--- a/arch/arm/include/asm/arch-stm32f7/fmc.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2013
- * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
- *
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _MACH_FMC_H_
-#define _MACH_FMC_H_
-
-struct stm32_fmc_regs {
- u32 sdcr1; /* Control register 1 */
- u32 sdcr2; /* Control register 2 */
- u32 sdtr1; /* Timing register 1 */
- u32 sdtr2; /* Timing register 2 */
- u32 sdcmr; /* Mode register */
- u32 sdrtr; /* Refresh timing register */
- u32 sdsr; /* Status register */
-};
-
-/*
- * FMC registers base
- */
-#define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)SDRAM_FMC_BASE)
-
-/* Control register SDCR */
-#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
-#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
-#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
-#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
-#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
-#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
-#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
-#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
-#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
-
-/* Timings register SDTR */
-#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
-#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
-#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
-#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
-#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
-#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
-#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
-
-
-#define FMC_SDCMR_NRFS_SHIFT 5
-
-#define FMC_SDCMR_MODE_NORMAL 0
-#define FMC_SDCMR_MODE_START_CLOCK 1
-#define FMC_SDCMR_MODE_PRECHARGE 2
-#define FMC_SDCMR_MODE_AUTOREFRESH 3
-#define FMC_SDCMR_MODE_WRITE_MODE 4
-#define FMC_SDCMR_MODE_SELFREFRESH 5
-#define FMC_SDCMR_MODE_POWERDOWN 6
-
-#define FMC_SDCMR_BANK_1 BIT(4)
-#define FMC_SDCMR_BANK_2 BIT(3)
-
-#define FMC_SDCMR_MODE_REGISTER_SHIFT 9
-
-#define FMC_SDSR_BUSY BIT(5)
-
-#define FMC_BUSY_WAIT() do { \
- __asm__ __volatile__ ("dsb" : : : "memory"); \
- while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \
- ; \
- } while (0)
-
-
-#endif /* _MACH_FMC_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f7/rcc.h b/arch/arm/include/asm/arch-stm32f7/rcc.h
index 0f8d50b..a33f8cf 100644
--- a/arch/arm/include/asm/arch-stm32f7/rcc.h
+++ b/arch/arm/include/asm/arch-stm32f7/rcc.h
@@ -8,44 +8,24 @@
#ifndef _STM32_RCC_H
#define _STM32_RCC_H
+#include <dt-bindings/mfd/stm32f7-rcc.h>
+
/*
* RCC AHB1ENR specific definitions
*/
-#define RCC_AHB1ENR_GPIO_A_EN BIT(0)
-#define RCC_AHB1ENR_GPIO_B_EN BIT(1)
-#define RCC_AHB1ENR_GPIO_C_EN BIT(2)
-#define RCC_AHB1ENR_GPIO_D_EN BIT(3)
-#define RCC_AHB1ENR_GPIO_E_EN BIT(4)
-#define RCC_AHB1ENR_GPIO_F_EN BIT(5)
-#define RCC_AHB1ENR_GPIO_G_EN BIT(6)
-#define RCC_AHB1ENR_GPIO_H_EN BIT(7)
-#define RCC_AHB1ENR_GPIO_I_EN BIT(8)
-#define RCC_AHB1ENR_GPIO_J_EN BIT(9)
-#define RCC_AHB1ENR_GPIO_K_EN BIT(10)
#define RCC_AHB1ENR_ETHMAC_EN BIT(25)
#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
-#define RCC_AHB1ENR_ETHMAC_PTP_EN BIT(28)
-
-/*
- * RCC AHB3ENR specific definitions
- */
-#define RCC_AHB3ENR_FMC_EN BIT(0)
-#define RCC_AHB3ENR_QSPI_EN BIT(1)
/*
* RCC APB1ENR specific definitions
*/
#define RCC_APB1ENR_TIM2EN BIT(0)
-#define RCC_APB1ENR_USART2EN BIT(17)
-#define RCC_APB1ENR_USART3EN BIT(18)
#define RCC_APB1ENR_PWREN BIT(28)
/*
* RCC APB2ENR specific definitions
*/
-#define RCC_APB2ENR_USART1EN BIT(4)
-#define RCC_APB2ENR_USART6EN BIT(5)
#define RCC_APB2ENR_SYSCFGEN BIT(14)
#endif
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h
index 14e3398..87aee60 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
@@ -57,12 +57,6 @@
[5 ... 7] = 256 * 1024
};
-enum clock {
- CLOCK_CORE,
- CLOCK_AHB,
- CLOCK_APB1,
- CLOCK_APB2
-};
#define STM32_BUS_MASK GENMASK(31, 16)
struct stm32_rcc_regs {
@@ -101,11 +95,6 @@
};
#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)
-struct stm32_rcc_ext_f7_regs {
- u32 dckcfgr2; /* dedicated clocks configuration register */
-};
-#define STM32_RCC_EXT_F7 ((struct stm32_rcc_ext_f7_regs *) (RCC_BASE + sizeof(struct stm32_rcc_regs)))
-
struct stm32_pwr_regs {
u32 cr1; /* power control register 1 */
u32 csr1; /* power control/status register 2 */
@@ -114,8 +103,6 @@
};
#define STM32_PWR ((struct stm32_pwr_regs *)PWR_BASE)
-int configure_clocks(void);
-unsigned long clock_get(enum clock clck);
void stm32_flash_latency_cfg(int latency);
#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
index 3c5604a..9c1ec02 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
@@ -21,24 +21,9 @@
};
enum periph_clock {
- USART1_CLOCK_CFG = 0,
- USART2_CLOCK_CFG,
- GPIO_A_CLOCK_CFG,
- GPIO_B_CLOCK_CFG,
- GPIO_C_CLOCK_CFG,
- GPIO_D_CLOCK_CFG,
- GPIO_E_CLOCK_CFG,
- GPIO_F_CLOCK_CFG,
- GPIO_G_CLOCK_CFG,
- GPIO_H_CLOCK_CFG,
- GPIO_I_CLOCK_CFG,
- GPIO_J_CLOCK_CFG,
- GPIO_K_CLOCK_CFG,
SYSCFG_CLOCK_CFG,
TIMER2_CLOCK_CFG,
- FMC_CLOCK_CFG,
STMMAC_CLOCK_CFG,
- QSPI_CLOCK_CFG,
};
#endif /* __ASM_ARM_ARCH_PERIPH_H */
diff --git a/arch/arm/mach-keystone/cmd_mon.c b/arch/arm/mach-keystone/cmd_mon.c
index 591e758..c2525bd 100644
--- a/arch/arm/mach-keystone/cmd_mon.c
+++ b/arch/arm/mach-keystone/cmd_mon.c
@@ -19,6 +19,7 @@
u32 addr, dpsc_base = 0x1E80000, freq, load_addr, size;
int rcode = 0;
struct image_header *header;
+ u32 ecrypt_bm_addr = 0;
if (argc < 2)
return CMD_RET_USAGE;
@@ -39,14 +40,17 @@
memcpy((void *)load_addr, (void *)(addr + sizeof(struct image_header)),
size);
- rcode = mon_install(load_addr, dpsc_base, freq);
+ if (argc >= 3)
+ ecrypt_bm_addr = simple_strtoul(argv[2], NULL, 16);
+
+ rcode = mon_install(load_addr, dpsc_base, freq, ecrypt_bm_addr);
printf("## installed monitor @ 0x%x, freq [%d], status %d\n",
load_addr, freq, rcode);
return 0;
}
-U_BOOT_CMD(mon_install, 2, 0, do_mon_install,
+U_BOOT_CMD(mon_install, 3, 0, do_mon_install,
"Install boot kernel at 'addr'",
""
);
diff --git a/arch/arm/mach-keystone/include/mach/mon.h b/arch/arm/mach-keystone/include/mach/mon.h
index eb7aa93..30c57e0 100644
--- a/arch/arm/mach-keystone/include/mach/mon.h
+++ b/arch/arm/mach-keystone/include/mach/mon.h
@@ -10,7 +10,7 @@
#ifndef _MACH_MON_H_
#define _MACH_MON_H_
-int mon_install(u32 addr, u32 dpsc, u32 freq);
+int mon_install(u32 addr, u32 dpsc, u32 freq, u32 bm_addr);
int mon_power_on(int core_id, void *ep);
int mon_power_off(int core_id);
diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c
index ebfb483..dd446ab 100644
--- a/arch/arm/mach-keystone/mon.c
+++ b/arch/arm/mach-keystone/mon.c
@@ -13,7 +13,7 @@
#include <spl.h>
asm(".arch_extension sec\n\t");
-int mon_install(u32 addr, u32 dpsc, u32 freq)
+int mon_install(u32 addr, u32 dpsc, u32 freq, u32 bm_addr)
{
int result;
@@ -22,11 +22,13 @@
"mov r0, %1\n"
"mov r1, %2\n"
"mov r2, %3\n"
+ "mov r3, %4\n"
"blx r0\n"
+ "mov %0, r0\n"
"ldmfd r13!, {lr}\n"
: "=&r" (result)
- : "r" (addr), "r" (dpsc), "r" (freq)
- : "cc", "r0", "r1", "r2", "memory");
+ : "r" (addr), "r" (dpsc), "r" (freq), "r" (bm_addr)
+ : "cc", "r0", "r1", "r2", "r3", "memory");
return result;
}
@@ -40,6 +42,7 @@
"mov r2, %2\n"
"mov r0, #0\n"
"smc #0\n"
+ "mov %0, r0\n"
"ldmfd r13!, {lr}\n"
: "=&r" (result)
: "r" (core_id), "r" (ep)
@@ -56,6 +59,7 @@
"mov r1, %1\n"
"mov r0, #1\n"
"smc #1\n"
+ "mov %0, r0\n"
"ldmfd r13!, {lr}\n"
: "=&r" (result)
: "r" (core_id)
@@ -89,6 +93,7 @@
"mov r0, %1\n"
"mov r1, %2\n"
"smc #2\n"
+ "mov %0, r0\n"
"ldmfd r13!, {r4-r12, lr}\n"
: "=&r" (result)
: "r" (cmd), "r" (arg1)
diff --git a/arch/mips/Makefile.postlink b/arch/mips/Makefile.postlink
new file mode 100644
index 0000000..7da3acd
--- /dev/null
+++ b/arch/mips/Makefile.postlink
@@ -0,0 +1,23 @@
+#
+# Copyright (c) 2017 Imagination Technologies Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PHONY := __archpost
+__archpost:
+
+-include include/config/auto.conf
+include scripts/Kbuild.include
+
+CMD_RELOCS = tools/mips-relocs
+quiet_cmd_relocs = RELOCS $@
+ cmd_relocs = $(CMD_RELOCS) $@
+
+u-boot: FORCE
+ @true
+ $(call if_changed,relocs)
+
+.PHONY: FORCE
+
+FORCE:
diff --git a/arch/mips/config.mk b/arch/mips/config.mk
index 2c72c15..cefdbe6 100644
--- a/arch/mips/config.mk
+++ b/arch/mips/config.mk
@@ -56,25 +56,14 @@
# LDFLAGS_vmlinux += -G 0 -static -n -nostdlib
# MODFLAGS += -mlong-calls
#
-# On the other hand, we want PIC in the U-Boot code to relocate it from ROM
-# to RAM. $28 is always used as gp.
-#
-ifdef CONFIG_SPL_BUILD
-PF_ABICALLS := -mno-abicalls
-PF_PIC := -fno-pic
-PF_PIE :=
-else
-PF_ABICALLS := -mabicalls
-PF_PIC := -fpic
-PF_PIE := -pie
-PF_OBJCOPY := -j .got -j .rel.dyn -j .padding
-PF_OBJCOPY += -j .dtb.init.rodata
+ifndef CONFIG_SPL_BUILD
+OBJCOPYFLAGS += -j .got -j .rel -j .padding -j .dtb.init.rodata
+LDFLAGS_FINAL += --emit-relocs
endif
-PLATFORM_CPPFLAGS += -G 0 $(PF_ABICALLS) $(PF_PIC)
+PLATFORM_CPPFLAGS += -G 0 -mno-abicalls -fno-pic
PLATFORM_CPPFLAGS += -msoft-float
PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
-LDFLAGS_FINAL += --gc-sections $(PF_PIE)
+LDFLAGS_FINAL += --gc-sections
OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list
-OBJCOPYFLAGS += $(PF_OBJCOPY)
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index d01ee9f..952c57a 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -221,18 +221,6 @@
ehb
#endif
- /*
- * Initialize $gp, force pointer sized alignment of bal instruction to
- * forbid the compiler to put nop's between bal and _gp. This is
- * required to keep _gp and ra aligned to 8 byte.
- */
- .align PTRLOG
- bal 1f
- nop
- PTR _gp
-1:
- PTR_L gp, 0(ra)
-
#ifdef CONFIG_MIPS_CM
PTR_LA t9, mips_cm_map
jalr t9
@@ -291,121 +279,3 @@
move ra, zero
END(_start)
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * a0 = addr_sp
- * a1 = gd
- * a2 = destination address
- */
-ENTRY(relocate_code)
- move sp, a0 # set new stack pointer
- move fp, sp
-
- move s0, a1 # save gd in s0
- move s2, a2 # save destination address in s2
-
- PTR_LI t0, CONFIG_SYS_MONITOR_BASE
- PTR_SUB s1, s2, t0 # s1 <-- relocation offset
-
- PTR_LA t2, __image_copy_end
- move t1, a2
-
- /*
- * t0 = source address
- * t1 = target address
- * t2 = source end address
- */
-1:
- PTR_L t3, 0(t0)
- PTR_S t3, 0(t1)
- PTR_ADDU t0, PTRSIZE
- blt t0, t2, 1b
- PTR_ADDU t1, PTRSIZE
-
- /*
- * Now we want to update GOT.
- *
- * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
- * generated by GNU ld. Skip these reserved entries from relocation.
- */
- PTR_LA t3, num_got_entries
- PTR_LA t8, _GLOBAL_OFFSET_TABLE_
- PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_
- PTR_ADDIU t8, t8, 2 * PTRSIZE # skipping first two entries
- PTR_LI t2, 2
-1:
- PTR_L t1, 0(t8)
- beqz t1, 2f
- PTR_ADD t1, s1
- PTR_S t1, 0(t8)
-2:
- PTR_ADDIU t2, 1
- blt t2, t3, 1b
- PTR_ADDIU t8, PTRSIZE
-
- /* Update dynamic relocations */
- PTR_LA t1, __rel_dyn_start
- PTR_LA t2, __rel_dyn_end
-
- b 2f # skip first reserved entry
- PTR_ADDIU t1, 2 * PTRSIZE
-
-1:
- lw t8, -4(t1) # t8 <-- relocation info
-
- PTR_LI t3, MIPS_RELOC
- bne t8, t3, 2f # skip non-MIPS_RELOC entries
- nop
-
- PTR_L t3, -(2 * PTRSIZE)(t1) # t3 <-- location to fix up in FLASH
-
- PTR_L t8, 0(t3) # t8 <-- original pointer
- PTR_ADD t8, s1 # t8 <-- adjusted pointer
-
- PTR_ADD t3, s1 # t3 <-- location to fix up in RAM
- PTR_S t8, 0(t3)
-
-2:
- blt t1, t2, 1b
- PTR_ADDIU t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes
-
- /*
- * Flush caches to ensure our newly modified instructions are visible
- * to the instruction cache. We're still running with the old GOT, so
- * apply the reloc offset to the start address.
- */
- PTR_LA a0, __text_start
- PTR_LA a1, __text_end
- PTR_SUB a1, a1, a0
- PTR_LA t9, flush_cache
- jalr t9
- PTR_ADD a0, s1
-
- PTR_ADD gp, s1 # adjust gp
-
- /*
- * Clear BSS
- *
- * GOT is now relocated. Thus __bss_start and __bss_end can be
- * accessed directly via $gp.
- */
- PTR_LA t1, __bss_start # t1 <-- __bss_start
- PTR_LA t2, __bss_end # t2 <-- __bss_end
-
-1:
- PTR_S zero, 0(t1)
- blt t1, t2, 1b
- PTR_ADDIU t1, PTRSIZE
-
- move a0, s0 # a0 <-- gd
- move a1, s2
- PTR_LA t9, board_init_r
- jr t9
- move ra, zero
-
- END(relocate_code)
diff --git a/arch/mips/cpu/u-boot.lds b/arch/mips/cpu/u-boot.lds
index 0129c99..bd5536f 100644
--- a/arch/mips/cpu/u-boot.lds
+++ b/arch/mips/cpu/u-boot.lds
@@ -34,15 +34,6 @@
*(.data*)
}
- . = .;
- _gp = ALIGN(16) + 0x7ff0;
-
- .got : {
- *(.got)
- }
-
- num_got_entries = SIZEOF(.got) >> PTR_COUNT_SHIFT;
-
. = ALIGN(4);
.sdata : {
*(.sdata*)
@@ -57,33 +48,19 @@
__image_copy_end = .;
__init_end = .;
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel.dyn)
- __rel_dyn_end = .;
- }
-
- .padding : {
- /*
- * Workaround for a binutils feature (or bug?).
- *
- * The GNU ld from binutils puts the dynamic relocation
- * entries into the .rel.dyn section. Sometimes it
- * allocates more dynamic relocation entries than it needs
- * and the unused slots are set to R_MIPS_NONE entries.
- *
- * However the size of the .rel.dyn section in the ELF
- * section header does not cover the unused entries, so
- * objcopy removes those during stripping.
- *
- * Create a small section here to avoid that.
- */
- LONG(0xFFFFFFFF)
+ /*
+ * .rel must come last so that the mips-relocs tool can shrink
+ * the section size & the PT_LOAD program header filesz.
+ */
+ .rel : {
+ __rel_start = .;
+ BYTE(0x0)
+ . += (32 * 1024) - 1;
}
_end = .;
- .bss __rel_dyn_start (OVERLAY) : {
+ .bss __rel_start (OVERLAY) : {
__bss_start = .;
*(.sbss.*)
*(.bss.*)
diff --git a/arch/mips/include/asm/relocs.h b/arch/mips/include/asm/relocs.h
new file mode 100644
index 0000000..92e9d04
--- /dev/null
+++ b/arch/mips/include/asm/relocs.h
@@ -0,0 +1,24 @@
+/*
+ * MIPS Relocations
+ *
+ * Copyright (c) 2017 Imagination Technologies Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_MIPS_RELOCS_H__
+#define __ASM_MIPS_RELOCS_H__
+
+#define R_MIPS_NONE 0
+#define R_MIPS_32 2
+#define R_MIPS_26 4
+#define R_MIPS_HI16 5
+#define R_MIPS_LO16 6
+#define R_MIPS_PC16 10
+#define R_MIPS_64 18
+#define R_MIPS_HIGHER 28
+#define R_MIPS_HIGHEST 29
+#define R_MIPS_PC21_S2 60
+#define R_MIPS_PC26_S2 61
+
+#endif /* __ASM_MIPS_RELOCS_H__ */
diff --git a/arch/mips/include/asm/sections.h b/arch/mips/include/asm/sections.h
index fc4640a..b9d2179 100644
--- a/arch/mips/include/asm/sections.h
+++ b/arch/mips/include/asm/sections.h
@@ -8,4 +8,11 @@
#include <asm-generic/sections.h>
+/**
+ * __rel_start: Relocation data generated by the mips-relocs tool
+ *
+ * See arch/mips/lib/reloc.c for details on the format & use of this data.
+ */
+extern uint8_t __rel_start[];
+
#endif
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 659c6ad..ef557c6 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -8,6 +8,7 @@
obj-y += cache.o
obj-y += cache_init.o
obj-y += genex.o
+obj-y += reloc.o
obj-y += stack.o
obj-y += traps.o
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index be87762..2b67905 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -279,17 +279,17 @@
boot_reloc_fdt(images);
boot_setup_fdt(images);
} else {
- if (CONFIG_IS_ENABLED(CONFIG_MIPS_BOOT_ENV_LEGACY))
- linux_env_legacy(images);
-
if (CONFIG_IS_ENABLED(MIPS_BOOT_CMDLINE_LEGACY)) {
linux_cmdline_legacy(images);
- if (!CONFIG_IS_ENABLED(CONFIG_MIPS_BOOT_ENV_LEGACY))
+ if (!CONFIG_IS_ENABLED(MIPS_BOOT_ENV_LEGACY))
linux_cmdline_append(images);
linux_cmdline_dump();
}
+
+ if (CONFIG_IS_ENABLED(MIPS_BOOT_ENV_LEGACY))
+ linux_env_legacy(images);
}
}
diff --git a/arch/mips/lib/reloc.c b/arch/mips/lib/reloc.c
new file mode 100644
index 0000000..d0c52c9
--- /dev/null
+++ b/arch/mips/lib/reloc.c
@@ -0,0 +1,164 @@
+/*
+ * MIPS Relocation
+ *
+ * Copyright (c) 2017 Imagination Technologies Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Relocation data, found in the .rel section, is generated by the mips-relocs
+ * tool & contains a record of all locations in the U-Boot binary that need to
+ * be fixed up during relocation.
+ *
+ * The data is a sequence of unsigned integers, which are of somewhat arbitrary
+ * size. This is achieved by encoding integers as a sequence of bytes, each of
+ * which contains 7 bits of data with the most significant bit indicating
+ * whether any further bytes need to be read. The least significant bits of the
+ * integer are found in the first byte - ie. it somewhat resembles little
+ * endian.
+ *
+ * Each pair of two integers represents a relocation that must be applied. The
+ * first integer represents the type of relocation as a standard ELF relocation
+ * type (ie. R_MIPS_*). The second integer represents the offset at which to
+ * apply the relocation, relative to the previous relocation or for the first
+ * relocation the start of the relocated .text section.
+ *
+ * The end of the relocation data is indicated when type R_MIPS_NONE (0) is
+ * read, at which point no further integers should be read. That is, the
+ * terminating R_MIPS_NONE reloc includes no offset.
+ */
+
+#include <common.h>
+#include <asm/relocs.h>
+#include <asm/sections.h>
+
+/**
+ * read_uint() - Read an unsigned integer from the buffer
+ * @buf: pointer to a pointer to the reloc buffer
+ *
+ * Read one whole unsigned integer from the relocation data pointed to by @buf,
+ * advancing @buf past the bytes encoding the integer.
+ *
+ * Returns: the integer read from @buf
+ */
+static unsigned long read_uint(uint8_t **buf)
+{
+ unsigned long val = 0;
+ unsigned int shift = 0;
+ uint8_t new;
+
+ do {
+ new = *(*buf)++;
+ val |= (new & 0x7f) << shift;
+ shift += 7;
+ } while (new & 0x80);
+
+ return val;
+}
+
+/**
+ * apply_reloc() - Apply a single relocation
+ * @type: the type of reloc (R_MIPS_*)
+ * @addr: the address that the reloc should be applied to
+ * @off: the relocation offset, ie. number of bytes we're moving U-Boot by
+ *
+ * Apply a single relocation of type @type at @addr. This function is
+ * intentionally simple, and does the bare minimum needed to fixup the
+ * relocated U-Boot - in particular, it does not check for overflows.
+ */
+static void apply_reloc(unsigned int type, void *addr, long off)
+{
+ uint32_t u32;
+
+ switch (type) {
+ case R_MIPS_26:
+ u32 = *(uint32_t *)addr;
+ u32 = (u32 & GENMASK(31, 26)) |
+ ((u32 + (off >> 2)) & GENMASK(25, 0));
+ *(uint32_t *)addr = u32;
+ break;
+
+ case R_MIPS_32:
+ *(uint32_t *)addr += off;
+ break;
+
+ case R_MIPS_64:
+ *(uint64_t *)addr += off;
+ break;
+
+ case R_MIPS_HI16:
+ *(uint32_t *)addr += off >> 16;
+ break;
+
+ default:
+ panic("Unhandled reloc type %u\n", type);
+ }
+}
+
+/**
+ * relocate_code() - Relocate U-Boot, generally from flash to DDR
+ * @start_addr_sp: new stack pointer
+ * @new_gd: pointer to relocated global data
+ * @relocaddr: the address to relocate to
+ *
+ * Relocate U-Boot from its current location (generally in flash) to a new one
+ * (generally in DDR). This function will copy the U-Boot binary & apply
+ * relocations as necessary, then jump to board_init_r in the new build of
+ * U-Boot. As such, this function does not return.
+ */
+void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaddr)
+{
+ unsigned long addr, length, bss_len;
+ uint8_t *buf, *bss_start;
+ unsigned int type;
+ long off;
+
+ /*
+ * Ensure that we're relocating by an offset which is a multiple of
+ * 64KiB, ie. doesn't change the least significant 16 bits of any
+ * addresses. This allows us to discard R_MIPS_LO16 relocs, saving
+ * space in the U-Boot binary & complexity in handling them.
+ */
+ off = relocaddr - (unsigned long)__text_start;
+ if (off & 0xffff)
+ panic("Mis-aligned relocation\n");
+
+ /* Copy U-Boot to RAM */
+ length = __image_copy_end - __text_start;
+ memcpy((void *)relocaddr, __text_start, length);
+
+ /* Now apply relocations to the copy in RAM */
+ buf = __rel_start;
+ addr = relocaddr;
+ while (true) {
+ type = read_uint(&buf);
+ if (type == R_MIPS_NONE)
+ break;
+
+ addr += read_uint(&buf) << 2;
+ apply_reloc(type, (void *)addr, off);
+ }
+
+ /* Ensure the icache is coherent */
+ flush_cache(relocaddr, length);
+
+ /* Clear the .bss section */
+ bss_start = (uint8_t *)((unsigned long)__bss_start + off);
+ bss_len = (unsigned long)&__bss_end - (unsigned long)__bss_start;
+ memset(bss_start, 0, bss_len);
+
+ /* Jump to the relocated U-Boot */
+ asm volatile(
+ "move $29, %0\n"
+ " move $4, %1\n"
+ " move $5, %2\n"
+ " move $31, $0\n"
+ " jr %3"
+ : /* no outputs */
+ : "r"(start_addr_sp),
+ "r"(new_gd),
+ "r"(relocaddr),
+ "r"((unsigned long)board_init_r + off));
+
+ /* Since we jumped to the new U-Boot above, we won't get here */
+ unreachable();
+}
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index fc4c60c..f31768e 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -13,8 +13,6 @@
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/fmc.h>
-#include <dm/platform_data/serial_stm32x7.h>
#include <asm/arch/stm32_periph.h>
#include <asm/arch/stm32_defs.h>
#include <asm/arch/syscfg.h>
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index bf8c8e1..00a31a97 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -36,11 +36,13 @@
#define board_is_x15() board_ti_is("BBRDX15_")
#define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
- (strncmp("B.10", board_ti_get_rev(), 3) <= 0))
+ !strncmp("B.10", board_ti_get_rev(), 3))
+#define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
+ !strncmp("C.00", board_ti_get_rev(), 3))
#define board_is_am572x_evm() board_ti_is("AM572PM_")
#define board_is_am572x_evm_reva3() \
(board_ti_is("AM572PM_") && \
- (strncmp("A.30", board_ti_get_rev(), 3) <= 0))
+ !strncmp("A.30", board_ti_get_rev(), 3))
#define board_is_am572x_idk() board_ti_is("AM572IDK")
#define board_is_am571x_idk() board_ti_is("AM571IDK")
@@ -474,6 +476,8 @@
if (board_is_x15()) {
if (board_is_x15_revb1())
name = "beagle_x15_revb1";
+ else if (board_is_x15_revc())
+ name = "beagle_x15_revc";
else
name = "beagle_x15";
} else if (board_is_am572x_evm()) {
@@ -683,7 +687,8 @@
/* Now do the weird minor deltas that should be safe */
if (board_is_x15() || board_is_am572x_evm()) {
- if (board_is_x15_revb1() || board_is_am572x_evm_reva3()) {
+ if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
+ board_is_x15_revc()) {
pconf = core_padconf_array_delta_x15_sr2_0;
pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
} else {
diff --git a/common/board_f.c b/common/board_f.c
index ffa84e3..49c8bc8 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -418,7 +418,7 @@
*/
gd->relocaddr -= gd->mon_len;
gd->relocaddr &= ~(4096 - 1);
-#ifdef CONFIG_E500
+#if defined(CONFIG_E500) || defined(CONFIG_MIPS)
/* round down to next 64 kB limit so that IVPR stays aligned */
gd->relocaddr &= ~(65536 - 1);
#endif
diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
index e03e017..121dcf2 100644
--- a/configs/odroid-c2_defconfig
+++ b/configs/odroid-c2_defconfig
@@ -14,9 +14,11 @@
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_DM_ETH=y
diff --git a/doc/device-tree-bindings/ram/st,stm32-fmc.txt b/doc/device-tree-bindings/ram/st,stm32-fmc.txt
index 3d1392c..99f76d5 100644
--- a/doc/device-tree-bindings/ram/st,stm32-fmc.txt
+++ b/doc/device-tree-bindings/ram/st,stm32-fmc.txt
@@ -40,12 +40,19 @@
pinctrl-names = "default";
status = "okay";
- mr-nbanks = <1>;
/* sdram memory configuration from sdram datasheet */
- bank1: bank@0 {
- st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
+ bank1: bank@0 {
+ st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
- st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
+ st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
+ TRCD_18>;
+ };
+
+ /* sdram memory configuration from sdram datasheet */
+ bank2: bank@1 {
+ st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
+ CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
TRCD_18>;
- };
-}
+ };
+ }
diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt
index afff301..136d3d7 100644
--- a/doc/uImage.FIT/source_file_format.txt
+++ b/doc/uImage.FIT/source_file_format.txt
@@ -159,8 +159,8 @@
Mandatory properties:
- description : Textual description of the component sub-image
- type : Name of component sub-image type, supported types are:
- "standalone", "kernel", "ramdisk", "firmware", "script", "filesystem",
- "flat_dt" and others (see uimage_type in common/image.c).
+ "standalone", "kernel", "kernel_noload", "ramdisk", "firmware", "script",
+ "filesystem", "flat_dt" and others (see uimage_type in common/image.c).
- data : Path to the external file which contains this node's binary data.
- compression : Compression used by included data. Supported compressions
are "gzip" and "bzip2". If no compression is used compression property
diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c
index fcdc3c0..255a583 100644
--- a/drivers/clk/clk_stm32f7.c
+++ b/drivers/clk/clk_stm32f7.c
@@ -12,6 +12,8 @@
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_periph.h>
+#include <dt-bindings/mfd/stm32f7-rcc.h>
+
#define RCC_CR_HSION BIT(0)
#define RCC_CR_HSEON BIT(16)
#define RCC_CR_HSERDY BIT(17)
@@ -83,6 +85,10 @@
#define APB_PSC_8 0x6
#define APB_PSC_16 0x7
+struct stm32_clk {
+ struct stm32_rcc_regs *base;
+};
+
#if !defined(CONFIG_STM32_HSE_HZ)
#error "CONFIG_STM32_HSE_HZ not defined!"
#else
@@ -104,23 +110,26 @@
#endif
#endif
-int configure_clocks(void)
+static int configure_clocks(struct udevice *dev)
{
+ struct stm32_clk *priv = dev_get_priv(dev);
+ struct stm32_rcc_regs *regs = priv->base;
+
/* Reset RCC configuration */
- setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
- writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
- clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
+ setbits_le32(®s->cr, RCC_CR_HSION);
+ writel(0, ®s->cfgr); /* Reset CFGR */
+ clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON
| RCC_CR_PLLON));
- writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
- clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
- writel(0, &STM32_RCC->cir); /* Disable all interrupts */
+ writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */
+ clrbits_le32(®s->cr, RCC_CR_HSEBYP);
+ writel(0, ®s->cir); /* Disable all interrupts */
/* Configure for HSE+PLL operation */
- setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
- while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
+ setbits_le32(®s->cr, RCC_CR_HSEON);
+ while (!(readl(®s->cr) & RCC_CR_HSERDY))
;
- setbits_le32(&STM32_RCC->cfgr, ((
+ setbits_le32(®s->cfgr, ((
sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
| (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
| (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
@@ -132,15 +141,15 @@
pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT;
pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT;
pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT;
- writel(pllcfgr, &STM32_RCC->pllcfgr);
+ writel(pllcfgr, ®s->pllcfgr);
/* Enable the main PLL */
- setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
- while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
+ setbits_le32(®s->cr, RCC_CR_PLLON);
+ while (!(readl(®s->cr) & RCC_CR_PLLRDY))
;
/* Enable high performance mode, System frequency up to 200 MHz */
- setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
+ setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN);
setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
/* Infinite wait! */
while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
@@ -152,18 +161,20 @@
;
stm32_flash_latency_cfg(5);
- clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
- setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
+ clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
+ setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL);
- while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
+ while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_PLL)
;
return 0;
}
-unsigned long clock_get(enum clock clck)
+static unsigned long stm32_clk_get_rate(struct clk *clk)
{
+ struct stm32_clk *priv = dev_get_priv(clk->dev);
+ struct stm32_rcc_regs *regs = priv->base;
u32 sysclk = 0;
u32 shift = 0;
/* Prescaler table lookups for clock computation */
@@ -174,53 +185,61 @@
0, 0, 0, 0, 1, 2, 3, 4
};
- if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
+ if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) ==
RCC_CFGR_SWS_PLL) {
u16 pllm, plln, pllp;
- pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
- plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
+ pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
+ plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
>> RCC_PLLCFGR_PLLN_SHIFT);
- pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
+ pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
+ } else {
+ return -EINVAL;
}
- switch (clck) {
- case CLOCK_CORE:
- return sysclk;
- break;
- case CLOCK_AHB:
+ switch (clk->id) {
+ /*
+ * AHB CLOCK: 3 x 32 bits consecutive registers are used :
+ * AHB1, AHB2 and AHB3
+ */
+ case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
shift = ahb_psc_table[(
- (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
+ (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK)
>> RCC_CFGR_HPRE_SHIFT)];
return sysclk >>= shift;
break;
- case CLOCK_APB1:
+ /* APB1 CLOCK */
+ case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
shift = apb_psc_table[(
- (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
+ (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK)
>> RCC_CFGR_PPRE1_SHIFT)];
return sysclk >>= shift;
break;
- case CLOCK_APB2:
+ /* APB2 CLOCK */
+ case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
shift = apb_psc_table[(
- (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
+ (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK)
>> RCC_CFGR_PPRE2_SHIFT)];
return sysclk >>= shift;
break;
default:
- return 0;
+ error("clock index %ld out of range\n", clk->id);
+ return -EINVAL;
break;
}
}
static int stm32_clk_enable(struct clk *clk)
{
+ struct stm32_clk *priv = dev_get_priv(clk->dev);
+ struct stm32_rcc_regs *regs = priv->base;
u32 offset = clk->id / 32;
u32 bit_index = clk->id % 32;
debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
__func__, clk->id, offset, bit_index);
- setbits_le32(&STM32_RCC->ahb1enr + offset, BIT(bit_index));
+ setbits_le32(®s->ahb1enr + offset, BIT(bit_index));
return 0;
}
@@ -247,7 +266,17 @@
static int stm32_clk_probe(struct udevice *dev)
{
debug("%s: stm32_clk_probe\n", __func__);
- configure_clocks();
+
+ struct stm32_clk *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+
+ addr = devfdt_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->base = (struct stm32_rcc_regs *)addr;
+
+ configure_clocks(dev);
return 0;
}
@@ -272,6 +301,7 @@
static struct clk_ops stm32_clk_ops = {
.of_xlate = stm32_clk_of_xlate,
.enable = stm32_clk_enable,
+ .get_rate = stm32_clk_get_rate,
};
static const struct udevice_id stm32_clk_ids[] = {
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index 2fa840c..87c9912 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -391,14 +391,33 @@
FUNCTION(i2c_slave_ao),
};
+static struct meson_bank meson_gxbb_periphs_banks[] = {
+ /* name first last pullen pull dir out in */
+ BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_22, EE_OFF), 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
+ BANK("Y", PIN(GPIOY_0, EE_OFF), PIN(GPIOY_16, EE_OFF), 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
+ BANK("DV", PIN(GPIODV_0, EE_OFF), PIN(GPIODV_29, EE_OFF), 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
+ BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_3, EE_OFF), 1, 20, 1, 20, 3, 20, 4, 20, 5, 20),
+ BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
+ BANK("CARD", PIN(CARD_0, EE_OFF), PIN(CARD_6, EE_OFF), 2, 20, 2, 20, 6, 20, 7, 20, 8, 20),
+ BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_17, EE_OFF), 2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
+ BANK("CLK", PIN(GPIOCLK_0, EE_OFF), PIN(GPIOCLK_3, EE_OFF), 3, 28, 3, 28, 9, 28, 10, 28, 11, 28),
+};
+
+static struct meson_bank meson_gxbb_aobus_banks[] = {
+ /* name first last pullen pull dir out in */
+ BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_13, 0), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
+};
+
struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
.name = "periphs-banks",
.pin_base = 14,
.groups = meson_gxbb_periphs_groups,
.funcs = meson_gxbb_periphs_functions,
+ .banks = meson_gxbb_periphs_banks,
.num_pins = 120,
.num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups),
.num_funcs = ARRAY_SIZE(meson_gxbb_periphs_functions),
+ .num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks),
};
struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
@@ -406,9 +425,11 @@
.pin_base = 0,
.groups = meson_gxbb_aobus_groups,
.funcs = meson_gxbb_aobus_functions,
+ .banks = meson_gxbb_aobus_banks,
.num_pins = 14,
.num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups),
.num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions),
+ .num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks),
};
static const struct udevice_id meson_gxbb_pinctrl_match[] = {
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index 6281f52..a860200 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -6,11 +6,14 @@
#include <common.h>
#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
#include <dm/pinctrl.h>
#include <fdt_support.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
+#include <asm/gpio.h>
#include "pinctrl-meson.h"
@@ -117,6 +120,143 @@
.set_state = pinctrl_generic_set_state,
};
+static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset,
+ enum meson_reg_type reg_type,
+ unsigned int *reg, unsigned int *bit)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev->parent);
+ struct meson_bank *bank = NULL;
+ struct meson_reg_desc *desc;
+ unsigned int pin;
+ int i;
+
+ pin = priv->data->pin_base + offset;
+
+ for (i = 0; i < priv->data->num_banks; i++) {
+ if (pin >= priv->data->banks[i].first &&
+ pin <= priv->data->banks[i].last) {
+ bank = &priv->data->banks[i];
+ break;
+ }
+ }
+
+ if (!bank)
+ return -EINVAL;
+
+ desc = &bank->regs[reg_type];
+ *reg = desc->reg * 4;
+ *bit = desc->bit + pin - bank->first;
+
+ return 0;
+}
+
+static int meson_gpio_get(struct udevice *dev, unsigned int offset)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev->parent);
+ unsigned int reg, bit;
+ int ret;
+
+ ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_IN, ®, &bit);
+ if (ret)
+ return ret;
+
+ return !!(readl(priv->reg_gpio + reg) & BIT(bit));
+}
+
+static int meson_gpio_set(struct udevice *dev, unsigned int offset, int value)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev->parent);
+ unsigned int reg, bit;
+ int ret;
+
+ ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_OUT, ®, &bit);
+ if (ret)
+ return ret;
+
+ clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), value ? BIT(bit) : 0);
+
+ return 0;
+}
+
+static int meson_gpio_get_direction(struct udevice *dev, unsigned int offset)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev->parent);
+ unsigned int reg, bit, val;
+ int ret;
+
+ ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_DIR, ®, &bit);
+ if (ret)
+ return ret;
+
+ val = readl(priv->reg_gpio + reg);
+
+ return (val & BIT(bit)) ? GPIOF_INPUT : GPIOF_OUTPUT;
+}
+
+static int meson_gpio_direction_input(struct udevice *dev, unsigned int offset)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev->parent);
+ unsigned int reg, bit;
+ int ret;
+
+ ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_DIR, ®, &bit);
+ if (ret)
+ return ret;
+
+ clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), 1);
+
+ return 0;
+}
+
+static int meson_gpio_direction_output(struct udevice *dev,
+ unsigned int offset, int value)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev->parent);
+ unsigned int reg, bit;
+ int ret;
+
+ ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_DIR, ®, &bit);
+ if (ret)
+ return ret;
+
+ clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), 0);
+
+ ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_OUT, ®, &bit);
+ if (ret)
+ return ret;
+
+ clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), value ? BIT(bit) : 0);
+
+ return 0;
+}
+
+static int meson_gpio_probe(struct udevice *dev)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev->parent);
+ struct gpio_dev_priv *uc_priv;
+
+ uc_priv = dev_get_uclass_priv(dev);
+ uc_priv->bank_name = priv->data->name;
+ uc_priv->gpio_count = priv->data->num_pins;
+
+ return 0;
+}
+
+static const struct dm_gpio_ops meson_gpio_ops = {
+ .set_value = meson_gpio_set,
+ .get_value = meson_gpio_get,
+ .get_function = meson_gpio_get_direction,
+ .direction_input = meson_gpio_direction_input,
+ .direction_output = meson_gpio_direction_output,
+};
+
+static struct driver meson_gpio_driver = {
+ .name = "meson-gpio",
+ .id = UCLASS_GPIO,
+ .probe = meson_gpio_probe,
+ .ops = &meson_gpio_ops,
+};
+
static fdt_addr_t parse_address(int offset, const char *name, int na, int ns)
{
int index, len = 0;
@@ -138,9 +278,12 @@
int meson_pinctrl_probe(struct udevice *dev)
{
struct meson_pinctrl *priv = dev_get_priv(dev);
+ struct uclass_driver *drv;
+ struct udevice *gpio_dev;
fdt_addr_t addr;
int node, gpio = -1, len;
int na, ns;
+ char *name;
na = fdt_address_cells(gd->fdt_blob, dev_of_offset(dev->parent));
if (na < 1) {
@@ -168,12 +311,32 @@
addr = parse_address(gpio, "mux", na, ns);
if (addr == FDT_ADDR_T_NONE) {
- debug("mux not found\n");
+ debug("mux address not found\n");
return -EINVAL;
}
-
priv->reg_mux = (void __iomem *)addr;
+
+ addr = parse_address(gpio, "gpio", na, ns);
+ if (addr == FDT_ADDR_T_NONE) {
+ debug("gpio address not found\n");
+ return -EINVAL;
+ }
+ priv->reg_gpio = (void __iomem *)addr;
priv->data = (struct meson_pinctrl_data *)dev_get_driver_data(dev);
+ /* Lookup GPIO driver */
+ drv = lists_uclass_lookup(UCLASS_GPIO);
+ if (!drv) {
+ puts("Cannot find GPIO driver\n");
+ return -ENOENT;
+ }
+
+ name = calloc(1, 32);
+ sprintf(name, "meson-gpio");
+
+ /* Create child device UCLASS_GPIO and bind it */
+ device_bind(dev, &meson_gpio_driver, name, NULL, gpio, &gpio_dev);
+ dev_set_of_offset(gpio_dev, gpio);
+
return 0;
}
diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
index 4127a60..90d2369 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.h
+++ b/drivers/pinctrl/meson/pinctrl-meson.h
@@ -28,17 +28,66 @@
const char *name;
struct meson_pmx_group *groups;
struct meson_pmx_func *funcs;
+ struct meson_bank *banks;
unsigned int pin_base;
unsigned int num_pins;
unsigned int num_groups;
unsigned int num_funcs;
+ unsigned int num_banks;
};
struct meson_pinctrl {
struct meson_pinctrl_data *data;
void __iomem *reg_mux;
+ void __iomem *reg_gpio;
};
+/**
+ * struct meson_reg_desc - a register descriptor
+ *
+ * @reg: register offset in the regmap
+ * @bit: bit index in register
+ *
+ * The structure describes the information needed to control pull,
+ * pull-enable, direction, etc. for a single pin
+ */
+struct meson_reg_desc {
+ unsigned int reg;
+ unsigned int bit;
+};
+
+/**
+ * enum meson_reg_type - type of registers encoded in @meson_reg_desc
+ */
+enum meson_reg_type {
+ REG_PULLEN,
+ REG_PULL,
+ REG_DIR,
+ REG_OUT,
+ REG_IN,
+ NUM_REG,
+};
+
+/**
+ * struct meson bank
+ *
+ * @name: bank name
+ * @first: first pin of the bank
+ * @last: last pin of the bank
+ * @regs: array of register descriptors
+ *
+ * A bank represents a set of pins controlled by a contiguous set of
+ * bits in the domain registers. The structure specifies which bits in
+ * the regmap control the different functionalities. Each member of
+ * the @regs array refers to the first pin of the bank.
+ */
+struct meson_bank {
+ const char *name;
+ unsigned int first;
+ unsigned int last;
+ struct meson_reg_desc regs[NUM_REG];
+};
+
#define PIN(x, b) (b + x)
#define GROUP(grp, r, b) \
@@ -65,6 +114,20 @@
.num_groups = ARRAY_SIZE(fn ## _groups), \
}
+#define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
+ { \
+ .name = n, \
+ .first = f, \
+ .last = l, \
+ .regs = { \
+ [REG_PULLEN] = { per, peb }, \
+ [REG_PULL] = { pr, pb }, \
+ [REG_DIR] = { dr, db }, \
+ [REG_OUT] = { or, ob }, \
+ [REG_IN] = { ir, ib }, \
+ }, \
+ }
+
#define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x)
extern const struct pinctrl_ops meson_pinctrl_ops;
diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c
index 902de2b..b1b0289 100644
--- a/drivers/ram/stm32_sdram.c
+++ b/drivers/ram/stm32_sdram.c
@@ -10,11 +10,99 @@
#include <dm.h>
#include <ram.h>
#include <asm/io.h>
-#include <asm/arch/fmc.h>
-#include <asm/arch/stm32.h>
DECLARE_GLOBAL_DATA_PTR;
+struct stm32_fmc_regs {
+ /* 0x0 */
+ u32 bcr1; /* NOR/PSRAM Chip select control register 1 */
+ u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */
+ u32 bcr2; /* NOR/PSRAM Chip select Control register 2 */
+ u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */
+ u32 bcr3; /* NOR/PSRAMChip select Control register 3 */
+ u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */
+ u32 bcr4; /* NOR/PSRAM Chip select Control register 4 */
+ u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */
+ u32 reserved1[24];
+
+ /* 0x80 */
+ u32 pcr; /* NAND Flash control register */
+ u32 sr; /* FIFO status and interrupt register */
+ u32 pmem; /* Common memory space timing register */
+ u32 patt; /* Attribute memory space timing registers */
+ u32 reserved2[1];
+ u32 eccr; /* ECC result registers */
+ u32 reserved3[27];
+
+ /* 0x104 */
+ u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */
+ u32 reserved4[1];
+ u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */
+ u32 reserved5[1];
+ u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */
+ u32 reserved6[1];
+ u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */
+ u32 reserved7[8];
+
+ /* 0x140 */
+ u32 sdcr1; /* SDRAM Control register 1 */
+ u32 sdcr2; /* SDRAM Control register 2 */
+ u32 sdtr1; /* SDRAM Timing register 1 */
+ u32 sdtr2; /* SDRAM Timing register 2 */
+ u32 sdcmr; /* SDRAM Mode register */
+ u32 sdrtr; /* SDRAM Refresh timing register */
+ u32 sdsr; /* SDRAM Status register */
+};
+
+/*
+ * NOR/PSRAM Control register BCR1
+ * FMC controller Enable, only availabe for H7
+ */
+#define FMC_BCR1_FMCEN BIT(31)
+
+/* Control register SDCR */
+#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
+#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
+#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
+#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
+#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
+#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
+#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
+#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
+#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
+
+/* Timings register SDTR */
+#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
+#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
+#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
+#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
+#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
+#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
+#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
+
+#define FMC_SDCMR_NRFS_SHIFT 5
+
+#define FMC_SDCMR_MODE_NORMAL 0
+#define FMC_SDCMR_MODE_START_CLOCK 1
+#define FMC_SDCMR_MODE_PRECHARGE 2
+#define FMC_SDCMR_MODE_AUTOREFRESH 3
+#define FMC_SDCMR_MODE_WRITE_MODE 4
+#define FMC_SDCMR_MODE_SELFREFRESH 5
+#define FMC_SDCMR_MODE_POWERDOWN 6
+
+#define FMC_SDCMR_BANK_1 BIT(4)
+#define FMC_SDCMR_BANK_2 BIT(3)
+
+#define FMC_SDCMR_MODE_REGISTER_SHIFT 9
+
+#define FMC_SDSR_BUSY BIT(5)
+
+#define FMC_BUSY_WAIT(regs) do { \
+ __asm__ __volatile__ ("dsb" : : : "memory"); \
+ while (regs->sdsr & FMC_SDSR_BUSY) \
+ ; \
+ } while (0)
+
struct stm32_sdram_control {
u8 no_columns;
u8 no_rows;
@@ -35,11 +123,29 @@
u8 twr;
u8 trcd;
};
+enum stm32_fmc_bank {
+ SDRAM_BANK1,
+ SDRAM_BANK2,
+ MAX_SDRAM_BANK,
+};
+
+enum stm32_fmc_family {
+ STM32F7_FMC,
+ STM32H7_FMC,
+};
+
+struct bank_params {
+ struct stm32_sdram_control *sdram_control;
+ struct stm32_sdram_timing *sdram_timing;
+ u32 sdram_ref_count;
+ enum stm32_fmc_bank target_bank;
+};
+
struct stm32_sdram_params {
+ struct stm32_fmc_regs *base;
u8 no_sdram_banks;
- struct stm32_sdram_control sdram_control;
- struct stm32_sdram_timing sdram_timing;
- u32 sdram_ref_count;
+ struct bank_params bank_params[MAX_SDRAM_BANK];
+ enum stm32_fmc_family family;
};
#define SDRAM_MODE_BL_SHIFT 0
@@ -49,90 +155,179 @@
int stm32_sdram_init(struct udevice *dev)
{
struct stm32_sdram_params *params = dev_get_platdata(dev);
+ struct stm32_sdram_control *control;
+ struct stm32_sdram_timing *timing;
+ struct stm32_fmc_regs *regs = params->base;
+ enum stm32_fmc_bank target_bank;
+ u32 ctb; /* SDCMR register: Command Target Bank */
+ u32 ref_count;
+ u8 i;
- writel(params->sdram_control.sdclk << FMC_SDCR_SDCLK_SHIFT
- | params->sdram_control.cas_latency << FMC_SDCR_CAS_SHIFT
- | params->sdram_control.no_banks << FMC_SDCR_NB_SHIFT
- | params->sdram_control.memory_width << FMC_SDCR_MWID_SHIFT
- | params->sdram_control.no_rows << FMC_SDCR_NR_SHIFT
- | params->sdram_control.no_columns << FMC_SDCR_NC_SHIFT
- | params->sdram_control.rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
- | params->sdram_control.rd_burst << FMC_SDCR_RBURST_SHIFT,
- &STM32_SDRAM_FMC->sdcr1);
+ /* disable the FMC controller */
+ if (params->family == STM32H7_FMC)
+ clrbits_le32(®s->bcr1, FMC_BCR1_FMCEN);
- writel(params->sdram_timing.trcd << FMC_SDTR_TRCD_SHIFT
- | params->sdram_timing.trp << FMC_SDTR_TRP_SHIFT
- | params->sdram_timing.twr << FMC_SDTR_TWR_SHIFT
- | params->sdram_timing.trc << FMC_SDTR_TRC_SHIFT
- | params->sdram_timing.tras << FMC_SDTR_TRAS_SHIFT
- | params->sdram_timing.txsr << FMC_SDTR_TXSR_SHIFT
- | params->sdram_timing.tmrd << FMC_SDTR_TMRD_SHIFT,
- &STM32_SDRAM_FMC->sdtr1);
+ for (i = 0; i < params->no_sdram_banks; i++) {
+ control = params->bank_params[i].sdram_control;
+ timing = params->bank_params[i].sdram_timing;
+ target_bank = params->bank_params[i].target_bank;
+ ref_count = params->bank_params[i].sdram_ref_count;
- writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK,
- &STM32_SDRAM_FMC->sdcmr);
- udelay(200); /* 200 us delay, page 10, "Power-Up" */
- FMC_BUSY_WAIT();
+ writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT
+ | control->cas_latency << FMC_SDCR_CAS_SHIFT
+ | control->no_banks << FMC_SDCR_NB_SHIFT
+ | control->memory_width << FMC_SDCR_MWID_SHIFT
+ | control->no_rows << FMC_SDCR_NR_SHIFT
+ | control->no_columns << FMC_SDCR_NC_SHIFT
+ | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
+ | control->rd_burst << FMC_SDCR_RBURST_SHIFT,
+ ®s->sdcr1);
- writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE,
- &STM32_SDRAM_FMC->sdcmr);
- udelay(100);
- FMC_BUSY_WAIT();
+ if (target_bank == SDRAM_BANK2)
+ writel(control->cas_latency << FMC_SDCR_CAS_SHIFT
+ | control->no_banks << FMC_SDCR_NB_SHIFT
+ | control->memory_width << FMC_SDCR_MWID_SHIFT
+ | control->no_rows << FMC_SDCR_NR_SHIFT
+ | control->no_columns << FMC_SDCR_NC_SHIFT,
+ ®s->sdcr2);
- writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH
- | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
- udelay(100);
- FMC_BUSY_WAIT();
+ writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
+ | timing->trp << FMC_SDTR_TRP_SHIFT
+ | timing->twr << FMC_SDTR_TWR_SHIFT
+ | timing->trc << FMC_SDTR_TRC_SHIFT
+ | timing->tras << FMC_SDTR_TRAS_SHIFT
+ | timing->txsr << FMC_SDTR_TXSR_SHIFT
+ | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
+ ®s->sdtr1);
- writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
- | params->sdram_control.cas_latency << SDRAM_MODE_CAS_SHIFT)
- << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
- &STM32_SDRAM_FMC->sdcmr);
- udelay(100);
- FMC_BUSY_WAIT();
+ if (target_bank == SDRAM_BANK2)
+ writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
+ | timing->trp << FMC_SDTR_TRP_SHIFT
+ | timing->twr << FMC_SDTR_TWR_SHIFT
+ | timing->trc << FMC_SDTR_TRC_SHIFT
+ | timing->tras << FMC_SDTR_TRAS_SHIFT
+ | timing->txsr << FMC_SDTR_TXSR_SHIFT
+ | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
+ ®s->sdtr2);
- writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL,
- &STM32_SDRAM_FMC->sdcmr);
- FMC_BUSY_WAIT();
+ if (target_bank == SDRAM_BANK1)
+ ctb = FMC_SDCMR_BANK_1;
+ else
+ ctb = FMC_SDCMR_BANK_2;
- /* Refresh timer */
- writel((params->sdram_ref_count) << 1, &STM32_SDRAM_FMC->sdrtr);
+ writel(ctb | FMC_SDCMR_MODE_START_CLOCK, ®s->sdcmr);
+ udelay(200); /* 200 us delay, page 10, "Power-Up" */
+ FMC_BUSY_WAIT(regs);
+
+ writel(ctb | FMC_SDCMR_MODE_PRECHARGE, ®s->sdcmr);
+ udelay(100);
+ FMC_BUSY_WAIT(regs);
+
+ writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT),
+ ®s->sdcmr);
+ udelay(100);
+ FMC_BUSY_WAIT(regs);
+
+ writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
+ | control->cas_latency << SDRAM_MODE_CAS_SHIFT)
+ << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
+ ®s->sdcmr);
+ udelay(100);
+ FMC_BUSY_WAIT(regs);
+
+ writel(ctb | FMC_SDCMR_MODE_NORMAL, ®s->sdcmr);
+ FMC_BUSY_WAIT(regs);
+
+ /* Refresh timer */
+ writel(ref_count << 1, ®s->sdrtr);
+ }
+
+ /* enable the FMC controller */
+ if (params->family == STM32H7_FMC)
+ setbits_le32(®s->bcr1, FMC_BCR1_FMCEN);
return 0;
}
static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
{
- int ret;
- int node = dev_of_offset(dev);
- const void *blob = gd->fdt_blob;
struct stm32_sdram_params *params = dev_get_platdata(dev);
+ struct bank_params *bank_params;
+ ofnode bank_node;
+ char *bank_name;
+ u8 bank = 0;
- params->no_sdram_banks = fdtdec_get_uint(blob, node, "mr-nbanks", 1);
- debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
+ dev_for_each_subnode(bank_node, dev) {
+ /* extract the bank index from DT */
+ bank_name = (char *)ofnode_get_name(bank_node);
+ strsep(&bank_name, "@");
+ if (!bank_name) {
+ error("missing sdram bank index");
+ return -EINVAL;
+ }
+
+ bank_params = ¶ms->bank_params[bank];
+ strict_strtoul(bank_name, 10,
+ (long unsigned int *)&bank_params->target_bank);
+
+ if (bank_params->target_bank >= MAX_SDRAM_BANK) {
+ error("Found bank %d , but only bank 0 and 1 are supported",
+ bank_params->target_bank);
+ return -EINVAL;
+ }
+
+ debug("Find bank %s %u\n", bank_name, bank_params->target_bank);
- fdt_for_each_subnode(node, blob, node) {
- ret = fdtdec_get_byte_array(blob, node, "st,sdram-control",
- (u8 *)¶ms->sdram_control,
- sizeof(params->sdram_control));
- if (ret)
- return ret;
- ret = fdtdec_get_byte_array(blob, node, "st,sdram-timing",
- (u8 *)¶ms->sdram_timing,
- sizeof(params->sdram_timing));
- if (ret)
- return ret;
+ params->bank_params[bank].sdram_control =
+ (struct stm32_sdram_control *)
+ ofnode_read_u8_array_ptr(bank_node,
+ "st,sdram-control",
+ sizeof(struct stm32_sdram_control));
- params->sdram_ref_count = fdtdec_get_int(blob, node,
+ if (!params->bank_params[bank].sdram_control) {
+ error("st,sdram-control not found for %s",
+ ofnode_get_name(bank_node));
+ return -EINVAL;
+ }
+
+
+ params->bank_params[bank].sdram_timing =
+ (struct stm32_sdram_timing *)
+ ofnode_read_u8_array_ptr(bank_node,
+ "st,sdram-timing",
+ sizeof(struct stm32_sdram_timing));
+
+ if (!params->bank_params[bank].sdram_timing) {
+ error("st,sdram-timing not found for %s",
+ ofnode_get_name(bank_node));
+ return -EINVAL;
+ }
+
+
+ bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node,
"st,sdram-refcount", 8196);
+ bank++;
}
+ params->no_sdram_banks = bank;
+ debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
+
return 0;
}
static int stm32_fmc_probe(struct udevice *dev)
{
+ struct stm32_sdram_params *params = dev_get_platdata(dev);
int ret;
+ fdt_addr_t addr;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ params->base = (struct stm32_fmc_regs *)addr;
+ params->family = dev_get_driver_data(dev);
+
#ifdef CONFIG_CLK
struct clk clk;
@@ -164,7 +359,8 @@
};
static const struct udevice_id stm32_fmc_ids[] = {
- { .compatible = "st,stm32-fmc" },
+ { .compatible = "st,stm32-fmc", .data = STM32F7_FMC },
+ { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC },
{ }
};
diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c
index 61e8167..bf118a7 100644
--- a/drivers/serial/serial_stm32x7.c
+++ b/drivers/serial/serial_stm32x7.c
@@ -11,7 +11,6 @@
#include <asm/io.h>
#include <serial.h>
#include <asm/arch/stm32.h>
-#include <dm/platform_data/serial_stm32x7.h>
#include "serial_stm32x7.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -20,16 +19,9 @@
{
struct stm32x7_serial_platdata *plat = dev->platdata;
struct stm32_usart *const usart = plat->base;
- u32 clock, int_div, mantissa, fraction, oversampling;
+ u32 int_div, mantissa, fraction, oversampling;
- if (((u32)usart & STM32_BUS_MASK) == APB1_PERIPH_BASE)
- clock = clock_get(CLOCK_APB1);
- else if (((u32)usart & STM32_BUS_MASK) == APB2_PERIPH_BASE)
- clock = clock_get(CLOCK_APB2);
- else
- return -EINVAL;
-
- int_div = DIV_ROUND_CLOSEST(clock, baudrate);
+ int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
if (int_div < 16) {
oversampling = 8;
@@ -102,6 +94,12 @@
}
#endif
+ plat->clock_rate = clk_get_rate(&clk);
+ if (plat->clock_rate < 0) {
+ clk_disable(&clk);
+ return plat->clock_rate;
+ };
+
/* Disable usart-> disable overrun-> enable usart */
clrbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
setbits_le32(&usart->cr3, USART_CR3_OVRDIS);
diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h
index facfdba..9fe37af 100644
--- a/drivers/serial/serial_stm32x7.h
+++ b/drivers/serial/serial_stm32x7.h
@@ -22,6 +22,11 @@
u32 tx_dr;
};
+/* Information about a serial port */
+struct stm32x7_serial_platdata {
+ struct stm32_usart *base; /* address of registers in physical memory */
+ unsigned long int clock_rate;
+};
#define USART_CR1_OVER8 (1 << 15)
#define USART_CR1_TE (1 << 3)
diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index f0434a4..ef2b64e 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -165,6 +165,7 @@
struct stm32_qspi_priv {
struct stm32_qspi_regs *regs;
+ ulong clock_rate;
u32 max_hz;
u32 mode;
@@ -471,6 +472,13 @@
dev_err(bus, "failed to enable clock\n");
return ret;
}
+
+ priv->clock_rate = clk_get_rate(&clk);
+ if (priv->clock_rate < 0) {
+ clk_disable(&clk);
+ return priv->clock_rate;
+ }
+
#endif
setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
@@ -536,7 +544,7 @@
if (speed > plat->max_hz)
speed = plat->max_hz;
- u32 qspi_clk = clock_get(CLOCK_AHB);
+ u32 qspi_clk = priv->clock_rate;
u32 prescaler = 255;
if (speed > 0) {
prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
index 7e45549..a438a1a 100644
--- a/include/configs/k2e_evm.h
+++ b/include/configs/k2e_evm.h
@@ -15,9 +15,18 @@
/* Platform type */
#define CONFIG_SOC_K2E
+#ifdef CONFIG_TI_SECURE_DEVICE
+#define DEFAULT_SEC_BOOT_ENV \
+ DEFAULT_FIT_TI_ARGS \
+ "findfdt=setenv fdtfile ${name_fdt}\0"
+#else
+#define DEFAULT_SEC_BOOT_ENV
+#endif
+
/* U-Boot general configuration */
#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
DEFAULT_FW_INITRAMFS_BOOT_ENV \
+ DEFAULT_SEC_BOOT_ENV \
"boot=ubi\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index b0b4206..1117e5e 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -23,6 +23,7 @@
DEFAULT_MMC_TI_ARGS \
DEFAULT_PMMC_BOOT_ENV \
DEFAULT_FW_INITRAMFS_BOOT_ENV \
+ DEFAULT_FIT_TI_ARGS \
"boot=mmc\0" \
"console=ttyS0,115200n8\0" \
"bootpart=0:2\0" \
@@ -51,11 +52,27 @@
"get_mon_mmc=load mmc ${bootpart} ${addr_mon} ${bootdir}/${name_mon}\0"\
"name_fs=arago-base-tisdk-image-k2g-evm.cpio\0"
+#ifndef CONFIG_TI_SECURE_DEVICE
#define CONFIG_BOOTCOMMAND \
+ "run findfdt; " \
+ "run envboot; " \
+ "run init_${boot}; " \
+ "run get_mon_${boot} run_mon; " \
+ "run set_name_pmmc get_pmmc_${boot} run_pmmc; " \
+ "run get_kern_${boot}; " \
+ "run init_fw_rd_${boot}; " \
+ "run get_fdt_${boot}; " \
+ "run run_kern"
+#else
+#define CONFIG_BOOTCOMMAND \
+ "run findfdt; " \
"run envboot; " \
- "run set_name_pmmc init_${boot} init_fw_rd_${boot} " \
- "get_pmmc_${boot} run_pmmc get_mon_${boot} run_mon " \
- "findfdt get_fdt_${boot} get_kern_${boot} run_kern"
+ "run run_mon_hs; " \
+ "run init_${boot}; " \
+ "run set_name_pmmc get_pmmc_${boot} run_pmmc; " \
+ "run get_fit_${boot}; " \
+ "bootm ${fit_loadaddr}#${name_fdt}"
+#endif
/* SPL SPI Loader Configuration */
#define CONFIG_SPL_TEXT_BASE 0x0c080000
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index 78b901f..dc0ac7d 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -15,9 +15,18 @@
/* Platform type */
#define CONFIG_SOC_K2HK
+#ifdef CONFIG_TI_SECURE_DEVICE
+#define DEFAULT_SEC_BOOT_ENV \
+ DEFAULT_FIT_TI_ARGS \
+ "findfdt=setenv fdtfile ${name_fdt}\0"
+#else
+#define DEFAULT_SEC_BOOT_ENV
+#endif
+
/* U-Boot general configuration */
#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
DEFAULT_FW_INITRAMFS_BOOT_ENV \
+ DEFAULT_SEC_BOOT_ENV \
"boot=ubi\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index a94748c..ccd7cd7 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -53,7 +53,7 @@
#define DEFAULT_FIT_TI_ARGS \
"boot_fit=0\0" \
- "fit_loadaddr=0x88000000\0" \
+ "fit_loadaddr=0x87000000\0" \
"fit_bootfile=fitImage\0" \
"update_to_fit=setenv loadaddr ${fit_loadaddr}; setenv bootfile ${fit_bootfile}\0" \
"loadfit=run args_mmc; bootm ${loadaddr}#${fdtfile};\0" \
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 3fadef7..c6122a0 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -249,7 +249,11 @@
"addr_secdb_key=0xc000000\0" \
"name_kern=zImage\0" \
"addr_mon=0x87000000\0" \
+ "addr_non_sec_mon=0x0c087fc0\0" \
+ "addr_load_sec_bm=0x0c08c000\0" \
"run_mon=mon_install ${addr_mon}\0" \
+ "run_mon_hs=mon_install ${addr_non_sec_mon} " \
+ "${addr_load_sec_bm}\0" \
"run_kern=bootz ${loadaddr} ${rd_spec} ${fdtaddr}\0" \
"init_net=run args_all args_net\0" \
"init_nfs=setenv autoload no; dhcp; run args_all args_net\0" \
@@ -263,7 +267,13 @@
"get_kern_ubi=ubifsload ${loadaddr} ${bootdir}/${name_kern}\0" \
"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
"get_mon_nfs=nfs ${addr_mon} ${nfs_root}/boot/${name_mon}\0" \
- "get_mon_ubi=ubifsload ${addr_mon} ${bootdir}/${name_mon}\0" \
+ "get_mon_ubi=ubifsload ${addr_mon} ${bootdir}/${name_mon}\0" \
+ "get_fit_net=dhcp ${fit_loadaddr} ${tftp_root}" \
+ "/${fit_bootfile}\0" \
+ "get_fit_nfs=nfs ${fit_loadaddr} ${nfs_root}/boot/${fit_bootfile}\0"\
+ "get_fit_ubi=ubifsload ${fit_loadaddr} ${bootdir}/${fit_bootfile}\0"\
+ "get_fit_mmc=load mmc ${bootpart} ${fit_loadaddr} " \
+ "${bootdir}/${fit_bootfile}\0" \
"get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \
"get_uboot_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_uboot}\0" \
"burn_uboot_spi=sf probe; sf erase 0 0x80000; " \
@@ -279,6 +289,8 @@
"get_fdt_ramfs=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \
"get_kern_ramfs=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \
"get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
+ "get_fit_ramfs=dhcp ${fit_loadaddr} ${tftp_root}" \
+ "/${fit_bootfile}\0" \
"get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs}\0" \
"get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \
"get_ubi_nfs=nfs ${addr_ubi} ${nfs_root}/boot/${name_ubi}\0" \
@@ -293,9 +305,21 @@
"1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"
#ifndef CONFIG_BOOTCOMMAND
+#ifndef CONFIG_TI_SECURE_DEVICE
+#define CONFIG_BOOTCOMMAND \
+ "run init_${boot}; " \
+ "run get_mon_${boot} run_mon; " \
+ "run get_kern_${boot}; " \
+ "run init_fw_rd_${boot}; " \
+ "run get_fdt_${boot}; " \
+ "run run_kern"
+#else
#define CONFIG_BOOTCOMMAND \
- "run init_${boot} get_mon_${boot} run_mon init_fw_rd_${boot} " \
- "get_fdt_${boot} get_kern_${boot} run_kern"
+ "run run_mon_hs; " \
+ "run init_${boot}; " \
+ "run get_fit_${boot}; " \
+ "bootm ${fit_loadaddr}#${name_fdt}"
+#endif
#endif
#define CONFIG_BOOTARGS \
diff --git a/include/dm/platform_data/serial_stm32x7.h b/include/dm/platform_data/serial_stm32x7.h
deleted file mode 100644
index 328a8a3..0000000
--- a/include/dm/platform_data/serial_stm32x7.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * (C) Copyright 2016
- * Vikas Manocha, <vikas.manocha@st.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __SERIAL_STM32x7_H
-#define __SERIAL_STM32x7_H
-
-/* Information about a serial port */
-struct stm32x7_serial_platdata {
- struct stm32_usart *base; /* address of registers in physical memory */
- unsigned int clock;
-};
-
-#endif /* __SERIAL_STM32x7_H */
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 692846c..e3e9f79 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -5,30 +5,50 @@
#ifndef __GXBB_CLKC_H
#define __GXBB_CLKC_H
-#define CLKID_CPUCLK 1
#define CLKID_HDMI_PLL 2
#define CLKID_FCLK_DIV2 4
#define CLKID_FCLK_DIV3 5
#define CLKID_FCLK_DIV4 6
+#define CLKID_GP0_PLL 9
#define CLKID_CLK81 12
#define CLKID_MPLL2 15
-#define CLKID_SPI 34
+#define CLKID_SPICC 21
#define CLKID_I2C 22
#define CLKID_SAR_ADC 23
+#define CLKID_RNG0 25
+#define CLKID_UART0 26
+#define CLKID_SPI 34
#define CLKID_ETH 36
+#define CLKID_AIU_GLUE 38
+#define CLKID_IEC958 39
+#define CLKID_I2S_OUT 40
+#define CLKID_MIXER_IFACE 44
+#define CLKID_AIU 47
+#define CLKID_UART1 48
#define CLKID_USB0 50
#define CLKID_USB1 51
#define CLKID_USB 55
#define CLKID_HDMI_PCLK 63
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_UART2 68
#define CLKID_SANA 69
#define CLKID_GCLK_VENCI_INT0 77
+#define CLKID_AOCLK_GATE 80
+#define CLKID_IEC958_GATE 81
#define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95
#define CLKID_SD_EMMC_C 96
#define CLKID_SAR_ADC_CLK 97
#define CLKID_SAR_ADC_SEL 98
+#define CLKID_MALI_0_SEL 100
+#define CLKID_MALI_0 102
+#define CLKID_MALI_1_SEL 103
+#define CLKID_MALI_1 105
+#define CLKID_MALI 106
+#define CLKID_CTS_AMCLK 107
+#define CLKID_CTS_MCLK_I958 110
+#define CLKID_CTS_I958 113
#endif /* __GXBB_CLKC_H */
diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
new file mode 100644
index 0000000..49bb3c2
--- /dev/null
+++ b/include/dt-bindings/clock/stm32fx-clock.h
@@ -0,0 +1,59 @@
+/*
+ * stm32fx-clock.h
+ *
+ * Copyright (C) 2016 STMicroelectronics
+ * Author: Gabriel Fernandez for STMicroelectronics.
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+/*
+ * List of clocks wich are not derived from system clock (SYSCLOCK)
+ *
+ * The index of these clocks is the secondary index of DT bindings
+ * (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt)
+ *
+ * e.g:
+ <assigned-clocks = <&rcc 1 CLK_LSE>;
+*/
+
+#ifndef _DT_BINDINGS_CLK_STMFX_H
+#define _DT_BINDINGS_CLK_STMFX_H
+
+#define SYSTICK 0
+#define FCLK 1
+#define CLK_LSI 2
+#define CLK_LSE 3
+#define CLK_HSE_RTC 4
+#define CLK_RTC 5
+#define PLL_VCO_I2S 6
+#define PLL_VCO_SAI 7
+#define CLK_LCD 8
+#define CLK_I2S 9
+#define CLK_SAI1 10
+#define CLK_SAI2 11
+#define CLK_I2SQ_PDIV 12
+#define CLK_SAIQ_PDIV 13
+
+#define END_PRIMARY_CLK 14
+
+#define CLK_HSI 14
+#define CLK_SYSCLK 15
+#define CLK_HDMI_CEC 16
+#define CLK_SPDIF 17
+#define CLK_USART1 18
+#define CLK_USART2 19
+#define CLK_USART3 20
+#define CLK_UART4 21
+#define CLK_UART5 22
+#define CLK_USART6 23
+#define CLK_UART7 24
+#define CLK_UART8 25
+#define CLK_I2C1 26
+#define CLK_I2C2 27
+#define CLK_I2C3 28
+#define CLK_I2C4 29
+#define CLK_LPTIMER 30
+
+#define END_PRIMARY_CLK_F7 31
+
+#endif
diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h
new file mode 100644
index 0000000..e36cc69
--- /dev/null
+++ b/include/dt-bindings/mfd/stm32f7-rcc.h
@@ -0,0 +1,112 @@
+/*
+ * This header provides constants for the STM32F7 RCC IP
+ */
+
+#ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H
+#define _DT_BINDINGS_MFD_STM32F7_RCC_H
+
+/* AHB1 */
+#define STM32F7_RCC_AHB1_GPIOA 0
+#define STM32F7_RCC_AHB1_GPIOB 1
+#define STM32F7_RCC_AHB1_GPIOC 2
+#define STM32F7_RCC_AHB1_GPIOD 3
+#define STM32F7_RCC_AHB1_GPIOE 4
+#define STM32F7_RCC_AHB1_GPIOF 5
+#define STM32F7_RCC_AHB1_GPIOG 6
+#define STM32F7_RCC_AHB1_GPIOH 7
+#define STM32F7_RCC_AHB1_GPIOI 8
+#define STM32F7_RCC_AHB1_GPIOJ 9
+#define STM32F7_RCC_AHB1_GPIOK 10
+#define STM32F7_RCC_AHB1_CRC 12
+#define STM32F7_RCC_AHB1_BKPSRAM 18
+#define STM32F7_RCC_AHB1_DTCMRAM 20
+#define STM32F7_RCC_AHB1_DMA1 21
+#define STM32F7_RCC_AHB1_DMA2 22
+#define STM32F7_RCC_AHB1_DMA2D 23
+#define STM32F7_RCC_AHB1_ETHMAC 25
+#define STM32F7_RCC_AHB1_ETHMACTX 26
+#define STM32F7_RCC_AHB1_ETHMACRX 27
+#define STM32FF_RCC_AHB1_ETHMACPTP 28
+#define STM32F7_RCC_AHB1_OTGHS 29
+#define STM32F7_RCC_AHB1_OTGHSULPI 30
+
+#define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
+#define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
+
+
+/* AHB2 */
+#define STM32F7_RCC_AHB2_DCMI 0
+#define STM32F7_RCC_AHB2_CRYP 4
+#define STM32F7_RCC_AHB2_HASH 5
+#define STM32F7_RCC_AHB2_RNG 6
+#define STM32F7_RCC_AHB2_OTGFS 7
+
+#define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8))
+#define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20)
+
+/* AHB3 */
+#define STM32F7_RCC_AHB3_FMC 0
+#define STM32F7_RCC_AHB3_QSPI 1
+
+#define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8))
+#define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40)
+
+/* APB1 */
+#define STM32F7_RCC_APB1_TIM2 0
+#define STM32F7_RCC_APB1_TIM3 1
+#define STM32F7_RCC_APB1_TIM4 2
+#define STM32F7_RCC_APB1_TIM5 3
+#define STM32F7_RCC_APB1_TIM6 4
+#define STM32F7_RCC_APB1_TIM7 5
+#define STM32F7_RCC_APB1_TIM12 6
+#define STM32F7_RCC_APB1_TIM13 7
+#define STM32F7_RCC_APB1_TIM14 8
+#define STM32F7_RCC_APB1_LPTIM1 9
+#define STM32F7_RCC_APB1_WWDG 11
+#define STM32F7_RCC_APB1_SPI2 14
+#define STM32F7_RCC_APB1_SPI3 15
+#define STM32F7_RCC_APB1_SPDIFRX 16
+#define STM32F7_RCC_APB1_UART2 17
+#define STM32F7_RCC_APB1_UART3 18
+#define STM32F7_RCC_APB1_UART4 19
+#define STM32F7_RCC_APB1_UART5 20
+#define STM32F7_RCC_APB1_I2C1 21
+#define STM32F7_RCC_APB1_I2C2 22
+#define STM32F7_RCC_APB1_I2C3 23
+#define STM32F7_RCC_APB1_I2C4 24
+#define STM32F7_RCC_APB1_CAN1 25
+#define STM32F7_RCC_APB1_CAN2 26
+#define STM32F7_RCC_APB1_CEC 27
+#define STM32F7_RCC_APB1_PWR 28
+#define STM32F7_RCC_APB1_DAC 29
+#define STM32F7_RCC_APB1_UART7 30
+#define STM32F7_RCC_APB1_UART8 31
+
+#define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8))
+#define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80)
+
+/* APB2 */
+#define STM32F7_RCC_APB2_TIM1 0
+#define STM32F7_RCC_APB2_TIM8 1
+#define STM32F7_RCC_APB2_USART1 4
+#define STM32F7_RCC_APB2_USART6 5
+#define STM32F7_RCC_APB2_ADC1 8
+#define STM32F7_RCC_APB2_ADC2 9
+#define STM32F7_RCC_APB2_ADC3 10
+#define STM32F7_RCC_APB2_SDMMC1 11
+#define STM32F7_RCC_APB2_SPI1 12
+#define STM32F7_RCC_APB2_SPI4 13
+#define STM32F7_RCC_APB2_SYSCFG 14
+#define STM32F7_RCC_APB2_TIM9 16
+#define STM32F7_RCC_APB2_TIM10 17
+#define STM32F7_RCC_APB2_TIM11 18
+#define STM32F7_RCC_APB2_SPI5 20
+#define STM32F7_RCC_APB2_SPI6 21
+#define STM32F7_RCC_APB2_SAI1 22
+#define STM32F7_RCC_APB2_SAI2 23
+#define STM32F7_RCC_APB2_LTDC 26
+
+#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8))
+#define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0)
+
+#endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */
diff --git a/tools/.gitignore b/tools/.gitignore
index 6ec71f5..ac0c979 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -11,6 +11,7 @@
/img2srec
/kwboot
/dumpimage
+/mips-relocs
/mkenvimage
/mkimage
/mkexynosspl
diff --git a/tools/Makefile b/tools/Makefile
index 62a7921..0743677 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -211,6 +211,8 @@
hostprogs-y += fdtgrep
fdtgrep-objs += $(LIBFDT_OBJS) fdtgrep.o
+hostprogs-$(CONFIG_MIPS) += mips-relocs
+
# We build some files with extra pedantic flags to try to minimize things
# that won't build on some weird host compiler -- though there are lots of
# exceptions for files that aren't complaint.
diff --git a/tools/mips-relocs.c b/tools/mips-relocs.c
new file mode 100644
index 0000000..8be69d3
--- /dev/null
+++ b/tools/mips-relocs.c
@@ -0,0 +1,432 @@
+/*
+ * MIPS Relocation Data Generator
+ *
+ * Copyright (c) 2017 Imagination Technologies Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <assert.h>
+#include <elf.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <limits.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/mman.h>
+#include <sys/stat.h>
+#include <unistd.h>
+
+#include <asm/relocs.h>
+
+#define hdr_field(pfx, idx, field) ({ \
+ uint64_t _val; \
+ unsigned int _size; \
+ \
+ if (is_64) { \
+ _val = pfx##hdr64[idx].field; \
+ _size = sizeof(pfx##hdr64[0].field); \
+ } else { \
+ _val = pfx##hdr32[idx].field; \
+ _size = sizeof(pfx##hdr32[0].field); \
+ } \
+ \
+ switch (_size) { \
+ case 1: \
+ break; \
+ case 2: \
+ _val = is_be ? be16toh(_val) : le16toh(_val); \
+ break; \
+ case 4: \
+ _val = is_be ? be32toh(_val) : le32toh(_val); \
+ break; \
+ case 8: \
+ _val = is_be ? be64toh(_val) : le64toh(_val); \
+ break; \
+ } \
+ \
+ _val; \
+})
+
+#define set_hdr_field(pfx, idx, field, val) ({ \
+ uint64_t _val; \
+ unsigned int _size; \
+ \
+ if (is_64) \
+ _size = sizeof(pfx##hdr64[0].field); \
+ else \
+ _size = sizeof(pfx##hdr32[0].field); \
+ \
+ switch (_size) { \
+ case 1: \
+ _val = val; \
+ break; \
+ case 2: \
+ _val = is_be ? htobe16(val) : htole16(val); \
+ break; \
+ case 4: \
+ _val = is_be ? htobe32(val) : htole32(val); \
+ break; \
+ case 8: \
+ _val = is_be ? htobe64(val) : htole64(val); \
+ break; \
+ default: \
+ /* We should never reach here */ \
+ _val = 0; \
+ assert(0); \
+ break; \
+ } \
+ \
+ if (is_64) \
+ pfx##hdr64[idx].field = _val; \
+ else \
+ pfx##hdr32[idx].field = _val; \
+})
+
+#define ehdr_field(field) \
+ hdr_field(e, 0, field)
+#define phdr_field(idx, field) \
+ hdr_field(p, idx, field)
+#define shdr_field(idx, field) \
+ hdr_field(s, idx, field)
+
+#define set_phdr_field(idx, field, val) \
+ set_hdr_field(p, idx, field, val)
+#define set_shdr_field(idx, field, val) \
+ set_hdr_field(s, idx, field, val)
+
+#define shstr(idx) (&shstrtab[idx])
+
+bool is_64, is_be;
+uint64_t text_base;
+
+struct mips_reloc {
+ uint8_t type;
+ uint64_t offset;
+} *relocs;
+size_t relocs_sz, relocs_idx;
+
+static int add_reloc(unsigned int type, uint64_t off)
+{
+ struct mips_reloc *new;
+ size_t new_sz;
+
+ switch (type) {
+ case R_MIPS_NONE:
+ case R_MIPS_LO16:
+ case R_MIPS_PC16:
+ case R_MIPS_HIGHER:
+ case R_MIPS_HIGHEST:
+ case R_MIPS_PC21_S2:
+ case R_MIPS_PC26_S2:
+ /* Skip these relocs */
+ return 0;
+
+ default:
+ break;
+ }
+
+ if (relocs_idx == relocs_sz) {
+ new_sz = relocs_sz ? relocs_sz * 2 : 128;
+ new = realloc(relocs, new_sz * sizeof(*relocs));
+ if (!new) {
+ fprintf(stderr, "Out of memory\n");
+ return -ENOMEM;
+ }
+
+ relocs = new;
+ relocs_sz = new_sz;
+ }
+
+ relocs[relocs_idx++] = (struct mips_reloc){
+ .type = type,
+ .offset = off,
+ };
+
+ return 0;
+}
+
+static int parse_mips32_rel(const void *_rel)
+{
+ const Elf32_Rel *rel = _rel;
+ uint32_t off, type;
+
+ off = is_be ? be32toh(rel->r_offset) : le32toh(rel->r_offset);
+ off -= text_base;
+
+ type = is_be ? be32toh(rel->r_info) : le32toh(rel->r_info);
+ type = ELF32_R_TYPE(type);
+
+ return add_reloc(type, off);
+}
+
+static int parse_mips64_rela(const void *_rel)
+{
+ const Elf64_Rela *rel = _rel;
+ uint64_t off, type;
+
+ off = is_be ? be64toh(rel->r_offset) : le64toh(rel->r_offset);
+ off -= text_base;
+
+ type = rel->r_info >> (64 - 8);
+
+ return add_reloc(type, off);
+}
+
+static void output_uint(uint8_t **buf, uint64_t val)
+{
+ uint64_t tmp;
+
+ do {
+ tmp = val & 0x7f;
+ val >>= 7;
+ tmp |= !!val << 7;
+ *(*buf)++ = tmp;
+ } while (val);
+}
+
+static int compare_relocs(const void *a, const void *b)
+{
+ const struct mips_reloc *ra = a, *rb = b;
+
+ return ra->offset - rb->offset;
+}
+
+int main(int argc, char *argv[])
+{
+ unsigned int i, j, i_rel_shdr, sh_type, sh_entsize, sh_entries;
+ size_t rel_size, rel_actual_size, load_sz;
+ const char *shstrtab, *sh_name, *rel_pfx;
+ int (*parse_fn)(const void *rel);
+ uint8_t *buf_start, *buf;
+ const Elf32_Ehdr *ehdr32;
+ const Elf64_Ehdr *ehdr64;
+ uintptr_t sh_offset;
+ Elf32_Phdr *phdr32;
+ Elf64_Phdr *phdr64;
+ Elf32_Shdr *shdr32;
+ Elf64_Shdr *shdr64;
+ struct stat st;
+ int err, fd;
+ void *elf;
+ bool skip;
+
+ fd = open(argv[1], O_RDWR);
+ if (fd == -1) {
+ fprintf(stderr, "Unable to open input file %s\n", argv[1]);
+ err = errno;
+ goto out_ret;
+ }
+
+ err = fstat(fd, &st);
+ if (err) {
+ fprintf(stderr, "Unable to fstat() input file\n");
+ goto out_close_fd;
+ }
+
+ elf = mmap(NULL, st.st_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
+ if (elf == MAP_FAILED) {
+ fprintf(stderr, "Unable to mmap() input file\n");
+ err = errno;
+ goto out_close_fd;
+ }
+
+ ehdr32 = elf;
+ ehdr64 = elf;
+
+ if (memcmp(&ehdr32->e_ident[EI_MAG0], ELFMAG, SELFMAG)) {
+ fprintf(stderr, "Input file is not an ELF\n");
+ err = -EINVAL;
+ goto out_free_relocs;
+ }
+
+ if (ehdr32->e_ident[EI_VERSION] != EV_CURRENT) {
+ fprintf(stderr, "Unrecognised ELF version\n");
+ err = -EINVAL;
+ goto out_free_relocs;
+ }
+
+ switch (ehdr32->e_ident[EI_CLASS]) {
+ case ELFCLASS32:
+ is_64 = false;
+ break;
+ case ELFCLASS64:
+ is_64 = true;
+ break;
+ default:
+ fprintf(stderr, "Unrecognised ELF class\n");
+ err = -EINVAL;
+ goto out_free_relocs;
+ }
+
+ switch (ehdr32->e_ident[EI_DATA]) {
+ case ELFDATA2LSB:
+ is_be = false;
+ break;
+ case ELFDATA2MSB:
+ is_be = true;
+ break;
+ default:
+ fprintf(stderr, "Unrecognised ELF data encoding\n");
+ err = -EINVAL;
+ goto out_free_relocs;
+ }
+
+ if (ehdr_field(e_type) != ET_EXEC) {
+ fprintf(stderr, "Input ELF is not an executable\n");
+ printf("type 0x%lx\n", ehdr_field(e_type));
+ err = -EINVAL;
+ goto out_free_relocs;
+ }
+
+ if (ehdr_field(e_machine) != EM_MIPS) {
+ fprintf(stderr, "Input ELF does not target MIPS\n");
+ err = -EINVAL;
+ goto out_free_relocs;
+ }
+
+ phdr32 = elf + ehdr_field(e_phoff);
+ phdr64 = elf + ehdr_field(e_phoff);
+ shdr32 = elf + ehdr_field(e_shoff);
+ shdr64 = elf + ehdr_field(e_shoff);
+ shstrtab = elf + shdr_field(ehdr_field(e_shstrndx), sh_offset);
+
+ i_rel_shdr = UINT_MAX;
+ for (i = 0; i < ehdr_field(e_shnum); i++) {
+ sh_name = shstr(shdr_field(i, sh_name));
+
+ if (!strcmp(sh_name, ".rel")) {
+ i_rel_shdr = i;
+ continue;
+ }
+
+ if (!strcmp(sh_name, ".text")) {
+ text_base = shdr_field(i, sh_addr);
+ continue;
+ }
+ }
+ if (i_rel_shdr == UINT_MAX) {
+ fprintf(stderr, "Unable to find .rel section\n");
+ err = -EINVAL;
+ goto out_free_relocs;
+ }
+ if (!text_base) {
+ fprintf(stderr, "Unable to find .text base address\n");
+ err = -EINVAL;
+ goto out_free_relocs;
+ }
+
+ rel_pfx = is_64 ? ".rela." : ".rel.";
+
+ for (i = 0; i < ehdr_field(e_shnum); i++) {
+ sh_type = shdr_field(i, sh_type);
+ if ((sh_type != SHT_REL) && (sh_type != SHT_RELA))
+ continue;
+
+ sh_name = shstr(shdr_field(i, sh_name));
+ if (strncmp(sh_name, rel_pfx, strlen(rel_pfx))) {
+ if (strcmp(sh_name, ".rel") && strcmp(sh_name, ".rel.dyn"))
+ fprintf(stderr, "WARNING: Unexpected reloc section name '%s'\n", sh_name);
+ continue;
+ }
+
+ /*
+ * Skip reloc sections which either don't correspond to another
+ * section in the ELF, or whose corresponding section isn't
+ * loaded as part of the U-Boot binary (ie. doesn't have the
+ * alloc flags set).
+ */
+ skip = true;
+ for (j = 0; j < ehdr_field(e_shnum); j++) {
+ if (strcmp(&sh_name[strlen(rel_pfx) - 1], shstr(shdr_field(j, sh_name))))
+ continue;
+
+ skip = !(shdr_field(j, sh_flags) & SHF_ALLOC);
+ break;
+ }
+ if (skip)
+ continue;
+
+ sh_offset = shdr_field(i, sh_offset);
+ sh_entsize = shdr_field(i, sh_entsize);
+ sh_entries = shdr_field(i, sh_size) / sh_entsize;
+
+ if (sh_type == SHT_REL) {
+ if (is_64) {
+ fprintf(stderr, "REL-style reloc in MIPS64 ELF?\n");
+ err = -EINVAL;
+ goto out_free_relocs;
+ } else {
+ parse_fn = parse_mips32_rel;
+ }
+ } else {
+ if (is_64) {
+ parse_fn = parse_mips64_rela;
+ } else {
+ fprintf(stderr, "RELA-style reloc in MIPS32 ELF?\n");
+ err = -EINVAL;
+ goto out_free_relocs;
+ }
+ }
+
+ for (j = 0; j < sh_entries; j++) {
+ err = parse_fn(elf + sh_offset + (j * sh_entsize));
+ if (err)
+ goto out_free_relocs;
+ }
+ }
+
+ /* Sort relocs in ascending order of offset */
+ qsort(relocs, relocs_idx, sizeof(*relocs), compare_relocs);
+
+ /* Make reloc offsets relative to their predecessor */
+ for (i = relocs_idx - 1; i > 0; i--)
+ relocs[i].offset -= relocs[i - 1].offset;
+
+ /* Write the relocations to the .rel section */
+ buf = buf_start = elf + shdr_field(i_rel_shdr, sh_offset);
+ for (i = 0; i < relocs_idx; i++) {
+ output_uint(&buf, relocs[i].type);
+ output_uint(&buf, relocs[i].offset >> 2);
+ }
+
+ /* Write a terminating R_MIPS_NONE (0) */
+ output_uint(&buf, R_MIPS_NONE);
+
+ /* Ensure the relocs didn't overflow the .rel section */
+ rel_size = shdr_field(i_rel_shdr, sh_size);
+ rel_actual_size = buf - buf_start;
+ if (rel_actual_size > rel_size) {
+ fprintf(stderr, "Relocs overflowed .rel section\n");
+ return -ENOMEM;
+ }
+
+ /* Update the .rel section's size */
+ set_shdr_field(i_rel_shdr, sh_size, rel_actual_size);
+
+ /* Shrink the PT_LOAD program header filesz (ie. shrink u-boot.bin) */
+ for (i = 0; i < ehdr_field(e_phnum); i++) {
+ if (phdr_field(i, p_type) != PT_LOAD)
+ continue;
+
+ load_sz = phdr_field(i, p_filesz);
+ load_sz -= rel_size - rel_actual_size;
+ set_phdr_field(i, p_filesz, load_sz);
+ break;
+ }
+
+ /* Make sure data is written back to the file */
+ err = msync(elf, st.st_size, MS_SYNC);
+ if (err) {
+ fprintf(stderr, "Failed to msync: %d\n", errno);
+ goto out_free_relocs;
+ }
+
+out_free_relocs:
+ free(relocs);
+ munmap(elf, st.st_size);
+out_close_fd:
+ close(fd);
+out_ret:
+ return err;
+}