arm: mx6: ddr: add pd_fast_exit flag to system information
DDR3 has a special Precharge power-down mode: fast-exit vs slow-exit.
In slow-exit mode the DLL is off but in some quiescent state that makes it easy
to turn on again in tXPDLL cycles (about 10tCK) vs the full tDLLK (512tCK).
In fast-exist mode the DLL is maintained such that it is ready again in about
3tCK.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index fef2231..653d58e 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -514,17 +514,21 @@
/* MR2 */
val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
((tcwl - 3) & 3) << 3;
+ debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));
mmdc0->mdscr = MR(val, 2, 3, cs);
/* MR3 */
+ debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));
mmdc0->mdscr = MR(0, 3, 3, cs);
/* MR1 */
val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
+ debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));
mmdc0->mdscr = MR(val, 1, 3, cs);
/* MR0 */
val = ((tcl - 1) << 4) | /* CAS */
(1 << 8) | /* DLL Reset */
((twr - 3) << 9); /* Write Recovery */
+ debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
mmdc0->mdscr = MR(val, 0, 3, cs);
/* ZQ calibration */
val = (1 << 10);
@@ -535,10 +539,11 @@
mmdc0->mdpdc = (tcke & 0x7) << 16 |
5 << 12 | /* PWDT_1: 256 cycles */
5 << 8 | /* PWDT_0: 256 cycles */
- 1 << 7 | /* SLOW_PD */
1 << 6 | /* BOTH_CS_PD */
(tcksrx & 0x7) << 3 |
(tcksre & 0x7);
+ if (!sysinfo->pd_fast_exit)
+ mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
/* Step 11: Configure ZQ calibration: one-time and periodic 1ms */