mach-snapdragon: generalise board support
Historically, Qualcomm boards have relied on heavy hardcoding in U-Boot,
in many cases to the specific SoC but also to the board itself (e.g.
memory map). This has been largely resolved by modernising the Qualcomm
drivers in U-Boot, however the board code still largely follows this
model.
This patch removes the board specific memory maps and duplicated board
init code, replacing it with generic init code.
The memory map is now built at runtime based on data read from DT, this
allows for the memory map to be provided without having to recompile
U-Boot. Support is also added for booting with appended DTBs, so that
the first-stage bootloader can populate the memory map for us.
The sdm845 specific init code is dropped entirely, it set an environment
variable depending on if a button was pressed, but this variable wasn't
used in U-Boot, and could be written to use the button command instead.
The KASLR detection is also dropped as with appended dtb, the kaslr seed
can be read directly from the DTB passed to U-Boot.
A new qcom_defconfig is added, with the aim of providing a generic
U-Boot configuration that will work on as many Qualcomm boards as
possible. It replaces the defconfig files for the Dragonboard 845c,
Galaxy S9, and QCS404 EVB. For now the db410c and 820c are excluded as
they still have some board code left.
Similarly, the config headers for db845c, starqltechn, and qcs404-evb
are replaced by a single qcom header.
The previously db410c-specific board_usb_init() function is made to be
generic and is added to mach-snapdragon. While we lack proper modelling
for USB configuration, using a well-known named pinctrl state is a
reasonably generic middleground, and works using upstream DT. This
function will do nothing unless the USB node has a pinctrl state named
"device", in which case it will be set when entering USB peripheral
mode.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fde85dc..0c78c1b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1096,6 +1096,9 @@
select OF_SEPARATE
select SMEM
select SPMI
+ select OF_BOARD
+ select SAVE_PREV_BL_FDT_ADDR
+ select LINUX_KERNEL_IMAGE_HEADER
imply CMD_DM
config ARCH_SOCFPGA
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7c2681e..d2307a6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -624,10 +624,11 @@
dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
-dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
-dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
-dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb
-dtb-$(CONFIG_TARGET_QCS404EVB) += qcs404-evb.dtb
+dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb \
+ dragonboard820c.dtb \
+ dragonboard845c.dtb \
+ starqltechn.dtb \
+ qcs404-evb.dtb
dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
index f897c39..96e44e2 100644
--- a/arch/arm/mach-snapdragon/Kconfig
+++ b/arch/arm/mach-snapdragon/Kconfig
@@ -3,6 +3,9 @@
config SYS_SOC
default "snapdragon"
+config SYS_VENDOR
+ default "qualcomm"
+
config SYS_MALLOC_F_LEN
default 0x2000
@@ -12,91 +15,24 @@
config SPL_SYS_MALLOC_F_LEN
default 0x2000
-config SDM845
- bool "Qualcomm Snapdragon 845 SoC"
- select LINUX_KERNEL_IMAGE_HEADER
- imply CLK_QCOM_SDM845
- imply PINCTRL_QCOM_SDM845
- imply BUTTON_QCOM_PMIC
-
config LNX_KRNL_IMG_TEXT_OFFSET_BASE
default 0x80000000
-choice
- prompt "Snapdragon board select"
-
-config TARGET_DRAGONBOARD410C
- bool "96Boards Dragonboard 410C"
- select BOARD_LATE_INIT
- select ENABLE_ARM_SOC_BOOT0_HOOK
- imply CLK_QCOM_APQ8016
- imply PINCTRL_QCOM_APQ8016
- imply BUTTON_QCOM_PMIC
+config SYS_BOARD
+ string "Qualcomm custom board"
help
- Support for 96Boards Dragonboard 410C. This board complies with
- 96Board Open Platform Specifications. Features:
- - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
- - 1GiB RAM
- - 8GiB eMMC, uSD slot
- - WiFi, Bluetooth and GPS module
- - 2x Host, 1x Device USB port
- - HDMI
- - 20-pin low speed and 40-pin high speed expanders, 4 LED, 3 buttons
+ The Dragonboard 410c and 820c have additional board init
+ code that isn't shared with other Qualcomm boards.
+ Based on this option board/qualcomm/<CONFIG_SYS_BOARD> will
+ be used.
-config TARGET_DRAGONBOARD820C
- bool "96Boards Dragonboard 820C"
- select LINUX_KERNEL_IMAGE_HEADER
- imply CLK_QCOM_APQ8096
- imply PINCTRL_QCOM_APQ8096
- imply BUTTON_QCOM_PMIC
+config SYS_CONFIG_NAME
+ string "Board configuration name"
+ default SYS_BOARD if SYS_BOARD != ""
+ default "qcom"
help
- Support for 96Boards Dragonboard 820C. This board complies with
- 96Board Open Platform Specifications. Features:
- - Qualcomm Snapdragon 820C SoC - APQ8096 (4xKyro CPU)
- - 3GiB RAM
- - 32GiB UFS drive
-
-config TARGET_DRAGONBOARD845C
- bool "96Boards Dragonboard 845C"
- help
- Support for 96Boards Dragonboard 845C aka Robotics RB3 Development
- Platform. This board complies with 96Boards Open Platform
- Specifications. Features:
- - Qualcomm Snapdragon SDA845 SoC
- - 4GiB RAM
- - 64GiB UFS drive
- select MISC_INIT_R
- select SDM845
-
-config TARGET_STARQLTECHN
- bool "Samsung S9 SM-G9600(starqltechn)"
- help
- Support for Samsung S9 SM-G9600(starqltechn) board.
- Features:
- - Qualcomm Snapdragon SDM845 SoC
- - 4GiB RAM
- - 64GiB UFS drive
- select MISC_INIT_R
- select SDM845
-
-config TARGET_QCS404EVB
- bool "Qualcomm Technologies, Inc. QCS404 EVB"
- select LINUX_KERNEL_IMAGE_HEADER
- imply CLK_QCOM_QCS404
- imply PINCTRL_QCOM_QCS404
- help
- Support for Qualcomm Technologies, Inc. QCS404 evaluation board.
- Features:
- - Qualcomm Snapdragon QCS404 SoC
- - 1GiB RAM
- - 8GiB eMMC, uSD slot
-
-endchoice
-
-source "board/qualcomm/dragonboard410c/Kconfig"
-source "board/qualcomm/dragonboard820c/Kconfig"
-source "board/qualcomm/dragonboard845c/Kconfig"
-source "board/samsung/starqltechn/Kconfig"
-source "board/qualcomm/qcs404-evb/Kconfig"
+ This option contains information about board configuration name.
+ Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
+ will be used for board configuration.
endif
diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index d02432d..857171e 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -2,8 +2,4 @@
#
# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
-obj-$(CONFIG_SDM845) += sysmap-sdm845.o
-obj-$(CONFIG_SDM845) += init_sdm845.o
-obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
-obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
-obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
+obj-y += board.o
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
new file mode 100644
index 0000000..a186785
--- /dev/null
+++ b/arch/arm/mach-snapdragon/board.c
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Common initialisation for Qualcomm Snapdragon boards.
+ *
+ * Copyright (c) 2024 Linaro Ltd.
+ * Author: Caleb Connolly <caleb.connolly@linaro.org>
+ */
+
+#include "time.h"
+#include <asm/armv8/mmu.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/psci.h>
+#include <asm/system.h>
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+#include <dm/uclass-internal.h>
+#include <dm/read.h>
+#include <env.h>
+#include <init.h>
+#include <linux/arm-smccc.h>
+#include <linux/bug.h>
+#include <linux/psci.h>
+#include <linux/sizes.h>
+#include <malloc.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } };
+
+struct mm_region *mem_map = rbx_mem_map;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+static int ddr_bank_cmp(const void *v1, const void *v2)
+{
+ const struct {
+ phys_addr_t start;
+ phys_size_t size;
+ } *res1 = v1, *res2 = v2;
+
+ if (!res1->size)
+ return 1;
+ if (!res2->size)
+ return -1;
+
+ return (res1->start >> 24) - (res2->start >> 24);
+}
+
+int dram_init_banksize(void)
+{
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret < 0)
+ return ret;
+
+ if (CONFIG_NR_DRAM_BANKS < 2)
+ return 0;
+
+ /* Sort our RAM banks -_- */
+ qsort(gd->bd->bi_dram, CONFIG_NR_DRAM_BANKS, sizeof(gd->bd->bi_dram[0]), ddr_bank_cmp);
+
+ return 0;
+}
+
+static void show_psci_version(void)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+
+ debug("PSCI: v%ld.%ld\n",
+ PSCI_VERSION_MAJOR(res.a0),
+ PSCI_VERSION_MINOR(res.a0));
+}
+
+void *board_fdt_blob_setup(int *err)
+{
+ phys_addr_t fdt;
+ /* Return DTB pointer passed by ABL */
+ *err = 0;
+ fdt = get_prev_bl_fdt_addr();
+
+ /*
+ * If we bail then the board will simply not boot, instead let's
+ * try and use the FDT built into U-Boot if there is one...
+ * This avoids having a hard dependency on the previous stage bootloader
+ */
+ if (IS_ENABLED(CONFIG_OF_SEPARATE) && (!fdt || fdt != ALIGN(fdt, SZ_4K))) {
+ debug("%s: Using built in FDT, bootloader gave us %#llx\n", __func__, fdt);
+ return (void *)gd->fdt_blob;
+ }
+
+ return (void *)fdt;
+}
+
+void reset_cpu(void)
+{
+ psci_system_reset();
+}
+
+/*
+ * Some Qualcomm boards require GPIO configuration when switching USB modes.
+ * Support setting this configuration via pinctrl state.
+ */
+int board_usb_init(int index, enum usb_init_type init)
+{
+ struct udevice *usb;
+ int ret = 0;
+
+ /* USB device */
+ ret = uclass_find_device_by_seq(UCLASS_USB, index, &usb);
+ if (ret) {
+ printf("Cannot find USB device\n");
+ return ret;
+ }
+
+ ret = dev_read_stringlist_search(usb, "pinctrl-names",
+ "device");
+ /* No "device" pinctrl state, so just bail */
+ if (ret < 0)
+ return 0;
+
+ /* Select "default" or "device" pinctrl */
+ switch (init) {
+ case USB_INIT_HOST:
+ pinctrl_select_state(usb, "default");
+ break;
+ case USB_INIT_DEVICE:
+ pinctrl_select_state(usb, "device");
+ break;
+ default:
+ debug("Unknown usb_init_type %d\n", init);
+ break;
+ }
+
+ return 0;
+}
+
+/*
+ * Some boards still need board specific init code, they can implement that by
+ * overriding this function.
+ *
+ * FIXME: get rid of board specific init code
+ */
+void __weak qcom_board_init(void)
+{
+}
+
+int board_init(void)
+{
+ show_psci_version();
+ qcom_board_init();
+ return 0;
+}
+
+static void build_mem_map(void)
+{
+ int i;
+
+ /*
+ * Ensure the peripheral block is sized to correctly cover the address range
+ * up to the first memory bank.
+ * Don't map the first page to ensure that we actually trigger an abort on a
+ * null pointer access rather than just hanging.
+ * FIXME: we should probably split this into more precise regions
+ */
+ mem_map[0].phys = 0x1000;
+ mem_map[0].virt = mem_map[0].phys;
+ mem_map[0].size = gd->bd->bi_dram[0].start - mem_map[0].phys;
+ mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+
+ debug("Configured memory map:\n");
+ debug(" 0x%016llx - 0x%016llx: Peripheral block\n",
+ mem_map[0].phys, mem_map[0].phys + mem_map[0].size);
+
+ /*
+ * Now add memory map entries for each DRAM bank, ensuring we don't
+ * overwrite the list terminator
+ */
+ for (i = 0; i < ARRAY_SIZE(rbx_mem_map) - 2 && gd->bd->bi_dram[i].size; i++) {
+ if (i == ARRAY_SIZE(rbx_mem_map) - 1) {
+ log_warning("Too many DRAM banks!\n");
+ break;
+ }
+ mem_map[i + 1].phys = gd->bd->bi_dram[i].start;
+ mem_map[i + 1].virt = mem_map[i + 1].phys;
+ mem_map[i + 1].size = gd->bd->bi_dram[i].size;
+ mem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+
+ debug(" 0x%016llx - 0x%016llx: DDR bank %d\n",
+ mem_map[i + 1].phys, mem_map[i + 1].phys + mem_map[i + 1].size, i);
+ }
+}
+
+u64 get_page_table_size(void)
+{
+ return SZ_64K;
+}
+
+void enable_caches(void)
+{
+ build_mem_map();
+
+ icache_enable();
+ dcache_enable();
+}
diff --git a/arch/arm/mach-snapdragon/init_sdm845.c b/arch/arm/mach-snapdragon/init_sdm845.c
deleted file mode 100644
index 067acc9..0000000
--- a/arch/arm/mach-snapdragon/init_sdm845.c
+++ /dev/null
@@ -1,73 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Common init part for boards based on SDM845
- *
- * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
- */
-
-#include <button.h>
-#include <init.h>
-#include <env.h>
-#include <common.h>
-#include <asm/system.h>
-#include <asm/gpio.h>
-#include <dm.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- return fdtdec_setup_mem_size_base();
-}
-
-void reset_cpu(void)
-{
- psci_system_reset();
-}
-
-__weak int board_init(void)
-{
- return 0;
-}
-
-/* Check for vol- and power buttons */
-__weak int misc_init_r(void)
-{
- struct udevice *btn;
- int ret;
- enum button_state_t state;
-
- ret = button_get_by_label("pwrkey", &btn);
- if (ret < 0) {
- printf("Couldn't find power button!\n");
- return ret;
- }
-
- state = button_get_state(btn);
- if (state == BUTTON_ON) {
- env_set("key_power", "1");
- printf("Power button pressed\n");
- } else {
- env_set("key_power", "0");
- }
-
- /*
- * search for kaslr address, set by primary bootloader by searching first
- * 0x100 relocated bytes at u-boot's initial load address range
- */
- uintptr_t start = gd->ram_base;
- uintptr_t end = start + 0x800000;
- u8 *addr = (u8 *)start;
- phys_addr_t *relocaddr = (phys_addr_t *)gd->relocaddr;
- u32 block_size = 0x1000;
-
- while (memcmp(addr, relocaddr, 0x100) && (uintptr_t)addr < end)
- addr += block_size;
-
- if ((uintptr_t)addr >= end)
- printf("KASLR not found in range 0x%lx - 0x%lx", start, end);
- else
- env_set_addr("KASLR", addr);
-
- return 0;
-}
diff --git a/arch/arm/mach-snapdragon/sysmap-apq8016.c b/arch/arm/mach-snapdragon/sysmap-apq8016.c
deleted file mode 100644
index ffa3f9a..0000000
--- a/arch/arm/mach-snapdragon/sysmap-apq8016.c
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Qualcomm APQ8016 memory map
- *
- * (C) Copyright 2016 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
- */
-
-#include <common.h>
-#include <asm/armv8/mmu.h>
-
-static struct mm_region apq8016_mem_map[] = {
- {
- .virt = 0x0UL, /* Peripheral block */
- .phys = 0x0UL, /* Peripheral block */
- .size = 0x8000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- .virt = 0x80000000UL, /* DDR */
- .phys = 0x80000000UL, /* DDR */
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = apq8016_mem_map;
diff --git a/arch/arm/mach-snapdragon/sysmap-apq8096.c b/arch/arm/mach-snapdragon/sysmap-apq8096.c
deleted file mode 100644
index 0614f83..0000000
--- a/arch/arm/mach-snapdragon/sysmap-apq8096.c
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Qualcomm APQ8096 memory map
- *
- * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org>
- */
-
-#include <common.h>
-#include <asm/armv8/mmu.h>
-
-static struct mm_region apq8096_mem_map[] = {
- {
- .virt = 0x0UL, /* Peripheral block */
- .phys = 0x0UL, /* Peripheral block */
- .size = 0x10000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- .virt = 0x80000000UL, /* DDR */
- .phys = 0x80000000UL, /* DDR */
- .size = 0xC0000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = apq8096_mem_map;
diff --git a/arch/arm/mach-snapdragon/sysmap-qcs404.c b/arch/arm/mach-snapdragon/sysmap-qcs404.c
deleted file mode 100644
index 64ca4ad..0000000
--- a/arch/arm/mach-snapdragon/sysmap-qcs404.c
+++ /dev/null
@@ -1,43 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Qualcomm QCS404 memory map
- *
- * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
- */
-
-#include <common.h>
-#include <asm/armv8/mmu.h>
-
-static struct mm_region qcs404_mem_map[] = {
- {
- .virt = 0x0UL, /* Peripheral block */
- .phys = 0x0UL, /* Peripheral block */
- .size = 0x8000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- .virt = 0x80000000UL, /* DDR */
- .phys = 0x80000000UL, /* DDR */
- .size = 0x05900000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x89600000UL, /* DDR */
- .phys = 0x89600000UL, /* DDR */
- .size = 0x162000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0xa0000000UL, /* DDR */
- .phys = 0xa0000000UL, /* DDR */
- .size = 0x20000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = qcs404_mem_map;
diff --git a/arch/arm/mach-snapdragon/sysmap-sdm845.c b/arch/arm/mach-snapdragon/sysmap-sdm845.c
deleted file mode 100644
index 721ac41..0000000
--- a/arch/arm/mach-snapdragon/sysmap-sdm845.c
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Qualcomm SDM845 memory map
- *
- * (C) Copyright 2021 Dzmitry Sankouski <dsankousk@gmail.com>
- */
-
-#include <common.h>
-#include <asm/armv8/mmu.h>
-
-static struct mm_region sdm845_mem_map[] = {
- {
- .virt = 0x0UL, /* Peripheral block */
- .phys = 0x0UL, /* Peripheral block */
- .size = 0x10000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- .virt = 0x80000000UL, /* DDR */
- .phys = 0x80000000UL, /* DDR */
- .size = 0x200000000UL, /* 8GiB - maximum allowed memory */
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = sdm845_mem_map;