arm: dts: k3-*-ddr: Add ss_cfg reg entry
Add ss_cfg memory region which maps the DDRSS configuration region
for the memory controller node.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Tested-by: Neha Malcom Francis <n-francis@ti.com>
diff --git a/arch/arm/dts/k3-j784s4-ddr.dtsi b/arch/arm/dts/k3-j784s4-ddr.dtsi
index 1c3242b..fc74c53 100644
--- a/arch/arm/dts/k3-j784s4-ddr.dtsi
+++ b/arch/arm/dts/k3-j784s4-ddr.dtsi
@@ -9,6 +9,10 @@
<0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg
<0x00 0x029d0000 0x00 0x029d0000 0x00 0x00004000>, // ddr2 cfg
<0x00 0x029f0000 0x00 0x029f0000 0x00 0x00004000>, // ddr3 cfg
+ <0x00 0x02980000 0x00 0x02980000 0x00 0x00000200>, // ss cfg 0
+ <0x00 0x029a0000 0x00 0x029a0000 0x00 0x00000200>, // ss cfg 1
+ <0x00 0x029c0000 0x00 0x029c0000 0x00 0x00000200>, // ss cfg 2
+ <0x00 0x029e0000 0x00 0x029e0000 0x00 0x00000200>, // ss cfg 3
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
msmc0: msmc {
@@ -26,8 +30,9 @@
memorycontroller0: memorycontroller@2990000 {
compatible = "ti,j721s2-ddrss";
reg = <0x0 0x02990000 0x0 0x4000>,
- <0x0 0x0114000 0x0 0x100>;
- reg-names = "cfg", "ctrl_mmr_lp4";
+ <0x0 0x0114000 0x0 0x100>,
+ <0x0 0x02980000 0x0 0x200>;
+ reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>,
<&k3_pds 131 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 191 1>, <&k3_clks 78 2>;
@@ -2234,8 +2239,9 @@
memorycontroller1: memorycontroller@29b0000 {
compatible = "ti,j721s2-ddrss";
reg = <0x0 0x029b0000 0x0 0x4000>,
- <0x0 0x0114000 0x0 0x100>;
- reg-names = "cfg", "ctrl_mmr_lp4";
+ <0x0 0x0114000 0x0 0x100>,
+ <0x0 0x029a0000 0x0 0x200>;
+ reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>,
<&k3_pds 132 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 192 1>, <&k3_clks 78 2>;
@@ -4442,8 +4448,9 @@
memorycontroller2: memorycontroller@29d0000 {
compatible = "ti,j721s2-ddrss";
reg = <0x0 0x029d0000 0x0 0x4000>,
- <0x0 0x0114000 0x0 0x100>;
- reg-names = "cfg", "ctrl_mmr_lp4";
+ <0x0 0x0114000 0x0 0x100>,
+ <0x0 0x029c0000 0x0 0x200>;
+ reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>,
<&k3_pds 133 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 193 1>, <&k3_clks 78 2>;
@@ -6650,8 +6657,9 @@
memorycontroller3: memorycontroller@29f0000 {
compatible = "ti,j721s2-ddrss";
reg = <0x0 0x029f0000 0x0 0x4000>,
- <0x0 0x0114000 0x0 0x100>;
- reg-names = "cfg", "ctrl_mmr_lp4";
+ <0x0 0x0114000 0x0 0x100>,
+ <0x0 0x29e0000 0x0 0x200>;
+ reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>,
<&k3_pds 139 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 194 1>, <&k3_clks 78 2>;