Merge branch 'master' of git://git.denx.de/u-boot-video
* 'master' of git://git.denx.de/u-boot-video:
video: cfb_console: Make the software cursor non-destructive
diff --git a/MAINTAINERS b/MAINTAINERS
index ad1b62f..0c0b4ee 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -701,10 +701,6 @@
Torsten Koschorrek <koschorrek@synertronixx.de>
scb9328 ARM920T (i.MXL)
-Frederik Kriewitz <frederik@kriewitz.eu>
-
- devkit8000 ARM ARMV7 (OMAP3530 SoC)
-
Sergey Kubushyn <ksi@koi8.net>
DV-EVM ARM926EJS
@@ -881,6 +877,10 @@
harmony Tegra2 (ARM7 & A9 Dual Core)
seaboard Tegra2 (ARM7 & A9 Dual Core)
+Thomas Weber <weber@corscience.de>
+
+ devkit8000 ARM ARMV7 (OMAP3530 SoC)
+
Lei Wen <leiwen@marvell.com>
dkb ARM926EJS (PANTHEON 88AP920 SOC)
@@ -1054,6 +1054,7 @@
RSK7203 SH7203
AP325RXA SH7723
SHMIN SH7706
+ ECOVEC SH7724
Mark Jonas <mark.jonas@de.bosch.com>
diff --git a/MAKEALL b/MAKEALL
index 2a77857..fa0121c 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -16,6 +16,7 @@
-c CPU, --cpu CPU Build all boards with cpu CPU
-v VENDOR, --vendor VENDOR Build all boards with vendor VENDOR
-s SOC, --soc SOC Build all boards with soc SOC
+ -l, --list List all targets to be built
-h, --help This help output
Selections by these options are logically ANDed; if the same option
@@ -47,8 +48,8 @@
exit ${ret}
}
-SHORT_OPTS="ha:c:v:s:"
-LONG_OPTS="help,arch:,cpu:,vendor:,soc:"
+SHORT_OPTS="ha:c:v:s:l"
+LONG_OPTS="help,arch:,cpu:,vendor:,soc:,list"
# Option processing based on util-linux-2.13/getopt-parse.bash
@@ -65,6 +66,7 @@
eval set -- "$TEMP"
SELECTED=''
+ONLY_LIST=''
while true ; do
case "$1" in
@@ -104,6 +106,9 @@
fi
SELECTED='y'
shift 2 ;;
+ -l|--list)
+ ONLY_LIST='y'
+ shift ;;
-h|--help)
usage ;;
--)
@@ -487,6 +492,11 @@
build_target() {
target=$1
+ if [ "$ONLY_LIST" == 'y' ] ; then
+ echo "$target"
+ return
+ fi
+
${MAKE} distclean >/dev/null
${MAKE} -s ${target}_config
@@ -530,6 +540,7 @@
#-----------------------------------------------------------------------
print_stats() {
+ if [ "$ONLY_LIST" == 'y' ] ; then return ; fi
echo ""
echo "--------------------- SUMMARY ----------------------------"
echo "Boards compiled: ${TOTAL_CNT}"
diff --git a/Makefile b/Makefile
index d84b350..f23bed6 100644
--- a/Makefile
+++ b/Makefile
@@ -277,6 +277,9 @@
endif
LIBS += drivers/rtc/librtc.o
LIBS += drivers/serial/libserial.o
+ifeq ($(CONFIG_GENERIC_LPC_TPM),y)
+LIBS += drivers/tpm/libtpm.o
+endif
LIBS += drivers/twserial/libtws.o
LIBS += drivers/usb/eth/libusb_eth.o
LIBS += drivers/usb/gadget/libusb_gadget.o
@@ -751,7 +754,7 @@
$(obj)tools/envcrc \
$(obj)tools/gdb/{astest,gdbcont,gdbsend} \
$(obj)tools/gen_eth_addr $(obj)tools/img2srec \
- $(obj)tools/mkimage $(obj)tools/mpc86x_clk \
+ $(obj)tools/mk{env,}image $(obj)tools/mpc86x_clk \
$(obj)tools/ncb $(obj)tools/ubsha1
@rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image} \
$(obj)board/matrix_vision/*/bootscript.img \
@@ -777,11 +780,14 @@
-o -name '*.o' -o -name '*.a' -o -name '*.exe' \) -print \
| xargs rm -f
-clobber: clean
- @find $(OBJTREE) -type f \( -name '*.depend*' \
- -o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
- -print0 \
- | xargs -0 rm -f
+# Removes everything not needed for testing u-boot
+tidy: clean
+ @find $(OBJTREE) -type f \( -name '*.depend*' \) -print | xargs rm -f
+
+clobber: tidy
+ @find $(OBJTREE) -type f \( -name '*.srec' \
+ -o -name '*.bin' -o -name u-boot.img \) \
+ -print0 | xargs -0 rm -f
@rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS \
$(obj)cscope.* $(obj)*.*~
@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL-y)
diff --git a/README b/README
index fda0190..3ddec77 100644
--- a/README
+++ b/README
@@ -1072,6 +1072,16 @@
CONFIG_SH_ETHER_CACHE_WRITEBACK
If this option is set, the driver enables cache flush.
+- TPM Support:
+ CONFIG_GENERIC_LPC_TPM
+ Support for generic parallel port TPM devices. Only one device
+ per system is supported at this time.
+
+ CONFIG_TPM_TIS_BASE_ADDRESS
+ Base address where the generic TPM device is mapped
+ to. Contemporary x86 systems usually map it at
+ 0xfed40000.
+
- USB Support:
At the moment only the UHCI host controller is
supported (PIP405, MIP405, MPC5200); define
diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c
index 170bbfc..a98a926 100644
--- a/arch/m68k/cpu/mcf52x2/cpu_init.c
+++ b/arch/m68k/cpu/mcf52x2/cpu_init.c
@@ -284,7 +284,7 @@
mbar_writeLong(MCF_FMPLL_SYNCR,
MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
#endif
- while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
+ while (!(mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK)) ;
}
/*
diff --git a/arch/sh/cpu/sh2/config.mk b/arch/sh/cpu/sh2/config.mk
index f46b38f..bdd3315 100644
--- a/arch/sh/cpu/sh2/config.mk
+++ b/arch/sh/cpu/sh2/config.mk
@@ -24,10 +24,11 @@
ENDIANNESS += -EB
ifdef CONFIG_SH2A
-PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb -mno-fdpic -ffreestanding
+PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb -ffreestanding
else # SH2
PLATFORM_CPPFLAGS += -m3e -mb
endif
+PLATFORM_CPPFLAGS += $(call cc-option,-mno-fdpic)
PLATFORM_RELFLAGS += -ffixed-r13
PLATFORM_LDFLAGS += $(ENDIANNESS)
diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c
index 377005c..dc75e39 100644
--- a/arch/sh/cpu/sh4/cache.c
+++ b/arch/sh/cpu/sh4/cache.c
@@ -106,3 +106,25 @@
return 0;
}
+
+void dcache_wback_range(u32 start, u32 end)
+{
+ u32 v;
+
+ start &= ~(L1_CACHE_BYTES - 1);
+ for (v = start; v < end; v += L1_CACHE_BYTES) {
+ asm volatile ("ocbwb %0" : /* no output */
+ : "m" (__m(v)));
+ }
+}
+
+void dcache_invalid_range(u32 start, u32 end)
+{
+ u32 v;
+
+ start &= ~(L1_CACHE_BYTES - 1);
+ for (v = start; v < end; v += L1_CACHE_BYTES) {
+ asm volatile ("ocbi %0" : /* no output */
+ : "m" (__m(v)));
+ }
+}
diff --git a/arch/sh/include/asm/cache.h b/arch/sh/include/asm/cache.h
index 6ffab4d..24941b3 100644
--- a/arch/sh/include/asm/cache.h
+++ b/arch/sh/include/asm/cache.h
@@ -10,27 +10,9 @@
struct __large_struct { unsigned long buf[100]; };
#define __m(x) (*(struct __large_struct *)(x))
-void dcache_wback_range(u32 start, u32 end)
-{
- u32 v;
-
- start &= ~(L1_CACHE_BYTES - 1);
- for (v = start; v < end; v += L1_CACHE_BYTES) {
- asm volatile ("ocbwb %0" : /* no output */
- : "m" (__m(v)));
- }
-}
-
-void dcache_invalid_range(u32 start, u32 end)
-{
- u32 v;
+void dcache_wback_range(u32 start, u32 end);
+void dcache_invalid_range(u32 start, u32 end);
- start &= ~(L1_CACHE_BYTES - 1);
- for (v = start; v < end; v += L1_CACHE_BYTES) {
- asm volatile ("ocbi %0" : /* no output */
- : "m" (__m(v)));
- }
-}
#else
/*
diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h
index 9b29d3a..4351e8e 100644
--- a/arch/sh/include/asm/cpu_sh4.h
+++ b/arch/sh/include/asm/cpu_sh4.h
@@ -44,6 +44,8 @@
# include <asm/cpu_sh7722.h>
#elif defined (CONFIG_CPU_SH7723)
# include <asm/cpu_sh7723.h>
+#elif defined (CONFIG_CPU_SH7724)
+# include <asm/cpu_sh7724.h>
#elif defined (CONFIG_CPU_SH7757)
# include <asm/cpu_sh7757.h>
#elif defined (CONFIG_CPU_SH7763)
diff --git a/arch/sh/include/asm/cpu_sh7724.h b/arch/sh/include/asm/cpu_sh7724.h
new file mode 100644
index 0000000..3bb51d3
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh7724.h
@@ -0,0 +1,234 @@
+/*
+ * (C) Copyright 2008, 2011 Renesas Solutions Corp.
+ *
+ * SH7724 Internal I/O register
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CPU_SH7724_H_
+#define _ASM_CPU_SH7724_H_
+
+#define CACHE_OC_NUM_WAYS 4
+#define CCR_CACHE_INIT 0x0000090d
+
+/* EXP */
+#define TRA 0xFF000020
+#define EXPEVT 0xFF000024
+#define INTEVT 0xFF000028
+
+/* MMU */
+#define PTEH 0xFF000000
+#define PTEL 0xFF000004
+#define TTB 0xFF000008
+#define TEA 0xFF00000C
+#define MMUCR 0xFF000010
+#define PASCR 0xFF000070
+#define IRMCR 0xFF000078
+
+/* CACHE */
+#define CCR 0xFF00001C
+#define RAMCR 0xFF000074
+
+/* INTC */
+
+/* BSC */
+#define MMSELR 0xFF800020
+#define CMNCR 0xFEC10000
+#define CS0BCR 0xFEC10004
+#define CS2BCR 0xFEC10008
+#define CS4BCR 0xFEC10010
+#define CS5ABCR 0xFEC10014
+#define CS5BBCR 0xFEC10018
+#define CS6ABCR 0xFEC1001C
+#define CS6BBCR 0xFEC10020
+#define CS0WCR 0xFEC10024
+#define CS2WCR 0xFEC10028
+#define CS4WCR 0xFEC10030
+#define CS5AWCR 0xFEC10034
+#define CS5BWCR 0xFEC10038
+#define CS6AWCR 0xFEC1003C
+#define CS6BWCR 0xFEC10040
+#define RBWTCNT 0xFEC10054
+
+/* SBSC */
+#define SBSC_SDCR 0xFE400008
+#define SBSC_SDWCR 0xFE40000C
+#define SBSC_SDPCR 0xFE400010
+#define SBSC_RTCSR 0xFE400014
+#define SBSC_RTCNT 0xFE400018
+#define SBSC_RTCOR 0xFE40001C
+#define SBSC_RFCR 0xFE400020
+
+/* DSBC */
+#define DBKIND 0xFD000008
+#define DBSTATE 0xFD00000C
+#define DBEN 0xFD000010
+#define DBCMDCNT 0xFD000014
+#define DBCKECNT 0xFD000018
+#define DBCONF 0xFD000020
+#define DBTR0 0xFD000030
+#define DBTR1 0xFD000034
+#define DBTR2 0xFD000038
+#define DBTR3 0xFD00003C
+#define DBRFPDN0 0xFD000040
+#define DBRFPDN1 0xFD000044
+#define DBRFPDN2 0xFD000048
+#define DBRFSTS 0xFD00004C
+#define DBMRCNT 0xFD000060
+#define DBPDCNT0 0xFD000108
+
+/* DMAC */
+
+/* CPG */
+#define FRQCRA 0xA4150000
+#define FRQCRB 0xA4150004
+#define FRQCR FRQCRA
+#define VCLKCR 0xA4150004
+#define SCLKACR 0xA4150008
+#define SCLKBCR 0xA415000C
+#define IRDACLKCR 0xA4150018
+#define PLLCR 0xA4150024
+#define DLLFRQ 0xA4150050
+
+/* LOW POWER MODE */
+#define STBCR 0xA4150020
+#define MSTPCR0 0xA4150030
+#define MSTPCR1 0xA4150034
+#define MSTPCR2 0xA4150038
+
+/* RWDT */
+#define RWTCNT 0xA4520000
+#define RWTCSR 0xA4520004
+#define WTCNT RWTCNT
+
+/* TMU */
+#define TSTR 0xFFD80004
+#define TCOR0 0xFFD80008
+#define TCNT0 0xFFD8000C
+#define TCR0 0xFFD80010
+#define TCOR1 0xFFD80014
+#define TCNT1 0xFFD80018
+#define TCR1 0xFFD8001C
+#define TCOR2 0xFFD80020
+#define TCNT2 0xFFD80024
+#define TCR2 0xFFD80028
+
+/* TPU */
+
+/* CMT */
+#define CMSTR 0xA44A0000
+#define CMCSR 0xA44A0060
+#define CMCNT 0xA44A0064
+#define CMCOR 0xA44A0068
+
+/* MSIOF */
+
+/* SCIF */
+#define SCIF0_BASE 0xFFE00000
+#define SCIF1_BASE 0xFFE10000
+#define SCIF2_BASE 0xFFE20000
+#define SCIF3_BASE 0xa4e30000
+#define SCIF4_BASE 0xa4e40000
+#define SCIF5_BASE 0xa4e50000
+
+/* RTC */
+/* IrDA */
+/* KEYSC */
+/* USB */
+/* IIC */
+/* FLCTL */
+/* VPU */
+/* VIO(CEU) */
+/* VIO(VEU) */
+/* VIO(BEU) */
+/* 2DG */
+/* LCDC */
+/* VOU */
+/* TSIF */
+/* SIU */
+/* ATAPI */
+
+/* PFC */
+#define PACR 0xA4050100
+#define PBCR 0xA4050102
+#define PCCR 0xA4050104
+#define PDCR 0xA4050106
+#define PECR 0xA4050108
+#define PFCR 0xA405010A
+#define PGCR 0xA405010C
+#define PHCR 0xA405010E
+#define PJCR 0xA4050110
+#define PKCR 0xA4050112
+#define PLCR 0xA4050114
+#define PMCR 0xA4050116
+#define PNCR 0xA4050118
+#define PQCR 0xA405011A
+#define PRCR 0xA405011C
+#define PSCR 0xA405011E
+#define PTCR 0xA4050140
+#define PUCR 0xA4050142
+#define PVCR 0xA4050144
+#define PWCR 0xA4050146
+#define PXCR 0xA4050148
+#define PYCR 0xA405014A
+#define PZCR 0xA405014C
+#define PSELA 0xA405014E
+#define PSELB 0xA4050150
+#define PSELC 0xA4050152
+#define PSELD 0xA4050154
+#define PSELE 0xA4050156
+#define HIZCRA 0xA4050158
+#define HIZCRB 0xA405015A
+#define HIZCRC 0xA405015C
+#define HIZCRD 0xA405015E
+#define MSELCRA 0xA4050180
+#define MSELCRB 0xA4050182
+#define PULCR 0xA4050184
+#define DRVCRA 0xA405018A
+#define DRVCRB 0xA405018C
+
+/* I/O Port */
+#define PADR 0xA4050120
+#define PBDR 0xA4050122
+#define PCDR 0xA4050124
+#define PDDR 0xA4050126
+#define PEDR 0xA4050128
+#define PFDR 0xA405012A
+#define PGDR 0xA405012C
+#define PHDR 0xA405012E
+#define PJDR 0xA4050130
+#define PKDR 0xA4050132
+#define PLDR 0xA4050134
+#define PMDR 0xA4050136
+#define PNDR 0xA4050138
+#define PQDR 0xA405013A
+#define PRDR 0xA405013C
+#define PSDR 0xA405013E
+#define PTDR 0xA4050160
+#define PUDR 0xA4050162
+#define PVDR 0xA4050164
+#define PWDR 0xA4050166
+#define PYDR 0xA4050168
+#define PZDR 0xA405016A
+
+/* Ether */
+#define EDMR 0xA4600000
+
+/* UBC */
+/* H-UDI */
+
+#endif /* _ASM_CPU_SH7724_H_ */
diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile
index 6aaf55a..256811a 100644
--- a/arch/sh/lib/Makefile
+++ b/arch/sh/lib/Makefile
@@ -28,6 +28,7 @@
GLSOBJS += ashiftlt.o
GLSOBJS += lshiftrt.o
GLSOBJS += ashldi3.o
+GLSOBJS += ashrsi3.o
GLSOBJS += lshrdi3.o
GLSOBJS += movmem.o
diff --git a/arch/sh/lib/ashrsi3.S b/arch/sh/lib/ashrsi3.S
new file mode 100644
index 0000000..6f3cf46
--- /dev/null
+++ b/arch/sh/lib/ashrsi3.S
@@ -0,0 +1,185 @@
+/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+ 2004, 2005, 2006
+ Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file into combinations with other programs,
+and to distribute those combinations without any restriction coming
+from the use of this file. (The General Public License restrictions
+do apply in other respects; for example, they cover modification of
+the file, and distribution when not linked into a combine
+executable.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING. If not, write to
+the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+Boston, MA 02110-1301, USA. */
+
+!! libgcc routines for the Renesas / SuperH SH CPUs.
+!! Contributed by Steve Chamberlain.
+!! sac@cygnus.com
+
+!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
+!! recoded in assembly by Toshiyasu Morita
+!! tm@netcom.com
+
+/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
+ ELF local label prefixes by J"orn Rennecke
+ amylaar@cygnus.com */
+
+!
+! __ashrsi3
+!
+! Entry:
+!
+! r4: Value to shift
+! r5: Shifts
+!
+! Exit:
+!
+! r0: Result
+!
+! Destroys:
+!
+! (none)
+!
+
+ .global __ashrsi3
+
+ .align 2
+__ashrsi3:
+ mov #31,r0
+ and r0,r5
+ mova ashrsi3_table,r0
+ mov.b @(r0,r5),r5
+#ifdef __sh1__
+ add r5,r0
+ jmp @r0
+#else
+ braf r5
+#endif
+ mov r4,r0
+
+ .align 2
+ashrsi3_table:
+ .byte ashrsi3_0-ashrsi3_table
+ .byte ashrsi3_1-ashrsi3_table
+ .byte ashrsi3_2-ashrsi3_table
+ .byte ashrsi3_3-ashrsi3_table
+ .byte ashrsi3_4-ashrsi3_table
+ .byte ashrsi3_5-ashrsi3_table
+ .byte ashrsi3_6-ashrsi3_table
+ .byte ashrsi3_7-ashrsi3_table
+ .byte ashrsi3_8-ashrsi3_table
+ .byte ashrsi3_9-ashrsi3_table
+ .byte ashrsi3_10-ashrsi3_table
+ .byte ashrsi3_11-ashrsi3_table
+ .byte ashrsi3_12-ashrsi3_table
+ .byte ashrsi3_13-ashrsi3_table
+ .byte ashrsi3_14-ashrsi3_table
+ .byte ashrsi3_15-ashrsi3_table
+ .byte ashrsi3_16-ashrsi3_table
+ .byte ashrsi3_17-ashrsi3_table
+ .byte ashrsi3_18-ashrsi3_table
+ .byte ashrsi3_19-ashrsi3_table
+ .byte ashrsi3_20-ashrsi3_table
+ .byte ashrsi3_21-ashrsi3_table
+ .byte ashrsi3_22-ashrsi3_table
+ .byte ashrsi3_23-ashrsi3_table
+ .byte ashrsi3_24-ashrsi3_table
+ .byte ashrsi3_25-ashrsi3_table
+ .byte ashrsi3_26-ashrsi3_table
+ .byte ashrsi3_27-ashrsi3_table
+ .byte ashrsi3_28-ashrsi3_table
+ .byte ashrsi3_29-ashrsi3_table
+ .byte ashrsi3_30-ashrsi3_table
+ .byte ashrsi3_31-ashrsi3_table
+
+ashrsi3_31:
+ rotcl r0
+ rts
+ subc r0,r0
+
+ashrsi3_30:
+ shar r0
+ashrsi3_29:
+ shar r0
+ashrsi3_28:
+ shar r0
+ashrsi3_27:
+ shar r0
+ashrsi3_26:
+ shar r0
+ashrsi3_25:
+ shar r0
+ashrsi3_24:
+ shlr16 r0
+ shlr8 r0
+ rts
+ exts.b r0,r0
+
+ashrsi3_23:
+ shar r0
+ashrsi3_22:
+ shar r0
+ashrsi3_21:
+ shar r0
+ashrsi3_20:
+ shar r0
+ashrsi3_19:
+ shar r0
+ashrsi3_18:
+ shar r0
+ashrsi3_17:
+ shar r0
+ashrsi3_16:
+ shlr16 r0
+ rts
+ exts.w r0,r0
+
+ashrsi3_15:
+ shar r0
+ashrsi3_14:
+ shar r0
+ashrsi3_13:
+ shar r0
+ashrsi3_12:
+ shar r0
+ashrsi3_11:
+ shar r0
+ashrsi3_10:
+ shar r0
+ashrsi3_9:
+ shar r0
+ashrsi3_8:
+ shar r0
+ashrsi3_7:
+ shar r0
+ashrsi3_6:
+ shar r0
+ashrsi3_5:
+ shar r0
+ashrsi3_4:
+ shar r0
+ashrsi3_3:
+ shar r0
+ashrsi3_2:
+ shar r0
+ashrsi3_1:
+ rts
+ shar r0
+
+ashrsi3_0:
+ rts
+ nop
diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c
index 69b5ca4..519a4fb 100644
--- a/arch/sparc/lib/board.c
+++ b/arch/sparc/lib/board.c
@@ -165,13 +165,10 @@
void board_init_f(ulong bootflag)
{
- cmd_tbl_t *cmdtp;
bd_t *bd;
unsigned char *s;
init_fnc_t **init_fnc_ptr;
int j;
- int i;
- char *e;
#ifndef CONFIG_SYS_NO_FLASH
ulong flash_size;
diff --git a/arch/sparc/lib/bootm.c b/arch/sparc/lib/bootm.c
index 4c226a3..e5b933d 100644
--- a/arch/sparc/lib/bootm.c
+++ b/arch/sparc/lib/bootm.c
@@ -97,8 +97,6 @@
char *bootargs;
ulong initrd_start, initrd_end;
ulong rd_len;
- unsigned int data, len, checksum;
- unsigned int initrd_addr, kernend;
void (*kernel) (struct linux_romvec *, void *);
struct lmb *lmb = &images->lmb;
int ret;
diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c
index 8f23375..1960fc1 100644
--- a/board/amcc/common/flash.c
+++ b/board/amcc/common/flash.c
@@ -396,7 +396,7 @@
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
+ int flag, prot, sect;
int i;
if ((s_first < 0) || (s_first > s_last)) {
@@ -427,8 +427,6 @@
printf("\n");
}
- l_sect = -1;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
@@ -454,7 +452,6 @@
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
}
- l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
@@ -825,7 +822,7 @@
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
+ int flag, prot, sect;
int i;
if ((s_first < 0) || (s_first > s_last)) {
@@ -856,8 +853,6 @@
printf("\n");
}
- l_sect = -1;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
@@ -883,7 +878,6 @@
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
}
- l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
diff --git a/board/amcc/taihu/flash.c b/board/amcc/taihu/flash.c
index e9fbbb1..63968a4 100644
--- a/board/amcc/taihu/flash.c
+++ b/board/amcc/taihu/flash.c
@@ -511,7 +511,7 @@
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
+ int flag, prot, sect;
int i;
if ((s_first < 0) || (s_first > s_last)) {
@@ -542,8 +542,6 @@
printf("\n");
}
- l_sect = -1;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
@@ -569,7 +567,6 @@
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
}
- l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
@@ -953,7 +950,7 @@
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
+ int flag, prot, sect;
int i;
if ((s_first < 0) || (s_first > s_last)) {
@@ -984,8 +981,6 @@
printf("\n");
}
- l_sect = -1;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
@@ -1011,7 +1006,6 @@
addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30303030; /* sector erase */
}
- l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
diff --git a/board/amcc/yucca/flash.c b/board/amcc/yucca/flash.c
index 20b6af9..ab513f9 100644
--- a/board/amcc/yucca/flash.c
+++ b/board/amcc/yucca/flash.c
@@ -422,7 +422,7 @@
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
+ int flag, prot, sect;
int i;
if ((s_first < 0) || (s_first > s_last)) {
@@ -449,8 +449,6 @@
printf("\n");
- l_sect = -1;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
@@ -476,7 +474,6 @@
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
}
- l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
@@ -831,7 +828,7 @@
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
+ int flag, prot, sect;
int i;
if ((s_first < 0) || (s_first > s_last)) {
@@ -858,8 +855,6 @@
printf("\n");
- l_sect = -1;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
@@ -885,7 +880,6 @@
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
}
- l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
diff --git a/board/esd/common/xilinx_jtag/micro.c b/board/esd/common/xilinx_jtag/micro.c
index 9823e5e..cba33b8 100644
--- a/board/esd/common/xilinx_jtag/micro.c
+++ b/board/esd/common/xilinx_jtag/micro.c
@@ -1831,7 +1831,6 @@
int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int iErrorCode;
- char* pzXsvfFileName;
unsigned long duration;
unsigned long long startClock, endClock;
@@ -1847,7 +1846,6 @@
}
iErrorCode = XSVF_ERRORCODE( XSVF_ERROR_NONE );
- pzXsvfFileName = 0;
xsvf_iDebugLevel = 0;
printf("XSVF Player v%s, Xilinx, Inc.\n", XSVF_VERSION);
diff --git a/board/esd/dasa_sim/flash.c b/board/esd/dasa_sim/flash.c
index d6a7737..e2f2aac 100644
--- a/board/esd/dasa_sim/flash.c
+++ b/board/esd/dasa_sim/flash.c
@@ -44,7 +44,6 @@
{
unsigned long size_b0;
int i;
- unsigned long base_b0;
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
@@ -63,8 +62,6 @@
/* Setup offsets */
flash_get_offsets (-size_b0, &flash_info[0]);
- base_b0 = -size_b0;
-
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-monitor_flash_len,
diff --git a/board/matrix_vision/common/mv_common.c b/board/matrix_vision/common/mv_common.c
index 404c8b4..acb72c5 100644
--- a/board/matrix_vision/common/mv_common.c
+++ b/board/matrix_vision/common/mv_common.c
@@ -29,6 +29,7 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_ENV_IS_NOWHERE
static char* entries_to_keep[] = {
"serial#", "ethaddr", "eth1addr", "model_info", "sensor_cnt",
"fpgadatasize", "ddr_size", "use_dhcp", "use_static_ipaddr",
@@ -38,7 +39,6 @@
#define MV_MAX_ENV_ENTRY_LENGTH 64
#define MV_KEEP_ENTRIES ARRAY_SIZE(entries_to_keep)
-#ifndef CONFIG_ENV_IS_NOWHERE
void mv_reset_environment(void)
{
int i;
diff --git a/board/renesas/ecovec/Makefile b/board/renesas/ecovec/Makefile
new file mode 100644
index 0000000..8fdc0c9
--- /dev/null
+++ b/board/renesas/ecovec/Makefile
@@ -0,0 +1,38 @@
+#
+# Copyright (C) 2011 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+# Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := ecovec.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(obj).depend $(COBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(COBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c
new file mode 100644
index 0000000..275b0ba
--- /dev/null
+++ b/board/renesas/ecovec/ecovec.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2009, 2011 Renesas Solutions Corp.
+ * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <netdev.h>
+
+/* USB power management register */
+#define UPONCR0 0xA40501D4
+
+int checkboard(void)
+{
+ puts("BOARD: ecovec\n");
+ return 0;
+}
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+static void debug_led(u8 led)
+{
+ /* PDGR[0-4] is debug LED */
+ outb((inb(PGDR) & ~0x0F) | (led & 0x0F), PGDR);
+}
+
+int board_late_init(void)
+{
+ u8 mac[6];
+ char env_mac[17];
+ int i;
+
+ udelay(1000);
+
+ /* SH-Eth (PLCR, PNCR, PXCR, PSELx )*/
+ outw(inw(PLCR) & ~0xFFF0, PLCR);
+ outw(inw(PNCR) & ~0x000F, PNCR);
+ outw(inw(PXCR) & ~0x0FC0, PXCR);
+ outw((inw(PSELB) & ~0x030F) | 0x020A, PSELB);
+ outw((inw(PSELC) & ~0x0307) | 0x0207, PSELC);
+ outw((inw(PSELE) & ~0x00c0) | 0x0080, PSELE);
+
+ debug_led(1 << 3);
+
+ outl(inl(MSTPCR2) & ~0x10000000, MSTPCR2);
+
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(CONFIG_SYS_I2C_MODULE); /* Use I2C 1 */
+
+ /* Read MAC address */
+ i2c_read(0x50, 0x10, 0, mac, 6);
+
+ /* Set MAC address */
+ sprintf(env_mac, "%02X:%02X:%02X:%02X:%02X:%02X",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ setenv("ethaddr", env_mac);
+
+ debug_led(0x0F);
+
+ return 0;
+}
+
+int board_init(void)
+{
+
+ /* LED (PTG) */
+ outw((inw(PGCR) & ~0xFF) | 0x66, PGCR);
+ outw((inw(HIZCRA) & ~0x02), HIZCRA);
+
+ debug_led(1 << 0);
+
+ /* SCIF0 (PTF, PTM) */
+ outw(inw(PFCR) & ~0x30, PFCR);
+ outw(inw(PMCR) & ~0x0C, PMCR);
+ outw((inw(PSELA) & ~0x40) | 0x40, PSELA);
+
+ debug_led(1 << 1);
+
+ /* RMII (PTA) */
+ outw((inw(PACR) & ~0x0C) | 0x04, PACR);
+ outb((inb(PADR) & ~0x02) | 0x02, PADR);
+
+ debug_led(1 << 2);
+
+ /* USB host */
+ outw((inw(PBCR) & ~0x300) | 0x100, PBCR);
+ outb((inb(PBDR) & ~0x10) | 0x10, PBDR);
+ outl(inl(MSTPCR2) & 0x100000, MSTPCR2);
+ outw(0x0600, UPONCR0);
+
+ debug_led(1 << 3);
+
+ /* debug switch */
+ outw((inw(PVCR) & ~0x03) | 0x02 , PVCR);
+
+ return 0;
+}
diff --git a/board/renesas/ecovec/lowlevel_init.S b/board/renesas/ecovec/lowlevel_init.S
new file mode 100644
index 0000000..9fc63e0
--- /dev/null
+++ b/board/renesas/ecovec/lowlevel_init.S
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com>
+ *
+ * board/renesas/ecovec/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+#include <configs/ecovec.h>
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+ /* jump to 0xA0020000 if bit 1 of PVDR_A */
+ mov.l PVDR_A, r1
+ mov.l PVDR_D, r2
+ mov.b @r1, r0
+ tst r0, r2
+ bt 1f
+ mov.l JUMP_A, r1
+ jmp @r1
+ nop
+
+1:
+ /* Disable watchdog */
+ write16 RWTCSR_A, RWTCSR_D
+
+ /* MMU Disable */
+ write32 MMUCR_A, MMUCR_D
+
+ /* Setup clocks */
+ write32 PLLCR_A, PLLCR_D
+ write32 FRQCRA_A, FRQCRA_D
+ write32 FRQCRB_A, FRQCRB_D
+
+ wait_timer TIMER_D
+
+ write32 MMSELR_A, MMSELR_D
+
+ /* Srtup BSC */
+ write32 CMNCR_A, CMNCR_D
+ write32 CS0BCR_A, CS0BCR_D
+ write32 CS0WCR_A, CS0WCR_D
+
+ wait_timer TIMER_D
+
+ /* Setup SDRAM */
+ write32 DBPDCNT0_A, DBPDCNT0_D0
+ write32 DBCONF_A, DBCONF_D
+ write32 DBTR0_A, DBTR0_D
+ write32 DBTR1_A, DBTR1_D
+ write32 DBTR2_A, DBTR2_D
+ write32 DBTR3_A, DBTR3_D
+ write32 DBKIND_A, DBKIND_D
+ write32 DBCKECNT_A, DBCKECNT_D
+
+ wait_timer TIMER_D
+
+ write32 DBCMDCNT_A, DBCMDCNT_D0
+ write32 DBMRCNT_A, DBMRCNT_D0
+ write32 DBMRCNT_A, DBMRCNT_D1
+ write32 DBMRCNT_A, DBMRCNT_D2
+ write32 DBMRCNT_A, DBMRCNT_D3
+ write32 DBCMDCNT_A, DBCMDCNT_D0
+ write32 DBCMDCNT_A, DBCMDCNT_D1
+ write32 DBCMDCNT_A, DBCMDCNT_D1
+ write32 DBMRCNT_A, DBMRCNT_D4
+ write32 DBMRCNT_A, DBMRCNT_D5
+ write32 DBMRCNT_A, DBMRCNT_D6
+
+ wait_timer TIMER_D
+
+ write32 DBEN_A, DBEN_D
+ write32 DBRFPDN1_A, DBRFPDN1_D
+ write32 DBRFPDN2_A, DBRFPDN2_D
+ write32 DBCMDCNT_A, DBCMDCNT_D0
+
+
+ /* Dummy read */
+ mov.l DUMMY_A ,r1
+ synco
+ mov.l @r1, r0
+ synco
+
+ mov.l SDRAM_A ,r1
+ synco
+ mov.l @r1, r0
+ synco
+ wait_timer TIMER_D
+
+ add #4, r1
+ synco
+ mov.l @r1, r0
+ synco
+ wait_timer TIMER_D
+
+ add #4, r1
+ synco
+ mov.l @r1, r0
+ synco
+ wait_timer TIMER_D
+
+ add #4, r1
+ synco
+ mov.l @r1, r0
+ synco
+ wait_timer TIMER_D
+
+ write32 DBCMDCNT_A, DBCMDCNT_D0
+ write32 DBCMDCNT_A, DBCMDCNT_D1
+ write32 DBPDCNT0_A, DBPDCNT0_D1
+ write32 DBRFPDN0_A, DBRFPDN0_D
+
+ wait_timer TIMER_D
+
+ write32 CCR_A, CCR_D
+
+ stc sr, r0
+ mov.l SR_MASK_D, r1
+ and r1, r0
+ ldc r0, sr
+
+ rts
+
+ .align 2
+
+PVDR_A: .long PVDR
+PVDR_D: .long 0x00000001
+JUMP_A: .long CONFIG_ECOVEC_ROMIMAGE_ADDR
+TIMER_D: .long 64
+RWTCSR_A: .long RWTCSR
+RWTCSR_D: .long 0x0000A507
+MMUCR_A: .long MMUCR
+MMUCR_D: .long 0x00000004
+PLLCR_A: .long PLLCR
+PLLCR_D: .long 0x00004000
+FRQCRA_A: .long FRQCRA
+FRQCRA_D: .long 0x8E003508
+FRQCRB_A: .long FRQCRB
+FRQCRB_D: .long 0x0
+MMSELR_A: .long MMSELR
+MMSELR_D: .long 0xA5A50000
+CMNCR_A: .long CMNCR
+CMNCR_D: .long 0x00000013
+CS0BCR_A: .long CS0BCR
+CS0BCR_D: .long 0x11110400
+CS0WCR_A: .long CS0WCR
+CS0WCR_D: .long 0x00000440
+DBPDCNT0_A: .long DBPDCNT0
+DBPDCNT0_D0: .long 0x00000181
+DBPDCNT0_D1: .long 0x00000080
+DBCONF_A: .long DBCONF
+DBCONF_D: .long 0x015B0002
+DBTR0_A: .long DBTR0
+DBTR0_D: .long 0x03061502
+DBTR1_A: .long DBTR1
+DBTR1_D: .long 0x02020102
+DBTR2_A: .long DBTR2
+DBTR2_D: .long 0x01090305
+DBTR3_A: .long DBTR3
+DBTR3_D: .long 0x00000002
+DBKIND_A: .long DBKIND
+DBKIND_D: .long 0x00000005
+DBCKECNT_A: .long DBCKECNT
+DBCKECNT_D: .long 0x00000001
+DBCMDCNT_A: .long DBCMDCNT
+DBCMDCNT_D0:.long 0x2
+DBCMDCNT_D1:.long 0x4
+DBMRCNT_A: .long DBMRCNT
+DBMRCNT_D0: .long 0x00020000
+DBMRCNT_D1: .long 0x00030000
+DBMRCNT_D2: .long 0x00010040
+DBMRCNT_D3: .long 0x00000532
+DBMRCNT_D4: .long 0x00000432
+DBMRCNT_D5: .long 0x000103C0
+DBMRCNT_D6: .long 0x00010040
+DBEN_A: .long DBEN
+DBEN_D: .long 0x01
+DBRFPDN0_A: .long DBRFPDN0
+DBRFPDN1_A: .long DBRFPDN1
+DBRFPDN2_A: .long DBRFPDN2
+DBRFPDN0_D: .long 0x00010000
+DBRFPDN1_D: .long 0x00000613
+DBRFPDN2_D: .long 0x238C003A
+SDRAM_A: .long 0xa8000000
+DUMMY_A: .long 0x0c400000
+CCR_A: .long CCR
+CCR_D: .long 0x0000090B
+SR_MASK_D: .long 0xEFFFFF0F
diff --git a/board/renesas/sh7757lcr/lowlevel_init.S b/board/renesas/sh7757lcr/lowlevel_init.S
index ab1aa49..5090fd0 100644
--- a/board/renesas/sh7757lcr/lowlevel_init.S
+++ b/board/renesas/sh7757lcr/lowlevel_init.S
@@ -326,12 +326,13 @@
/* step 26 */
wait_DBCMD
+#if defined(CONFIG_SH7757LCR_DDR_ECC)
/* enable DDR-ECC */
write32 ECD_ECDEN_A, ECD_ECDEN_D
write32 ECD_INTSR_A, ECD_INTSR_D
write32 ECD_SPACER_A, ECD_SPACER_D
write32 ECD_MCR_A, ECD_MCR_D
-
+#endif
bra exit_ddr
nop
diff --git a/boards.cfg b/boards.cfg
index 67b2d59..d9021aa 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -993,6 +993,7 @@
sh7785lcr sh sh4 sh7785lcr renesas -
sh7785lcr_32bit sh sh4 sh7785lcr renesas - sh7785lcr:SH_32BIT=1
MigoR sh sh4 MigoR renesas -
+ecovec sh sh4 ecovec renesas -
grsim_leon2 sparc leon2 - gaisler
gr_cpci_ax2000 sparc leon3 - gaisler
gr_ep2s60 sparc leon3 - gaisler
diff --git a/common/Makefile b/common/Makefile
index 1b672ad..1be7236 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -152,6 +152,7 @@
COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o
COBJS-$(CONFIG_CMD_TIME) += cmd_time.o
COBJS-$(CONFIG_SYS_HUSH_PARSER) += cmd_test.o
+COBJS-$(CONFIG_CMD_TPM) += cmd_tpm.o
COBJS-$(CONFIG_CMD_TSI148) += cmd_tsi148.o
COBJS-$(CONFIG_CMD_UBI) += cmd_ubi.o
COBJS-$(CONFIG_CMD_UBIFS) += cmd_ubifs.o
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 6c48594..67cb0da 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -26,25 +26,45 @@
*/
#include <common.h>
#include <command.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
-static void print_num(const char *, ulong);
+__maybe_unused
+static void print_num(const char *name, ulong value)
+{
+ printf("%-12s= 0x%08lX\n", name, value);
+}
-#if !(defined(CONFIG_ARM) || defined(CONFIG_M68K) || \
- defined(CONFIG_SANDBOX) || defined(CONFIG_X86)) \
- || defined(CONFIG_CMD_NET)
-#define HAVE_PRINT_ETH
-static void print_eth(int idx);
-#endif
+__maybe_unused
+static void print_eth(int idx)
+{
+ char name[10], *val;
+ if (idx)
+ sprintf(name, "eth%iaddr", idx);
+ else
+ strcpy(name, "ethaddr");
+ val = getenv(name);
+ if (!val)
+ val = "(not set)";
+ printf("%-12s= %s\n", name, val);
+}
-#if (!defined(CONFIG_ARM) && !defined(CONFIG_X86) && !defined(CONFIG_SANDBOX))
-#define HAVE_PRINT_LNUM
-static void print_lnum(const char *, u64);
-#endif
+__maybe_unused
+static void print_lnum(const char *name, u64 value)
+{
+ printf("%-12s= 0x%.8llX\n", name, value);
+}
+
+__maybe_unused
+static void print_mhz(const char *name, unsigned long hz)
+{
+ char buf[32];
+
+ printf("%-12s= %6s MHz\n", name, strmhz(buf, hz));
+}
#if defined(CONFIG_PPC)
-static void print_mhz(const char *, unsigned long);
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@@ -209,8 +229,6 @@
#elif defined(CONFIG_M68K)
-static void print_mhz(const char *, unsigned long);
-
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
bd_t *bd = gd->bd;
@@ -258,8 +276,6 @@
#elif defined(CONFIG_BLACKFIN)
-static void print_mhz(const char *, unsigned long);
-
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
bd_t *bd = gd->bd;
@@ -378,8 +394,6 @@
#elif defined(CONFIG_X86)
-static void print_mhz(const char *, unsigned long);
-
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i;
@@ -465,46 +479,6 @@
#error "a case for this architecture does not exist!"
#endif
-static void print_num(const char *name, ulong value)
-{
- printf("%-12s= 0x%08lX\n", name, value);
-}
-
-#ifdef HAVE_PRINT_ETH
-static void print_eth(int idx)
-{
- char name[10], *val;
- if (idx)
- sprintf(name, "eth%iaddr", idx);
- else
- strcpy(name, "ethaddr");
- val = getenv(name);
- if (!val)
- val = "(not set)";
- printf("%-12s= %s\n", name, val);
-}
-#endif
-
-#ifdef HAVE_PRINT_LNUM
-static void print_lnum(const char *name, u64 value)
-{
- printf("%-12s= 0x%.8llX\n", name, value);
-}
-#endif
-
-#if defined(CONFIG_PPC) || \
- defined(CONFIG_M68K) || \
- defined(CONFIG_BLACKFIN) || \
- defined(CONFIG_X86)
-static void print_mhz(const char *name, unsigned long hz)
-{
- char buf[32];
-
- printf("%-12s= %6s MHz\n", name, strmhz(buf, hz));
-}
-#endif /* CONFIG_PPC */
-
-
/* -------------------------------------------------------------------- */
U_BOOT_CMD(
diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c
index 3efd700..9426f5b 100644
--- a/common/cmd_pxe.c
+++ b/common/cmd_pxe.c
@@ -1273,10 +1273,21 @@
menu_destroy(m);
- if (err < 1)
- return;
+ /*
+ * err == 1 means we got a choice back from menu_get_choice.
+ *
+ * err == -ENOENT if the menu was setup to select the default but no
+ * default was set. in that case, we should continue trying to boot
+ * labels that haven't been attempted yet.
+ *
+ * otherwise, the user interrupted or there was some other error and
+ * we give up.
+ */
- label_boot(choice);
+ if (err == 1)
+ label_boot(choice);
+ else if (err != -ENOENT)
+ return;
boot_unattempted_labels(cfg);
}
diff --git a/common/cmd_tpm.c b/common/cmd_tpm.c
new file mode 100644
index 0000000..6f5cd48
--- /dev/null
+++ b/common/cmd_tpm.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <tpm.h>
+
+#define MAX_TRANSACTION_SIZE 30
+
+/*
+ * tpm_write() expects a variable number of parameters: the internal address
+ * followed by data to write, byte by byte.
+ *
+ * Returns 0 on success or -1 on errors (wrong arguments or TPM failure).
+ */
+static int tpm_process(int argc, char * const argv[], cmd_tbl_t *cmdtp)
+{
+ u8 tpm_buffer[MAX_TRANSACTION_SIZE];
+ u32 write_size, read_size;
+ char *p;
+ int rv = -1;
+
+ for (write_size = 0; write_size < argc; write_size++) {
+ u32 datum = simple_strtoul(argv[write_size], &p, 0);
+ if (*p || (datum > 0xff)) {
+ printf("\n%s: bad data value\n\n", argv[write_size]);
+ cmd_usage(cmdtp);
+ return rv;
+ }
+ tpm_buffer[write_size] = (u8)datum;
+ }
+
+ read_size = sizeof(tpm_buffer);
+ if (!tis_sendrecv(tpm_buffer, write_size, tpm_buffer, &read_size)) {
+ int i;
+ puts("Got TPM response:\n");
+ for (i = 0; i < read_size; i++)
+ printf(" %2.2x", tpm_buffer[i]);
+ puts("\n");
+ rv = 0;
+ } else {
+ puts("tpm command failed\n");
+ }
+ return rv;
+}
+
+static int do_tpm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rv = 0;
+
+ /*
+ * Verify that in case it is present, the first argument, it is
+ * exactly one character in size.
+ */
+ if (argc < 7) {
+ puts("command should be at least six bytes in size\n");
+ return -1;
+ }
+
+ if (tis_init()) {
+ puts("tis_init() failed!\n");
+ return -1;
+ }
+
+ if (tis_open()) {
+ puts("tis_open() failed!\n");
+ return -1;
+ }
+
+ rv = tpm_process(argc - 1, argv + 1, cmdtp);
+
+ if (tis_close()) {
+ puts("tis_close() failed!\n");
+ rv = -1;
+ }
+
+ return rv;
+}
+
+U_BOOT_CMD(tpm, MAX_TRANSACTION_SIZE, 1, do_tpm,
+ "<byte> [<byte> ...] - write data and read response",
+ "send arbitrary data (at least 6 bytes) to the TPM "
+ "device and read the response"
+);
diff --git a/common/env_nand.c b/common/env_nand.c
index ce13def..3cb75c8 100644
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -30,8 +30,6 @@
* MA 02111-1307 USA
*/
-#define DEBUG
-
#include <common.h>
#include <command.h>
#include <environment.h>
diff --git a/common/exports.c b/common/exports.c
index 717e4af..b97ca48 100644
--- a/common/exports.c
+++ b/common/exports.c
@@ -1,5 +1,6 @@
#include <common.h>
#include <exports.h>
+#include <spi.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/common/menu.c b/common/menu.c
index ca1baef..5e0817c 100644
--- a/common/menu.c
+++ b/common/menu.c
@@ -88,7 +88,7 @@
void *extra)
{
if (!m->item_data_print) {
- putc(item->key);
+ puts(item->key);
putc('\n');
} else {
m->item_data_print(item->data);
diff --git a/common/miiphyutil.c b/common/miiphyutil.c
index 35ad357..2cc23b4 100644
--- a/common/miiphyutil.c
+++ b/common/miiphyutil.c
@@ -102,6 +102,7 @@
/*****************************************************************************
*
* Register read and write MII access routines for the device <name>.
+ * This API is now deprecated. Please use mdio_alloc and mdio_register, instead.
*/
void miiphy_register(const char *name,
int (*read)(const char *devname, unsigned char addr,
@@ -281,6 +282,8 @@
* Read to variable <value> from the PHY attached to device <devname>,
* use PHY address <addr> and register <reg>.
*
+ * This API is deprecated. Use phy_read on a phy_device found via phy_connect
+ *
* Returns:
* 0 on success
*/
@@ -307,6 +310,8 @@
* Write <value> to the PHY attached to device <devname>,
* use PHY address <addr> and register <reg>.
*
+ * This API is deprecated. Use phy_write on a phy_device found by phy_connect
+ *
* Returns:
* 0 on success
*/
@@ -350,6 +355,8 @@
* Model: 6 bits (unsigned char)
* Revision: 4 bits (unsigned char)
*
+ * This API is deprecated.
+ *
* Returns:
* 0 on success
*/
@@ -389,6 +396,9 @@
/*****************************************************************************
*
* Reset the PHY.
+ *
+ * This API is deprecated. Use PHYLIB.
+ *
* Returns:
* 0 on success
*/
diff --git a/common/serial.c b/common/serial.c
index 5b83d6a..75cc1bb 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -29,8 +29,8 @@
DECLARE_GLOBAL_DATA_PTR;
-static struct serial_device *serial_devices = NULL;
-static struct serial_device *serial_current = NULL;
+static struct serial_device *serial_devices;
+static struct serial_device *serial_current;
void serial_register(struct serial_device *dev)
{
@@ -47,14 +47,14 @@
serial_devices = dev;
}
-void serial_initialize (void)
+void serial_initialize(void)
{
#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
- serial_register (&serial_smc_device);
+ serial_register(&serial_smc_device);
#endif
-#if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \
- || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
- serial_register (&serial_scc_device);
+#if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
+ defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
+ serial_register(&serial_scc_device);
#endif
#if defined(CONFIG_SYS_NS16550_SERIAL)
@@ -71,13 +71,13 @@
serial_register(&eserial4_device);
#endif
#endif /* CONFIG_SYS_NS16550_SERIAL */
-#if defined (CONFIG_FFUART)
+#if defined(CONFIG_FFUART)
serial_register(&serial_ffuart_device);
#endif
-#if defined (CONFIG_BTUART)
+#if defined(CONFIG_BTUART)
serial_register(&serial_btuart_device);
#endif
-#if defined (CONFIG_STUART)
+#if defined(CONFIG_STUART)
serial_register(&serial_stuart_device);
#endif
#if defined(CONFIG_S3C2410)
@@ -122,18 +122,18 @@
serial_register(&uartlite_serial3_device);
# endif /* XILINX_UARTLITE_BASEADDR3 */
#endif /* CONFIG_XILINX_UARTLITE */
- serial_assign (default_serial_console ()->name);
+ serial_assign(default_serial_console()->name);
}
-void serial_stdio_init (void)
+void serial_stdio_init(void)
{
struct stdio_dev dev;
struct serial_device *s = serial_devices;
while (s) {
- memset (&dev, 0, sizeof (dev));
+ memset(&dev, 0, sizeof(dev));
- strcpy (dev.name, s->name);
+ strcpy(dev.name, s->name);
dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT;
dev.start = s->init;
@@ -143,18 +143,18 @@
dev.getc = s->getc;
dev.tstc = s->tstc;
- stdio_register (&dev);
+ stdio_register(&dev);
s = s->next;
}
}
-int serial_assign (char *name)
+int serial_assign(const char *name)
{
struct serial_device *s;
for (s = serial_devices; s; s = s->next) {
- if (strcmp (s->name, name) == 0) {
+ if (strcmp(s->name, name) == 0) {
serial_current = s;
return 0;
}
@@ -163,13 +163,12 @@
return 1;
}
-void serial_reinit_all (void)
+void serial_reinit_all(void)
{
struct serial_device *s;
- for (s = serial_devices; s; s = s->next) {
- s->init ();
- }
+ for (s = serial_devices; s; s = s->next)
+ s->init();
}
static struct serial_device *get_current(void)
@@ -192,27 +191,27 @@
return get_current()->init();
}
-void serial_setbrg (void)
+void serial_setbrg(void)
{
get_current()->setbrg();
}
-int serial_getc (void)
+int serial_getc(void)
{
return get_current()->getc();
}
-int serial_tstc (void)
+int serial_tstc(void)
{
return get_current()->tstc();
}
-void serial_putc (const char c)
+void serial_putc(const char c)
{
get_current()->putc(c);
}
-void serial_puts (const char *s)
+void serial_puts(const char *s)
{
get_current()->puts(s);
}
diff --git a/disk/part_efi.c b/disk/part_efi.c
index e7f2714..ddf80a7 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -130,7 +130,7 @@
}
/* This function validates AND fills in the GPT header and PTE */
if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
- &(gpt_head), &gpt_pte) != 1) {
+ gpt_head, &gpt_pte) != 1) {
printf("%s: *** ERROR: Invalid GPT ***\n", __func__);
return;
}
@@ -169,7 +169,7 @@
/* This function validates AND fills in the GPT header and PTE */
if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
- &(gpt_head), &gpt_pte) != 1) {
+ gpt_head, &gpt_pte) != 1) {
printf("%s: *** ERROR: Invalid GPT ***\n", __func__);
return -1;
}
diff --git a/doc/README.sh7757lcr b/doc/README.sh7757lcr
index 49fea50..109f715 100644
--- a/doc/README.sh7757lcr
+++ b/doc/README.sh7757lcr
@@ -61,3 +61,17 @@
ETHERC ch1 = 00:00:87:6c:21:81
GETHERC ch0 = 00:00:87:6c:21:82
GETHERC ch1 = 00:00:87:6c:21:83
+
+
+Update SPI ROM:
+============================
+
+1. Copy u-boot image to RAM area.
+2. Probe SPI device.
+ => sf probe 0
+ 8192 KiB M25P64 at 0:0 is now current device
+3. Erase SPI ROM.
+ => sf erase 0 80000
+4. Write u-boot image to SPI ROM.
+ => sf write 0x89000000 0 80000
+
diff --git a/doc/feature-removal-schedule.txt b/doc/feature-removal-schedule.txt
index 00d87e4..e04ba2d 100644
--- a/doc/feature-removal-schedule.txt
+++ b/doc/feature-removal-schedule.txt
@@ -7,6 +7,17 @@
---------------------------
+What: Users of the legacy miiphy_* code
+When: undetermined
+
+Why: We now have a PHY library, which allows everyone to share PHY
+ drivers. All new drivers should use this infrastructure, and
+ all old drivers should get converted to use it.
+
+Who: Andy Fleming <afleming@freescale.com> and driver maintainers
+
+---------------------------
+
What: boards with xxx_config targets in top level Makefile
When: Release v2012.03
diff --git a/doc/git-mailrc b/doc/git-mailrc
new file mode 100644
index 0000000..4039e55
--- /dev/null
+++ b/doc/git-mailrc
@@ -0,0 +1,101 @@
+# To use this file, run in your u-boot tree:
+# git config sendemail.aliasesfile doc/git-mailrc
+# git config sendemail.aliasfiletype mutt
+#
+# Then when sending patches, you can use:
+# git send-email --to u-boot --cc i2c ...
+
+alias uboot u-boot@lists.denx.de
+alias u-boot uboot
+
+# Maintainer aliases. Use the same alias here as patchwork to keep
+# things simple and easy to look up/coordinate.
+alias aaribaud Albert Aribaud <albert.u.boot@aribaud.net>
+alias afleming Andy Fleming <afleming@freescale.com>
+alias ag Anatolij Gustschin <agust@denx.de>
+alias galak Kumar Gala <galak@kernel.crashing.org>
+alias gruss Graeme Russ <graeme.russ@gmail.com>
+alias hs Heiko Schocher <hs@denx.de>
+alias iwamatsu Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+alias jasonjin Jason Jin <jason.jin@freescale.com>
+alias kimphill Kim Phillips <kim.phillips@freescale.com>
+alias macpaul Macpaul Lin <macpaul@andestech.com>
+alias marex Marek Vasut <marek.vasut@gmail.com>
+alias monstr Michal Simek <monstr@monstr.eu>
+alias prafulla Prafulla Wadaskar <prafulla@marvell.com>
+alias prom Minkyu Kang <mk7.kang@samsung.com>
+alias rbohmer Remy Bohmer <linux@bohmer.net>
+alias reinhardm Reinhard Meyer <u-boot@emk-elektronik.de>
+alias sbabic Stefano Babic <sbabic@denx.de>
+alias scottwood Scott Wood <scottwood@freescale.com>
+alias smcnutt Scott McNutt <smcnutt@psyent.com>
+alias stroese Stefan Roese <sr@denx.de>
+alias vapier Mike Frysinger <vapier@gentoo.org>
+alias wd Wolfgang Denk <wd@denx.de>
+
+# Architecture aliases
+alias arch arm, avr32, bfin, m68k, microblaze, mips, nds32, nios2, powerpc, sandbox, superh, sparc, x86
+alias arches arch
+
+alias arm uboot, aaribaud
+alias at91 uboot, reinhardm
+alias davinci omap
+alias imx uboot, sbabic
+alias kirkwood uboot, prafulla
+alias omap uboot, Sandeep Paulraj <s-paulraj@ti.com>
+alias pxa uboot, marex
+alias s3c samsung
+alias s5pc samsung
+alias samsung uboot, prom
+alias tegra uboot, Simon Glass <sjg@chromium.org>, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com>
+alias tegra2 tegra
+
+alias avr32 uboot, reinhardm
+
+alias bfin uboot, vapier
+alias blackfin bfin
+
+alias m68k uboot, jasonjin
+alias coldfire m68k
+
+alias microblaze uboot, monstr
+alias mb microblaze
+
+alias mips uboot, Shinya Kuribayashi <skuribay@pobox.com>
+
+alias nds32 uboot, macpaul
+
+alias nios uboot, Thomas Chou <thomas@wytron.com.tw>, smcnutt
+alias nios2 nios
+
+alias powerpc uboot, afleming, kimphill, galak, stroese, wd
+alias ppc powerpc
+alias mpc5xxx uboot, wd
+alias mpc8xx uboot, wd
+alias mpc82xx uboot, wd
+alias mpc83xx uboot, kimphill
+alias mpc85xx uboot, afleming, galak
+alias mpc86xx uboot, afleming, galak
+alias ppc4xx uboot, stroese
+alias ppc7xx uboot, wd
+alias ppc74xx uboot, wd
+
+alias sandbox Simon Glass <sjg@chromium.org>
+alias sb sandbox
+
+alias sparc uboot, Daniel Hellstrom <daniel@gaisler.com>
+
+alias superh uboot, iwamatsu
+alias sh superh
+
+alias x86 uboot, gruss
+
+# Subsystem aliases
+alias cfi uboot, stroese
+alias fdt uboot, Jerry Van Baren <vanbaren@cideas.com>
+alias i2c uboot, hs
+alias mmc uboot, afleming
+alias nand uboot, scottwood
+alias net uboot, wd
+alias usb uboot, rbohmer
+alias video uboot, ag
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index ced4c94..f689cc4 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -233,8 +233,7 @@
goto out;
}
- debug("SF: Successfully erased %zu bytes @ %#x\n",
- len * erase_size, start);
+ debug("SF: Successfully erased %zu bytes @ %#x\n", len, start);
out:
spi_release_bus(flash->spi);
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index fd13428..de7cdd7 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -531,6 +531,7 @@
struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
void *p = (void *)dataptr;
u32 cmd_sts;
+ u32 txuq0_reg_addr;
/* Copy buffer if it's misaligned */
if ((u32) dataptr & 0x07) {
@@ -552,7 +553,8 @@
p_txdesc->byte_cnt = datasize;
/* Set this tc desc as zeroth TXUQ */
- MVGBE_REG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
+ txuq0_reg_addr = (u32)®s->tcqdp[TXUQ];
+ writel((u32) p_txdesc, txuq0_reg_addr);
/* ensure tx desc writes above are performed before we start Tx DMA */
isb();
@@ -583,6 +585,7 @@
struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
u32 cmd_sts;
u32 timeout = 0;
+ u32 rxdesc_curr_addr;
/* wait untill rx packet available or timeout */
do {
@@ -637,8 +640,8 @@
p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
p_rxdesc_curr->byte_cnt = 0;
- writel((unsigned)p_rxdesc_curr->nxtdesc_p,
- (u32) &dmvgbe->p_rxdesc_curr);
+ rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr;
+ writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr);
return 0;
}
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index a59834b..feced39 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -38,6 +38,7 @@
COBJS-$(CONFIG_PHY_MICREL) += micrel.o
COBJS-$(CONFIG_PHY_NATSEMI) += natsemi.o
COBJS-$(CONFIG_PHY_REALTEK) += realtek.o
+COBJS-$(CONFIG_PHY_SMSC) += smsc.o
COBJS-$(CONFIG_PHY_TERANETICS) += teranetics.o
COBJS-$(CONFIG_PHY_VITESSE) += vitesse.o
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index bd1cdc4..e51e799 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -43,6 +43,24 @@
#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
+/* 88E1111 Extended PHY Specific Control Register */
+#define MIIM_88E1111_PHY_EXT_CR 0x14
+#define MIIM_88E1111_RX_DELAY 0x80
+#define MIIM_88E1111_TX_DELAY 0x2
+
+/* 88E1111 Extended PHY Specific Status Register */
+#define MIIM_88E1111_PHY_EXT_SR 0x1b
+#define MIIM_88E1111_HWCFG_MODE_MASK 0xf
+#define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb
+#define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3
+#define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4
+#define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9
+#define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000
+#define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000
+
+#define MIIM_88E1111_COPPER 0
+#define MIIM_88E1111_FIBER 1
+
/* 88E1118 PHY defines */
#define MIIM_88E1118_PHY_PAGE 22
#define MIIM_88E1118_PHY_LED_PAGE 3
@@ -162,19 +180,102 @@
static int m88e1111s_config(struct phy_device *phydev)
{
int reg;
+ int timeout;
if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
- reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x1b);
- reg = (reg & 0xfff0) | 0xb;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1b, reg);
- } else {
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1b, 0x1f);
+ reg = phy_read(phydev,
+ MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
+ if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
+ (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
+ reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
+ } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
+ reg &= ~MIIM_88E1111_TX_DELAY;
+ reg |= MIIM_88E1111_RX_DELAY;
+ } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
+ reg &= ~MIIM_88E1111_RX_DELAY;
+ reg |= MIIM_88E1111_TX_DELAY;
+ }
+
+ phy_write(phydev,
+ MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
+
+ reg = phy_read(phydev,
+ MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
+
+ reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
+
+ if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES)
+ reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII;
+ else
+ reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;
+
+ phy_write(phydev,
+ MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg);
+ }
+
+ if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
+ reg = phy_read(phydev,
+ MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
+
+ reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
+ reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
+ reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
+
+ phy_write(phydev, MDIO_DEVAD_NONE,
+ MIIM_88E1111_PHY_EXT_SR, reg);
+ }
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
+ reg = phy_read(phydev,
+ MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
+ reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
+ phy_write(phydev,
+ MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
+
+ reg = phy_read(phydev, MDIO_DEVAD_NONE,
+ MIIM_88E1111_PHY_EXT_SR);
+ reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
+ MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
+ reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
+ phy_write(phydev, MDIO_DEVAD_NONE,
+ MIIM_88E1111_PHY_EXT_SR, reg);
+
+ /* soft reset */
+ timeout = 1000;
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
+ udelay(1000);
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
+ while ((reg & BMCR_RESET) && --timeout) {
+ udelay(1000);
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
+ }
+ if (!timeout)
+ printf("%s: phy soft reset timeout\n", __func__);
+
+ reg = phy_read(phydev, MDIO_DEVAD_NONE,
+ MIIM_88E1111_PHY_EXT_SR);
+ reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
+ MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
+ reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI |
+ MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
+ phy_write(phydev, MDIO_DEVAD_NONE,
+ MIIM_88E1111_PHY_EXT_SR, reg);
}
- phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0cd2);
+ /* soft reset */
+ timeout = 1000;
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
+ udelay(1000);
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
+ while ((reg & BMCR_RESET) && --timeout) {
+ udelay(1000);
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
+ }
+ if (!timeout)
+ printf("%s: phy soft reset timeout\n", __func__);
genphy_config_aneg(phydev);
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 8da7688..eb55180 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -444,6 +444,9 @@
#ifdef CONFIG_PHY_REALTEK
phy_realtek_init();
#endif
+#ifdef CONFIG_PHY_SMSC
+ phy_smsc_init();
+#endif
#ifdef CONFIG_PHY_TERANETICS
phy_teranetics_init();
#endif
diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
new file mode 100644
index 0000000..6dee8eb
--- /dev/null
+++ b/drivers/net/phy/smsc.c
@@ -0,0 +1,92 @@
+/*
+ * SMSC PHY drivers
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Base code from drivers/net/phy/davicom.c
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * author Andy Fleming
+ *
+ * Some code get from linux kenrel
+ * Copyright (c) 2006 Herbert Valerio Riedel <hvr@gnu.org>
+ *
+ */
+#include <miiphy.h>
+
+static int smsc_parse_status(struct phy_device *phydev)
+{
+ int mii_reg;
+
+ mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
+
+ if (mii_reg & (BMSR_100FULL | BMSR_100HALF))
+ phydev->speed = SPEED_100;
+ else
+ phydev->speed = SPEED_10;
+
+ if (mii_reg & (BMSR_10FULL | BMSR_100FULL))
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+
+ return 0;
+}
+
+static int smsc_startup(struct phy_device *phydev)
+{
+ genphy_update_link(phydev);
+ smsc_parse_status(phydev);
+ return 0;
+}
+
+static struct phy_driver lan8700_driver = {
+ .name = "SMSC LAN8700",
+ .uid = 0x0007c0c0,
+ .mask = 0xffff0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &genphy_config_aneg,
+ .startup = &smsc_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+static struct phy_driver lan911x_driver = {
+ .name = "SMSC LAN911x Internal PHY",
+ .uid = 0x0007c0d0,
+ .mask = 0xffff0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &genphy_config_aneg,
+ .startup = &smsc_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+static struct phy_driver lan8710_driver = {
+ .name = "SMSC LAN8710/LAN8720",
+ .uid = 0x0007c0f0,
+ .mask = 0xffff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = &genphy_config_aneg,
+ .startup = &smsc_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+int phy_smsc_init(void)
+{
+ phy_register(&lan8710_driver);
+ phy_register(&lan911x_driver);
+ phy_register(&lan8700_driver);
+
+ return 0;
+}
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 17dd0d2..27d0401 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -25,6 +25,7 @@
#include <malloc.h>
#include <net.h>
#include <netdev.h>
+#include <miiphy.h>
#include <asm/errno.h>
#include <asm/io.h>
@@ -45,144 +46,6 @@
#define SH_ETH_PHY_DELAY 50000
-/*
- * Bits are written to the PHY serially using the
- * PIR register, just like a bit banger.
- */
-static void sh_eth_mii_write_phy_bits(int port, u32 val, int len)
-{
- int i;
- u32 pir;
-
- /* Bit positions is 1 less than the number of bits */
- for (i = len - 1; i >= 0; i--) {
- /* Write direction, bit to write, clock is low */
- pir = 2 | ((val & 1 << i) ? 1 << 2 : 0);
- outl(pir, PIR(port));
- udelay(1);
- /* Write direction, bit to write, clock is high */
- pir = 3 | ((val & 1 << i) ? 1 << 2 : 0);
- outl(pir, PIR(port));
- udelay(1);
- /* Write direction, bit to write, clock is low */
- pir = 2 | ((val & 1 << i) ? 1 << 2 : 0);
- outl(pir, PIR(port));
- udelay(1);
- }
-}
-
-static void sh_eth_mii_bus_release(int port)
-{
- /* Read direction, clock is low */
- outl(0, PIR(port));
- udelay(1);
- /* Read direction, clock is high */
- outl(1, PIR(port));
- udelay(1);
- /* Read direction, clock is low */
- outl(0, PIR(port));
- udelay(1);
-}
-
-static void sh_eth_mii_ind_bus_release(int port)
-{
- /* Read direction, clock is low */
- outl(0, PIR(port));
- udelay(1);
-}
-
-static void sh_eth_mii_read_phy_bits(int port, u32 *val, int len)
-{
- int i;
- u32 pir;
-
- *val = 0;
- for (i = len - 1; i >= 0; i--) {
- /* Read direction, clock is high */
- outl(1, PIR(port));
- udelay(1);
- /* Read bit */
- pir = inl(PIR(port));
- *val |= (pir & 8) ? 1 << i : 0;
- /* Read direction, clock is low */
- outl(0, PIR(port));
- udelay(1);
- }
-}
-
-#define PHY_INIT 0xFFFFFFFF
-#define PHY_READ 0x02
-#define PHY_WRITE 0x01
-/*
- * To read a phy register, mii managements frames are sent to the phy.
- * The frames look like this:
- * pre (32 bits): 0xffff ffff
- * st (2 bits): 01
- * op (2bits): 10: read 01: write
- * phyad (5 bits): xxxxx
- * regad (5 bits): xxxxx
- * ta (Bus release):
- * data (16 bits): read data
- */
-static u32 sh_eth_mii_read_phy_reg(int port, u8 phy_addr, int reg)
-{
- u32 val;
-
- /* Sent mii management frame */
- /* pre */
- sh_eth_mii_write_phy_bits(port, PHY_INIT, 32);
- /* st (start of frame) */
- sh_eth_mii_write_phy_bits(port, 0x1, 2);
- /* op (code) */
- sh_eth_mii_write_phy_bits(port, PHY_READ, 2);
- /* phy address */
- sh_eth_mii_write_phy_bits(port, phy_addr, 5);
- /* Register to read */
- sh_eth_mii_write_phy_bits(port, reg, 5);
-
- /* Bus release */
- sh_eth_mii_bus_release(port);
-
- /* Read register */
- sh_eth_mii_read_phy_bits(port, &val, 16);
-
- return val;
-}
-
-/*
- * To write a phy register, mii managements frames are sent to the phy.
- * The frames look like this:
- * pre (32 bits): 0xffff ffff
- * st (2 bits): 01
- * op (2bits): 10: read 01: write
- * phyad (5 bits): xxxxx
- * regad (5 bits): xxxxx
- * ta (2 bits): 10
- * data (16 bits): write data
- * idle (Independent bus release)
- */
-static void sh_eth_mii_write_phy_reg(int port, u8 phy_addr, int reg, u16 val)
-{
- /* Sent mii management frame */
- /* pre */
- sh_eth_mii_write_phy_bits(port, PHY_INIT, 32);
- /* st (start of frame) */
- sh_eth_mii_write_phy_bits(port, 0x1, 2);
- /* op (code) */
- sh_eth_mii_write_phy_bits(port, PHY_WRITE, 2);
- /* phy address */
- sh_eth_mii_write_phy_bits(port, phy_addr, 5);
- /* Register to read */
- sh_eth_mii_write_phy_bits(port, reg, 5);
- /* ta */
- sh_eth_mii_write_phy_bits(port, PHY_READ, 2);
- /* Write register data */
- sh_eth_mii_write_phy_bits(port, val, 16);
-
- /* Independent bus release */
- sh_eth_mii_ind_bus_release(port);
-}
-
int sh_eth_send(struct eth_device *dev, volatile void *packet, int len)
{
struct sh_eth_dev *eth = dev->priv;
@@ -480,62 +343,26 @@
static int sh_eth_phy_config(struct sh_eth_dev *eth)
{
- int port = eth->port, timeout, ret = 0;
+ int port = eth->port, ret = 0;
struct sh_eth_info *port_info = ð->port_info[port];
- u32 val;
-
- /* Reset phy */
- sh_eth_mii_write_phy_reg
- (port, port_info->phy_addr, PHY_CTRL, PHY_C_RESET);
- timeout = 10;
- while (timeout--) {
- val = sh_eth_mii_read_phy_reg(port,
- port_info->phy_addr, PHY_CTRL);
- if (!(val & PHY_C_RESET))
- break;
- udelay(SH_ETH_PHY_DELAY);
- }
-
- if (timeout < 0) {
- printf(SHETHER_NAME ": phy reset timeout\n");
- ret = -EIO;
- goto err_tout;
- }
-
- /* Advertise 100/10 baseT full/half duplex */
- sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_ANA,
- (PHY_A_FDX|PHY_A_HDX|PHY_A_10FDX|PHY_A_10HDX|PHY_A_EXT));
- /* Autonegotiation, normal operation, full duplex, enable tx */
- sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL,
- (PHY_C_ANEGEN|PHY_C_RANEG));
- /* Wait for autonegotiation to complete */
- timeout = 100;
- while (timeout--) {
- val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1);
- if (val & PHY_S_ANEGC)
- break;
-
- udelay(SH_ETH_PHY_DELAY);
- }
-
- if (timeout < 0) {
- printf(SHETHER_NAME ": phy auto-negotiation failed\n");
- ret = -ETIMEDOUT;
- goto err_tout;
- }
+ struct eth_device *dev = port_info->dev;
+ struct phy_device *phydev;
- return ret;
+ phydev = phy_connect(miiphy_get_dev_by_name(dev->name),
+ port_info->phy_addr, dev, PHY_INTERFACE_MODE_MII);
+ port_info->phydev = phydev;
+ phy_config(phydev);
-err_tout:
return ret;
}
static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
{
int port = eth->port, ret = 0;
- u32 val, phy_status;
+ u32 val;
struct sh_eth_info *port_info = ð->port_info[port];
struct eth_device *dev = port_info->dev;
+ struct phy_device *phy;
/* Configure e-dmac registers */
outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port));
@@ -582,31 +409,31 @@
printf(SHETHER_NAME ": phy config timeout\n");
goto err_phy_cfg;
}
- /* Read phy status to finish configuring the e-mac */
- phy_status = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1);
+ phy = port_info->phydev;
+ phy_startup(phy);
/* Set the transfer speed */
#ifdef CONFIG_CPU_SH7763
- if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) {
+ if (phy->speed == 100) {
printf(SHETHER_NAME ": 100Base/");
outl(GECMR_100B, GECMR(port));
- } else {
+ } else if (phy->speed == 10) {
printf(SHETHER_NAME ": 10Base/");
outl(GECMR_10B, GECMR(port));
}
#endif
#if defined(CONFIG_CPU_SH7757)
- if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) {
+ if (phy->speed == 100) {
printf("100Base/");
outl(1, RTRATE(port));
- } else {
+ } else if (phy->speed == 10) {
printf("10Base/");
outl(0, RTRATE(port));
}
#endif
/* Check if full duplex mode is supported by the phy */
- if (phy_status & (PHY_S_100X_F|PHY_S_10T_F)) {
+ if (phy->duplex) {
printf("Full\n");
outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
} else {
@@ -707,6 +534,9 @@
/* Register Device to EtherNet subsystem */
eth_register(dev);
+ bb_miiphy_buses[0].priv = eth;
+ miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);
+
if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
puts("Please set MAC address\n");
@@ -722,3 +552,86 @@
printf(SHETHER_NAME ": Failed\n");
return ret;
}
+
+/******* for bb_miiphy *******/
+static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
+{
+ return 0;
+}
+
+static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
+{
+ struct sh_eth_dev *eth = bus->priv;
+ int port = eth->port;
+
+ outl(inl(PIR(port)) | PIR_MMD, PIR(port));
+
+ return 0;
+}
+
+static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+ struct sh_eth_dev *eth = bus->priv;
+ int port = eth->port;
+
+ outl(inl(PIR(port)) & ~PIR_MMD, PIR(port));
+
+ return 0;
+}
+
+static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+ struct sh_eth_dev *eth = bus->priv;
+ int port = eth->port;
+
+ if (v)
+ outl(inl(PIR(port)) | PIR_MDO, PIR(port));
+ else
+ outl(inl(PIR(port)) & ~PIR_MDO, PIR(port));
+
+ return 0;
+}
+
+static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+ struct sh_eth_dev *eth = bus->priv;
+ int port = eth->port;
+
+ *v = (inl(PIR(port)) & PIR_MDI) >> 3;
+
+ return 0;
+}
+
+static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+ struct sh_eth_dev *eth = bus->priv;
+ int port = eth->port;
+
+ if (v)
+ outl(inl(PIR(port)) | PIR_MDC, PIR(port));
+ else
+ outl(inl(PIR(port)) & ~PIR_MDC, PIR(port));
+
+ return 0;
+}
+
+static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
+{
+ udelay(10);
+
+ return 0;
+}
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+ {
+ .name = "sh_eth",
+ .init = sh_eth_bb_init,
+ .mdio_active = sh_eth_bb_mdio_active,
+ .mdio_tristate = sh_eth_bb_mdio_tristate,
+ .set_mdio = sh_eth_bb_set_mdio,
+ .get_mdio = sh_eth_bb_get_mdio,
+ .set_mdc = sh_eth_bb_set_mdc,
+ .delay = sh_eth_bb_delay,
+ }
+};
+int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 51e5d5b..dd6a422 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -89,6 +89,7 @@
u8 mac_addr[6];
u8 phy_addr;
struct eth_device *dev;
+ struct phy_device *phydev;
};
struct sh_eth_dev {
@@ -435,61 +436,3 @@
FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
};
-enum PHY_OFFSETS {
- PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
- PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
- PHY_16 = 16,
-};
-
-/* PHY_CTRL */
-enum PHY_CTRL_BIT {
- PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
- PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
- PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
-};
-#define DM9161_PHY_C_ANEGEN 0 /* auto nego special */
-
-/* PHY_STAT */
-enum PHY_STAT_BIT {
- PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
- PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
- PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
- PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
-};
-
-/* PHY_ANA */
-enum PHY_ANA_BIT {
- PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
- PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
- PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
- PHY_A_SEL = 0x001e,
- PHY_A_EXT = 0x0001,
-};
-
-/* PHY_ANL */
-enum PHY_ANL_BIT {
- PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
- PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
- PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
- PHY_L_SEL = 0x001f,
-};
-
-/* PHY_ANE */
-enum PHY_ANE_BIT {
- PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
- PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
-};
-
-/* DM9161 */
-enum PHY_16_BIT {
- PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
- PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
- PHY_16_TXselect = 0x0400,
- PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
- PHY_16_Force100LNK = 0x0080,
- PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
- PHY_16_RPDCTR_EN = 0x0010,
- PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
- PHY_16_Sleepmode = 0x0002,
- PHY_16_RemoteLoopOut = 0x0001,
-};
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index ee0c64d..1ae35d3 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -27,6 +27,7 @@
COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
COBJS-$(CONFIG_PCI) += pci.o pci_auto.o pci_indirect.o
+COBJS-$(CONFIG_FTPCI100) += pci_ftpci100.o
COBJS-$(CONFIG_IXP_PCI) += pci_ixp.o
COBJS-$(CONFIG_SH4_PCI) += pci_sh4.o
COBJS-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
diff --git a/drivers/pci/pci_ftpci100.c b/drivers/pci/pci_ftpci100.c
new file mode 100644
index 0000000..a795a97
--- /dev/null
+++ b/drivers/pci/pci_ftpci100.c
@@ -0,0 +1,330 @@
+/*
+ * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <common.h>
+#include <malloc.h>
+#include <pci.h>
+
+#include <asm/io.h>
+#include <asm/types.h> /* u32, u16.... used by pci.h */
+
+#include "pci_ftpci100.h"
+
+struct ftpci100_data {
+ unsigned int reg_base;
+ unsigned int io_base;
+ unsigned int mem_base;
+ unsigned int mmio_base;
+ unsigned int ndevs;
+};
+
+static struct pci_config devs[FTPCI100_MAX_FUNCTIONS];
+static struct pci_controller local_hose;
+
+static void setup_pci_bar(unsigned int bus, unsigned int dev, unsigned func,
+ unsigned char header, struct ftpci100_data *priv)
+{
+ struct pci_controller *hose = (struct pci_controller *)&local_hose;
+ unsigned int i, tmp32, bar_no, iovsmem = 1;
+ pci_dev_t dev_nu;
+
+ /* A device is present, add an entry to the array */
+ devs[priv->ndevs].bus = bus;
+ devs[priv->ndevs].dev = dev;
+ devs[priv->ndevs].func = func;
+
+ dev_nu = PCI_BDF(bus, dev, func);
+
+ if ((header & 0x7f) == 0x01)
+ /* PCI-PCI Bridge */
+ bar_no = 2;
+ else
+ bar_no = 6;
+
+ /* Allocate address spaces by configuring BARs */
+ for (i = 0; i < bar_no; i++) {
+ pci_hose_write_config_dword(hose, dev_nu,
+ PCI_BASE_ADDRESS_0 + i * 4, 0xffffffff);
+ pci_hose_read_config_dword(hose, dev_nu,
+ PCI_BASE_ADDRESS_0 + i * 4, &tmp32);
+
+ if (tmp32 == 0x0)
+ continue;
+
+ /* IO space */
+ if (tmp32 & 0x1) {
+ iovsmem = 0;
+ unsigned int size_mask = ~(tmp32 & 0xfffffffc);
+
+ if (priv->io_base & size_mask)
+ priv->io_base = (priv->io_base & ~size_mask) + \
+ size_mask + 1;
+
+ devs[priv->ndevs].bar[i].addr = priv->io_base;
+ devs[priv->ndevs].bar[i].size = size_mask + 1;
+
+ pci_hose_write_config_dword(hose, dev_nu,
+ PCI_BASE_ADDRESS_0 + i * 4,
+ priv->io_base);
+
+ debug("Allocated IO address 0x%X-" \
+ "0x%X for Bus %d, Device %d, Function %d\n",
+ priv->io_base,
+ priv->io_base + size_mask, bus, dev, func);
+
+ priv->io_base += size_mask + 1;
+ } else {
+ /* Memory space */
+ unsigned int is_64bit = ((tmp32 & 0x6) == 0x4);
+ unsigned int is_pref = tmp32 & 0x8;
+ unsigned int size_mask = ~(tmp32 & 0xfffffff0);
+ unsigned int alloc_base;
+ unsigned int *addr_mem_base;
+
+ if (is_pref)
+ addr_mem_base = &priv->mem_base;
+ else
+ addr_mem_base = &priv->mmio_base;
+
+ alloc_base = *addr_mem_base;
+
+ if (alloc_base & size_mask)
+ alloc_base = (alloc_base & ~size_mask) \
+ + size_mask + 1;
+
+ pci_hose_write_config_dword(hose, dev_nu,
+ PCI_BASE_ADDRESS_0 + i * 4, alloc_base);
+
+ debug("Allocated %s address 0x%X-" \
+ "0x%X for Bus %d, Device %d, Function %d\n",
+ is_pref ? "MEM" : "MMIO", alloc_base,
+ alloc_base + size_mask, bus, dev, func);
+
+ devs[priv->ndevs].bar[i].addr = alloc_base;
+ devs[priv->ndevs].bar[i].size = size_mask + 1;
+
+ debug("BAR address BAR size\n");
+ debug("%010x %08d\n",
+ devs[priv->ndevs].bar[0].addr,
+ devs[priv->ndevs].bar[0].size);
+
+ alloc_base += size_mask + 1;
+ *addr_mem_base = alloc_base;
+
+ if (is_64bit) {
+ i++;
+ pci_hose_write_config_dword(hose, dev_nu,
+ PCI_BASE_ADDRESS_0 + i * 4, 0x0);
+ }
+ }
+ }
+
+ /* Enable Bus Master, Memory Space, and IO Space */
+ pci_hose_read_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, &tmp32);
+ pci_hose_write_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, 0x08);
+ pci_hose_read_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, &tmp32);
+
+ pci_hose_read_config_dword(hose, dev_nu, PCI_COMMAND, &tmp32);
+
+ tmp32 &= 0xffff;
+
+ if (iovsmem == 0)
+ tmp32 |= 0x5;
+ else
+ tmp32 |= 0x6;
+
+ pci_hose_write_config_dword(hose, dev_nu, PCI_COMMAND, tmp32);
+}
+
+static void pci_bus_scan(struct ftpci100_data *priv)
+{
+ struct pci_controller *hose = (struct pci_controller *)&local_hose;
+ unsigned int bus, dev, func;
+ pci_dev_t dev_nu;
+ unsigned int data32;
+ unsigned int tmp;
+ unsigned char header;
+ unsigned char int_pin;
+ unsigned int niobars;
+ unsigned int nmbars;
+
+ priv->ndevs = 1;
+
+ nmbars = 0;
+ niobars = 0;
+
+ for (bus = 0; bus < MAX_BUS_NUM; bus++)
+ for (dev = 0; dev < MAX_DEV_NUM; dev++)
+ for (func = 0; func < MAX_FUN_NUM; func++) {
+ dev_nu = PCI_BDF(bus, dev, func);
+ pci_hose_read_config_dword(hose, dev_nu,
+ PCI_VENDOR_ID, &data32);
+
+ /*
+ * some broken boards return 0 or ~0,
+ * if a slot is empty.
+ */
+ if (data32 == 0xffffffff ||
+ data32 == 0x00000000 ||
+ data32 == 0x0000ffff ||
+ data32 == 0xffff0000)
+ continue;
+
+ pci_hose_read_config_dword(hose, dev_nu,
+ PCI_HEADER_TYPE, &tmp);
+ header = (unsigned char)tmp;
+ setup_pci_bar(bus, dev, func, header, priv);
+
+ devs[priv->ndevs].v_id = (u16)(data32 & \
+ 0x0000ffff);
+
+ devs[priv->ndevs].d_id = (u16)((data32 & \
+ 0xffff0000) >> 16);
+
+ /* Figure out what INTX# line the card uses */
+ pci_hose_read_config_byte(hose, dev_nu,
+ PCI_INTERRUPT_PIN, &int_pin);
+
+ /* assign the appropriate irq line */
+ if (int_pin > PCI_IRQ_LINES) {
+ printf("more irq lines than expect\n");
+ } else if (int_pin != 0) {
+ /* This device uses an interrupt line */
+ devs[priv->ndevs].pin = int_pin;
+ }
+
+ pci_hose_read_config_dword(hose, dev_nu,
+ PCI_CLASS_DEVICE, &data32);
+
+ debug("%06d %03d %03d " \
+ "%04d %08x %08x " \
+ "%03d %08x %06d %08x\n",
+ priv->ndevs, devs[priv->ndevs].bus,
+ devs[priv->ndevs].dev,
+ devs[priv->ndevs].func,
+ devs[priv->ndevs].d_id,
+ devs[priv->ndevs].v_id,
+ devs[priv->ndevs].pin,
+ devs[priv->ndevs].bar[0].addr,
+ devs[priv->ndevs].bar[0].size,
+ data32 >> 8);
+
+ priv->ndevs++;
+ }
+}
+
+static void ftpci_preinit(struct ftpci100_data *priv)
+{
+ struct ftpci100_ahbc *ftpci100;
+ struct pci_controller *hose = (struct pci_controller *)&local_hose;
+ u32 pci_config_addr;
+ u32 pci_config_data;
+
+ priv->reg_base = CONFIG_FTPCI100_BASE;
+ priv->io_base = CONFIG_FTPCI100_BASE + CONFIG_FTPCI100_IO_SIZE;
+ priv->mmio_base = CONFIG_FTPCI100_MEM_BASE;
+ priv->mem_base = CONFIG_FTPCI100_MEM_BASE + CONFIG_FTPCI100_MEM_SIZE;
+
+ ftpci100 = (struct ftpci100_ahbc *)priv->reg_base;
+
+ pci_config_addr = (u32) &ftpci100->conf;
+ pci_config_data = (u32) &ftpci100->data;
+
+ /* print device name */
+ printf("FTPCI100\n");
+
+ /* dump basic configuration */
+ debug("%s: Config addr is %08X, data port is %08X\n",
+ __func__, pci_config_addr, pci_config_data);
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 0,
+ CONFIG_PCI_MEM_BUS,
+ CONFIG_PCI_MEM_PHYS,
+ CONFIG_PCI_MEM_SIZE,
+ PCI_REGION_MEM);
+ hose->region_count++;
+
+ /* PCI IO space */
+ pci_set_region(hose->regions + 1,
+ CONFIG_PCI_IO_BUS,
+ CONFIG_PCI_IO_PHYS,
+ CONFIG_PCI_IO_SIZE,
+ PCI_REGION_IO);
+ hose->region_count++;
+
+#if defined(CONFIG_PCI_SYS_BUS)
+ /* PCI System Memory space */
+ pci_set_region(hose->regions + 2,
+ CONFIG_PCI_SYS_BUS,
+ CONFIG_PCI_SYS_PHYS,
+ CONFIG_PCI_SYS_SIZE,
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+ hose->region_count++;
+#endif
+
+ /* setup indirect read/write function */
+ pci_setup_indirect(hose, pci_config_addr, pci_config_data);
+
+ /* register hose */
+ pci_register_hose(hose);
+}
+
+void pci_ftpci_init(void)
+{
+ struct ftpci100_data *priv = NULL;
+ struct pci_controller *hose = (struct pci_controller *)&local_hose;
+ pci_dev_t bridge_num;
+
+ struct pci_device_id bridge_ids[] = {
+ {FTPCI100_BRIDGE_VENDORID, FTPCI100_BRIDGE_DEVICEID},
+ {0, 0}
+ };
+
+ priv = malloc(sizeof(struct ftpci100_data));
+
+ if (!priv) {
+ printf("%s(): failed to malloc priv\n", __func__);
+ return;
+ }
+
+ memset(priv, 0, sizeof(struct ftpci100_data));
+
+ ftpci_preinit(priv);
+
+ debug("Device bus dev func deviceID vendorID pin address" \
+ " size class\n");
+
+ pci_bus_scan(priv);
+
+ /*
+ * Setup the PCI Bridge Window to 1GB,
+ * it will cause USB OHCI Host controller Unrecoverable Error
+ * if it is not set.
+ */
+ bridge_num = pci_find_devices(bridge_ids, 0);
+ if (bridge_num == -1) {
+ printf("PCI Bridge not found\n");
+ return;
+ }
+ pci_hose_write_config_dword(hose, bridge_num, PCI_MEM_BASE_SIZE1,
+ FTPCI100_BASE_ADR_SIZE(1024));
+}
diff --git a/drivers/pci/pci_ftpci100.h b/drivers/pci/pci_ftpci100.h
new file mode 100644
index 0000000..19c81a8
--- /dev/null
+++ b/drivers/pci/pci_ftpci100.h
@@ -0,0 +1,94 @@
+/*
+ * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation
+ *
+ * Copyright (C) 2010 Andes Technology Corporation
+ * Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __FTPCI100_H
+#define __FTPCI100_H
+
+/* AHB Control Registers */
+struct ftpci100_ahbc {
+ unsigned int iosize; /* 0x00 - I/O Space Size Signal */
+ unsigned int prot; /* 0x04 - AHB Protection */
+ unsigned int rsved[8]; /* 0x08-0x24 - Reserved */
+ unsigned int conf; /* 0x28 - PCI Configuration */
+ unsigned int data; /* 0x2c - PCI Configuration DATA */
+};
+
+/*
+ * FTPCI100_IOSIZE_REG's constant definitions
+ */
+#define FTPCI100_BASE_IO_SIZE(x) (ffs(x) - 1) /* 1M - 2048M */
+
+/*
+ * PCI Configuration Register
+ */
+#define PCI_INT_MASK 0x4c
+#define PCI_MEM_BASE_SIZE1 0x50
+#define PCI_MEM_BASE_SIZE2 0x54
+#define PCI_MEM_BASE_SIZE3 0x58
+
+/*
+ * PCI_INT_MASK's bit definitions
+ */
+#define PCI_INTA_ENABLE (1 << 22)
+#define PCI_INTB_ENABLE (1 << 23)
+#define PCI_INTC_ENABLE (1 << 24)
+#define PCI_INTD_ENABLE (1 << 25)
+
+/*
+ * PCI_MEM_BASE_SIZE1's constant definitions
+ */
+#define FTPCI100_BASE_ADR_SIZE(x) ((ffs(x) - 1) << 16) /* 1M - 2048M */
+
+#define FTPCI100_MAX_FUNCTIONS 20
+#define PCI_IRQ_LINES 4
+
+#define MAX_BUS_NUM 256
+#define MAX_DEV_NUM 32
+#define MAX_FUN_NUM 8
+
+#define PCI_MAX_BAR_PER_FUNC 6
+
+/*
+ * PCI_MEM_SIZE
+ */
+#define FTPCI100_MEM_SIZE(x) (ffs(x) << 24)
+
+/* This definition is used by pci_ftpci_init() */
+#define FTPCI100_BRIDGE_VENDORID 0x159b
+#define FTPCI100_BRIDGE_DEVICEID 0x4321
+
+struct pcibar {
+ unsigned int size;
+ unsigned int addr;
+};
+
+struct pci_config {
+ unsigned int bus;
+ unsigned int dev; /* device */
+ unsigned int func;
+ unsigned int pin;
+ unsigned short v_id; /* vendor id */
+ unsigned short d_id; /* device id */
+ struct pcibar bar[PCI_MAX_BAR_PER_FUNC + 1];
+};
+
+#endif
diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile
new file mode 100644
index 0000000..be11c8b
--- /dev/null
+++ b/drivers/tpm/Makefile
@@ -0,0 +1,43 @@
+# Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)libtpm.o
+
+COBJS-$(CONFIG_GENERIC_LPC_TPM) = generic_lpc_tpm.o
+
+COBJS := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(LIB)
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/drivers/tpm/generic_lpc_tpm.c b/drivers/tpm/generic_lpc_tpm.c
new file mode 100644
index 0000000..6c494eb
--- /dev/null
+++ b/drivers/tpm/generic_lpc_tpm.c
@@ -0,0 +1,495 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * The code in this file is based on the article "Writing a TPM Device Driver"
+ * published on http://ptgmedia.pearsoncmg.com.
+ *
+ * One principal difference is that in the simplest config the other than 0
+ * TPM localities do not get mapped by some devices (for instance, by Infineon
+ * slb9635), so this driver provides access to locality 0 only.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <tpm.h>
+
+#define PREFIX "lpc_tpm: "
+
+struct tpm_locality {
+ u32 access;
+ u8 padding0[4];
+ u32 int_enable;
+ u8 vector;
+ u8 padding1[3];
+ u32 int_status;
+ u32 int_capability;
+ u32 tpm_status;
+ u8 padding2[8];
+ u8 data;
+ u8 padding3[3803];
+ u32 did_vid;
+ u8 rid;
+ u8 padding4[251];
+};
+
+/*
+ * This pointer refers to the TPM chip, 5 of its localities are mapped as an
+ * array.
+ */
+#define TPM_TOTAL_LOCALITIES 5
+static struct tpm_locality *lpc_tpm_dev =
+ (struct tpm_locality *)CONFIG_TPM_TIS_BASE_ADDRESS;
+
+/* Some registers' bit field definitions */
+#define TIS_STS_VALID (1 << 7) /* 0x80 */
+#define TIS_STS_COMMAND_READY (1 << 6) /* 0x40 */
+#define TIS_STS_TPM_GO (1 << 5) /* 0x20 */
+#define TIS_STS_DATA_AVAILABLE (1 << 4) /* 0x10 */
+#define TIS_STS_EXPECT (1 << 3) /* 0x08 */
+#define TIS_STS_RESPONSE_RETRY (1 << 1) /* 0x02 */
+
+#define TIS_ACCESS_TPM_REG_VALID_STS (1 << 7) /* 0x80 */
+#define TIS_ACCESS_ACTIVE_LOCALITY (1 << 5) /* 0x20 */
+#define TIS_ACCESS_BEEN_SEIZED (1 << 4) /* 0x10 */
+#define TIS_ACCESS_SEIZE (1 << 3) /* 0x08 */
+#define TIS_ACCESS_PENDING_REQUEST (1 << 2) /* 0x04 */
+#define TIS_ACCESS_REQUEST_USE (1 << 1) /* 0x02 */
+#define TIS_ACCESS_TPM_ESTABLISHMENT (1 << 0) /* 0x01 */
+
+#define TIS_STS_BURST_COUNT_MASK (0xffff)
+#define TIS_STS_BURST_COUNT_SHIFT (8)
+
+/*
+ * Error value returned if a tpm register does not enter the expected state
+ * after continuous polling. No actual TPM register reading ever returns -1,
+ * so this value is a safe error indication to be mixed with possible status
+ * register values.
+ */
+#define TPM_TIMEOUT_ERR (-1)
+
+/* Error value returned on various TPM driver errors. */
+#define TPM_DRIVER_ERR (1)
+
+ /* 1 second is plenty for anything TPM does. */
+#define MAX_DELAY_US (1000 * 1000)
+
+/* Retrieve burst count value out of the status register contents. */
+static u16 burst_count(u32 status)
+{
+ return (status >> TIS_STS_BURST_COUNT_SHIFT) & TIS_STS_BURST_COUNT_MASK;
+}
+
+/*
+ * Structures defined below allow creating descriptions of TPM vendor/device
+ * ID information for run time discovery. The only device the system knows
+ * about at this time is Infineon slb9635.
+ */
+struct device_name {
+ u16 dev_id;
+ const char * const dev_name;
+};
+
+struct vendor_name {
+ u16 vendor_id;
+ const char *vendor_name;
+ const struct device_name *dev_names;
+};
+
+static const struct device_name infineon_devices[] = {
+ {0xb, "SLB9635 TT 1.2"},
+ {0}
+};
+
+static const struct vendor_name vendor_names[] = {
+ {0x15d1, "Infineon", infineon_devices},
+};
+
+/*
+ * Cached vendor/device ID pair to indicate that the device has been already
+ * discovered.
+ */
+static u32 vendor_dev_id;
+
+/* TPM access wrappers to support tracing */
+static u8 tpm_read_byte(const u8 *ptr)
+{
+ u8 ret = readb(ptr);
+ debug(PREFIX "Read reg 0x%4.4x returns 0x%2.2x\n",
+ (u32)ptr - (u32)lpc_tpm_dev, ret);
+ return ret;
+}
+
+static u32 tpm_read_word(const u32 *ptr)
+{
+ u32 ret = readl(ptr);
+ debug(PREFIX "Read reg 0x%4.4x returns 0x%8.8x\n",
+ (u32)ptr - (u32)lpc_tpm_dev, ret);
+ return ret;
+}
+
+static void tpm_write_byte(u8 value, u8 *ptr)
+{
+ debug(PREFIX "Write reg 0x%4.4x with 0x%2.2x\n",
+ (u32)ptr - (u32)lpc_tpm_dev, value);
+ writeb(value, ptr);
+}
+
+static void tpm_write_word(u32 value, u32 *ptr)
+{
+ debug(PREFIX "Write reg 0x%4.4x with 0x%8.8x\n",
+ (u32)ptr - (u32)lpc_tpm_dev, value);
+ writel(value, ptr);
+}
+
+/*
+ * tis_wait_reg()
+ *
+ * Wait for at least a second for a register to change its state to match the
+ * expected state. Normally the transition happens within microseconds.
+ *
+ * @reg - pointer to the TPM register
+ * @mask - bitmask for the bitfield(s) to watch
+ * @expected - value the field(s) are supposed to be set to
+ *
+ * Returns the register contents in case the expected value was found in the
+ * appropriate register bits, or TPM_TIMEOUT_ERR on timeout.
+ */
+static u32 tis_wait_reg(u32 *reg, u8 mask, u8 expected)
+{
+ u32 time_us = MAX_DELAY_US;
+
+ while (time_us > 0) {
+ u32 value = tpm_read_word(reg);
+ if ((value & mask) == expected)
+ return value;
+ udelay(1); /* 1 us */
+ time_us--;
+ }
+ return TPM_TIMEOUT_ERR;
+}
+
+/*
+ * Probe the TPM device and try determining its manufacturer/device name.
+ *
+ * Returns 0 on success (the device is found or was found during an earlier
+ * invocation) or TPM_DRIVER_ERR if the device is not found.
+ */
+int tis_init(void)
+{
+ u32 didvid = tpm_read_word(&lpc_tpm_dev[0].did_vid);
+ int i;
+ const char *device_name = "unknown";
+ const char *vendor_name = device_name;
+ u16 vid, did;
+
+ if (vendor_dev_id)
+ return 0; /* Already probed. */
+
+ if (!didvid || (didvid == 0xffffffff)) {
+ printf("%s: No TPM device found\n", __func__);
+ return TPM_DRIVER_ERR;
+ }
+
+ vendor_dev_id = didvid;
+
+ vid = didvid & 0xffff;
+ did = (didvid >> 16) & 0xffff;
+ for (i = 0; i < ARRAY_SIZE(vendor_names); i++) {
+ int j = 0;
+ u16 known_did;
+
+ if (vid == vendor_names[i].vendor_id)
+ vendor_name = vendor_names[i].vendor_name;
+
+ while ((known_did = vendor_names[i].dev_names[j].dev_id) != 0) {
+ if (known_did == did) {
+ device_name =
+ vendor_names[i].dev_names[j].dev_name;
+ break;
+ }
+ j++;
+ }
+ break;
+ }
+
+ printf("Found TPM %s by %s\n", device_name, vendor_name);
+ return 0;
+}
+
+/*
+ * tis_senddata()
+ *
+ * send the passed in data to the TPM device.
+ *
+ * @data - address of the data to send, byte by byte
+ * @len - length of the data to send
+ *
+ * Returns 0 on success, TPM_DRIVER_ERR on error (in case the device does
+ * not accept the entire command).
+ */
+static u32 tis_senddata(const u8 * const data, u32 len)
+{
+ u32 offset = 0;
+ u16 burst = 0;
+ u32 max_cycles = 0;
+ u8 locality = 0;
+ u32 value;
+
+ value = tis_wait_reg(&lpc_tpm_dev[locality].tpm_status,
+ TIS_STS_COMMAND_READY, TIS_STS_COMMAND_READY);
+ if (value == TPM_TIMEOUT_ERR) {
+ printf("%s:%d - failed to get 'command_ready' status\n",
+ __FILE__, __LINE__);
+ return TPM_DRIVER_ERR;
+ }
+ burst = burst_count(value);
+
+ while (1) {
+ unsigned count;
+
+ /* Wait till the device is ready to accept more data. */
+ while (!burst) {
+ if (max_cycles++ == MAX_DELAY_US) {
+ printf("%s:%d failed to feed %d bytes of %d\n",
+ __FILE__, __LINE__, len - offset, len);
+ return TPM_DRIVER_ERR;
+ }
+ udelay(1);
+ burst = burst_count(tpm_read_word(&lpc_tpm_dev
+ [locality].tpm_status));
+ }
+
+ max_cycles = 0;
+
+ /*
+ * Calculate number of bytes the TPM is ready to accept in one
+ * shot.
+ *
+ * We want to send the last byte outside of the loop (hence
+ * the -1 below) to make sure that the 'expected' status bit
+ * changes to zero exactly after the last byte is fed into the
+ * FIFO.
+ */
+ count = min(burst, len - offset - 1);
+ while (count--)
+ tpm_write_byte(data[offset++],
+ &lpc_tpm_dev[locality].data);
+
+ value = tis_wait_reg(&lpc_tpm_dev[locality].tpm_status,
+ TIS_STS_VALID, TIS_STS_VALID);
+
+ if ((value == TPM_TIMEOUT_ERR) || !(value & TIS_STS_EXPECT)) {
+ printf("%s:%d TPM command feed overflow\n",
+ __FILE__, __LINE__);
+ return TPM_DRIVER_ERR;
+ }
+
+ burst = burst_count(value);
+ if ((offset == (len - 1)) && burst) {
+ /*
+ * We need to be able to send the last byte to the
+ * device, so burst size must be nonzero before we
+ * break out.
+ */
+ break;
+ }
+ }
+
+ /* Send the last byte. */
+ tpm_write_byte(data[offset++], &lpc_tpm_dev[locality].data);
+ /*
+ * Verify that TPM does not expect any more data as part of this
+ * command.
+ */
+ value = tis_wait_reg(&lpc_tpm_dev[locality].tpm_status,
+ TIS_STS_VALID, TIS_STS_VALID);
+ if ((value == TPM_TIMEOUT_ERR) || (value & TIS_STS_EXPECT)) {
+ printf("%s:%d unexpected TPM status 0x%x\n",
+ __FILE__, __LINE__, value);
+ return TPM_DRIVER_ERR;
+ }
+
+ /* OK, sitting pretty, let's start the command execution. */
+ tpm_write_word(TIS_STS_TPM_GO, &lpc_tpm_dev[locality].tpm_status);
+ return 0;
+}
+
+/*
+ * tis_readresponse()
+ *
+ * read the TPM device response after a command was issued.
+ *
+ * @buffer - address where to read the response, byte by byte.
+ * @len - pointer to the size of buffer
+ *
+ * On success stores the number of received bytes to len and returns 0. On
+ * errors (misformatted TPM data or synchronization problems) returns
+ * TPM_DRIVER_ERR.
+ */
+static u32 tis_readresponse(u8 *buffer, u32 *len)
+{
+ u16 burst;
+ u32 value;
+ u32 offset = 0;
+ u8 locality = 0;
+ const u32 has_data = TIS_STS_DATA_AVAILABLE | TIS_STS_VALID;
+ u32 expected_count = *len;
+ int max_cycles = 0;
+
+ /* Wait for the TPM to process the command. */
+ value = tis_wait_reg(&lpc_tpm_dev[locality].tpm_status,
+ has_data, has_data);
+ if (value == TPM_TIMEOUT_ERR) {
+ printf("%s:%d failed processing command\n",
+ __FILE__, __LINE__);
+ return TPM_DRIVER_ERR;
+ }
+
+ do {
+ while ((burst = burst_count(value)) == 0) {
+ if (max_cycles++ == MAX_DELAY_US) {
+ printf("%s:%d TPM stuck on read\n",
+ __FILE__, __LINE__);
+ return TPM_DRIVER_ERR;
+ }
+ udelay(1);
+ value = tpm_read_word(&lpc_tpm_dev
+ [locality].tpm_status);
+ }
+
+ max_cycles = 0;
+
+ while (burst-- && (offset < expected_count)) {
+ buffer[offset++] = tpm_read_byte(&lpc_tpm_dev
+ [locality].data);
+
+ if (offset == 6) {
+ /*
+ * We got the first six bytes of the reply,
+ * let's figure out how many bytes to expect
+ * total - it is stored as a 4 byte number in
+ * network order, starting with offset 2 into
+ * the body of the reply.
+ */
+ u32 real_length;
+ memcpy(&real_length,
+ buffer + 2,
+ sizeof(real_length));
+ expected_count = be32_to_cpu(real_length);
+
+ if ((expected_count < offset) ||
+ (expected_count > *len)) {
+ printf("%s:%d bad response size %d\n",
+ __FILE__, __LINE__,
+ expected_count);
+ return TPM_DRIVER_ERR;
+ }
+ }
+ }
+
+ /* Wait for the next portion. */
+ value = tis_wait_reg(&lpc_tpm_dev[locality].tpm_status,
+ TIS_STS_VALID, TIS_STS_VALID);
+ if (value == TPM_TIMEOUT_ERR) {
+ printf("%s:%d failed to read response\n",
+ __FILE__, __LINE__);
+ return TPM_DRIVER_ERR;
+ }
+
+ if (offset == expected_count)
+ break; /* We got all we needed. */
+
+ } while ((value & has_data) == has_data);
+
+ /*
+ * Make sure we indeed read all there was. The TIS_STS_VALID bit is
+ * known to be set.
+ */
+ if (value & TIS_STS_DATA_AVAILABLE) {
+ printf("%s:%d wrong receive status %x\n",
+ __FILE__, __LINE__, value);
+ return TPM_DRIVER_ERR;
+ }
+
+ /* Tell the TPM that we are done. */
+ tpm_write_word(TIS_STS_COMMAND_READY, &lpc_tpm_dev
+ [locality].tpm_status);
+ *len = offset;
+ return 0;
+}
+
+int tis_open(void)
+{
+ u8 locality = 0; /* we use locality zero for everything. */
+
+ if (tis_close())
+ return TPM_DRIVER_ERR;
+
+ /* now request access to locality. */
+ tpm_write_word(TIS_ACCESS_REQUEST_USE, &lpc_tpm_dev[locality].access);
+
+ /* did we get a lock? */
+ if (tis_wait_reg(&lpc_tpm_dev[locality].access,
+ TIS_ACCESS_ACTIVE_LOCALITY,
+ TIS_ACCESS_ACTIVE_LOCALITY) == TPM_TIMEOUT_ERR) {
+ printf("%s:%d - failed to lock locality %d\n",
+ __FILE__, __LINE__, locality);
+ return TPM_DRIVER_ERR;
+ }
+
+ tpm_write_word(TIS_STS_COMMAND_READY,
+ &lpc_tpm_dev[locality].tpm_status);
+ return 0;
+}
+
+int tis_close(void)
+{
+ u8 locality = 0;
+
+ if (tpm_read_word(&lpc_tpm_dev[locality].access) &
+ TIS_ACCESS_ACTIVE_LOCALITY) {
+ tpm_write_word(TIS_ACCESS_ACTIVE_LOCALITY,
+ &lpc_tpm_dev[locality].access);
+
+ if (tis_wait_reg(&lpc_tpm_dev[locality].access,
+ TIS_ACCESS_ACTIVE_LOCALITY, 0) ==
+ TPM_TIMEOUT_ERR) {
+ printf("%s:%d - failed to release locality %d\n",
+ __FILE__, __LINE__, locality);
+ return TPM_DRIVER_ERR;
+ }
+ }
+ return 0;
+}
+
+int tis_sendrecv(const u8 *sendbuf, size_t send_size,
+ u8 *recvbuf, size_t *recv_len)
+{
+ if (tis_senddata(sendbuf, send_size)) {
+ printf("%s:%d failed sending data to TPM\n",
+ __FILE__, __LINE__);
+ return TPM_DRIVER_ERR;
+ }
+
+ return tis_readresponse(recvbuf, recv_len);
+}
diff --git a/examples/standalone/atmel_df_pow2.c b/examples/standalone/atmel_df_pow2.c
index b5b4503..2e14aba 100644
--- a/examples/standalone/atmel_df_pow2.c
+++ b/examples/standalone/atmel_df_pow2.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <exports.h>
+#include <spi.h>
#define CMD_ID 0x9f
#define CMD_STAT 0xd7
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index 11c7565..a6add6a 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -1,3 +1,4 @@
+#include <common.h>
#include <exports.h>
#ifndef GCC_VERSION
diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h
new file mode 100644
index 0000000..2e2a9a7
--- /dev/null
+++ b/include/configs/ecovec.h
@@ -0,0 +1,200 @@
+/*
+ * Configuation settings for the Renesas Solutions ECOVEC board
+ *
+ * Copyright (C) 2009 - 2011 Renesas Solutions Corp.
+ * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ECOVEC_H
+#define __ECOVEC_H
+
+/*
+ * Address Interface BusWidth
+ *-----------------------------------------
+ * 0x0000_0000 U-Boot 16bit
+ * 0x0004_0000 Linux romImage 16bit
+ * 0x0014_0000 MTD for Linux 16bit
+ * 0x0400_0000 Internal I/O 16/32bit
+ * 0x0800_0000 DRAM 32bit
+ * 0x1800_0000 MFI 16bit
+ */
+
+#undef DEBUG
+#define CONFIG_SH 1
+#define CONFIG_SH4 1
+#define CONFIG_SH4A 1
+#define CONFIG_CPU_SH7724 1
+#define BOARD_LATE_INIT 1
+#define CONFIG_ECOVEC 1
+
+#define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000
+#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_SAVEENV
+
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttySC0,115200"
+
+#define CONFIG_VERSION_VARIABLE
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SH_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MULTI_BUS 1
+#define CONFIG_SYS_MAX_I2C_BUS 2
+#define CONFIG_SYS_I2C_MODULE 1
+#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SH_I2C_DATA_HIGH 4
+#define CONFIG_SH_I2C_DATA_LOW 5
+#define CONFIG_SH_I2C_CLOCK 41666666
+#define CONFIG_SH_I2C_BASE0 0xA4470000
+#define CONFIG_SH_I2C_BASE1 0xA4750000
+
+/* Ether */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_SH_ETHER 1
+#define CONFIG_SH_ETHER_USE_PORT (0)
+#define CONFIG_SH_ETHER_PHY_ADDR (0x1f)
+#define CONFIG_PHYLIB
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* USB / R8A66597 */
+#define CONFIG_USB_R8A66597_HCD
+#define CONFIG_R8A66597_BASE_ADDR 0xA4D80000
+#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
+#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
+#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
+#define CONFIG_SUPERH_ON_CHIP_R8A66597
+
+/* undef to save memory */
+#define CONFIG_SYS_LONGHELP
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT "=> "
+/* Buffer size for input from the Console */
+#define CONFIG_SYS_CBSIZE 256
+/* Buffer size for Console output */
+#define CONFIG_SYS_PBSIZE 256
+/* max args accepted for monitor commands */
+#define CONFIG_SYS_MAXARGS 16
+/* Buffer size for Boot Arguments passed to kernel */
+#define CONFIG_SYS_BARGSIZE 512
+/* List of legal baudrate settings for this board */
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE 1
+#define CONFIG_SCIF 1
+#define CONFIG_CONS_SCIF0 1
+
+/* Suppress display of console information at boot */
+#undef CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE (0x88000000)
+#define CONFIG_SYS_SDRAM_SIZE (256 * 1024 * 1024)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
+
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 200 * 1024 * 1024)
+/* Enable alternate, more extensive, memory test */
+#undef CONFIG_SYS_ALT_MEMTEST
+/* Scratch address used by the alternate memory test */
+#undef CONFIG_SYS_MEMTEST_SCRATCH
+
+/* Enable temporary baudrate change while serial download */
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/* FLASH */
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_CFI
+#undef CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BASE (0xA0000000)
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+
+/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+/* Timeout for Flash erase operations (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
+
+/*
+ * Use hardware flash sectors protection instead
+ * of U-Boot software protection
+ */
+#undef CONFIG_SYS_FLASH_PROTECTION
+#undef CONFIG_SYS_DIRECT_FLASH_TFTP
+
+/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
+/* Monitor size */
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE (256)
+#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
+#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ 41666666
+#define CONFIG_SYS_TMU_CLK_DIV 4
+#define CONFIG_SYS_HZ 1000
+
+#endif /* __ECOVEC_H */
diff --git a/include/configs/espt.h b/include/configs/espt.h
index 38058c7..3df1fae 100644
--- a/include/configs/espt.h
+++ b/include/configs/espt.h
@@ -39,6 +39,7 @@
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_ENV
#define CONFIG_CMD_NFS
@@ -120,5 +121,8 @@
#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT (1)
#define CONFIG_SH_ETHER_PHY_ADDR (0x00)
+#define CONFIG_PHYLIB
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
#endif /* __SH7763RDP_H */
diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h
index e837f40..dd6c41d 100644
--- a/include/configs/gr_cpci_ax2000.h
+++ b/include/configs/gr_cpci_ax2000.h
@@ -108,7 +108,7 @@
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "getkernel=tftpboot \$\(scratch\)\ \$\(bootfile\)\0" \
+ "getkernel=tftpboot $(scratch) $(bootfile)\0" \
"bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.206:192.168.0.20:192.168.0.1:255.255.255.0:ax2000:eth0\0"
#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SRAM
diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h
index 0cddeee..7068ff8 100644
--- a/include/configs/gr_ep2s60.h
+++ b/include/configs/gr_ep2s60.h
@@ -115,7 +115,7 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
"scratch=40800000\0" \
- "getkernel=tftpboot \$\(scratch\)\ \$\(bootfile\)\0" \
+ "getkernel=tftpboot $(scratch) $(bootfile)\0" \
"bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.207:192.168.0.20:192.168.0.1:255.255.255.0:ml401:eth0\0" \
""
diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h
index 7e8e6f5..5006322 100644
--- a/include/configs/gr_xc3s_1500.h
+++ b/include/configs/gr_xc3s_1500.h
@@ -91,7 +91,7 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
"scratch=40200000\0" \
- "getkernel=tftpboot \$\(scratch\)\ \$\(bootfile\)\0" \
+ "getkernel=tftpboot $(scratch) $(bootfile)\0" \
"bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.206:192.168.0.20:192.168.0.1:255.255.255.0:grxc3s1500_daniel:eth0\0" \
""
diff --git a/include/configs/grsim.h b/include/configs/grsim.h
index c14749b..f3639dd 100644
--- a/include/configs/grsim.h
+++ b/include/configs/grsim.h
@@ -113,7 +113,7 @@
"net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/export/roofs\0" \
"scratch=40000000\0" \
- "getkernel=tftpboot \$\(scratch\)\ \$\(bootfile\)\0" \
+ "getkernel=tftpboot $(scratch) $(bootfile)\0" \
"ethaddr=00:00:7A:CC:00:12\0" \
"bootargs=console=ttyS0,38400" \
""
diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h
index 88d2aad..fb9a3f9 100644
--- a/include/configs/grsim_leon2.h
+++ b/include/configs/grsim_leon2.h
@@ -110,7 +110,7 @@
"net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/export/roofs\0" \
"scratch=40000000\0" \
- "getkernel=tftpboot \$\(scratch\)\ \$\(bootfile\)\0" \
+ "getkernel=tftpboot $(scratch) $(bootfile)\0" \
"ethaddr=00:00:7A:CC:00:12\0" \
"bootargs=console=ttyS0,38400" \
""
diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h
index 2d6eb33..c1f9ce8 100644
--- a/include/configs/sh7757lcr.h
+++ b/include/configs/sh7757lcr.h
@@ -31,12 +31,14 @@
#define CONFIG_SH_32BIT 1
#define CONFIG_CPU_SH7757 1
#define CONFIG_SH7757LCR 1
+#define CONFIG_SH7757LCR_DDR_ECC 1
#define CONFIG_SYS_TEXT_BASE 0x8ef80000
#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7757lcr/u-boot.lds"
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_NFS
#define CONFIG_CMD_DFL
@@ -101,6 +103,9 @@
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 1
#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
+#define CONFIG_PHYLIB
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
#define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000
#define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024)
diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h
index b8eb13d..59728f5 100644
--- a/include/configs/sh7763rdp.h
+++ b/include/configs/sh7763rdp.h
@@ -39,6 +39,7 @@
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_NFS
@@ -120,5 +121,8 @@
#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT (1)
#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
+#define CONFIG_PHYLIB
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
#endif /* __SH7763RDP_H */
diff --git a/include/exports.h b/include/exports.h
index 9492566..63aa4b2 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -3,8 +3,6 @@
#ifndef __ASSEMBLY__
-#include <common.h>
-
/* These are declarations of exported functions available in C code */
unsigned long get_version(void);
int getc(void);
@@ -12,7 +10,7 @@
void putc(const char);
void puts(const char*);
int printf(const char* fmt, ...);
-void install_hdlr(int, interrupt_handler_t*, void*);
+void install_hdlr(int, void (*interrupt_handler_t)(void *), void*);
void free_hdlr(int);
void *malloc(size_t);
void free(void*);
@@ -30,7 +28,6 @@
int i2c_write (uchar, uint, int , uchar* , int);
int i2c_read (uchar, uint, int , uchar* , int);
#endif
-#include <spi.h>
void app_startup(char * const *);
diff --git a/include/net.h b/include/net.h
index ad9afbf..fa5d525 100644
--- a/include/net.h
+++ b/include/net.h
@@ -33,7 +33,8 @@
#define PKTALIGN 32
-typedef ulong IPaddr_t;
+/* IPv4 addresses are always 32 bits in size */
+typedef u32 IPaddr_t;
/**
diff --git a/include/serial.h b/include/serial.h
index 5926244..fbc1036 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -24,14 +24,15 @@
extern struct serial_device serial_smc_device;
extern struct serial_device serial_scc_device;
-extern struct serial_device * default_serial_console (void);
+extern struct serial_device *default_serial_console(void);
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || \
- defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
- defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
- defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
- defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
- defined(CONFIG_TEGRA2)
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
+ defined(CONFIG_405EX) || defined(CONFIG_440) || \
+ defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
+ defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
+ defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
+ defined(CONFIG_TEGRA2)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
#if defined(CONFIG_SYS_NS16550_SERIAL)
@@ -92,7 +93,7 @@
extern void serial_register(struct serial_device *);
extern void serial_initialize(void);
extern void serial_stdio_init(void);
-extern int serial_assign(char * name);
+extern int serial_assign(const char *name);
extern void serial_reinit_all(void);
/* For usbtty */
diff --git a/include/tpm.h b/include/tpm.h
new file mode 100644
index 0000000..6b21e9c
--- /dev/null
+++ b/include/tpm.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _INCLUDE_TPM_H_
+#define _INCLUDE_TPM_H_
+
+#include <common.h>
+
+/*
+ * tis_init()
+ *
+ * Initialize the TPM device. Returns 0 on success or -1 on
+ * failure (in case device probing did not succeed).
+ */
+int tis_init(void);
+
+/*
+ * tis_open()
+ *
+ * Requests access to locality 0 for the caller. After all commands have been
+ * completed the caller is supposed to call tis_close().
+ *
+ * Returns 0 on success, -1 on failure.
+ */
+int tis_open(void);
+
+/*
+ * tis_close()
+ *
+ * terminate the currect session with the TPM by releasing the locked
+ * locality. Returns 0 on success of -1 on failure (in case lock
+ * removal did not succeed).
+ */
+int tis_close(void);
+
+/*
+ * tis_sendrecv()
+ *
+ * Send the requested data to the TPM and then try to get its response
+ *
+ * @sendbuf - buffer of the data to send
+ * @send_size size of the data to send
+ * @recvbuf - memory to save the response to
+ * @recv_len - pointer to the size of the response buffer
+ *
+ * Returns 0 on success (and places the number of response bytes at recv_len)
+ * or -1 on failure.
+ */
+int tis_sendrecv(const uint8_t *sendbuf, size_t send_size, uint8_t *recvbuf,
+ size_t *recv_len);
+
+#endif /* _INCLUDE_TPM_H_ */
diff --git a/lib/qsort.c b/lib/qsort.c
index 86c392c..5709884 100644
--- a/lib/qsort.c
+++ b/lib/qsort.c
@@ -16,6 +16,7 @@
* bcc and gcc. */
#include <linux/types.h>
+#include <common.h>
#include <exports.h>
void qsort(void *base,
diff --git a/net/net.c b/net/net.c
index d0fe1c4..045405b 100644
--- a/net/net.c
+++ b/net/net.c
@@ -728,7 +728,7 @@
*/
if (memcmp(ether, NetEtherNullAddr, 6) == 0) {
- debug("sending ARP for %08lx\n", dest);
+ debug("sending ARP for %08x\n", dest);
NetArpWaitPacketIP = dest;
NetArpWaitPacketMAC = ether;
@@ -751,7 +751,7 @@
return 1; /* waiting */
}
- debug("sending UDP to %08lx/%pM\n", dest, ether);
+ debug("sending UDP to %08x/%pM\n", dest, ether);
pkt = (uchar *)NetTxPacket;
pkt += NetSetEther(pkt, ether, PROT_IP);
@@ -775,7 +775,7 @@
memcpy(mac, NetEtherNullAddr, 6);
- debug("sending ARP for %08lx\n", NetPingIP);
+ debug("sending ARP for %08x\n", NetPingIP);
NetArpWaitPacketIP = NetPingIP;
NetArpWaitPacketMAC = mac;
diff --git a/net/nfs.c b/net/nfs.c
index 5e717e3..b5b482c 100644
--- a/net/nfs.c
+++ b/net/nfs.c
@@ -688,7 +688,7 @@
}
if (BootFile[0] == '\0') {
- sprintf (default_filename, "/nfsroot/%02lX%02lX%02lX%02lX.img",
+ sprintf(default_filename, "/nfsroot/%02X%02X%02X%02X.img",
NetOurIP & 0xFF,
(NetOurIP >> 8) & 0xFF,
(NetOurIP >> 16) & 0xFF,
diff --git a/net/tftp.c b/net/tftp.c
index 4999707..7aa3e23 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -708,7 +708,7 @@
TftpRemoteIP = NetServerIP;
if (BootFile[0] == '\0') {
- sprintf(default_filename, "%02lX%02lX%02lX%02lX.img",
+ sprintf(default_filename, "%02X%02X%02X%02X.img",
NetOurIP & 0xFF,
(NetOurIP >> 8) & 0xFF,
(NetOurIP >> 16) & 0xFF,
diff --git a/tools/aisimage.c b/tools/aisimage.c
index 6a10111..c645708 100644
--- a/tools/aisimage.c
+++ b/tools/aisimage.c
@@ -180,7 +180,7 @@
static uint32_t *ais_insert_cmd_header(uint32_t cmd, uint32_t nargs,
uint32_t *parms, struct image_type_params *tparams,
- uint32_t *ptr, uint32_t size)
+ uint32_t *ptr)
{
int i;
@@ -285,7 +285,7 @@
uint32_t nargs, cmd_parms[10];
uint32_t value, size;
char *name = params->imagename;
- uint32_t *aishdr, tsize;
+ uint32_t *aishdr;
fd = fopen(name, "r");
if (fd == 0) {
@@ -363,7 +363,7 @@
if (cmd != CMD_INVALID) {
/* Now insert the command into the header */
aishdr = ais_insert_cmd_header(cmd, nargs, cmd_parms,
- tparams, aishdr, tsize);
+ tparams, aishdr);
}
}
diff --git a/tools/envcrc.c b/tools/envcrc.c
index 111d9f6..51e3f54 100644
--- a/tools/envcrc.c
+++ b/tools/envcrc.c
@@ -61,7 +61,6 @@
#endif /* CONFIG_ENV_IS_IN_FLASH */
#if defined(ENV_IS_EMBEDDED) && !defined(CONFIG_BUILD_ENVCRC)
-# include <environment.h>
# define CONFIG_BUILD_ENVCRC 1
#endif
@@ -74,13 +73,14 @@
#define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE)
-extern uint32_t crc32 (uint32_t, const unsigned char *, unsigned int);
-
#ifdef CONFIG_BUILD_ENVCRC
+# include <environment.h>
extern unsigned int env_size;
extern env_t environment;
#endif /* CONFIG_BUILD_ENVCRC */
+extern uint32_t crc32 (uint32_t, const unsigned char *, unsigned int);
+
int main (int argc, char **argv)
{
#ifdef CONFIG_BUILD_ENVCRC
diff --git a/tools/os_support.c b/tools/os_support.c
index 1ed89e6..319c0fe 100644
--- a/tools/os_support.c
+++ b/tools/os_support.c
@@ -23,6 +23,6 @@
#ifdef __MINGW32__
#include "mingw_support.c"
#endif
-#ifdef __APPLE__
+#if defined(__APPLE__) && __DARWIN_C_LEVEL < 200809L
#include "getline.c"
#endif
diff --git a/tools/os_support.h b/tools/os_support.h
index 7dcbee4..5bf7add 100644
--- a/tools/os_support.h
+++ b/tools/os_support.h
@@ -28,7 +28,7 @@
#include "mingw_support.h"
#endif
-#ifdef __APPLE__
+#if defined(__APPLE__) && __DARWIN_C_LEVEL < 200809L
#include "getline.h"
#endif