armv8: lx2160ardb : Add support for LX2160ARDB platform
LX2160ARDB is an evaluation board that supports LX2160A
family SoCs. This patch add base support for this board.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
[PK: Sqaush patches from Yinbo Zhu, Peng Ma, Chuanhua Han
and re-arrange defconfig]
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 455f06c..1b9d27e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1083,6 +1083,19 @@
development platform that supports the QorIQ LS2081A/LS2041A
Layerscape Architecture processor.
+config TARGET_LX2160ARDB
+ bool "Support lx2160ardb"
+ select ARCH_LX2160A
+ select ARCH_MISC_INIT
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select BOARD_LATE_INIT
+ help
+ Support for NXP LX2160ARDB platform.
+ The lx2160ardb (LX2160A Reference design board (RDB)
+ is a high-performance development platform that supports the
+ QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
+
config TARGET_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"
select ARM64
@@ -1555,6 +1568,7 @@
source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig"
+source "board/freescale/lx2160a/Kconfig"
source "board/freescale/mx35pdk/Kconfig"
source "board/freescale/s32v234evb/Kconfig"
source "board/grinn/chiliboard/Kconfig"
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 1c12bbd..cc6d078 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -106,7 +106,7 @@
!TARGET_LS1012AFRWY && \
!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
- !TARGET_LS2081ARDB && \
+ !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
!ARCH_UNIPHIER && !TARGET_S32V234EVB
help
Most armv8 systems have PSCI support enabled in EL3, either through
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fbc0f8a..25b56e9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -246,7 +246,8 @@
fsl-ls2081a-rdb.dtb \
fsl-ls2088a-rdb-qspi.dtb \
fsl-ls1088a-rdb.dtb \
- fsl-ls1088a-qds.dtb
+ fsl-ls1088a-qds.dtb \
+ fsl-lx2160a-rdb.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts
new file mode 100644
index 0000000..4b52644
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2160a-rdb.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160ARDB device tree source
+ *
+ * Author: Priyanka Jain <priyanka.jain@nxp.com>
+ * Sriram Dash <sriram.dash@nxp.com>
+ *
+ * Copyright 2018 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a.dtsi"
+
+/ {
+ model = "NXP Layerscape LX2160ARDB Board";
+ compatible = "fsl,lx2160ardb", "fsl,lx2160a";
+
+};
+
+&esdhc0 {
+ status = "okay";
+};
+
+&esdhc1 {
+ status = "okay";
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index b407dc6..510b070 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -89,7 +89,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2110000 0x0 0x10000>;
- interrupts = <0 240 0x4>; /* Level high type */
+ interrupts = <0 26 0x4>; /* Level high type */
num-cs = <6>;
};
@@ -115,4 +115,65 @@
interrupts = <0 81 0x4>; /* Level high type */
dr_mode = "host";
};
+
+ esdhc0: esdhc@2140000 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x2140000 0x0 0x10000>;
+ interrupts = <0 28 0x4>; /* Level high type */
+ clocks = <&clockgen 4 1>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ little-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ esdhc1: esdhc@2150000 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x2150000 0x0 0x10000>;
+ interrupts = <0 63 0x4>; /* Level high type */
+ clocks = <&clockgen 4 1>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ non-removable;
+ little-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ sata0: sata@3200000 {
+ compatible = "fsl,ls2080a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>;
+ interrupts = <0 133 4>;
+ clocks = <&clockgen 4 3>;
+ status = "disabled";
+
+ };
+
+ sata1: sata@3210000 {
+ compatible = "fsl,ls2080a-ahci";
+ reg = <0x0 0x3210000 0x0 0x10000>;
+ interrupts = <0 136 4>;
+ clocks = <&clockgen 4 3>;
+ status = "disabled";
+
+ };
+
+ sata2: sata@3220000 {
+ compatible = "fsl,ls2080a-ahci";
+ reg = <0x0 0x3220000 0x0 0x10000>;
+ interrupts = <0 97 4>;
+ clocks = <&clockgen 4 3>;
+ status = "disabled";
+
+ };
+
+ sata3: sata@3230000 {
+ compatible = "fsl,ls2080a-ahci";
+ reg = <0x0 0x3230000 0x0 0x10000>;
+ interrupts = <0 100 4>;
+ clocks = <&clockgen 4 3>;
+ status = "disabled";
+
+ };
};