| commit | 55eb5fad1298abb5e0d8830e127625efbf98652c | [log] [tgz] |
|---|---|---|
| author | York Sun <yorksun@freescale.com> | Thu Mar 19 09:30:26 2015 -0700 |
| committer | York Sun <yorksun@freescale.com> | Thu Apr 23 08:55:53 2015 -0700 |
| tree | 669eca4ca7d0e4d6d62ce480455d346f2b192f2f | |
| parent | f1a5216b77b76abf8348a7ca203c81e1ec1847f0 [diff] |
drivers/ddr/fsl: Update DDR driver for DDR4 Add/update registers for DDR4, including DQ mappings. Allow raw timing method used for all controllers. Update mode_9 register to 0x500 for improved stability. Check DDR controller version number individually in case a SoC has multiple DDR controllers of different versions. Increase read-write turnaround for DDR4 high speeds. Signed-off-by: York Sun <yorksun@freescale.com>