rockchip: add px30 architecture core
Add core architecture code to support the px30 soc.
This includes a separate tpl board file due to very limited
sram size as well as a non-dm sdram driver, as this also has
to fit into the tiny sram.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
diff --git a/arch/arm/include/asm/arch-px30/boot0.h b/arch/arm/include/asm/arch-px30/boot0.h
new file mode 100644
index 0000000..2e78b07
--- /dev/null
+++ b/arch/arm/include/asm/arch-px30/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-px30/gpio.h b/arch/arm/include/asm/arch-px30/gpio.h
new file mode 100644
index 0000000..eca79d5
--- /dev/null
+++ b/arch/arm/include/asm/arch-px30/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 7746b66..3cb934a 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -1,5 +1,27 @@
if ARCH_ROCKCHIP
+config ROCKCHIP_PX30
+ bool "Support Rockchip PX30"
+ select ARM64
+ select SUPPORT_SPL
+ select SUPPORT_TPL
+ select SPL
+ select TPL
+ select TPL_TINY_FRAMEWORK if TPL
+ select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
+ select TPL_NEEDS_SEPARATE_STACK if TPL
+ imply SPL_SEPARATE_BSS
+ select SPL_SERIAL_SUPPORT
+ select TPL_SERIAL_SUPPORT
+ select DEBUG_UART_BOARD_INIT
+ imply ROCKCHIP_COMMON_BOARD
+ imply SPL_ROCKCHIP_COMMON_BOARD
+ help
+ The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35
+ including NEON and GPU, Mali-400 graphics, several DDR3 options
+ and video codec support. Peripherals include Gigabit Ethernet,
+ USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+
config ROCKCHIP_RK3036
bool "Support Rockchip RK3036"
select CPU_V7A
@@ -317,6 +339,7 @@
config SPL_MMC_SUPPORT
default y if !SPL_ROCKCHIP_BACK_TO_BROM
+source "arch/arm/mach-rockchip/px30/Kconfig"
source "arch/arm/mach-rockchip/rk3036/Kconfig"
source "arch/arm/mach-rockchip/rk3128/Kconfig"
source "arch/arm/mach-rockchip/rk3188/Kconfig"
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index a9563ad..3b58158 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -11,6 +11,7 @@
obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl-boot-order.o
obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o
+obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
@@ -27,6 +28,7 @@
obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram.o
+obj-$(CONFIG_ROCKCHIP_PX30) += px30/
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
diff --git a/arch/arm/mach-rockchip/px30-board-tpl.c b/arch/arm/mach-rockchip/px30-board-tpl.c
new file mode 100644
index 0000000..8c8976f
--- /dev/null
+++ b/arch/arm/mach-rockchip/px30-board-tpl.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/sdram_px30.h>
+
+#define TIMER_LOAD_COUNT0 0x00
+#define TIMER_LOAD_COUNT1 0x04
+#define TIMER_CUR_VALUE0 0x08
+#define TIMER_CUR_VALUE1 0x0c
+#define TIMER_CONTROL_REG 0x10
+
+#define TIMER_EN 0x1
+#define TIMER_FMODE (0 << 1)
+#define TIMER_RMODE (1 << 1)
+
+void secure_timer_init(void)
+{
+ writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_LOAD_COUNT0);
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_LOAD_COUNT1);
+ writel(TIMER_EN | TIMER_FMODE,
+ CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+ /*
+ * Debug UART can be used from here if required:
+ *
+ * debug_uart_init();
+ * printch('a');
+ * printhex8(0x1234);
+ * printascii("string");
+ */
+ printascii("U-Boot TPL board init\n");
+#endif
+
+ secure_timer_init();
+ ret = sdram_init();
+ if (ret)
+ printascii("sdram_init failed\n");
+
+ /* return to maskrom */
+ back_to_bootrom(BROM_BOOT_NEXTSTAGE);
+}
diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig
new file mode 100644
index 0000000..109a37b
--- /dev/null
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -0,0 +1,41 @@
+if ROCKCHIP_PX30
+
+config TARGET_EVB_PX30
+ bool "EVB_PX30"
+
+config ROCKCHIP_BOOT_MODE_REG
+ default 0xff010200
+
+config SYS_SOC
+ default "px30"
+
+config SYS_MALLOC_F_LEN
+ default 0x400
+
+config SPL_SERIAL_SUPPORT
+ default y
+
+config TPL_LDSCRIPT
+ default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
+
+config TPL_TEXT_BASE
+ default 0xff0e1000
+
+config TPL_MAX_SIZE
+ default 10240
+
+config TPL_STACK
+ default 0xff0e4fff
+
+config DEBUG_UART2_CHANNEL
+ int "Mux channel to use for debug UART2"
+ depends on DEBUG_UART_BOARD_INIT
+ default 0
+ help
+ UART2 can use two different set of pins to route the output.
+ For using the UART for early debugging the route to use needs
+ to be declared (0 or 1).
+
+source "board/rockchip/evb_px30/Kconfig"
+
+endif
diff --git a/arch/arm/mach-rockchip/px30/Makefile b/arch/arm/mach-rockchip/px30/Makefile
new file mode 100644
index 0000000..080ce14
--- /dev/null
+++ b/arch/arm/mach-rockchip/px30/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += clk_px30.o
+
+ifndef CONFIG_TPL_BUILD
+obj-y += syscon_px30.o
+endif
+
+obj-y += px30.o
diff --git a/arch/arm/mach-rockchip/px30/clk_px30.c b/arch/arm/mach-rockchip/px30/clk_px30.c
new file mode 100644
index 0000000..0bd6b47
--- /dev/null
+++ b/arch/arm/mach-rockchip/px30/clk_px30.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_px30.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(rockchip_px30_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+ struct px30_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->cru;
+}
diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c
new file mode 100644
index 0000000..bacdcc0
--- /dev/null
+++ b/arch/arm/mach-rockchip/px30/px30.c
@@ -0,0 +1,248 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
+ */
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/grf_px30.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/uart.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_px30.h>
+#include <dt-bindings/clock/px30-cru.h>
+
+static struct mm_region px30_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0xff000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xff000000UL,
+ .phys = 0xff000000UL,
+ .size = 0x01000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = px30_mem_map;
+
+#define PMU_PWRDN_CON 0xff000018
+#define GRF_BASE 0xff140000
+#define CRU_BASE 0xff2b0000
+#define VIDEO_PHY_BASE 0xff2e0000
+#define SERVICE_CORE_ADDR 0xff508000
+#define DDR_FW_BASE 0xff534000
+
+#define FW_DDR_CON 0x40
+
+#define QOS_PRIORITY 0x08
+
+#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3))
+
+/* GRF_GPIO1CL_IOMUX */
+enum {
+ GPIO1C1_SHIFT = 4,
+ GPIO1C1_MASK = 0xf << GPIO1C1_SHIFT,
+ GPIO1C1_GPIO = 0,
+ GPIO1C1_UART1_TX,
+
+ GPIO1C0_SHIFT = 0,
+ GPIO1C0_MASK = 0xf << GPIO1C0_SHIFT,
+ GPIO1C0_GPIO = 0,
+ GPIO1C0_UART1_RX,
+};
+
+/* GRF_GPIO1DL_IOMUX */
+enum {
+ GPIO1D3_SHIFT = 12,
+ GPIO1D3_MASK = 0xf << GPIO1D3_SHIFT,
+ GPIO1D3_GPIO = 0,
+ GPIO1D3_SDMMC_D1,
+ GPIO1D3_UART2_RXM0,
+
+ GPIO1D2_SHIFT = 8,
+ GPIO1D2_MASK = 0xf << GPIO1D2_SHIFT,
+ GPIO1D2_GPIO = 0,
+ GPIO1D2_SDMMC_D0,
+ GPIO1D2_UART2_TXM0,
+};
+
+/* GRF_GPIO1DH_IOMUX */
+enum {
+ GPIO1D7_SHIFT = 12,
+ GPIO1D7_MASK = 0xf << GPIO1D7_SHIFT,
+ GPIO1D7_GPIO = 0,
+ GPIO1D7_SDMMC_CMD,
+
+ GPIO1D6_SHIFT = 8,
+ GPIO1D6_MASK = 0xf << GPIO1D6_SHIFT,
+ GPIO1D6_GPIO = 0,
+ GPIO1D6_SDMMC_CLK,
+
+ GPIO1D5_SHIFT = 4,
+ GPIO1D5_MASK = 0xf << GPIO1D5_SHIFT,
+ GPIO1D5_GPIO = 0,
+ GPIO1D5_SDMMC_D3,
+
+ GPIO1D4_SHIFT = 0,
+ GPIO1D4_MASK = 0xf << GPIO1D4_SHIFT,
+ GPIO1D4_GPIO = 0,
+ GPIO1D4_SDMMC_D2,
+};
+
+/* GRF_GPIO2BH_IOMUX */
+enum {
+ GPIO2B6_SHIFT = 8,
+ GPIO2B6_MASK = 0xf << GPIO2B6_SHIFT,
+ GPIO2B6_GPIO = 0,
+ GPIO2B6_CIF_D1M0,
+ GPIO2B6_UART2_RXM1,
+
+ GPIO2B4_SHIFT = 0,
+ GPIO2B4_MASK = 0xf << GPIO2B4_SHIFT,
+ GPIO2B4_GPIO = 0,
+ GPIO2B4_CIF_D0M0,
+ GPIO2B4_UART2_TXM1,
+};
+
+/* GRF_GPIO3AL_IOMUX */
+enum {
+ GPIO3A2_SHIFT = 8,
+ GPIO3A2_MASK = 0xf << GPIO3A2_SHIFT,
+ GPIO3A2_GPIO = 0,
+ GPIO3A2_UART5_TX = 4,
+
+ GPIO3A1_SHIFT = 4,
+ GPIO3A1_MASK = 0xf << GPIO3A1_SHIFT,
+ GPIO3A1_GPIO = 0,
+ GPIO3A1_UART5_RX = 4,
+};
+
+int arch_cpu_init(void)
+{
+ static struct px30_grf * const grf = (void *)GRF_BASE;
+ u32 __maybe_unused val;
+
+#ifdef CONFIG_SPL_BUILD
+ /* We do some SoC one time setting here. */
+ /* Disable the ddr secure region setting to make it non-secure */
+ writel(0x0, DDR_FW_BASE + FW_DDR_CON);
+
+ /* Set cpu qos priority */
+ writel(QOS_PRIORITY_LEVEL(1, 1), SERVICE_CORE_ADDR + QOS_PRIORITY);
+
+#if !defined(CONFIG_DEBUG_UART_BOARD_INIT) || \
+ (CONFIG_DEBUG_UART_BASE != 0xff160000) || \
+ (CONFIG_DEBUG_UART_CHANNEL != 0)
+ /* fix sdmmc pinmux if not using uart2-channel0 as debug uart */
+ rk_clrsetreg(&grf->gpio1dl_iomux,
+ GPIO1D3_MASK | GPIO1D2_MASK,
+ GPIO1D3_SDMMC_D1 << GPIO1D3_SHIFT |
+ GPIO1D2_SDMMC_D0 << GPIO1D2_SHIFT);
+ rk_clrsetreg(&grf->gpio1dh_iomux,
+ GPIO1D7_MASK | GPIO1D6_MASK | GPIO1D5_MASK | GPIO1D4_MASK,
+ GPIO1D7_SDMMC_CMD << GPIO1D7_SHIFT |
+ GPIO1D6_SDMMC_CLK << GPIO1D6_SHIFT |
+ GPIO1D5_SDMMC_D3 << GPIO1D5_SHIFT |
+ GPIO1D4_SDMMC_D2 << GPIO1D4_SHIFT);
+#endif
+
+#endif
+
+ /* Enable PD_VO (default disable at reset) */
+ rk_clrreg(PMU_PWRDN_CON, 1 << 13);
+
+ /* Disable video phy bandgap by default */
+ writel(0x82, VIDEO_PHY_BASE + 0x0000);
+ writel(0x05, VIDEO_PHY_BASE + 0x03ac);
+
+ /* Clear the force_jtag */
+ rk_clrreg(&grf->cpu_con[1], 1 << 7);
+
+ return 0;
+}
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+ static struct px30_grf * const grf = (void *)GRF_BASE;
+ static struct px30_cru * const cru = (void *)CRU_BASE;
+
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff158000)
+ /* uart_sel_clk default select 24MHz */
+ rk_clrsetreg(&cru->clksel_con[34],
+ UART1_PLL_SEL_MASK | UART1_DIV_CON_MASK,
+ UART1_PLL_SEL_24M << UART1_PLL_SEL_SHIFT | 0);
+ rk_clrsetreg(&cru->clksel_con[35],
+ UART1_CLK_SEL_MASK,
+ UART1_CLK_SEL_UART1 << UART1_CLK_SEL_SHIFT);
+
+ rk_clrsetreg(&grf->gpio1cl_iomux,
+ GPIO1C1_MASK | GPIO1C0_MASK,
+ GPIO1C1_UART1_TX << GPIO1C1_SHIFT |
+ GPIO1C0_UART1_RX << GPIO1C0_SHIFT);
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff178000)
+ /* uart_sel_clk default select 24MHz */
+ rk_clrsetreg(&cru->clksel_con[46],
+ UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK,
+ UART5_PLL_SEL_24M << UART5_PLL_SEL_SHIFT | 0);
+ rk_clrsetreg(&cru->clksel_con[47],
+ UART5_CLK_SEL_MASK,
+ UART5_CLK_SEL_UART5 << UART5_CLK_SEL_SHIFT);
+
+ rk_clrsetreg(&grf->gpio3al_iomux,
+ GPIO3A2_MASK | GPIO3A1_MASK,
+ GPIO3A2_UART5_TX << GPIO3A2_SHIFT |
+ GPIO3A1_UART5_RX << GPIO3A1_SHIFT);
+#else
+ /* GRF_IOFUNC_CON0 */
+ enum {
+ CON_IOMUX_UART2SEL_SHIFT = 10,
+ CON_IOMUX_UART2SEL_MASK = 3 << CON_IOMUX_UART2SEL_SHIFT,
+ CON_IOMUX_UART2SEL_M0 = 0,
+ CON_IOMUX_UART2SEL_M1,
+ CON_IOMUX_UART2SEL_USBPHY,
+ };
+
+ /* uart_sel_clk default select 24MHz */
+ rk_clrsetreg(&cru->clksel_con[37],
+ UART2_PLL_SEL_MASK | UART2_DIV_CON_MASK,
+ UART2_PLL_SEL_24M << UART2_PLL_SEL_SHIFT | 0);
+ rk_clrsetreg(&cru->clksel_con[38],
+ UART2_CLK_SEL_MASK,
+ UART2_CLK_SEL_UART2 << UART2_CLK_SEL_SHIFT);
+
+#if (CONFIG_DEBUG_UART2_CHANNEL == 1)
+ /* Enable early UART2 */
+ rk_clrsetreg(&grf->iofunc_con0,
+ CON_IOMUX_UART2SEL_MASK,
+ CON_IOMUX_UART2SEL_M1 << CON_IOMUX_UART2SEL_SHIFT);
+
+ rk_clrsetreg(&grf->gpio2bh_iomux,
+ GPIO2B6_MASK | GPIO2B4_MASK,
+ GPIO2B6_UART2_RXM1 << GPIO2B6_SHIFT |
+ GPIO2B4_UART2_TXM1 << GPIO2B4_SHIFT);
+#else
+ rk_clrsetreg(&grf->iofunc_con0,
+ CON_IOMUX_UART2SEL_MASK,
+ CON_IOMUX_UART2SEL_M0 << CON_IOMUX_UART2SEL_SHIFT);
+
+ rk_clrsetreg(&grf->gpio1dl_iomux,
+ GPIO1D3_MASK | GPIO1D2_MASK,
+ GPIO1D3_UART2_RXM0 << GPIO1D3_SHIFT |
+ GPIO1D2_UART2_TXM0 << GPIO1D2_SHIFT);
+#endif /* CONFIG_DEBUG_UART2_CHANNEL == 1 */
+
+#endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */
+}
+#endif /* CONFIG_DEBUG_UART_BOARD_INIT */
diff --git a/arch/arm/mach-rockchip/px30/syscon_px30.c b/arch/arm/mach-rockchip/px30/syscon_px30.c
new file mode 100644
index 0000000..0331491
--- /dev/null
+++ b/arch/arm/mach-rockchip/px30/syscon_px30.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+
+static const struct udevice_id px30_syscon_ids[] = {
+ { .compatible = "rockchip,px30-pmu", .data = ROCKCHIP_SYSCON_PMU },
+ { .compatible = "rockchip,px30-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF },
+ { .compatible = "rockchip,px30-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_px30) = {
+ .id = UCLASS_SYSCON,
+ .name = "px30_syscon",
+ .of_match = px30_syscon_ids,
+};
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int px30_syscon_bind_of_platdata(struct udevice *dev)
+{
+ dev->driver_data = dev->driver->of_match->data;
+ debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(rockchip_px30_pmu) = {
+ .name = "rockchip_px30_pmu",
+ .id = UCLASS_SYSCON,
+ .of_match = px30_syscon_ids,
+ .bind = px30_syscon_bind_of_platdata,
+};
+
+U_BOOT_DRIVER(rockchip_px30_pmugrf) = {
+ .name = "rockchip_px30_pmugrf",
+ .id = UCLASS_SYSCON,
+ .of_match = px30_syscon_ids + 1,
+ .bind = px30_syscon_bind_of_platdata,
+};
+
+U_BOOT_DRIVER(rockchip_px30_grf) = {
+ .name = "rockchip_px30_grf",
+ .id = UCLASS_SYSCON,
+ .of_match = px30_syscon_ids + 2,
+ .bind = px30_syscon_bind_of_platdata,
+};
+#endif