rockchip: clk: rk3368: implement MMC/SD clock reparenting
The original clock support for MMC/SD cards on the RK3368 suffered
from a tendency to select a divider less-or-equal to the the one
giving the requested clock-rate: this can lead to higher-than-expected
(or rather: higher than supported) clock rates for the MMC/SD
communiction.
This change rewrites the MMC/SD clock generation to:
* always generate a clock less-than-or-equal to the requested clock
* support reparenting among the CPLL, GPLL and OSC24M parents to
generate the highest clock that does not exceed the requested rate
In addition to this, the Linux DTS uses HCLK_MMC/HCLK_SDMMC instead of
SCLK_MMC/SCLK_SDMMC: to match this (and to ensure that clock setup
always works), we adjust the driver appropriately.
This includes the changes from:
- rockchip: clk: rk3368: convert MMC_PLL_SEL_* definitions to shifted-value form
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
index bf09e2f..21f11e0 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -92,10 +92,10 @@
/* CLKSEL51_CON */
MMC_PLL_SEL_SHIFT = 8,
MMC_PLL_SEL_MASK = GENMASK(9, 8),
- MMC_PLL_SEL_CPLL = 0,
- MMC_PLL_SEL_GPLL,
- MMC_PLL_SEL_USBPHY_480M,
- MMC_PLL_SEL_24M,
+ MMC_PLL_SEL_CPLL = (0 << MMC_PLL_SEL_SHIFT),
+ MMC_PLL_SEL_GPLL = (1 << MMC_PLL_SEL_SHIFT),
+ MMC_PLL_SEL_USBPHY_480M = (2 << MMC_PLL_SEL_SHIFT),
+ MMC_PLL_SEL_24M = (3 << MMC_PLL_SEL_SHIFT),
MMC_CLK_DIV_SHIFT = 0,
MMC_CLK_DIV_MASK = GENMASK(6, 0),