tree 4874c74b6becbc28e8f226702993b05518c269dc
parent 10a0abb239ed71c7e78daf814db782caed6fcd21
author Caleb Connolly <caleb.connolly@linaro.org> 1699360864 +0000
committer Caleb Connolly <caleb.connolly@linaro.org> 1705407984 +0000

clk/qcom: add mnd_width to clk_rcg_set_rate_mnd()

This property is needed on some platforms to ensure that only the
relevant bits are set in the M/N/D registers.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>