mips: traps: Set WG bit in EBase register on Octeon
WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of
the exception base register.
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 7538e6b..1738130 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -366,6 +366,7 @@
* Bits in the coprocessor 0 EBase register.
*/
#define EBASE_CPUNUM 0x3ff
+#define EBASE_WG (_ULCAST_(1) << 11)
/*
* Bits in the coprocessor 0 config register.
diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c
index b1ae02f..6ff9d20 100644
--- a/arch/mips/lib/traps.c
+++ b/arch/mips/lib/traps.c
@@ -108,6 +108,10 @@
saved_ebase = read_c0_ebase() & 0xfffff000;
+ /* Set WG bit on Octeon to enable writing to bits 63:30 */
+ if (IS_ENABLED(CONFIG_ARCH_OCTEON))
+ ebase |= EBASE_WG;
+
write_c0_ebase(ebase);
clear_c0_status(ST0_BEV);
execution_hazard_barrier();