tree 7a6452a49664a4ae7783fa56a98f46092d02505e
parent c3b5b1b78913a1126eb531d6a8836fb872ec6323
author Caleb Connolly <caleb.connolly@linaro.org> 1713193420 +0100
committer Caleb Connolly <caleb.connolly@linaro.org> 1713871756 +0200

serial: msm: calculate bit clock divider

The driver currently requires the bit clock divider be hardcoded in
devicetree (or use the hardcoded default from apq8016).

The bit clock divider is used to derive the baud rate from the core
clock:

  baudrate = clk_rate / csr_div

clk_rate is the actual programmed core clock rate which is returned by
clk_set_rate(), and this UART driver only supports a baudrate of 115200.
We can therefore determine the appropriate value for UARTDM_CSR by
iterating over the possible values and finding the one where the
equation above holds true for a baudrate of 115200.

Implement this logic and drop the non-standard DT bindings for this
driver.

Tested on dragonboard410c.

Tested-by: Robert Marko <robert.marko@sartura.hr>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>