Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
diff --git a/Kconfig b/Kconfig
index f34f341..153ee2b 100644
--- a/Kconfig
+++ b/Kconfig
@@ -58,6 +58,14 @@
endmenu # General setup
+menuconfig EXPERT
+ bool "Configure standard U-Boot features (expert users)"
+ help
+ This option allows certain base U-Boot options and settings
+ to be disabled or tweaked. This is for specialized
+ environments which can tolerate a "non-standard" U-Boot.
+ Only use this if you really know what you are doing.
+
menu "Boot images"
config SPL_BUILD
@@ -93,6 +101,28 @@
help
If you want to build TPL as well as the normal image and SPL, say Y.
+config FIT
+ bool "Support Flattened Image Tree"
+ depends on !SPL_BUILD
+ help
+ This option allows to boot the new uImage structrure,
+ Flattened Image Tree. FIT is formally a FDT, which can include
+ images of various types (kernel, FDT blob, ramdisk, etc.)
+ in a single blob. To boot this new uImage structure,
+ pass the the address of the blob to the "bootm" command.
+
+config FIT_VERBOSE
+ bool "Display verbose messages on FIT boot"
+ depends on FIT
+
+config FIT_SIGNATURE
+ bool "Enabel signature verification of FIT uImages"
+ depends on FIT
+ help
+ This option enables signature verification of FIT uImages,
+ using a hash signed and verified using RSA.
+ See doc/uImage.FIT/signature.txt for more details.
+
config SYS_EXTRA_OPTIONS
string "Extra Options (DEPRECATED)"
depends on !SPL_BUILD
diff --git a/Makefile b/Makefile
index ddea534..79cb45c 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
VERSION = 2015
PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
NAME =
# *DOCUMENTATION*
@@ -610,9 +610,6 @@
libs-y += lib/
libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
libs-y += $(CPUDIR)/
-ifdef SOC
-libs-y += $(CPUDIR)/$(SOC)/
-endif
libs-$(CONFIG_OF_EMBED) += dts/
libs-y += arch/$(ARCH)/lib/
libs-y += fs/
@@ -749,6 +746,9 @@
endif
ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
+# We can't do this yet due to the need for binary blobs
+# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
+
# enable combined SPL/u-boot/dtb rules for tegra
ifneq ($(CONFIG_TEGRA),)
ifeq ($(CONFIG_SPL),y)
@@ -817,7 +817,8 @@
u-boot.hex u-boot.srec: u-boot FORCE
$(call if_changed,objcopy)
-OBJCOPYFLAGS_u-boot.bin := -O binary
+OBJCOPYFLAGS_u-boot.bin := -O binary \
+ $(if $(CONFIG_X86_RESET_VECTOR),-R .start16 -R .resetvec)
binary_size_check: u-boot.bin FORCE
@file_size=$(shell wc -c u-boot.bin | awk '{print $$1}') ; \
@@ -956,6 +957,36 @@
$(call if_changed,mkimage)
@dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@
+# x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including
+# reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in
+# the middle.
+ifneq ($(CONFIG_X86_RESET_VECTOR),)
+rom: u-boot.rom FORCE
+
+u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \
+ $(srctree)/board/$(BOARDDIR)/mrc.bin
+ $(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) u-boot.tmp
+ if [ -n "$(CONFIG_HAVE_INTEL_ME)" ]; then \
+ $(objtree)/tools/ifdtool -D \
+ $(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp; \
+ $(objtree)/tools/ifdtool \
+ -i ME:$(srctree)/board/$(BOARDDIR)/me.bin u-boot.tmp; \
+ fi
+ $(objtree)/tools/ifdtool -w \
+ $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin u-boot.tmp
+ $(objtree)/tools/ifdtool -w \
+ $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin \
+ u-boot.tmp
+ $(objtree)/tools/ifdtool -w \
+ $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \
+ u-boot.tmp
+ mv u-boot.tmp $@
+
+OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
+u-boot-x86-16bit.bin: u-boot FORCE
+ $(call if_changed,objcopy)
+endif
+
ifneq ($(CONFIG_SUNXI),)
OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
--pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
diff --git a/README b/README
index 837dca0..66770b6 100644
--- a/README
+++ b/README
@@ -623,6 +623,120 @@
exists, unlike the similar options in the Linux kernel. Do not
set these options unless they apply!
+- Driver Model
+ Driver model is a new framework for devices in U-Boot
+ introduced in early 2014. U-Boot is being progressively
+ moved over to this. It offers a consistent device structure,
+ supports grouping devices into classes and has built-in
+ handling of platform data and device tree.
+
+ To enable transition to driver model in a relatively
+ painful fashion, each subsystem can be independently
+ switched between the legacy/ad-hoc approach and the new
+ driver model using the options below. Also, many uclass
+ interfaces include compatibility features which may be
+ removed once the conversion of that subsystem is complete.
+ As a result, the API provided by the subsystem may in fact
+ not change with driver model.
+
+ See doc/driver-model/README.txt for more information.
+
+ CONFIG_DM
+
+ Enable driver model. This brings in the core support,
+ including scanning of platform data on start-up. If
+ CONFIG_OF_CONTROL is enabled, the device tree will be
+ scanned also when available.
+
+ CONFIG_CMD_DM
+
+ Enable driver model test commands. These allow you to print
+ out the driver model tree and the uclasses.
+
+ CONFIG_DM_DEMO
+
+ Enable some demo devices and the 'demo' command. These are
+ really only useful for playing around while trying to
+ understand driver model in sandbox.
+
+ CONFIG_SPL_DM
+
+ Enable driver model in SPL. You will need to provide a
+ suitable malloc() implementation. If you are not using the
+ full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
+ consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you
+ must provide CONFIG_SYS_MALLOC_F_LEN to set the size.
+ In most cases driver model will only allocate a few uclasses
+ and devices in SPL, so 1KB should be enable. See
+ CONFIG_SYS_MALLOC_F_LEN for more details on how to enable
+ it.
+
+ CONFIG_DM_SERIAL
+
+ Enable driver model for serial. This replaces
+ drivers/serial/serial.c with the serial uclass, which
+ implements serial_putc() etc. The uclass interface is
+ defined in include/serial.h.
+
+ CONFIG_DM_GPIO
+
+ Enable driver model for GPIO access. The standard GPIO
+ interface (gpio_get_value(), etc.) is then implemented by
+ the GPIO uclass. Drivers provide methods to query the
+ particular GPIOs that they provide. The uclass interface
+ is defined in include/asm-generic/gpio.h.
+
+ CONFIG_DM_SPI
+
+ Enable driver model for SPI. The SPI slave interface
+ (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
+ the SPI uclass. Drivers provide methods to access the SPI
+ buses that they control. The uclass interface is defined in
+ include/spi.h. The existing spi_slave structure is attached
+ as 'parent data' to every slave on each bus. Slaves
+ typically use driver-private data instead of extending the
+ spi_slave structure.
+
+ CONFIG_DM_SPI_FLASH
+
+ Enable driver model for SPI flash. This SPI flash interface
+ (spi_flash_probe(), spi_flash_write(), etc.) is then
+ implemented by the SPI flash uclass. There is one standard
+ SPI flash driver which knows how to probe most chips
+ supported by U-Boot. The uclass interface is defined in
+ include/spi_flash.h, but is currently fully compatible
+ with the old interface to avoid confusion and duplication
+ during the transition parent. SPI and SPI flash must be
+ enabled together (it is not possible to use driver model
+ for one and not the other).
+
+ CONFIG_DM_CROS_EC
+
+ Enable driver model for the Chrome OS EC interface. This
+ allows the cros_ec SPI driver to operate with CONFIG_DM_SPI
+ but otherwise makes few changes. Since cros_ec also supports
+ I2C and LPC (which don't support driver model yet), a full
+ conversion is not yet possible.
+
+
+ ** Code size options: The following options are enabled by
+ default except in SPL. Enable them explicitly to get these
+ features in SPL.
+
+ CONFIG_DM_WARN
+
+ Enable the dm_warn() function. This can use up quite a bit
+ of space for its strings.
+
+ CONFIG_DM_STDIO
+
+ Enable registering a serial device with the stdio library.
+
+ CONFIG_DM_DEVICE_REMOVE
+
+ Enable removing of devices.
+
+
- Linux Kernel Interface:
CONFIG_CLOCKS_IN_MHZ
@@ -669,6 +783,13 @@
Board code has addition modification that it wants to make
to the flat device tree before handing it off to the kernel
+ CONFIG_OF_SYSTEM_SETUP
+
+ Other code has addition modification that it wants to make
+ to the flat device tree before handing it off to the kernel.
+ This causes ft_system_setup() to be called before booting
+ the kernel.
+
CONFIG_OF_BOOT_CPU
This define fills in the correct boot CPU in the boot
@@ -989,6 +1110,7 @@
CONFIG_CMD_EXT4 * ext4 command support
CONFIG_CMD_FS_GENERIC * filesystem commands (e.g. load, ls)
that work for multiple fs types
+ CONFIG_CMD_FS_UUID * Look up a filesystem UUID
CONFIG_CMD_SAVEENV saveenv
CONFIG_CMD_FDC * Floppy Disk Support
CONFIG_CMD_FAT * FAT command support
@@ -2834,18 +2956,6 @@
Enable auto completion of commands using TAB.
- CONFIG_SYS_HUSH_PARSER
-
- Define this variable to enable the "hush" shell (from
- Busybox) as command line interpreter, thus enabling
- powerful command line syntax like
- if...then...else...fi conditionals or `&&' and '||'
- constructs ("shell scripts").
-
- If undefined, you get the old, much simpler behaviour
- with a somewhat smaller memory footprint.
-
-
CONFIG_SYS_PROMPT_HUSH_PS2
This defines the secondary prompt string, which is
@@ -3407,7 +3517,7 @@
to 128 or 256, although it does not have to be power of 2).
default: 4096
-
+
CONFIG_MTD_UBI_BEB_LIMIT
This option specifies the maximum bad physical eraseblocks UBI
expects on the MTD device (per 1024 eraseblocks). If the
@@ -3881,6 +3991,11 @@
Pre-relocation malloc() is only supported on ARM and sandbox
at present but is fairly easy to enable for other archs.
+- CONFIG_SYS_MALLOC_SIMPLE
+ Provides a simple and small malloc() and calloc() for those
+ boards which do not use the full malloc in SPL (which is
+ enabled with CONFIG_SYS_SPL_MALLOC_START).
+
- CONFIG_SYS_BOOTM_LEN:
Normally compressed uImages are limited to an
uncompressed size of 8 MBytes. If this is not enough,
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9b492be..b9ac59e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -415,6 +415,8 @@
config TARGET_VEXPRESS_CA15_TC2
bool "Support vexpress_ca15_tc2"
select CPU_V7
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
config TARGET_VEXPRESS_CA5X2
bool "Support vexpress_ca5x2"
@@ -521,12 +523,12 @@
bool "Support bcm28155_ap"
select CPU_V7
-config TARGET_BCM958300K
- bool "Support bcm958300k"
+config TARGET_BCMCYGNUS
+ bool "Support bcmcygnus"
select CPU_V7
-config TARGET_BCM958622HR
- bool "Support bcm958622hr"
+config TARGET_BCMNSP
+ bool "Support bcmnsp"
select CPU_V7
config ARCH_EXYNOS
@@ -826,6 +828,8 @@
source "arch/arm/cpu/armv7/zynq/Kconfig"
+source "arch/arm/cpu/armv7/Kconfig"
+
source "board/aristainetos/Kconfig"
source "board/BuR/kwb/Kconfig"
source "board/BuR/tseries/Kconfig"
@@ -861,8 +865,8 @@
source "board/bluewater/snapper9260/Kconfig"
source "board/boundary/nitrogen6x/Kconfig"
source "board/broadcom/bcm28155_ap/Kconfig"
-source "board/broadcom/bcm958300k/Kconfig"
-source "board/broadcom/bcm958622hr/Kconfig"
+source "board/broadcom/bcmcygnus/Kconfig"
+source "board/broadcom/bcmnsp/Kconfig"
source "board/calao/sbc35_a9g20/Kconfig"
source "board/calao/tny_a9260/Kconfig"
source "board/calao/usb_a9263/Kconfig"
diff --git a/arch/arm/cpu/arm1136/Makefile b/arch/arm/cpu/arm1136/Makefile
index 3279f12..56a9390 100644
--- a/arch/arm/cpu/arm1136/Makefile
+++ b/arch/arm/cpu/arm1136/Makefile
@@ -7,3 +7,6 @@
extra-y = start.o
obj-y = cpu.o
+
+obj-$(CONFIG_MX31) += mx31/
+obj-$(CONFIG_MX35) += mx35/
diff --git a/arch/arm/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile
index deec427..ead2303 100644
--- a/arch/arm/cpu/arm1176/Makefile
+++ b/arch/arm/cpu/arm1176/Makefile
@@ -10,3 +10,6 @@
extra-y = start.o
obj-y = cpu.o
+
+obj-$(CONFIG_BCM2835) += bcm2835/
+obj-$(CONFIG_TNETV107X) += tnetv107x/
diff --git a/arch/arm/cpu/arm1176/tnetv107x/clock.c b/arch/arm/cpu/arm1176/tnetv107x/clock.c
index 47c23bb..7ba28d3 100644
--- a/arch/arm/cpu/arm1176/tnetv107x/clock.c
+++ b/arch/arm/cpu/arm1176/tnetv107x/clock.c
@@ -16,7 +16,7 @@
#define BIT(x) (1 << (x))
#define MAX_PREDIV 64
-#define MAX_POSTDIV 8
+#define MAX_POSTDIV 8UL
#define MAX_MULT 512
#define MAX_DIV (MAX_PREDIV * MAX_POSTDIV)
@@ -362,7 +362,7 @@
pllctl_reg_write(data->pll, ctl, tmp);
mult = data->pll_freq / fpll;
- for (mult = max(mult, 1); mult <= MAX_MULT; mult++) {
+ for (mult = max(mult, 1UL); mult <= MAX_MULT; mult++) {
div = (fpll * mult) / data->pll_freq;
if (div < 1 || div > MAX_DIV)
continue;
diff --git a/arch/arm/cpu/arm720t/Makefile b/arch/arm/cpu/arm720t/Makefile
index 6badb3b..9f61ea2 100644
--- a/arch/arm/cpu/arm720t/Makefile
+++ b/arch/arm/cpu/arm720t/Makefile
@@ -9,3 +9,7 @@
obj-y = interrupts.o cpu.o
obj-$(CONFIG_TEGRA) += tegra-common/
+obj-$(CONFIG_TEGRA20) += tegra20/
+obj-$(CONFIG_TEGRA30) += tegra30/
+obj-$(CONFIG_TEGRA114) += tegra114/
+obj-$(CONFIG_TEGRA124) += tegra124/
diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile
index aac8043..a72e5de 100644
--- a/arch/arm/cpu/arm920t/Makefile
+++ b/arch/arm/cpu/arm920t/Makefile
@@ -9,3 +9,10 @@
obj-y += cpu.o
obj-$(CONFIG_USE_IRQ) += interrupts.o
+
+obj-$(if $(filter a320,$(SOC)),y) += a320/
+obj-$(CONFIG_AT91FAMILY) += at91/
+obj-$(CONFIG_EP93XX) += ep93xx/
+obj-$(CONFIG_IMX) += imx/
+obj-$(CONFIG_KS8695) += ks8695/
+obj-$(CONFIG_S3C24X0) += s3c24x0/
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index 1252995..adcea9f 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -13,3 +13,18 @@
extra-y :=
endif
endif
+
+obj-$(CONFIG_ARMADA100) += armada100/
+obj-$(CONFIG_AT91FAMILY) += at91/
+obj-$(CONFIG_ARCH_DAVINCI) += davinci/
+obj-$(CONFIG_KIRKWOOD) += kirkwood/
+obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
+obj-$(CONFIG_MB86R0x) += mb86r0x/
+obj-$(CONFIG_MX25) += mx25/
+obj-$(CONFIG_MX27) += mx27/
+obj-$(if $(filter mxs,$(SOC)),y) += mxs/
+obj-$(CONFIG_ARCH_NOMADIK) += nomadik/
+obj-$(CONFIG_ORION5X) += orion5x/
+obj-$(CONFIG_PANTHEON) += pantheon/
+obj-$(if $(filter spear,$(SOC)),y) += spear/
+obj-$(CONFIG_ARCH_VERSATILE) += versatile/
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
index 7a7fd7d..efb53d6 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <dm.h>
#include <asm/io.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91_common.h>
@@ -229,3 +230,16 @@
at91_set_a_periph(AT91_PIO_PORTC, 30, 0);
at91_set_a_periph(AT91_PIO_PORTC, 31, 0);
}
+
+/* Platform data for the GPIOs */
+static const struct at91_port_platdata at91sam9260_plat[] = {
+ { ATMEL_BASE_PIOA, "PA" },
+ { ATMEL_BASE_PIOB, "PB" },
+ { ATMEL_BASE_PIOC, "PC" },
+};
+
+U_BOOT_DEVICES(at91sam9260_gpios) = {
+ { "gpio_at91", &at91sam9260_plat[0] },
+ { "gpio_at91", &at91sam9260_plat[1] },
+ { "gpio_at91", &at91sam9260_plat[2] },
+};
diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile b/arch/arm/cpu/arm926ejs/mx27/Makefile
index 4976bbb..0edf144 100644
--- a/arch/arm/cpu/arm926ejs/mx27/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx27/Makefile
@@ -5,3 +5,7 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y = generic.o reset.o timer.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y += relocate.o
+endif
diff --git a/arch/arm/cpu/arm926ejs/mx27/relocate.S b/arch/arm/cpu/arm926ejs/mx27/relocate.S
new file mode 100644
index 0000000..0c4b272
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mx27/relocate.S
@@ -0,0 +1,51 @@
+/*
+ * relocate - i.MX27-specific vector relocation
+ *
+ * Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+
+/*
+ * The i.MX27 SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0xFFFF0000),
+ * thus only the low address (0x00000000) is useable; but that is
+ * in ROM. Therefore, vectors cannot be changed at all.
+ *
+ * However, these ROM-based vectors actually just perform indirect
+ * calls through pointers located in RAM at SoC-specific addresses,
+ * as follows:
+ *
+ * Offset Exception Use by ROM code
+ * 0x00000000 reset indirect branch to [0x00000014]
+ * 0x00000004 undefined instruction indirect branch to [0xfffffef0]
+ * 0x00000008 software interrupt indirect branch to [0xfffffef4]
+ * 0x0000000c prefetch abort indirect branch to [0xfffffef8]
+ * 0x00000010 data abort indirect branch to [0xfffffefc]
+ * 0x00000014 (reserved in ARMv5) vector to ROM reset: 0xc0000000
+ * 0x00000018 IRQ indirect branch to [0xffffff00]
+ * 0x0000001c FIQ indirect branch to [0xffffff04]
+ *
+ * In order to initialize exceptions on i.MX27, we must copy U-Boot's
+ * indirect (not exception!) vector table into 0xfffffef0..0xffffff04
+ * taking care not to copy vectors number 5 (reserved exception).
+ */
+
+ .section .text.relocate_vectors,"ax",%progbits
+
+ENTRY(relocate_vectors)
+
+ ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
+ ldr r1, =32 /* size of vector table */
+ add r0, r0, r1 /* skip to indirect table */
+ ldr r1, =0xFFFFFEF0 /* i.MX27 indirect table */
+ ldmia r0!, {r2-r8} /* load indirect vectors 1..7 */
+ stmia r1!, {r2-r5, r7,r8} /* write all but vector 5 */
+
+ bx lr
+
+ENDPROC(relocate_vectors)
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg
index 1520bba..83953da 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg
+++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg
@@ -1,3 +1,4 @@
+DISPLAYPROGRESS
SECTION 0x0 BOOTABLE
TAG LAST
LOAD 0x1000 spl/u-boot-spl.bin
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
index 55510e9..e702809 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
+++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
@@ -1,3 +1,4 @@
+DISPLAYPROGRESS
SECTION 0x0 BOOTABLE
TAG LAST
LOAD 0x1000 spl/u-boot-spl.bin
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
index bb78cb0..3f7bf59 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
+++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
@@ -1,3 +1,4 @@
+DISPLAYPROGRESS
SECTION 0x0 BOOTABLE
TAG LAST
LOAD 0x1000 spl/u-boot-spl.bin
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index d25019a..1c54ab7 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -1002,7 +1002,8 @@
uint32_t powered_by_linreg = 0;
int adjust_up, tmp;
- new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV);
+ new_brownout = DIV_ROUND_CLOSEST(new_target - new_brownout,
+ cfg->step_mV);
cur_target = readl(cfg->reg);
cur_target &= cfg->trg_mask;
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
new file mode 100644
index 0000000..61e7c82
--- /dev/null
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -0,0 +1,34 @@
+if CPU_V7
+
+config CPU_V7_HAS_NONSEC
+ bool
+
+config CPU_V7_HAS_VIRT
+ bool
+
+config ARMV7_NONSEC
+ boolean "Enable support for booting in non-secure mode" if EXPERT
+ depends on CPU_V7_HAS_NONSEC
+ default y
+ ---help---
+ Say Y here to enable support for booting in non-secure / SVC mode.
+
+config ARMV7_BOOT_SEC_DEFAULT
+ boolean "Boot in secure mode by default" if EXPERT
+ depends on ARMV7_NONSEC
+ default n
+ ---help---
+ Say Y here to boot in secure mode by default even if non-secure mode
+ is supported. This option is useful to boot kernels which do not
+ suppport booting in non-secure mode. Only set this if you need it.
+ This can be overriden at run-time by setting the bootm_boot_mode env.
+ variable to "sec" or "nonsec".
+
+config ARMV7_VIRT
+ boolean "Enable support for hardware virtualization" if EXPERT
+ depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC
+ default y
+ ---help---
+ Say Y here to boot in hypervisor (HYP) mode when booting non-secure.
+
+endif
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index afeed4d..e419716 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -37,3 +37,28 @@
ifneq (,$(filter s5pc1xx exynos,$(SOC)))
obj-y += s5p-common/
endif
+
+obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
+obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/
+obj-$(CONFIG_AT91FAMILY) += at91/
+obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
+obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
+obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
+obj-$(CONFIG_ARCH_EXYNOS) += exynos/
+obj-$(CONFIG_ARCH_HIGHBANK) += highbank/
+obj-$(CONFIG_ARCH_KEYSTONE) += keystone/
+obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
+obj-$(if $(filter mx5,$(SOC)),y) += mx5/
+obj-$(CONFIG_MX6) += mx6/
+obj-$(CONFIG_OMAP34XX) += omap3/
+obj-$(CONFIG_OMAP44XX) += omap4/
+obj-$(CONFIG_OMAP54XX) += omap5/
+obj-$(CONFIG_RMOBILE) += rmobile/
+obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/
+obj-$(CONFIG_SOCFPGA) += socfpga/
+obj-$(CONFIG_ARCH_SUNXI) += sunxi/
+obj-$(CONFIG_TEGRA20) += tegra20/
+obj-$(CONFIG_U8500) += u8500/
+obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/
+obj-$(CONFIG_VF610) += vf610/
+obj-$(CONFIG_ZYNQ) += zynq/
diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.h b/arch/arm/cpu/armv7/bcm281xx/clk-core.h
index 882a297..4a694d7 100644
--- a/arch/arm/cpu/armv7/bcm281xx/clk-core.h
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.h
@@ -73,10 +73,6 @@
struct refclk *refclk_str_to_clk(const char *name);
-#define U8_MAX ((u8)~0U)
-#define U32_MAX ((u32)~0U)
-#define U64_MAX ((u64)~0U)
-
/* The common clock framework uses u8 to represent a parent index */
#define PARENT_COUNT_MAX ((u32)U8_MAX)
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig
index 090be93..f3eadb4 100644
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ b/arch/arm/cpu/armv7/exynos/Kconfig
@@ -26,6 +26,8 @@
config TARGET_ARNDALE
bool "Exynos5250 Arndale board"
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
@@ -44,11 +46,16 @@
select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
-config TARGET_PEACH_PIT
+config TARGET_PEACH_PI
bool "Peach Pi board"
select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
+config TARGET_PEACH_PIT
+ bool "Peach Pit board"
+ select SUPPORT_SPL
+ select OF_CONTROL if !SPL_BUILD
+
endchoice
config SYS_SOC
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 7558eff..8fab135 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -118,7 +118,8 @@
div = PLL_DIV_1024;
else if (proid_is_exynos4412())
div = PLL_DIV_65535;
- else if (proid_is_exynos5250() || proid_is_exynos5420())
+ else if (proid_is_exynos5250() || proid_is_exynos5420()
+ || proid_is_exynos5800())
div = PLL_DIV_65536;
else
return 0;
@@ -1422,8 +1423,8 @@
return 1;
for (i = 1; i <= loops; i++) {
- const unsigned int effective_div = max(min(input_rate / i /
- target_rate, cap), 1);
+ const unsigned int effective_div =
+ max(min(input_rate / i / target_rate, cap), 1U);
const unsigned int effective_rate = input_rate / i /
effective_div;
const int error = target_rate - effective_rate;
@@ -1581,7 +1582,7 @@
unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_pll_clk(pllreg);
return exynos5_get_pll_clk(pllreg);
} else {
@@ -1617,7 +1618,7 @@
unsigned long get_pwm_clk(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_pwm_clk();
return clock_get_periph_rate(PERIPH_ID_PWM0);
} else {
@@ -1630,7 +1631,7 @@
unsigned long get_uart_clk(int dev_index)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_uart_clk(dev_index);
return exynos5_get_uart_clk(dev_index);
} else {
@@ -1643,7 +1644,7 @@
unsigned long get_mmc_clk(int dev_index)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_mmc_clk(dev_index);
return exynos5_get_mmc_clk(dev_index);
} else {
@@ -1654,7 +1655,7 @@
void set_mmc_clk(int dev_index, unsigned int div)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
exynos5420_set_mmc_clk(dev_index, div);
else
exynos5_set_mmc_clk(dev_index, div);
@@ -1668,7 +1669,7 @@
if (cpu_is_exynos4())
return exynos4_get_lcd_clk();
else {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_lcd_clk();
else
return exynos5_get_lcd_clk();
@@ -1682,7 +1683,7 @@
else {
if (proid_is_exynos5250())
exynos5_set_lcd_clk();
- else if (proid_is_exynos5420())
+ else if (proid_is_exynos5420() || proid_is_exynos5800())
exynos5420_set_lcd_clk();
}
}
@@ -1696,7 +1697,7 @@
int set_spi_clk(int periph_id, unsigned int rate)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_set_spi_clk(periph_id, rate);
return exynos5_set_spi_clk(periph_id, rate);
} else {
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
index b6a9bc1..0aff3d0 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
+++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
@@ -971,7 +971,7 @@
void system_clock_init(void)
{
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
exynos5420_system_clock_init();
else
exynos5250_system_clock_init();
diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
index b86dd2d..7c0b12a 100644
--- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
@@ -464,6 +464,16 @@
+ DMC_OFFSET);
pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE;
+ if (CONFIG_NR_DRAM_BANKS > 4) {
+ /* Need both controllers. */
+ mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2;
+ mem->chips_per_channel = 2;
+ mem->chips_to_configure = 2;
+ } else {
+ /* 2GB requires a single controller */
+ mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1;
+ }
+
/* Enable PAUSE for DREX */
setbits_le32(&clk->pause, ENABLE_BIT);
@@ -832,6 +842,25 @@
setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
+ /*
+ * As per Exynos5800 UM ver 0.00 section 17.13.2.1
+ * CONCONTROL register bit 3 [update_mode], Exynos5800 does not
+ * support the PHY initiated update. And it is recommended to set
+ * this field to 1'b1 during initialization
+ *
+ * When we apply PHY-initiated mode, DLL lock value is determined
+ * once at DMC init time and not updated later when we change the MIF
+ * voltage based on ASV group in kernel. Applying MC-initiated mode
+ * makes sure that DLL tracing is ON so that silicon is able to
+ * compensate the voltage variation.
+ */
+ val = readl(&drex0->concontrol);
+ val |= CONCONTROL_UPDATE_MODE;
+ writel(val , &drex0->concontrol);
+ val = readl(&drex1->concontrol);
+ val |= CONCONTROL_UPDATE_MODE;
+ writel(val , &drex1->concontrol);
+
return 0;
}
#endif
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index 3d95dc3..94d0297 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -837,7 +837,7 @@
int exynos_pinmux_config(int peripheral, int flags)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_pinmux_config(peripheral, flags);
else if (proid_is_exynos5250())
return exynos5_pinmux_config(peripheral, flags);
diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
index e1ab3d6..1520d64 100644
--- a/arch/arm/cpu/armv7/exynos/power.c
+++ b/arch/arm/cpu/armv7/exynos/power.c
@@ -53,10 +53,37 @@
}
}
+void exynos4412_set_usbhost_phy_ctrl(unsigned int enable)
+{
+ struct exynos4412_power *power =
+ (struct exynos4412_power *)samsung_get_base_power();
+
+ if (enable) {
+ /* Enabling USBHOST_PHY */
+ setbits_le32(&power->usbhost_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ setbits_le32(&power->hsic1_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ setbits_le32(&power->hsic2_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ } else {
+ /* Disabling USBHOST_PHY */
+ clrbits_le32(&power->usbhost_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ clrbits_le32(&power->hsic1_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ clrbits_le32(&power->hsic2_phy_control,
+ POWER_USB_HOST_PHY_CTRL_EN);
+ }
+}
+
void set_usbhost_phy_ctrl(unsigned int enable)
{
if (cpu_is_exynos5())
exynos5_set_usbhost_phy_ctrl(enable);
+ else if (cpu_is_exynos4())
+ if (proid_is_exynos4412())
+ exynos4412_set_usbhost_phy_ctrl(enable);
}
static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c
index 658e4cb..bc237c9 100644
--- a/arch/arm/cpu/armv7/exynos/spl_boot.c
+++ b/arch/arm/cpu/armv7/exynos/spl_boot.c
@@ -151,7 +151,7 @@
}
for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) {
- todo = min(uboot_size - upto, (1 << 15));
+ todo = min(uboot_size - upto, (unsigned int)(1 << 15));
spi_rx_tx(regs, todo, (void *)(uboot_addr),
(void *)(SPI_FLASH_UBOOT_POS), i);
}
@@ -195,10 +195,16 @@
void (*end_bootop_from_emmc)(void);
#endif
#ifdef CONFIG_USB_BOOTING
- u32 (*usb_copy)(void);
int is_cr_z_set;
unsigned int sec_boot_check;
+ /*
+ * Note that older hardware (before Exynos5800) does not expect any
+ * arguments, but it does not hurt to pass them, so a common function
+ * prototype is used.
+ */
+ u32 (*usb_copy)(u32 num_of_block, u32 *dst);
+
/* Read iRAM location to check for secondary USB boot mode */
sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
@@ -240,7 +246,7 @@
*/
is_cr_z_set = config_branch_prediction(0);
usb_copy = get_irom_func(USB_INDEX);
- usb_copy();
+ usb_copy(0, (u32 *)CONFIG_SYS_TEXT_BASE);
config_branch_prediction(is_cr_z_set);
break;
#endif
diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
index 2d53669..3753c14 100644
--- a/arch/arm/cpu/armv7/mx5/soc.c
+++ b/arch/arm/cpu/armv7/mx5/soc.c
@@ -85,37 +85,6 @@
}
#endif
-void set_chipselect_size(int const cs_size)
-{
- unsigned int reg;
- struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- reg = readl(&iomuxc_regs->gpr1);
-
- switch (cs_size) {
- case CS0_128:
- reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
- reg |= 0x5;
- break;
- case CS0_64M_CS1_64M:
- reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
- reg |= 0x1B;
- break;
- case CS0_64M_CS1_32M_CS2_32M:
- reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
- reg |= 0x4B;
- break;
- case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
- reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
- reg |= 0x249;
- break;
- default:
- printf("Unknown chip select size: %d\n", cs_size);
- break;
- }
-
- writel(reg, &iomuxc_regs->gpr1);
-}
-
#ifdef CONFIG_MX53
void boot_mode_apply(unsigned cfg_val)
{
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 6c9c78c..ab7ac3d 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -596,6 +596,14 @@
ungate_sata_clock();
return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
}
+
+void disable_sata_clock(void)
+{
+ struct mxc_ccm_reg *const imx_ccm =
+ (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
+}
#endif
int enable_pcie_clock(void)
@@ -673,6 +681,36 @@
}
#endif
+static void enable_pll3(void)
+{
+ struct anatop_regs __iomem *anatop =
+ (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+
+ /* make sure pll3 is enabled */
+ if ((readl(&anatop->usb1_pll_480_ctrl) &
+ BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
+ /* enable pll's power */
+ writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
+ &anatop->usb1_pll_480_ctrl_set);
+ writel(0x80, &anatop->ana_misc2_clr);
+ /* wait for pll lock */
+ while ((readl(&anatop->usb1_pll_480_ctrl) &
+ BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
+ ;
+ /* disable bypass */
+ writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
+ &anatop->usb1_pll_480_ctrl_clr);
+ /* enable pll output */
+ writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
+ &anatop->usb1_pll_480_ctrl_set);
+ }
+}
+
+void enable_thermal_clk(void)
+{
+ enable_pll3();
+}
+
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 5fd2a63..5f5f497 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -22,6 +22,8 @@
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <asm/bootm.h>
+#include <dm.h>
+#include <imx_thermal.h>
enum ldo_reg {
LDO_ARM,
@@ -37,6 +39,19 @@
u32 fpga_rev;
};
+#if defined(CONFIG_IMX6_THERMAL)
+static const struct imx_thermal_plat imx6_thermal_plat = {
+ .regs = (void *)ANATOP_BASE_ADDR,
+ .fuse_bank = 1,
+ .fuse_word = 6,
+};
+
+U_BOOT_DEVICE(imx6_thermal) = {
+ .name = "imx_thermal",
+ .platdata = &imx6_thermal_plat,
+};
+#endif
+
u32 get_nr_cpus(void)
{
struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
diff --git a/arch/arm/cpu/armv7/omap-common/abb.c b/arch/arm/cpu/armv7/omap-common/abb.c
index 423aeb9..a0add66 100644
--- a/arch/arm/cpu/armv7/omap-common/abb.c
+++ b/arch/arm/cpu/armv7/omap-common/abb.c
@@ -48,9 +48,9 @@
*/
/* calculate SR2_WTCNT_VALUE */
- sys_rate = DIV_ROUND(V_OSCK, 1000000);
- clk_cycles = DIV_ROUND(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate);
- sr2_cnt = DIV_ROUND(OMAP_ABB_SETTLING_TIME * 10, clk_cycles);
+ sys_rate = DIV_ROUND_CLOSEST(V_OSCK, 1000000);
+ clk_cycles = DIV_ROUND_CLOSEST(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate);
+ sr2_cnt = DIV_ROUND_CLOSEST(OMAP_ABB_SETTLING_TIME * 10, clk_cycles);
setbits_le32(setup,
sr2_cnt << (ffs(OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK) - 1));
diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c
index 3b4dd3f..a24baa1 100644
--- a/arch/arm/cpu/armv7/omap-common/sata.c
+++ b/arch/arm/cpu/armv7/omap-common/sata.c
@@ -74,6 +74,11 @@
return ret;
}
+int reset_sata(int dev)
+{
+ return 0;
+}
+
/* On OMAP platforms SATA provides the SCSI subsystem */
void scsi_init(void)
{
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index a0e49d1..49f4032 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -180,6 +180,21 @@
}
#endif
+void clock_set_pll3(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ if (clk == 0) {
+ clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
+ return;
+ }
+
+ /* PLL3 rate = 3000000 * m */
+ writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
+ CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg);
+}
+
unsigned int clock_get_pll5p(void)
{
struct sunxi_ccm_reg *const ccm =
@@ -200,3 +215,15 @@
int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
return 24000000 * n * k / 2;
}
+
+void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
+{
+ int pll = clock_get_pll5p();
+ int div = 1;
+
+ while ((pll / div) > hz)
+ div++;
+
+ writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_RST | CCM_DE_CTRL_PLL5P |
+ CCM_DE_CTRL_M(div), clk_cfg);
+}
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 16ab6f3..8e949c6 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -127,6 +127,23 @@
}
#endif
+void clock_set_pll3(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
+
+ if (clk == 0) {
+ clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
+ return;
+ }
+
+ /* PLL3 rate = 24000000 * n / m */
+ writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
+ CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
+ &ccm->pll3_cfg);
+}
+
void clock_set_pll5(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
@@ -151,3 +168,15 @@
int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
return 24000000 * n * k / 2;
}
+
+void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
+{
+ int pll = clock_get_pll6() * 2;
+ int div = 1;
+
+ while ((pll / div) > hz)
+ div++;
+
+ writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
+ clk_cfg);
+}
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c
index dc9fdb9..ec8aaa7 100644
--- a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c
@@ -428,9 +428,9 @@
#ifdef CONFIG_MACH_SUN4I
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
if (on)
- setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
+ setbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT);
else
- clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
+ clrbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT);
#endif
}
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
index 10a6241..699173c 100644
--- a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
@@ -142,9 +142,6 @@
writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST,
&mctl_phy->ptr0);
- /* Unknown magic performed by boot0 */
- if ((readl(SUNXI_RTC_BASE + 0x20c) & 3) == 2)
- setbits_le32(&mctl_phy->ptr0, 1 << 18);
writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1);
writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2);
diff --git a/arch/arm/cpu/armv7/tegra114/Makefile b/arch/arm/cpu/armv7/tegra114/Makefile
deleted file mode 100644
index 77e2319..0000000
--- a/arch/arm/cpu/armv7/tegra114/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-#
-# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-
-# necessary to create built-in.o
-obj- := __dummy__.o
diff --git a/arch/arm/cpu/armv7/tegra124/Makefile b/arch/arm/cpu/armv7/tegra124/Makefile
deleted file mode 100644
index 9478d44..0000000
--- a/arch/arm/cpu/armv7/tegra124/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2013-2014
-# NVIDIA Corporation <www.nvidia.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# necessary to create built-in.o
-obj- := __dummy__.o
diff --git a/arch/arm/cpu/armv7/tegra20/display.c b/arch/arm/cpu/armv7/tegra20/display.c
index d98cec9..61efed6 100644
--- a/arch/arm/cpu/armv7/tegra20/display.c
+++ b/arch/arm/cpu/armv7/tegra20/display.c
@@ -45,8 +45,8 @@
writel(0, &dc->win.h_initial_dda);
writel(0, &dc->win.v_initial_dda);
- h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1);
- v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1);
+ h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
+ v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);
val = h_dda << H_DDA_INC_SHIFT;
val |= v_dda << V_DDA_INC_SHIFT;
diff --git a/arch/arm/cpu/armv7/tegra30/Makefile b/arch/arm/cpu/armv7/tegra30/Makefile
deleted file mode 100644
index 413eba1..0000000
--- a/arch/arm/cpu/armv7/tegra30/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-#
-# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-
-# necessary to create built-in.o
-obj- := __dummy__.o
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index 7d93f59..0c10223 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -14,3 +14,5 @@
obj-y += cache.o
obj-y += tlb.o
obj-y += transition.o
+
+obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds
index 4beddf0..a69b006 100644
--- a/arch/arm/cpu/u-boot-spl.lds
+++ b/arch/arm/cpu/u-boot-spl.lds
@@ -34,6 +34,13 @@
. = ALIGN(4);
. = .;
+#ifdef CONFIG_SPL_DM
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list_*_driver_*)));
+ KEEP(*(SORT(.u_boot_list_*_uclass_*)));
+ }
+#endif
+ . = ALIGN(4);
__image_copy_end = .;
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ba6dec9..e5846ea 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -12,7 +12,8 @@
exynos5250-snow.dtb \
exynos5250-smdk5250.dtb \
exynos5420-smdk5420.dtb \
- exynos5420-peach-pit.dtb
+ exynos5420-peach-pit.dtb \
+ exynos5800-peach-pi.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts
index 2a1f1dd..c78efec 100644
--- a/arch/arm/dts/exynos4412-odroid.dts
+++ b/arch/arm/dts/exynos4412-odroid.dts
@@ -67,4 +67,15 @@
div = <0x3>;
index = <4>;
};
+
+ ehci@12580000 {
+ compatible = "samsung,exynos-ehci";
+ reg = <0x12580000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ phy {
+ compatible = "samsung,exynos-usb-phy";
+ reg = <0x125B0000 0x100>;
+ };
+ };
};
diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts
index 6fd9275..95af025 100644
--- a/arch/arm/dts/exynos5250-snow.dts
+++ b/arch/arm/dts/exynos5250-snow.dts
@@ -131,11 +131,11 @@
};
ehci@12110000 {
- samsung,vbus-gpio = <&gpio 0x309 0>; /* X11 */
+ samsung,vbus-gpio = <&gpio 0xb1 0>; /* X11 */
};
xhci@12000000 {
- samsung,vbus-gpio = <&gpio 0x317 0>; /* X27 */
+ samsung,vbus-gpio = <&gpio 0xbf 0>; /* X27 */
};
tmu@10060000 {
diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts
new file mode 100644
index 0000000..8aedf8e
--- /dev/null
+++ b/arch/arm/dts/exynos5800-peach-pi.dts
@@ -0,0 +1,157 @@
+/*
+ * SAMSUNG/GOOGLE Peach-Pit board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "exynos54xx.dtsi"
+
+/ {
+ model = "Samsung/Google Peach Pi board based on Exynos5800";
+
+ compatible = "google,pit-rev#", "google,pit",
+ "google,peach", "samsung,exynos5800", "samsung,exynos5";
+
+ config {
+ google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */
+ hwid = "PIT TEST A-A 7848";
+ lazy-init = <1>;
+ };
+
+ aliases {
+ serial0 = "/serial@12C30000";
+ console = "/serial@12C30000";
+ pmic = "/i2c@12ca0000";
+ };
+
+ dmc {
+ mem-manuf = "samsung";
+ mem-type = "ddr3";
+ clock-frequency = <800000000>;
+ arm-frequency = <1700000000>;
+ };
+
+ tmu@10060000 {
+ samsung,min-temp = <25>;
+ samsung,max-temp = <125>;
+ samsung,start-warning = <95>;
+ samsung,start-tripping = <105>;
+ samsung,hw-tripping = <110>;
+ samsung,efuse-min-value = <40>;
+ samsung,efuse-value = <55>;
+ samsung,efuse-max-value = <100>;
+ samsung,slope = <274761730>;
+ samsung,dc-value = <25>;
+ };
+
+ /* MAX77802 is on i2c bus 4 */
+ i2c@12ca0000 {
+ clock-frequency = <400000>;
+ power-regulator@9 {
+ compatible = "maxim,max77802-pmic";
+ reg = <0x9>;
+ };
+ };
+
+ i2c@12cd0000 { /* i2c7 */
+ clock-frequency = <100000>;
+ soundcodec@20 {
+ reg = <0x20>;
+ compatible = "maxim,max98090-codec";
+ };
+
+ edp-lvds-bridge@48 {
+ compatible = "parade,ps8625";
+ reg = <0x48>;
+ };
+ };
+
+ sound@3830000 {
+ samsung,codec-type = "max98090";
+ };
+
+ i2c@12e10000 { /* i2c9 */
+ clock-frequency = <400000>;
+ tpm@20 {
+ compatible = "infineon,slb9645-tpm";
+ reg = <0x20>;
+ };
+ };
+
+ spi@12d30000 { /* spi1 */
+ spi-max-frequency = <50000000>;
+ firmware_storage_spi: flash@0 {
+ reg = <0>;
+
+ /*
+ * A region for the kernel to store a panic event
+ * which the firmware will add to the log.
+ */
+ elog-panic-event-offset = <0x01e00000 0x100000>;
+
+ elog-shrink-size = <0x400>;
+ elog-full-threshold = <0xc00>;
+ };
+ };
+
+ spi@12d40000 { /* spi2 */
+ spi-max-frequency = <4000000>;
+ spi-deactivate-delay = <200>;
+ cros-ec@0 {
+ reg = <0>;
+ compatible = "google,cros-ec";
+ spi-half-duplex;
+ spi-max-timeout-ms = <1100>;
+ spi-frame-header = <0xec>;
+ ec-interrupt = <&gpio 93 1>; /* GPX1_5 */
+
+ /*
+ * This describes the flash memory within the EC. Note
+ * that the STM32L flash erases to 0, not 0xff.
+ */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ flash@8000000 {
+ reg = <0x08000000 0x20000>;
+ erase-value = <0>;
+ };
+ };
+ };
+
+ xhci@12000000 {
+ samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */
+ };
+
+ xhci@12400000 {
+ samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
+ };
+
+ fimd@14400000 {
+ samsung,vl-freq = <60>;
+ samsung,vl-col = <1920>;
+ samsung,vl-row = <1080>;
+ samsung,vl-width = <1920>;
+ samsung,vl-height = <1080>;
+
+ samsung,vl-clkp;
+ samsung,vl-dp;
+ samsung,vl-bpix = <4>;
+
+ samsung,vl-hspw = <80>;
+ samsung,vl-hbpd = <172>;
+ samsung,vl-hfpd = <60>;
+ samsung,vl-vspw = <10>;
+ samsung,vl-vbpd = <25>;
+ samsung,vl-vfpd = <10>;
+ samsung,vl-cmd-allow-len = <0xf>;
+
+ samsung,winid = <3>;
+ samsung,interface-mode = <1>;
+ samsung,dp-enabled = <1>;
+ samsung,dual-lcd-enabled = <0>;
+ };
+};
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 09fc227..b58df7d 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -17,6 +17,8 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <ipu_pixfmt.h>
+#include <thermal.h>
+#include <sata.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
@@ -134,6 +136,11 @@
{
u32 cpurev;
+#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
+ struct udevice *thermal_dev;
+ int cpu_tmp, ret;
+#endif
+
cpurev = get_cpu_rev();
printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
@@ -141,6 +148,21 @@
(cpurev & 0x000F0) >> 4,
(cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
+
+#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
+ ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
+ if (!ret) {
+ ret = thermal_get_temp(thermal_dev, &cpu_tmp);
+
+ if (!ret)
+ printf("CPU: Temperature %d C\n", cpu_tmp);
+ else
+ printf("CPU: Temperature: invalid sensor data\n");
+ } else {
+ printf("CPU: Temperature: Can't find sensor device\n");
+ }
+#endif
+
printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
@@ -180,10 +202,44 @@
return get_periph_clk() / (ahb_podf + 1);
}
-#if defined(CONFIG_VIDEO_IPUV3)
void arch_preboot_os(void)
{
+#if defined(CONFIG_CMD_SATA)
+ sata_stop();
+#endif
+#if defined(CONFIG_VIDEO_IPUV3)
/* disable video before launching O/S */
ipuv3_fb_shutdown();
-}
#endif
+}
+
+void set_chipselect_size(int const cs_size)
+{
+ unsigned int reg;
+ struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ reg = readl(&iomuxc_regs->gpr[1]);
+
+ switch (cs_size) {
+ case CS0_128:
+ reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
+ reg |= 0x5;
+ break;
+ case CS0_64M_CS1_64M:
+ reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
+ reg |= 0x1B;
+ break;
+ case CS0_64M_CS1_32M_CS2_32M:
+ reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
+ reg |= 0x4B;
+ break;
+ case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
+ reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
+ reg |= 0x249;
+ break;
+ default:
+ printf("Unknown chip select size: %d\n", cs_size);
+ break;
+ }
+
+ writel(reg, &iomuxc_regs->gpr[1]);
+}
diff --git a/board/compulab/cm_fx6/imximage.cfg b/arch/arm/imx-common/spl_sd.cfg
similarity index 87%
rename from board/compulab/cm_fx6/imximage.cfg
rename to arch/arm/imx-common/spl_sd.cfg
index 420947e..5fc3e8a 100644
--- a/board/compulab/cm_fx6/imximage.cfg
+++ b/arch/arm/imx-common/spl_sd.cfg
@@ -4,5 +4,5 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-IMAGE_VERSION 2
+IMAGE_VERSION 2
BOOT_FROM sd
diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h
index 532411e..e062da1 100644
--- a/arch/arm/include/asm/arch-armada100/config.h
+++ b/arch/arm/include/asm/arch-armada100/config.h
@@ -16,7 +16,6 @@
#define _ARMD1_CONFIG_H
#include <asm/arch/armada100.h>
-#define CONFIG_ARM926EJS 1 /* Basic Architecture */
/* default Dcache Line length for armada100 */
#define CONFIG_SYS_CACHELINE_SIZE 32
diff --git a/arch/arm/include/asm/arch-at91/at91rm9200.h b/arch/arm/include/asm/arch-at91/at91rm9200.h
index 25bb071..d177bdc 100644
--- a/arch/arm/include/asm/arch-at91/at91rm9200.h
+++ b/arch/arm/include/asm/arch-at91/at91rm9200.h
@@ -7,7 +7,6 @@
#define __AT91RM9200_H__
#define CONFIG_AT91FAMILY /* it's a member of AT91 family */
-#define CONFIG_ARM920T /* it's an ARM920T Core */
#define CONFIG_ARCH_CPU_INIT /* we need arch_cpu_init() for hw timers */
#define CONFIG_AT91_GPIO /* and require always gpio features */
diff --git a/arch/arm/include/asm/arch-at91/at91sam9260.h b/arch/arm/include/asm/arch-at91/at91sam9260.h
index 1e613fa..8950d67 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9260.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9260.h
@@ -21,7 +21,6 @@
/*
* defines to be used in other places
*/
-#define CONFIG_ARM926EJS /* ARM926EJS Core */
#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
@@ -137,9 +136,11 @@
/*
* Other misc defines
*/
+#ifndef CONFIG_DM_GPIO
#define ATMEL_PIO_PORTS 3 /* these SoCs have 3 PIO */
-#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
+#endif
+#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
/*
* SoC specific defines
diff --git a/arch/arm/include/asm/arch-at91/at91sam9261.h b/arch/arm/include/asm/arch-at91/at91sam9261.h
index f7ad113..6dfcf4c 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9261.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9261.h
@@ -21,7 +21,6 @@
/*
* defines to be used in other places
*/
-#define CONFIG_ARM926EJS /* ARM926EJS Core */
#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
diff --git a/arch/arm/include/asm/arch-at91/at91sam9263.h b/arch/arm/include/asm/arch-at91/at91sam9263.h
index 3206af8..64a3888 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9263.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9263.h
@@ -17,7 +17,6 @@
/*
* defines to be used in other places
*/
-#define CONFIG_ARM926EJS /* ARM926EJS Core */
#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45.h b/arch/arm/include/asm/arch-at91/at91sam9g45.h
index 9cbfc27..6df8cdb5 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9g45.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9g45.h
@@ -15,7 +15,6 @@
/*
* defines to be used in other places
*/
-#define CONFIG_ARM926EJS /* ARM926EJS Core */
#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl.h b/arch/arm/include/asm/arch-at91/at91sam9rl.h
index 00b6aa4..3a8e6d6 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9rl.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9rl.h
@@ -17,7 +17,6 @@
/*
* defines to be used in other places
*/
-#define CONFIG_ARM926EJS /* ARM926EJS Core */
#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h b/arch/arm/include/asm/arch-at91/at91sam9x5.h
index d49c184..36a5cdf 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9x5.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9x5.h
@@ -12,7 +12,6 @@
#ifndef __AT91SAM9X5_H__
#define __AT91SAM9X5_H__
-#define CONFIG_ARM926EJS /* ARM926EJS Core */
#define CONFIG_AT91FAMILY /* it's a member of AT91 family */
/*
diff --git a/arch/arm/include/asm/arch-at91/atmel_serial.h b/arch/arm/include/asm/arch-at91/atmel_serial.h
new file mode 100644
index 0000000..5bc094b
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/atmel_serial.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ATMEL_SERIAL_H
+#define _ATMEL_SERIAL_H
+
+/* Information about a serial port */
+struct atmel_serial_platdata {
+ uint32_t base_addr;
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-at91/gpio.h b/arch/arm/include/asm/arch-at91/gpio.h
index 7121388..6d2a7b7 100644
--- a/arch/arm/include/asm/arch-at91/gpio.h
+++ b/arch/arm/include/asm/arch-at91/gpio.h
@@ -253,4 +253,10 @@
return gpio % 32;
}
+/* Platform data for each GPIO port */
+struct at91_port_platdata {
+ uint32_t base_addr;
+ const char *bank_name;
+};
+
#endif /* __ASM_ARCH_AT91_GPIO_H */
diff --git a/arch/arm/include/asm/arch-at91/sama5d3.h b/arch/arm/include/asm/arch-at91/sama5d3.h
index f7bc4ad..227ba80 100644
--- a/arch/arm/include/asm/arch-at91/sama5d3.h
+++ b/arch/arm/include/asm/arch-at91/sama5d3.h
@@ -16,7 +16,6 @@
/*
* defines to be used in other places
*/
-#define CONFIG_ARMV7 /* ARM A5 Core */
#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index 78aceef..29674ad 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -227,6 +227,13 @@
/* Exynos5420 */
s5p_cpu_id = 0x5420;
break;
+ case 0x422:
+ /*
+ * Exynos5800 is a variant of Exynos5420
+ * and has product id 0x5422
+ */
+ s5p_cpu_id = 0x5800;
+ break;
}
}
@@ -255,6 +262,7 @@
IS_EXYNOS_TYPE(exynos4412, 0x4412)
IS_EXYNOS_TYPE(exynos5250, 0x5250)
IS_EXYNOS_TYPE(exynos5420, 0x5420)
+IS_EXYNOS_TYPE(exynos5800, 0x5800)
#define SAMSUNG_BASE(device, base) \
static inline unsigned int __attribute__((no_instrument_function)) \
@@ -265,7 +273,7 @@
return EXYNOS4X12_##base; \
return EXYNOS4_##base; \
} else if (cpu_is_exynos5()) { \
- if (proid_is_exynos5420()) \
+ if (proid_is_exynos5420() || proid_is_exynos5800()) \
return EXYNOS5420_##base; \
return EXYNOS5_##base; \
} \
diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h
index ec3f9b6..4990a1a 100644
--- a/arch/arm/include/asm/arch-exynos/dmc.h
+++ b/arch/arm/include/asm/arch-exynos/dmc.h
@@ -450,6 +450,7 @@
#define CONCONTROL_RD_FETCH_SHIFT 12
#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT)
#define CONCONTROL_AREF_EN_SHIFT 5
+#define CONCONTROL_UPDATE_MODE (1 << 3)
/* PRECHCONFIG register field */
#define PRECHCONFIG_TP_CNT_SHIFT 24
diff --git a/arch/arm/include/asm/arch-exynos/ehci.h b/arch/arm/include/asm/arch-exynos/ehci.h
index d2d70bd..3800fa9 100644
--- a/arch/arm/include/asm/arch-exynos/ehci.h
+++ b/arch/arm/include/asm/arch-exynos/ehci.h
@@ -12,6 +12,13 @@
#define CLK_24MHZ 5
+#define PHYPWR_NORMAL_MASK_PHY0 (0x39 << 0)
+#define PHYPWR_NORMAL_MASK_PHY1 (0x7 << 6)
+#define PHYPWR_NORMAL_MASK_HSIC0 (0x7 << 9)
+#define PHYPWR_NORMAL_MASK_HSIC1 (0x7 << 12)
+#define RSTCON_HOSTPHY_SWRST (0xf << 3)
+#define RSTCON_SWRST (0x1 << 0)
+
#define HOST_CTRL0_PHYSWRSTALL (1 << 31)
#define HOST_CTRL0_COMMONON_N (1 << 9)
#define HOST_CTRL0_SIDDQ (1 << 6)
@@ -61,6 +68,12 @@
unsigned int usbotgtune;
};
+struct exynos4412_usb_phy {
+ unsigned int usbphyctrl;
+ unsigned int usbphyclk;
+ unsigned int usbphyrstcon;
+};
+
/* Switch on the VBUS power. */
int board_usb_vbus_init(void);
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index 02287de..9699954 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1398,7 +1398,7 @@
static inline struct gpio_info *get_gpio_data(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_gpio_data;
else
return exynos5_gpio_data;
@@ -1415,7 +1415,7 @@
static inline unsigned int get_bank_num(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return EXYNOS5420_GPIO_NUM_PARTS;
else
return EXYNOS5_GPIO_NUM_PARTS;
diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h
index e8a98a5..3f97b31 100644
--- a/arch/arm/include/asm/arch-exynos/power.h
+++ b/arch/arm/include/asm/arch-exynos/power.h
@@ -210,6 +210,13 @@
unsigned int gps_alive_option;
};
+struct exynos4412_power {
+ unsigned char res1[0x0704];
+ unsigned int usbhost_phy_control;
+ unsigned int hsic1_phy_control;
+ unsigned int hsic2_phy_control;
+};
+
struct exynos5_power {
unsigned int om_stat;
unsigned char res1[0x18];
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index a3cc96f..254136e 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -12,3 +12,8 @@
#define MXC_CPU_MX6Q 0x63
#define MXC_CPU_MX6D 0x64
#define MXC_CPU_MX6SOLO 0x65 /* dummy ID */
+
+#define CS0_128 0
+#define CS0_64M_CS1_64M 1
+#define CS0_64M_CS1_32M_CS2_32M 2
+#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h
index ccc8e4e..e77ac40 100644
--- a/arch/arm/include/asm/arch-kirkwood/config.h
+++ b/arch/arm/include/asm/arch-kirkwood/config.h
@@ -24,7 +24,6 @@
#endif /* CONFIG_KW88F6281 */
#include <asm/arch/soc.h>
-#define CONFIG_ARM926EJS 1 /* Basic Architecture */
#define CONFIG_SYS_CACHELINE_SIZE 32
/* default Dcache Line length for kirkwood */
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
index c985401..8f6426b 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -10,7 +10,6 @@
#define _LPC32XX_CONFIG_H
/* Basic CPU architecture */
-#define CONFIG_ARM926EJS
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_NR_DRAM_BANKS_MAX 2
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 054c680..f059d0f 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -202,11 +202,6 @@
*/
#define WBED 1
-#define CS0_128 0
-#define CS0_64M_CS1_64M 1
-#define CS0_64M_CS1_32M_CS2_32M 2
-#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
-
/*
* CSPI register definitions
*/
@@ -414,8 +409,7 @@
#if defined(CONFIG_MX51)
struct iomuxc {
- u32 gpr0;
- u32 gpr1;
+ u32 gpr[2];
u32 omux0;
u32 omux1;
u32 omux2;
@@ -424,9 +418,7 @@
};
#elif defined(CONFIG_MX53)
struct iomuxc {
- u32 gpr0;
- u32 gpr1;
- u32 gpr2;
+ u32 gpr[3];
u32 omux0;
u32 omux1;
u32 omux2;
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 3c58a0a..323805c 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -60,10 +60,12 @@
int enable_cspi_clock(unsigned char enable, unsigned spi_num);
int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
int enable_sata_clock(void);
+void disable_sata_clock(void);
int enable_pcie_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
int enable_spi_clk(unsigned char enable, unsigned spi_num);
void enable_ipu_clock(void);
int enable_fec_anatop_clock(enum enet_freq freq);
void enable_enet_clk(unsigned char enable);
+void enable_thermal_clk(void);
#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index a159309..5314298 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -332,6 +332,43 @@
#define SRC_SCR_CORE_3_ENABLE_OFFSET 24
#define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
+/* WEIM registers */
+struct weim {
+ u32 cs0gcr1;
+ u32 cs0gcr2;
+ u32 cs0rcr1;
+ u32 cs0rcr2;
+ u32 cs0wcr1;
+ u32 cs0wcr2;
+
+ u32 cs1gcr1;
+ u32 cs1gcr2;
+ u32 cs1rcr1;
+ u32 cs1rcr2;
+ u32 cs1wcr1;
+ u32 cs1wcr2;
+
+ u32 cs2gcr1;
+ u32 cs2gcr2;
+ u32 cs2rcr1;
+ u32 cs2rcr2;
+ u32 cs2wcr1;
+ u32 cs2wcr2;
+
+ u32 cs3gcr1;
+ u32 cs3gcr2;
+ u32 cs3rcr1;
+ u32 cs3rcr2;
+ u32 cs3wcr1;
+ u32 cs3wcr2;
+
+ u32 unused[12];
+
+ u32 wcr;
+ u32 wiar;
+ u32 ear;
+};
+
/* System Reset Controller (SRC) */
struct src {
u32 scr;
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index c35a9051..28ba844 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -26,6 +26,7 @@
const char *get_imx_type(u32 imxtype);
unsigned imx_ddr_size(void);
+void set_chipselect_size(int const);
/*
* Initializes on-chip ethernet controllers.
diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h
index fdccd22..1eed7b1 100644
--- a/arch/arm/include/asm/arch-pantheon/config.h
+++ b/arch/arm/include/asm/arch-pantheon/config.h
@@ -11,7 +11,6 @@
#include <asm/arch/pantheon.h>
-#define CONFIG_ARM926EJS 1 /* Basic Architecture */
/* default Dcache Line length for pantheon */
#define CONFIG_SYS_CACHELINE_SIZE 32
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
index b40c16b..64acff3 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -25,9 +25,11 @@
int clock_init(void);
int clock_twi_onoff(int port, int state);
void clock_set_pll1(unsigned int hz);
+void clock_set_pll3(unsigned int hz);
void clock_set_pll5(unsigned int hz);
unsigned int clock_get_pll5p(void);
unsigned int clock_get_pll6(void);
+void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz);
void clock_init_safe(void);
void clock_init_uart(void);
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 9dca800..eb88969 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -62,7 +62,7 @@
u32 gps_clk_cfg; /* 0xd0 */
u32 spi3_clk_cfg; /* 0xd4 */
u8 res5[0x28];
- u32 dram_clk_cfg; /* 0x100 */
+ u32 dram_clk_gate; /* 0x100 */
u32 be0_clk_cfg; /* 0x104 */
u32 be1_clk_cfg; /* 0x108 */
u32 fe0_clk_cfg; /* 0x10c */
@@ -186,12 +186,20 @@
/* ahb clock gate bit offset (second register) */
#define AHB_GATE_OFFSET_GMAC 17
+#define AHB_GATE_OFFSET_DE_BE0 12
+#define AHB_GATE_OFFSET_HDMI 11
+#define AHB_GATE_OFFSET_LCD1 5
+#define AHB_GATE_OFFSET_LCD0 4
#define CCM_AHB_GATE_GPS (0x1 << 26)
#define CCM_AHB_GATE_SDRAM (0x1 << 14)
#define CCM_AHB_GATE_DLL (0x1 << 15)
#define CCM_AHB_GATE_ACE (0x1 << 16)
+#define CCM_PLL3_CTRL_M(n) (((n) & 0x7f) << 0)
+#define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 15)
+#define CCM_PLL3_CTRL_EN (0x1 << 31)
+
#define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0)
#define CCM_PLL5_CTRL_M_MASK CCM_PLL5_CTRL_M(0x3)
#define CCM_PLL5_CTRL_M_X(n) ((n) - 1)
@@ -253,6 +261,34 @@
#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
+#define CCM_DRAM_GATE_OFFSET_DE_BE0 26
+
+#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24)
+#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24)
+#define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24)
+#define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24)
+#define CCM_LCD_CH0_CTRL_RST (0x1 << 30)
+#define CCM_LCD_CH0_CTRL_GATE (0x1 << 31)
+
+#define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+/* We leave bit 11 set to 0, so sclk1 == sclk2 */
+#define CCM_LCD_CH1_CTRL_PLL3 (0 << 24)
+#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24)
+#define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24)
+#define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24)
+/* Enable / disable both ch1 sclk1 and sclk2 at the same time */
+#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31 | 0x1 << 15)
+
+#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+#define CCM_HDMI_CTRL_PLL_MASK (3 << 24)
+#define CCM_HDMI_CTRL_PLL3 (0 << 24)
+#define CCM_HDMI_CTRL_PLL7 (1 << 24)
+#define CCM_HDMI_CTRL_PLL3_2X (2 << 24)
+#define CCM_HDMI_CTRL_PLL7_2X (3 << 24)
+/* No separate ddc gate on sun4i, sun5i and sun7i */
+#define CCM_HDMI_CTRL_DDC_GATE 0
+#define CCM_HDMI_CTRL_GATE (0x1 << 31)
+
#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
@@ -266,4 +302,13 @@
#define CCM_USB_CTRL_PHY1_CLK 0
#define CCM_USB_CTRL_PHY2_CLK 0
+/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */
+#define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+#define CCM_DE_CTRL_PLL_MASK (3 << 24)
+#define CCM_DE_CTRL_PLL3 (0 << 24)
+#define CCM_DE_CTRL_PLL7 (1 << 24)
+#define CCM_DE_CTRL_PLL5P (2 << 24)
+#define CCM_DE_CTRL_RST (1 << 30)
+#define CCM_DE_CTRL_GATE (1 << 31)
+
#endif /* _SUNXI_CLOCK_SUN4I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index e16a764..3599054 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -176,13 +176,18 @@
#define CCM_PLL1_CTRL_MAGIC (0x1 << 16)
#define CCM_PLL1_CTRL_EN (0x1 << 31)
+#define CCM_PLL3_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+#define CCM_PLL3_CTRL_N(n) ((((n) - 1) & 0x7f) << 8)
+#define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 24)
+#define CCM_PLL3_CTRL_EN (0x1 << 31)
+
#define CCM_PLL5_CTRL_M(n) ((((n) - 1) & 0x3) << 0)
#define CCM_PLL5_CTRL_K(n) ((((n) - 1) & 0x3) << 4)
#define CCM_PLL5_CTRL_N(n) ((((n) - 1) & 0x1f) << 8)
#define CCM_PLL5_CTRL_UPD (0x1 << 20)
#define CCM_PLL5_CTRL_EN (0x1 << 31)
-#define PLL6_CFG_DEFAULT 0x90041811
+#define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */
#define CCM_PLL6_CTRL_N_SHIFT 8
#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
@@ -193,17 +198,26 @@
#define AXI_GATE_OFFSET_DRAM 0
+/* ahb_gate0 offsets */
#define AHB_GATE_OFFSET_USB_OHCI1 30
#define AHB_GATE_OFFSET_USB_OHCI0 29
#define AHB_GATE_OFFSET_USB_EHCI1 27
#define AHB_GATE_OFFSET_USB_EHCI0 26
#define AHB_GATE_OFFSET_MCTL 14
+#define AHB_GATE_OFFSET_GMAC 17
#define AHB_GATE_OFFSET_MMC3 11
#define AHB_GATE_OFFSET_MMC2 10
#define AHB_GATE_OFFSET_MMC1 9
#define AHB_GATE_OFFSET_MMC0 8
#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
+/* ahb_gate1 offsets */
+#define AHB_GATE_OFFSET_DRC0 25
+#define AHB_GATE_OFFSET_DE_BE0 12
+#define AHB_GATE_OFFSET_HDMI 11
+#define AHB_GATE_OFFSET_LCD1 5
+#define AHB_GATE_OFFSET_LCD0 4
+
#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
#define CCM_MMC_CTRL_PLL6 (0x1 << 24)
@@ -216,6 +230,12 @@
#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
+#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
+#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
+#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
+#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
+#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
+
#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */
#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8)
@@ -223,8 +243,35 @@
#define CCM_DRAMCLK_CFG_UPD (0x1 << 16)
#define CCM_DRAMCLK_CFG_RST (0x1 << 31)
+#define CCM_DRAM_GATE_OFFSET_DE_BE0 26
+
+#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24)
+#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24)
+#define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24)
+#define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24)
+#define CCM_LCD_CH0_CTRL_MIPI_PLL (4 << 24)
+#define CCM_LCD_CH0_CTRL_GATE (0x1 << 31)
+
+#define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+#define CCM_LCD_CH1_CTRL_PLL3 (0 << 24)
+#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24)
+#define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24)
+#define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24)
+#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31)
+
+#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+#define CCM_HDMI_CTRL_PLL_MASK (3 << 24)
+#define CCM_HDMI_CTRL_PLL3 (0 << 24)
+#define CCM_HDMI_CTRL_PLL7 (1 << 24)
+#define CCM_HDMI_CTRL_PLL3_2X (2 << 24)
+#define CCM_HDMI_CTRL_PLL7_2X (3 << 24)
+#define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30)
+#define CCM_HDMI_CTRL_GATE (0x1 << 31)
+
#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */
+/* ahb_reset0 offsets */
+#define AHB_RESET_OFFSET_GMAC 17
#define AHB_RESET_OFFSET_MCTL 14
#define AHB_RESET_OFFSET_MMC3 11
#define AHB_RESET_OFFSET_MMC2 10
@@ -232,10 +279,28 @@
#define AHB_RESET_OFFSET_MMC0 8
#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n))
+/* ahb_reset0 offsets */
+#define AHB_RESET_OFFSET_DRC0 25
+#define AHB_RESET_OFFSET_DE_BE0 12
+#define AHB_RESET_OFFSET_HDMI 11
+#define AHB_RESET_OFFSET_LCD1 5
+#define AHB_RESET_OFFSET_LCD0 4
+
/* apb2 reset */
#define APB2_RESET_UART_SHIFT (16)
#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)
#define APB2_RESET_TWI_SHIFT (0)
#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT)
+/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */
+#define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+#define CCM_DE_CTRL_PLL_MASK (0xf << 24)
+#define CCM_DE_CTRL_PLL3 (0 << 24)
+#define CCM_DE_CTRL_PLL7 (1 << 24)
+#define CCM_DE_CTRL_PLL6_2X (2 << 24)
+#define CCM_DE_CTRL_PLL8 (3 << 24)
+#define CCM_DE_CTRL_PLL9 (4 << 24)
+#define CCM_DE_CTRL_PLL10 (5 << 24)
+#define CCM_DE_CTRL_GATE (1 << 31)
+
#endif /* _SUNXI_CLOCK_SUN6I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
index bdee89e..2c92b5c 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -99,9 +99,13 @@
#define SUNXI_SCR_BASE 0x01c2c400
+#ifndef CONFIG_MACH_SUN6I
#define SUNXI_GPS_BASE 0x01c30000
#define SUNXI_MALI400_BASE 0x01c40000
#define SUNXI_GMAC_BASE 0x01c50000
+#else
+#define SUNXI_GMAC_BASE 0x01c30000
+#endif
#define SUNXI_DRAM_COM_BASE 0x01c62000
#define SUNXI_DRAM_CTL0_BASE 0x01c63000
diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h
new file mode 100644
index 0000000..ddb71c1
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/display.h
@@ -0,0 +1,187 @@
+/*
+ * Sunxi platform display controller register and constant defines
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_DISPLAY_H
+#define _SUNXI_DISPLAY_H
+
+struct sunxi_de_be_reg {
+ u8 res0[0x800]; /* 0x000 */
+ u32 mode; /* 0x800 */
+ u32 backcolor; /* 0x804 */
+ u32 disp_size; /* 0x808 */
+ u8 res1[0x4]; /* 0x80c */
+ u32 layer0_size; /* 0x810 */
+ u32 layer1_size; /* 0x814 */
+ u32 layer2_size; /* 0x818 */
+ u32 layer3_size; /* 0x81c */
+ u32 layer0_pos; /* 0x820 */
+ u32 layer1_pos; /* 0x824 */
+ u32 layer2_pos; /* 0x828 */
+ u32 layer3_pos; /* 0x82c */
+ u8 res2[0x10]; /* 0x830 */
+ u32 layer0_stride; /* 0x840 */
+ u32 layer1_stride; /* 0x844 */
+ u32 layer2_stride; /* 0x848 */
+ u32 layer3_stride; /* 0x84c */
+ u32 layer0_addr_low32b; /* 0x850 */
+ u32 layer1_addr_low32b; /* 0x854 */
+ u32 layer2_addr_low32b; /* 0x858 */
+ u32 layer3_addr_low32b; /* 0x85c */
+ u32 layer0_addr_high4b; /* 0x860 */
+ u32 layer1_addr_high4b; /* 0x864 */
+ u32 layer2_addr_high4b; /* 0x868 */
+ u32 layer3_addr_high4b; /* 0x86c */
+ u32 reg_ctrl; /* 0x870 */
+ u8 res3[0xc]; /* 0x874 */
+ u32 color_key_max; /* 0x880 */
+ u32 color_key_min; /* 0x884 */
+ u32 color_key_config; /* 0x888 */
+ u8 res4[0x4]; /* 0x88c */
+ u32 layer0_attr0_ctrl; /* 0x890 */
+ u32 layer1_attr0_ctrl; /* 0x894 */
+ u32 layer2_attr0_ctrl; /* 0x898 */
+ u32 layer3_attr0_ctrl; /* 0x89c */
+ u32 layer0_attr1_ctrl; /* 0x8a0 */
+ u32 layer1_attr1_ctrl; /* 0x8a4 */
+ u32 layer2_attr1_ctrl; /* 0x8a8 */
+ u32 layer3_attr1_ctrl; /* 0x8ac */
+};
+
+struct sunxi_lcdc_reg {
+ u32 ctrl; /* 0x00 */
+ u32 int0; /* 0x04 */
+ u32 int1; /* 0x08 */
+ u8 res0[0x04]; /* 0x0c */
+ u32 frame_ctrl; /* 0x10 */
+ u8 res1[0x2c]; /* 0x14 */
+ u32 tcon0_ctrl; /* 0x40 */
+ u32 tcon0_dclk; /* 0x44 */
+ u32 tcon0_basic_timing0; /* 0x48 */
+ u32 tcon0_basic_timing1; /* 0x4c */
+ u32 tcon0_basic_timing2; /* 0x50 */
+ u32 tcon0_basic_timing3; /* 0x54 */
+ u32 tcon0_hv_intf; /* 0x58 */
+ u8 res2[0x04]; /* 0x5c */
+ u32 tcon0_cpu_intf; /* 0x60 */
+ u32 tcon0_cpu_wr_dat; /* 0x64 */
+ u32 tcon0_cpu_rd_dat0; /* 0x68 */
+ u32 tcon0_cpu_rd_dat1; /* 0x6c */
+ u32 tcon0_ttl_timing0; /* 0x70 */
+ u32 tcon0_ttl_timing1; /* 0x74 */
+ u32 tcon0_ttl_timing2; /* 0x78 */
+ u32 tcon0_ttl_timing3; /* 0x7c */
+ u32 tcon0_ttl_timing4; /* 0x80 */
+ u32 tcon0_lvds_intf; /* 0x84 */
+ u32 tcon0_io_polarity; /* 0x88 */
+ u32 tcon0_io_tristate; /* 0x8c */
+ u32 tcon1_ctrl; /* 0x90 */
+ u32 tcon1_timing_source; /* 0x94 */
+ u32 tcon1_timing_scale; /* 0x98 */
+ u32 tcon1_timing_out; /* 0x9c */
+ u32 tcon1_timing_h; /* 0xa0 */
+ u32 tcon1_timing_v; /* 0xa4 */
+ u32 tcon1_timing_sync; /* 0xa8 */
+ u8 res3[0x44]; /* 0xac */
+ u32 tcon1_io_polarity; /* 0xf0 */
+ u32 tcon1_io_tristate; /* 0xf4 */
+};
+
+struct sunxi_hdmi_reg {
+ u32 version_id; /* 0x000 */
+ u32 ctrl; /* 0x004 */
+ u32 irq; /* 0x008 */
+ u32 hpd; /* 0x00c */
+ u32 video_ctrl; /* 0x010 */
+ u32 video_size; /* 0x014 */
+ u32 video_bp; /* 0x018 */
+ u32 video_fp; /* 0x01c */
+ u32 video_spw; /* 0x020 */
+ u32 video_polarity; /* 0x024 */
+ u8 res0[0x1d8]; /* 0x028 */
+ u32 pad_ctrl0; /* 0x200 */
+ u32 pad_ctrl1; /* 0x204 */
+ u32 pll_ctrl; /* 0x208 */
+ u32 pll_dbg0; /* 0x20c */
+};
+
+/*
+ * DE-BE register constants.
+ */
+#define SUNXI_DE_BE_WIDTH(x) (((x) - 1) << 0)
+#define SUNXI_DE_BE_HEIGHT(y) (((y) - 1) << 16)
+#define SUNXI_DE_BE_MODE_ENABLE (1 << 0)
+#define SUNXI_DE_BE_MODE_START (1 << 1)
+#define SUNXI_DE_BE_MODE_LAYER0_ENABLE (1 << 8)
+#define SUNXI_DE_BE_LAYER_STRIDE(x) ((x) << 5)
+#define SUNXI_DE_BE_REG_CTRL_LOAD_REGS (1 << 0)
+#define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888 (0x09 << 8)
+
+/*
+ * LCDC register constants.
+ */
+#define SUNXI_LCDC_X(x) (((x) - 1) << 16)
+#define SUNXI_LCDC_Y(y) (((y) - 1) << 0)
+#define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0)
+#define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0)
+#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0)
+#define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31)
+#define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28)
+#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
+#define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31)
+#define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0)
+#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16)
+#define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0)
+#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) (((n) * 2) << 16)
+
+/*
+ * HDMI register constants.
+ */
+#define SUNXI_HDMI_X(x) (((x) - 1) << 0)
+#define SUNXI_HDMI_Y(y) (((y) - 1) << 16)
+#define SUNXI_HDMI_CTRL_ENABLE (1 << 31)
+#define SUNXI_HDMI_IRQ_STATUS_FIFO_UF (1 << 0)
+#define SUNXI_HDMI_IRQ_STATUS_FIFO_OF (1 << 1)
+#define SUNXI_HDMI_IRQ_STATUS_BITS 0x73
+#define SUNXI_HDMI_HPD_DETECT (1 << 0)
+#define SUNXI_HDMI_VIDEO_CTRL_ENABLE (1 << 31)
+#define SUNXI_HDMI_VIDEO_POL_HOR (1 << 0)
+#define SUNXI_HDMI_VIDEO_POL_VER (1 << 1)
+#define SUNXI_HDMI_VIDEO_POL_TX_CLK (0x3e0 << 16)
+
+#ifdef CONFIG_MACH_SUN6I
+#define SUNXI_HDMI_PAD_CTRL0_HDP 0x7e80000f
+#define SUNXI_HDMI_PAD_CTRL0_RUN 0x7e8000ff
+#else
+#define SUNXI_HDMI_PAD_CTRL0_HDP 0xfe800000
+#define SUNXI_HDMI_PAD_CTRL0_RUN 0xfe800000
+#endif
+
+#ifdef CONFIG_MACH_SUN4I
+#define SUNXI_HDMI_PAD_CTRL1 0x00d8c820
+#elif defined CONFIG_MACH_SUN6I
+#define SUNXI_HDMI_PAD_CTRL1 0x01ded030
+#else
+#define SUNXI_HDMI_PAD_CTRL1 0x00d8c830
+#endif
+#define SUNXI_HDMI_PAD_CTRL1_HALVE (1 << 6)
+
+#ifdef CONFIG_MACH_SUN6I
+#define SUNXI_HDMI_PLL_CTRL 0xba48a308
+#define SUNXI_HDMI_PLL_CTRL_DIV(n) (((n) - 1) << 4)
+#else
+#define SUNXI_HDMI_PLL_CTRL 0xfa4ef708
+#define SUNXI_HDMI_PLL_CTRL_DIV(n) ((n) << 4)
+#endif
+#define SUNXI_HDMI_PLL_CTRL_DIV_MASK (0xf << 4)
+
+#define SUNXI_HDMI_PLL_DBG0_PLL3 (0 << 21)
+#define SUNXI_HDMI_PLL_DBG0_PLL7 (1 << 21)
+
+int sunxi_simplefb_setup(void *blob);
+
+#endif /* _SUNXI_DISPLAY_H */
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index c734cf0..366c0dc 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -134,6 +134,7 @@
#define SUNXI_GPIO_OUTPUT 1
#define SUNXI_GPA0_EMAC 2
+#define SUN6I_GPA0_GMAC 2
#define SUN7I_GPA0_GMAC 5
#define SUNXI_GPB0_TWI0 2
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 4949d57..a7f7c67 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -237,6 +237,26 @@
}
}
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+static bool boot_nonsec(void)
+{
+ char *s = getenv("bootm_boot_mode");
+#ifdef CONFIG_ARMV7_BOOT_SEC_DEFAULT
+ bool nonsec = false;
+#else
+ bool nonsec = true;
+#endif
+
+ if (s && !strcmp(s, "sec"))
+ nonsec = false;
+
+ if (s && !strcmp(s, "nonsec"))
+ nonsec = true;
+
+ return nonsec;
+}
+#endif
+
/* Subcommand: GO */
static void boot_jump_linux(bootm_headers_t *images, int flag)
{
@@ -285,12 +305,13 @@
if (!fake) {
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
- armv7_init_nonsec();
- secure_ram_addr(_do_nonsec_entry)(kernel_entry,
- 0, machid, r2);
-#else
- kernel_entry(0, machid, r2);
+ if (boot_nonsec()) {
+ armv7_init_nonsec();
+ secure_ram_addr(_do_nonsec_entry)(kernel_entry,
+ 0, machid, r2);
+ } else
#endif
+ kernel_entry(0, machid, r2);
}
#endif
}
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 4e597a4..f1c0792 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -11,7 +11,7 @@
__weak void flush_cache(unsigned long start, unsigned long size)
{
-#if defined(CONFIG_ARM1136)
+#if defined(CONFIG_CPU_ARM1136)
#if !defined(CONFIG_SYS_ICACHE_OFF)
asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */
@@ -21,14 +21,14 @@
asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */
#endif
-#endif /* CONFIG_ARM1136 */
+#endif /* CONFIG_CPU_ARM1136 */
-#ifdef CONFIG_ARM926EJS
+#ifdef CONFIG_CPU_ARM926EJS
/* test and clean, page 2-23 of arm926ejs manual */
asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
/* disable write buffer as well (page 2-22) */
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-#endif /* CONFIG_ARM926EJS */
+#endif /* CONFIG_CPU_ARM926EJS */
return;
}
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index 29cdad0..22df3e5 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -78,7 +78,7 @@
strlo r0, [r1] /* clear 32-bit GD word */
addlo r1, r1, #4 /* move to next */
blo clr_gd
-#if defined(CONFIG_SYS_MALLOC_F_LEN) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SYS_MALLOC_F_LEN)
sub sp, sp, #CONFIG_SYS_MALLOC_F_LEN
str sp, [r9, #GD_MALLOC_BASE]
#endif
@@ -104,6 +104,11 @@
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
b relocate_code
here:
+/*
+ * now relocate vectors
+ */
+
+ bl relocate_vectors
/* Set up final (full) environment */
diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index b4a258c..92f5314 100644
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -11,6 +11,47 @@
#include <linux/linkage.h>
/*
+ * Default/weak exception vectors relocation routine
+ *
+ * This routine covers the standard ARM cases: normal (0x00000000),
+ * high (0xffff0000) and VBAR. SoCs which do not comply with any of
+ * the standard cases must provide their own, strong, version.
+ */
+
+ .section .text.relocate_vectors,"ax",%progbits
+ .weak relocate_vectors
+
+ENTRY(relocate_vectors)
+
+#ifdef CONFIG_HAS_VBAR
+ /*
+ * If the ARM processor has the security extensions,
+ * use VBAR to relocate the exception vectors.
+ */
+ ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
+ mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
+#else
+ /*
+ * Copy the relocated exception vectors to the
+ * correct address
+ * CP15 c1 V bit gives us the location of the vectors:
+ * 0x00000000 or 0xFFFF0000.
+ */
+ ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
+ mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */
+ ands r2, r2, #(1 << 13)
+ ldreq r1, =0x00000000 /* If V=0 */
+ ldrne r1, =0xFFFF0000 /* If V=1 */
+ ldmia r0!, {r2-r8,r10}
+ stmia r1!, {r2-r8,r10}
+ ldmia r0!, {r2-r8,r10}
+ stmia r1!, {r2-r8,r10}
+#endif
+ bx lr
+
+ENDPROC(relocate_vectors)
+
+/*
* void relocate_code(addr_moni)
*
* This function relocates the monitor code.
@@ -54,34 +95,6 @@
cmp r2, r3
blo fixloop
- /*
- * Relocate the exception vectors
- */
-#ifdef CONFIG_HAS_VBAR
- /*
- * If the ARM processor has the security extensions,
- * use VBAR to relocate the exception vectors.
- */
- ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
- mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
-#else
- /*
- * Copy the relocated exception vectors to the
- * correct address
- * CP15 c1 V bit gives us the location of the vectors:
- * 0x00000000 or 0xFFFF0000.
- */
- ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
- mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */
- ands r2, r2, #(1 << 13)
- ldreq r1, =0x00000000 /* If V=0 */
- ldrne r1, =0xFFFF0000 /* If V=1 */
- ldmia r0!, {r2-r8,r10}
- stmia r1!, {r2-r8,r10}
- ldmia r0!, {r2-r8,r10}
- stmia r1!, {r2-r8,r10}
-#endif
-
relocate_done:
#ifdef __XSCALE__
@@ -96,9 +109,9 @@
/* ARMv4- don't know bx lr but the assembler fails to see that */
#ifdef __ARM_ARCH_4__
- mov pc, lr
+ mov pc, lr
#else
- bx lr
+ bx lr
#endif
ENDPROC(relocate_code)
diff --git a/arch/avr32/cpu/Makefile b/arch/avr32/cpu/Makefile
index 5e11721..00cede3 100644
--- a/arch/avr32/cpu/Makefile
+++ b/arch/avr32/cpu/Makefile
@@ -16,3 +16,5 @@
obj-y += interrupts.o
obj-$(CONFIG_PORTMUX_PIO) += portmux-pio.o
obj-$(CONFIG_PORTMUX_GPIO) += portmux-gpio.o
+
+obj-$(if $(filter at32ap700x,$(SOC)),y) += at32ap700x/
diff --git a/arch/avr32/cpu/at32ap700x/clk.c b/arch/avr32/cpu/at32ap700x/clk.c
index d5dbe3b..0fc6088 100644
--- a/arch/avr32/cpu/at32ap700x/clk.c
+++ b/arch/avr32/cpu/at32ap700x/clk.c
@@ -72,7 +72,7 @@
sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN));
rate = parent_rate;
} else {
- divider = min(255, divider / 2 - 1);
+ divider = min(255UL, divider / 2 - 1);
sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN) | SM_BIT(DIVEN)
| SM_BF(DIV, divider));
rate = parent_rate / (2 * (divider + 1));
diff --git a/arch/blackfin/cpu/jtag-console.c b/arch/blackfin/cpu/jtag-console.c
index b8be318..b0abeda 100644
--- a/arch/blackfin/cpu/jtag-console.c
+++ b/arch/blackfin/cpu/jtag-console.c
@@ -168,7 +168,7 @@
inbound_len = emudat;
} else {
/* store the bytes */
- leftovers_len = min(4, inbound_len);
+ leftovers_len = min((size_t)4, inbound_len);
inbound_len -= leftovers_len;
leftovers = emudat;
}
diff --git a/arch/blackfin/lib/string.c b/arch/blackfin/lib/string.c
index f0a061b..211df7b 100644
--- a/arch/blackfin/lib/string.c
+++ b/arch/blackfin/lib/string.c
@@ -121,7 +121,7 @@
*dshift = WDSIZE_P;
#endif
- *bpos = min(limit, ffs(ldst | lsrc | count)) - 1;
+ *bpos = min(limit, (unsigned long)ffs(ldst | lsrc | count)) - 1;
}
/* This version misbehaves for count values of 0 and 2^16+.
@@ -157,7 +157,7 @@
#ifdef PSIZE
/* The max memory DMA peripheral transfer size is 4 bytes. */
- dsize |= min(2, bpos) << PSIZE_P;
+ dsize |= min(2UL, bpos) << PSIZE_P;
#endif
/* Copy sram functions from sdram to sram */
diff --git a/arch/mips/cpu/mips32/Makefile b/arch/mips/cpu/mips32/Makefile
index e0e6309..fa82dd3 100644
--- a/arch/mips/cpu/mips32/Makefile
+++ b/arch/mips/cpu/mips32/Makefile
@@ -8,3 +8,5 @@
extra-y = start.o
obj-y = cache.o
obj-y += cpu.o interrupts.o time.o
+
+obj-$(CONFIG_SOC_AU1X00) += au1x00/
diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c
index a3dac70..74bdb77 100644
--- a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c
+++ b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c
@@ -54,8 +54,6 @@
#define readl(a) au_readl((long)(a))
#define writel(v,a) au_writel((v),(int)(a))
-#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
-
#define DEBUG
#ifdef DEBUG
#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile
index 206d304..8ab1fce 100644
--- a/arch/nds32/cpu/n1213/Makefile
+++ b/arch/nds32/cpu/n1213/Makefile
@@ -9,7 +9,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# necessary to create built-in.o
-obj- := __dummy__.o
-
extra-y = start.o
+
+obj-$(if $(filter ag101,$(SOC)),y) += ag101/
+obj-$(if $(filter ag102,$(SOC)),y) += ag102/
diff --git a/arch/nios2/cpu/fdt.c b/arch/nios2/cpu/fdt.c
index 4d88f16..5024682 100644
--- a/arch/nios2/cpu/fdt.c
+++ b/arch/nios2/cpu/fdt.c
@@ -18,11 +18,13 @@
DECLARE_GLOBAL_DATA_PTR;
-void __ft_board_setup(void *blob, bd_t *bd)
+int __ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
-void ft_board_setup(void *blob, bd_t *bd) \
+int ft_board_setup(void *blob, bd_t *bd)
__attribute__((weak, alias("__ft_board_setup")));
void ft_cpu_setup(void *blob, bd_t *bd)
@@ -32,5 +34,7 @@
* Note: aliases in the dts are required for this
*/
fdt_fixup_ethernet(blob);
+
+ return 0;
}
#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */
diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S
index 02c706e..94eb0d3 100644
--- a/arch/powerpc/cpu/mpc5xxx/start.S
+++ b/arch/powerpc/cpu/mpc5xxx/start.S
@@ -76,6 +76,21 @@
* been done in the SPL u-boot version.
*/
GET_GOT /* initialize GOT access */
+
+ /*
+ * The GD (global data) struct needs to get cleared. Lets do
+ * this by calling memset().
+ * This function is called when the platform is build with SPL
+ * support from the main (full-blown) U-Boot. And the GD needs
+ * to get cleared (again) so that the following generic
+ * board support code, defined via CONFIG_SYS_GENERIC_BOARD,
+ * initializes all variables correctly.
+ */
+ mr r3, r2 /* parameter 1: GD pointer */
+ li r4,0 /* parameter 2: value to fill */
+ li r5,GD_SIZE /* parameter 3: count */
+ bl memset
+
bl board_init_f /* run 1st part of board init code (in Flash)*/
/* NOTREACHED - board_init_f() does not return */
#else
diff --git a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c
index 3c8b2d9..b7c1b55 100644
--- a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c
+++ b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c
@@ -42,8 +42,6 @@
#define readl(a) (*((volatile u32 *)(a)))
#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
-#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
-
#ifdef DEBUG
#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
#else
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 2a1abe0..69a600c 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -68,6 +68,9 @@
config TARGET_TQM834X
bool "Support TQM834x"
+config TARGET_HRCON
+ bool "Support hrcon"
+
endchoice
source "board/esd/vme8349/Kconfig"
@@ -88,5 +91,6 @@
source "board/sbc8349/Kconfig"
source "board/tqc/tqm834x/Kconfig"
source "board/ve8313/Kconfig"
+source "board/gdsys/mpc8308/Kconfig"
endmenu
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 129ec66..4adba95 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -300,7 +300,7 @@
unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
u64 memsize = (u64)memsize_in_meg << 20;
- memsize = min(memsize, CONFIG_MAX_MEM_MAPPED);
+ memsize = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED);
memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM);
if (memsize)
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
index f8d03cb..71bb9d7 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
@@ -1661,7 +1661,7 @@
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
/* If a dimm is installed in a particular slot ... */
if (dimm_populated[dimm_num] != SDRAM_NONE)
- t_wr_ns = max(t_wr_ns,
+ t_wr_ns = max(t_wr_ns, (unsigned long)
spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
}
@@ -1838,12 +1838,18 @@
else
sdram_ddr1 = false;
- t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
- t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
- t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
- t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
- t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
- t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
+ t_rcd_ns = max(t_rcd_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
+ t_rrd_ns = max(t_rrd_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
+ t_rp_ns = max(t_rp_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
+ t_ras_ns = max(t_ras_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 30));
+ t_rc_ns = max(t_rc_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 41));
+ t_rfc_ns = max(t_rfc_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 42));
}
}
@@ -1916,9 +1922,12 @@
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
/* If a dimm is installed in a particular slot ... */
if (dimm_populated[dimm_num] != SDRAM_NONE) {
- t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
- t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
- t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
+ t_wpc_ns = max(t_wtr_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
+ t_wtr_ns = max(t_wtr_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
+ t_rpc_ns = max(t_rpc_ns,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
}
}
@@ -2314,7 +2323,8 @@
for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
/* If a dimm is installed in a particular slot ... */
if (dimm_populated[dimm_num] != SDRAM_NONE)
- ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
+ ecc = max(ecc,
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11));
}
if (ecc == 0)
return;
diff --git a/arch/powerpc/cpu/ppc4xx/fdt.c b/arch/powerpc/cpu/ppc4xx/fdt.c
index bd905d1..eef9c5a 100644
--- a/arch/powerpc/cpu/ppc4xx/fdt.c
+++ b/arch/powerpc/cpu/ppc4xx/fdt.c
@@ -18,7 +18,7 @@
DECLARE_GLOBAL_DATA_PTR;
-void __ft_board_setup(void *blob, bd_t *bd)
+int __ft_board_setup(void *blob, bd_t *bd)
{
int rc;
int i;
@@ -60,8 +60,11 @@
printf("Unable to update property EBC mappings, err=%s\n",
fdt_strerror(rc));
}
+
+ return 0;
}
-void ft_board_setup(void *blob, bd_t *bd) __attribute__((weak, alias("__ft_board_setup")));
+int ft_board_setup(void *blob, bd_t *bd)
+ __attribute__((weak, alias("__ft_board_setup")));
/*
* Fixup all PCIe nodes by setting the device_type property
diff --git a/arch/powerpc/cpu/ppc4xx/usb_ohci.c b/arch/powerpc/cpu/ppc4xx/usb_ohci.c
index d1e78f6..65a0675 100644
--- a/arch/powerpc/cpu/ppc4xx/usb_ohci.c
+++ b/arch/powerpc/cpu/ppc4xx/usb_ohci.c
@@ -40,8 +40,6 @@
#define readl(a) (*((volatile u32 *)(a)))
#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
-#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
-
#ifdef DEBUG
#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
#else
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index f60cb0a..8e0e190 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -71,6 +71,22 @@
INTERLAKEN,
QSGMII_SW1_A, /* Indicates ports on L2 Switch */
QSGMII_SW1_B,
+ SGMII_2500_FM1_DTSEC1,
+ SGMII_2500_FM1_DTSEC2,
+ SGMII_2500_FM1_DTSEC3,
+ SGMII_2500_FM1_DTSEC4,
+ SGMII_2500_FM1_DTSEC5,
+ SGMII_2500_FM1_DTSEC6,
+ SGMII_2500_FM1_DTSEC9,
+ SGMII_2500_FM1_DTSEC10,
+ SGMII_2500_FM2_DTSEC1,
+ SGMII_2500_FM2_DTSEC2,
+ SGMII_2500_FM2_DTSEC3,
+ SGMII_2500_FM2_DTSEC4,
+ SGMII_2500_FM2_DTSEC5,
+ SGMII_2500_FM2_DTSEC6,
+ SGMII_2500_FM2_DTSEC9,
+ SGMII_2500_FM2_DTSEC10,
};
enum srds {
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 33099a4..ef15e7a 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -126,7 +126,7 @@
#endif
size = min(bootm_size, get_effective_memsize());
- size = min(size, CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE);
+ size = min(size, (ulong)CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE);
if (size < bootm_size) {
ulong base = bootmap_base + size;
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 1c4aa3f..31c9344 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -385,7 +385,7 @@
return os_dirent_typename[OS_FILET_UNKNOWN];
}
-ssize_t os_get_filesize(const char *fname)
+int os_get_filesize(const char *fname, loff_t *size)
{
struct stat buf;
int ret;
@@ -393,7 +393,8 @@
ret = stat(fname, &buf);
if (ret)
return ret;
- return buf.st_size;
+ *size = buf.st_size;
+ return 0;
}
void os_putc(int ch)
@@ -427,11 +428,11 @@
{
struct sandbox_state *state = state_get_current();
int fd, ret;
- int size;
+ loff_t size;
- size = os_get_filesize(fname);
- if (size < 0)
- return -ENOENT;
+ ret = os_get_filesize(fname, &size);
+ if (ret < 0)
+ return ret;
if (size != state->ram_size)
return -ENOSPC;
fd = open(fname, O_RDONLY);
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index 53a99ae..0df7770 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -39,7 +39,7 @@
max_arg_len = 0;
for (i = 0; i < num_options; ++i)
- max_arg_len = max(strlen(sb_opt[i]->flag), max_arg_len);
+ max_arg_len = max((int)strlen(sb_opt[i]->flag), max_arg_len);
max_noarg_len = max_arg_len + 7;
for (i = 0; i < num_options; ++i) {
diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c
index 59adad6..ba73b7e 100644
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c
@@ -49,14 +49,14 @@
static int state_read_file(struct sandbox_state *state, const char *fname)
{
- int size;
+ loff_t size;
int ret;
int fd;
- size = os_get_filesize(fname);
- if (size < 0) {
+ ret = os_get_filesize(fname, &size);
+ if (ret < 0) {
printf("Cannot find sandbox state file '%s'\n", fname);
- return -ENOENT;
+ return ret;
}
state->state_fdt = os_malloc(size);
if (!state->state_fdt) {
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 0dba8ac..6e29868 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -12,9 +12,81 @@
config TARGET_COREBOOT
bool "Support coreboot"
+ help
+ This target is used for running U-Boot on top of Coreboot. In
+ this case Coreboot does the early inititalisation, and U-Boot
+ takes over once the RAM, video and CPU are fully running.
+ U-Boot is loaded as a fallback payload from Coreboot, in
+ Coreboot terminology. This method was used for the Chromebook
+ Pixel when launched.
+
+config TARGET_CHROMEBOOK_LINK
+ bool "Support Chromebook link"
+ help
+ This is the Chromebook Pixel released in 2013. It uses an Intel
+ i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
+ SDRAM. It has a Panther Point platform controller hub, PCIe
+ WiFi and Bluetooth. It also includes a 720p webcam, USB SD
+ reader, microphone and speakers, display port and 32GB SATA
+ solid state drive. There is a Chrome OS EC connected on LPC,
+ and it provides a 2560x1700 high resolution touch-enabled LCD
+ display.
endchoice
+config RAMBASE
+ hex
+ default 0x100000
+
+config RAMTOP
+ hex
+ default 0x200000
+
+config XIP_ROM_SIZE
+ hex
+ default 0x10000
+
+config CPU_ADDR_BITS
+ int
+ default 36
+
+config HPET_ADDRESS
+ hex
+ default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
+
+config SMM_TSEG
+ bool
+ default n
+
+config SMM_TSEG_SIZE
+ hex
+
+config ROM_SIZE
+ hex
+ default 0x800000
+
+config HAVE_INTEL_ME
+ bool "Platform requires Intel Management Engine"
+ help
+ Newer higher-end devices have an Intel Management Engine (ME)
+ which is a very large binary blob (typically 1.5MB) which is
+ required for the platform to work. This enforces a particular
+ SPI flash format. You will need to supply the me.bin file in
+ your board directory.
+
+config X86_RAMTEST
+ bool "Perform a simple RAM test after SDRAM initialisation"
+ help
+ If there is something wrong with SDRAM then the platform will
+ often crash within U-Boot or the kernel. This option enables a
+ very simple RAM test that quickly checks whether the SDRAM seems
+ to work correctly. It is not exhaustive but can save time by
+ detecting obvious failures.
+
+source "arch/x86/cpu/ivybridge/Kconfig"
+
+source "board/coreboot/coreboot/Kconfig"
+
-source "board/chromebook-x86/coreboot/Kconfig"
+source "board/google/chromebook_link/Kconfig"
endmenu
diff --git a/arch/x86/config.mk b/arch/x86/config.mk
index 3e7fedb..bb2da46 100644
--- a/arch/x86/config.mk
+++ b/arch/x86/config.mk
@@ -15,7 +15,6 @@
$(call cc-option, -mpreferred-stack-boundary=2)
PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86)
PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
-PLATFORM_CPPFLAGS += -DREALMODE_BASE=0x7c0
PLATFORM_CPPFLAGS += -march=i386 -m32
# Support generic board on x86
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 9d38ef7..2b9e9b9 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -11,3 +11,6 @@
extra-y = start.o
obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
obj-y += interrupts.o cpu.o call64.o
+
+obj-$(CONFIG_SYS_COREBOOT) += coreboot/
+obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile
index cd0bf4e..35e6cdd 100644
--- a/arch/x86/cpu/coreboot/Makefile
+++ b/arch/x86/cpu/coreboot/Makefile
@@ -13,10 +13,10 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_SYS_COREBOOT) += car.o
-obj-$(CONFIG_SYS_COREBOOT) += coreboot.o
-obj-$(CONFIG_SYS_COREBOOT) += tables.o
-obj-$(CONFIG_SYS_COREBOOT) += ipchecksum.o
-obj-$(CONFIG_SYS_COREBOOT) += sdram.o
-obj-$(CONFIG_SYS_COREBOOT) += timestamp.o
+obj-y += car.o
+obj-y += coreboot.o
+obj-y += tables.o
+obj-y += ipchecksum.o
+obj-y += sdram.o
+obj-y += timestamp.o
obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index e24f13a..2df7288 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -13,25 +13,25 @@
#include <ns16550.h>
#include <asm/msr.h>
#include <asm/cache.h>
+#include <asm/cpu.h>
#include <asm/io.h>
-#include <asm/arch-coreboot/tables.h>
-#include <asm/arch-coreboot/sysinfo.h>
+#include <asm/arch/tables.h>
+#include <asm/arch/sysinfo.h>
#include <asm/arch/timestamp.h>
DECLARE_GLOBAL_DATA_PTR;
-/*
- * Miscellaneous platform dependent initializations
- */
-int cpu_init_f(void)
+int arch_cpu_init(void)
{
int ret = get_coreboot_info(&lib_sysinfo);
- if (ret != 0)
+ if (ret != 0) {
printf("Failed to parse coreboot tables.\n");
+ return ret;
+ }
timestamp_init();
- return ret;
+ return x86_cpu_init_f();
}
int board_early_init_f(void)
@@ -50,27 +50,9 @@
return 0;
}
-void show_boot_progress(int val)
+int print_cpuinfo(void)
{
-#if MIN_PORT80_KCLOCKS_DELAY
- /*
- * Scale the time counter reading to avoid using 64 bit arithmetics.
- * Can't use get_timer() here becuase it could be not yet
- * initialized or even implemented.
- */
- if (!gd->arch.tsc_prev) {
- gd->arch.tsc_base_kclocks = rdtsc() / 1000;
- gd->arch.tsc_prev = 0;
- } else {
- uint32_t now;
-
- do {
- now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
- } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
- gd->arch.tsc_prev = now;
- }
-#endif
- outb(val, 0x80);
+ return default_print_cpuinfo();
}
int last_stage_init(void)
@@ -98,7 +80,7 @@
#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
-int board_final_cleanup(void)
+void board_final_cleanup(void)
{
/* Un-cache the ROM so the kernel has one
* more MTRR available.
@@ -120,8 +102,6 @@
/* Issue SMI to Coreboot to lock down ME and registers */
printf("Finalizing Coreboot\n");
outb(0xcb, 0xb2);
-
- return 0;
}
void panic_puts(const char *str)
diff --git a/arch/x86/cpu/coreboot/ipchecksum.c b/arch/x86/cpu/coreboot/ipchecksum.c
index 57733d8..5f6c009 100644
--- a/arch/x86/cpu/coreboot/ipchecksum.c
+++ b/arch/x86/cpu/coreboot/ipchecksum.c
@@ -30,7 +30,7 @@
*/
#include <compiler.h>
-#include <asm/arch-coreboot/ipchecksum.h>
+#include <asm/arch/ipchecksum.h>
unsigned short ipchksum(const void *vptr, unsigned long nbytes)
{
diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index 33f16a3..6a3dd93 100644
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -13,14 +13,12 @@
#include <pci.h>
#include <asm/pci.h>
-static struct pci_controller coreboot_hose;
-
static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
struct pci_config_table *table)
{
u8 secondary;
hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
- hose->last_busno = max(hose->last_busno, secondary);
+ hose->last_busno = max(hose->last_busno, (int)secondary);
pci_hose_scan_bus(hose, secondary);
}
@@ -31,19 +29,13 @@
{}
};
-void pci_init_board(void)
+void board_pci_setup_hose(struct pci_controller *hose)
{
- coreboot_hose.config_table = pci_coreboot_config_table;
- coreboot_hose.first_busno = 0;
- coreboot_hose.last_busno = 0;
-
- pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff,
- PCI_REGION_MEM);
- coreboot_hose.region_count = 1;
-
- pci_setup_type1(&coreboot_hose);
-
- pci_register_hose(&coreboot_hose);
+ hose->config_table = pci_coreboot_config_table;
+ hose->first_busno = 0;
+ hose->last_busno = 0;
- pci_hose_scan(&coreboot_hose);
+ pci_set_region(hose->regions + 0, 0x0, 0x0, 0xffffffff,
+ PCI_REGION_MEM);
+ hose->region_count = 1;
}
diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c
index 959feaa..e98a230 100644
--- a/arch/x86/cpu/coreboot/sdram.c
+++ b/arch/x86/cpu/coreboot/sdram.c
@@ -11,8 +11,10 @@
#include <asm/e820.h>
#include <asm/u-boot-x86.h>
#include <asm/global_data.h>
+#include <asm/init_helpers.h>
#include <asm/processor.h>
#include <asm/sections.h>
+#include <asm/zimage.h>
#include <asm/arch/sysinfo.h>
#include <asm/arch/tables.h>
@@ -22,7 +24,7 @@
{
int i;
- unsigned num_entries = min(lib_sysinfo.n_memranges, max_entries);
+ unsigned num_entries = min((unsigned)lib_sysinfo.n_memranges, max_entries);
if (num_entries < lib_sysinfo.n_memranges) {
printf("Warning: Limiting e820 map to %d entries.\n",
num_entries);
@@ -79,7 +81,7 @@
return (ulong)dest_addr;
}
-int dram_init_f(void)
+int dram_init(void)
{
int i;
phys_size_t ram_size = 0;
@@ -94,10 +96,11 @@
gd->ram_size = ram_size;
if (ram_size == 0)
return -1;
- return 0;
+
+ return calculate_relocation_address();
}
-int dram_init_banksize(void)
+void dram_init_banksize(void)
{
int i, j;
@@ -114,10 +117,4 @@
}
}
}
- return 0;
-}
-
-int dram_init(void)
-{
- return dram_init_banksize();
}
diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c
index 0d91adc..92b7528 100644
--- a/arch/x86/cpu/coreboot/tables.c
+++ b/arch/x86/cpu/coreboot/tables.c
@@ -8,9 +8,9 @@
*/
#include <common.h>
-#include <asm/arch-coreboot/ipchecksum.h>
-#include <asm/arch-coreboot/sysinfo.h>
-#include <asm/arch-coreboot/tables.h>
+#include <asm/arch/ipchecksum.h>
+#include <asm/arch/sysinfo.h>
+#include <asm/arch/tables.h>
/*
* This needs to be in the .data section so that it's copied over during
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 2e25253..b391b7a 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -13,6 +13,9 @@
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
+ * Part of this file is adapted from coreboot
+ * src/arch/x86/lib/cpu.c
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -22,11 +25,14 @@
#include <malloc.h>
#include <asm/control_regs.h>
#include <asm/cpu.h>
+#include <asm/post.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
#include <asm/interrupt.h>
#include <linux/compiler.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* Constructor for a conventional segment GDT (or LDT) entry
* This is a macro so it can be used in initialisers
@@ -43,6 +49,52 @@
u32 ptr;
} __packed;
+struct cpu_device_id {
+ unsigned vendor;
+ unsigned device;
+};
+
+struct cpuinfo_x86 {
+ uint8_t x86; /* CPU family */
+ uint8_t x86_vendor; /* CPU vendor */
+ uint8_t x86_model;
+ uint8_t x86_mask;
+};
+
+/*
+ * List of cpu vendor strings along with their normalized
+ * id values.
+ */
+static struct {
+ int vendor;
+ const char *name;
+} x86_vendors[] = {
+ { X86_VENDOR_INTEL, "GenuineIntel", },
+ { X86_VENDOR_CYRIX, "CyrixInstead", },
+ { X86_VENDOR_AMD, "AuthenticAMD", },
+ { X86_VENDOR_UMC, "UMC UMC UMC ", },
+ { X86_VENDOR_NEXGEN, "NexGenDriven", },
+ { X86_VENDOR_CENTAUR, "CentaurHauls", },
+ { X86_VENDOR_RISE, "RiseRiseRise", },
+ { X86_VENDOR_TRANSMETA, "GenuineTMx86", },
+ { X86_VENDOR_TRANSMETA, "TransmetaCPU", },
+ { X86_VENDOR_NSC, "Geode by NSC", },
+ { X86_VENDOR_SIS, "SiS SiS SiS ", },
+};
+
+static const char *const x86_vendor_name[] = {
+ [X86_VENDOR_INTEL] = "Intel",
+ [X86_VENDOR_CYRIX] = "Cyrix",
+ [X86_VENDOR_AMD] = "AMD",
+ [X86_VENDOR_UMC] = "UMC",
+ [X86_VENDOR_NEXGEN] = "NexGen",
+ [X86_VENDOR_CENTAUR] = "Centaur",
+ [X86_VENDOR_RISE] = "Rise",
+ [X86_VENDOR_TRANSMETA] = "Transmeta",
+ [X86_VENDOR_NSC] = "NSC",
+ [X86_VENDOR_SIS] = "SiS",
+};
+
static void load_ds(u32 segment)
{
asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
@@ -115,6 +167,129 @@
return 0;
}
+/*
+ * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
+ * by the fact that they preserve the flags across the division of 5/2.
+ * PII and PPro exhibit this behavior too, but they have cpuid available.
+ */
+
+/*
+ * Perform the Cyrix 5/2 test. A Cyrix won't change
+ * the flags, while other 486 chips will.
+ */
+static inline int test_cyrix_52div(void)
+{
+ unsigned int test;
+
+ __asm__ __volatile__(
+ "sahf\n\t" /* clear flags (%eax = 0x0005) */
+ "div %b2\n\t" /* divide 5 by 2 */
+ "lahf" /* store flags into %ah */
+ : "=a" (test)
+ : "0" (5), "q" (2)
+ : "cc");
+
+ /* AH is 0x02 on Cyrix after the divide.. */
+ return (unsigned char) (test >> 8) == 0x02;
+}
+
+/*
+ * Detect a NexGen CPU running without BIOS hypercode new enough
+ * to have CPUID. (Thanks to Herbert Oppmann)
+ */
+
+static int deep_magic_nexgen_probe(void)
+{
+ int ret;
+
+ __asm__ __volatile__ (
+ " movw $0x5555, %%ax\n"
+ " xorw %%dx,%%dx\n"
+ " movw $2, %%cx\n"
+ " divw %%cx\n"
+ " movl $0, %%eax\n"
+ " jnz 1f\n"
+ " movl $1, %%eax\n"
+ "1:\n"
+ : "=a" (ret) : : "cx", "dx");
+ return ret;
+}
+
+static bool has_cpuid(void)
+{
+ return flag_is_changeable_p(X86_EFLAGS_ID);
+}
+
+static int build_vendor_name(char *vendor_name)
+{
+ struct cpuid_result result;
+ result = cpuid(0x00000000);
+ unsigned int *name_as_ints = (unsigned int *)vendor_name;
+
+ name_as_ints[0] = result.ebx;
+ name_as_ints[1] = result.edx;
+ name_as_ints[2] = result.ecx;
+
+ return result.eax;
+}
+
+static void identify_cpu(struct cpu_device_id *cpu)
+{
+ char vendor_name[16];
+ int i;
+
+ vendor_name[0] = '\0'; /* Unset */
+ cpu->device = 0; /* fix gcc 4.4.4 warning */
+
+ /* Find the id and vendor_name */
+ if (!has_cpuid()) {
+ /* Its a 486 if we can modify the AC flag */
+ if (flag_is_changeable_p(X86_EFLAGS_AC))
+ cpu->device = 0x00000400; /* 486 */
+ else
+ cpu->device = 0x00000300; /* 386 */
+ if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
+ memcpy(vendor_name, "CyrixInstead", 13);
+ /* If we ever care we can enable cpuid here */
+ }
+ /* Detect NexGen with old hypercode */
+ else if (deep_magic_nexgen_probe())
+ memcpy(vendor_name, "NexGenDriven", 13);
+ }
+ if (has_cpuid()) {
+ int cpuid_level;
+
+ cpuid_level = build_vendor_name(vendor_name);
+ vendor_name[12] = '\0';
+
+ /* Intel-defined flags: level 0x00000001 */
+ if (cpuid_level >= 0x00000001) {
+ cpu->device = cpuid_eax(0x00000001);
+ } else {
+ /* Have CPUID level 0 only unheard of */
+ cpu->device = 0x00000400;
+ }
+ }
+ cpu->vendor = X86_VENDOR_UNKNOWN;
+ for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
+ if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
+ cpu->vendor = x86_vendors[i].vendor;
+ break;
+ }
+ }
+}
+
+static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
+{
+ c->x86 = (tfms >> 8) & 0xf;
+ c->x86_model = (tfms >> 4) & 0xf;
+ c->x86_mask = tfms & 0xf;
+ if (c->x86 == 0xf)
+ c->x86 += (tfms >> 20) & 0xff;
+ if (c->x86 >= 0x6)
+ c->x86_model += ((tfms >> 16) & 0xF) << 4;
+}
+
int x86_cpu_init_f(void)
{
const u32 em_rst = ~X86_CR0_EM;
@@ -128,9 +303,22 @@
"movl %%eax, %%cr0\n" \
: : "i" (em_rst), "i" (mp_ne_set) : "eax");
+ /* identify CPU via cpuid and store the decoded info into gd->arch */
+ if (has_cpuid()) {
+ struct cpu_device_id cpu;
+ struct cpuinfo_x86 c;
+
+ identify_cpu(&cpu);
+ get_fms(&c, cpu.device);
+ gd->arch.x86 = c.x86;
+ gd->arch.x86_vendor = cpu.vendor;
+ gd->arch.x86_model = c.x86_model;
+ gd->arch.x86_mask = c.x86_mask;
+ gd->arch.x86_device = cpu.device;
+ }
+
return 0;
}
-int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));
int x86_cpu_init_r(void)
{
@@ -198,14 +386,13 @@
"generate_gpf:\n"
"ljmp $0x70, $0x47114711\n");
-void __reset_cpu(ulong addr)
+__weak void reset_cpu(ulong addr)
{
printf("Resetting using x86 Triple Fault\n");
set_vector(13, generate_gpf); /* general protection fault handler */
set_vector(8, generate_gpf); /* double fault handler */
generate_gpf(); /* start the show */
}
-void reset_cpu(ulong addr) __attribute__((weak, alias("__reset_cpu")));
int dcache_status(void)
{
@@ -279,66 +466,63 @@
: "eax");
}
-static bool has_cpuid(void)
+static bool can_detect_long_mode(void)
{
- unsigned long flag;
-
- asm volatile("pushf\n" \
- "pop %%eax\n"
- "mov %%eax, %%ecx\n" /* ecx = flags */
- "xor %1, %%eax\n"
- "push %%eax\n"
- "popf\n" /* flags ^= $2 */
- "pushf\n"
- "pop %%eax\n" /* eax = flags */
- "push %%ecx\n"
- "popf\n" /* flags = ecx */
- "xor %%ecx, %%eax\n"
- "mov %%eax, %0"
- : "=r" (flag)
- : "i" (1 << 21)
- : "eax", "ecx", "memory");
+ return cpuid_eax(0x80000000) > 0x80000000UL;
+}
- return flag != 0;
+static bool has_long_mode(void)
+{
+ return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
}
-static bool can_detect_long_mode(void)
+int cpu_has_64bit(void)
{
- unsigned long flag;
+ return has_cpuid() && can_detect_long_mode() &&
+ has_long_mode();
+}
- asm volatile("mov $0x80000000, %%eax\n"
- "cpuid\n"
- "mov %%eax, %0"
- : "=r" (flag)
- :
- : "eax", "ebx", "ecx", "edx", "memory");
+const char *cpu_vendor_name(int vendor)
+{
+ const char *name;
+ name = "<invalid cpu vendor>";
+ if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
+ (x86_vendor_name[vendor] != 0))
+ name = x86_vendor_name[vendor];
- return flag > 0x80000000UL;
+ return name;
}
-static bool has_long_mode(void)
+char *cpu_get_name(char *name)
{
- unsigned long flag;
+ unsigned int *name_as_ints = (unsigned int *)name;
+ struct cpuid_result regs;
+ char *ptr;
+ int i;
- asm volatile("mov $0x80000001, %%eax\n"
- "cpuid\n"
- "mov %%edx, %0"
- : "=r" (flag)
- :
- : "eax", "ebx", "ecx", "edx", "memory");
+ /* This bit adds up to 48 bytes */
+ for (i = 0; i < 3; i++) {
+ regs = cpuid(0x80000002 + i);
+ name_as_ints[i * 4 + 0] = regs.eax;
+ name_as_ints[i * 4 + 1] = regs.ebx;
+ name_as_ints[i * 4 + 2] = regs.ecx;
+ name_as_ints[i * 4 + 3] = regs.edx;
+ }
+ name[CPU_MAX_NAME_LEN - 1] = '\0';
- return flag & (1 << 29) ? true : false;
-}
+ /* Skip leading spaces. */
+ ptr = name;
+ while (*ptr == ' ')
+ ptr++;
-int cpu_has_64bit(void)
-{
- return has_cpuid() && can_detect_long_mode() &&
- has_long_mode();
+ return ptr;
}
-int print_cpuinfo(void)
+int default_print_cpuinfo(void)
{
- printf("CPU: %s\n", cpu_has_64bit() ? "x86_64" : "x86");
+ printf("CPU: %s, vendor %s, device %xh\n",
+ cpu_has_64bit() ? "x86_64" : "x86",
+ cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
return 0;
}
@@ -384,3 +568,26 @@
return -EFAULT;
}
+
+void show_boot_progress(int val)
+{
+#if MIN_PORT80_KCLOCKS_DELAY
+ /*
+ * Scale the time counter reading to avoid using 64 bit arithmetics.
+ * Can't use get_timer() here becuase it could be not yet
+ * initialized or even implemented.
+ */
+ if (!gd->arch.tsc_prev) {
+ gd->arch.tsc_base_kclocks = rdtsc() / 1000;
+ gd->arch.tsc_prev = 0;
+ } else {
+ uint32_t now;
+
+ do {
+ now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
+ } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
+ gd->arch.tsc_prev = now;
+ }
+#endif
+ outb(val, POST_PORT);
+}
diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c
index 6f3d85f..51e2c59 100644
--- a/arch/x86/cpu/interrupts.c
+++ b/arch/x86/cpu/interrupts.c
@@ -31,7 +31,7 @@
"pushl $"#x"\n" \
"jmp irq_common_entry\n"
-void dump_regs(struct irq_regs *regs)
+static void dump_regs(struct irq_regs *regs)
{
unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
unsigned long d0, d1, d2, d3, d6, d7;
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
new file mode 100644
index 0000000..afca957
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -0,0 +1,172 @@
+#
+# From Coreboot src/northbridge/intel/sandybridge/Kconfig
+#
+# Copyright (C) 2010 Google Inc.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+
+config NORTHBRIDGE_INTEL_SANDYBRIDGE
+ bool
+ select CACHE_MRC_BIN
+ select CPU_INTEL_MODEL_206AX
+
+config NORTHBRIDGE_INTEL_IVYBRIDGE
+ bool
+ select CACHE_MRC_BIN
+ select CPU_INTEL_MODEL_306AX
+
+if NORTHBRIDGE_INTEL_SANDYBRIDGE
+
+config VGA_BIOS_ID
+ string
+ default "8086,0106"
+
+config CACHE_MRC_SIZE_KB
+ int
+ default 256
+
+config MRC_CACHE_BASE
+ hex
+ default 0xff800000
+
+config MRC_CACHE_LOCATION
+ hex
+ depends on !CHROMEOS
+ default 0x1ec000
+
+config MRC_CACHE_SIZE
+ hex
+ depends on !CHROMEOS
+ default 0x10000
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xff7f0000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x10000
+
+endif
+
+if NORTHBRIDGE_INTEL_IVYBRIDGE
+
+config VGA_BIOS_ID
+ string
+ default "8086,0166"
+
+config EXTERNAL_MRC_BLOB
+ bool
+ default n
+
+config CACHE_MRC_SIZE_KB
+ int
+ default 512
+
+config MRC_CACHE_BASE
+ hex
+ default 0xff800000
+
+config MRC_CACHE_LOCATION
+ hex
+ depends on !CHROMEOS
+ default 0x370000
+
+config MRC_CACHE_SIZE
+ hex
+ depends on !CHROMEOS
+ default 0x10000
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xff7e0000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x20000
+
+endif
+
+if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE
+
+config HAVE_MRC
+ bool "Add a System Agent binary"
+ help
+ Select this option to add a System Agent binary to
+ the resulting U-Boot image. MRC stands for Memory Reference Code.
+ It is a binary blob which U-Boot uses to set up SDRAM.
+
+ Note: Without this binary U-Boot will not be able to set up its
+ SDRAM so will not boot.
+
+config DCACHE_RAM_MRC_VAR_SIZE
+ hex
+ default 0x4000
+ help
+ This is the amount of CAR (Cache as RAM) reserved for use by the
+ memory reference code. This should be set to 16KB (0x4000 hex)
+ so that MRC has enough space to run.
+
+config MRC_FILE
+ string "Intel System Agent path and filename"
+ depends on HAVE_MRC
+ default "systemagent-ivybridge.bin" if NORTHBRIDGE_INTEL_IVYBRIDGE
+ default "systemagent-sandybridge.bin" if NORTHBRIDGE_INTEL_SANDYBRIDGE
+ help
+ The path and filename of the file to use as System Agent
+ binary.
+
+config CPU_SPECIFIC_OPTIONS
+ def_bool y
+ select SMM_TSEG
+ select ARCH_BOOTBLOCK_X86_32
+ select ARCH_ROMSTAGE_X86_32
+ select ARCH_RAMSTAGE_X86_32
+ select SMP
+ select SSE2
+ select UDELAY_LAPIC
+ select CPU_MICROCODE_IN_CBFS
+ select TSC_SYNC_MFENCE
+ select HAVE_INTEL_ME
+ select X86_RAMTEST
+
+config SMM_TSEG_SIZE
+ hex
+ default 0x800000
+
+config ENABLE_VMX
+ bool "Enable VMX for virtualization"
+ default n
+ help
+ Virtual Machine Extensions are provided in many x86 CPUs. These
+ provide various facilities for allowing a host OS to provide an
+ environment where potentially several guest OSes have only
+ limited access to the underlying hardware. This is achieved
+ without resorting to software trapping and/or instruction set
+ emulation (which would be very slow).
+
+ Intel's implementation of this is called VT-x. This option enables
+ VT-x this so that the OS that is booted by U-Boot can make use of
+ these facilities. If this option is not enabled, then the host OS
+ will be unable to support virtualisation, or it will run very
+ slowly.
+
+endif
+
+config CPU_INTEL_SOCKET_RPGA989
+ bool
+
+if CPU_INTEL_SOCKET_RPGA989
+
+config SOCKET_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select MMX
+ select SSE
+ select CACHE_AS_RAM
+
+config CACHE_MRC_BIN
+ bool
+ default n
+
+endif
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
new file mode 100644
index 0000000..721b37e
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -0,0 +1,16 @@
+#
+# Copyright (c) 2014 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += car.o
+obj-y += cpu.o
+obj-y += early_init.o
+obj-y += early_me.o
+obj-y += lpc.o
+obj-y += me_status.o
+obj-y += microcode_intel.o
+obj-y += pci.o
+obj-y += report_platform.o
+obj-y += sdram.o
diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S
new file mode 100644
index 0000000..dca68e4
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/car.S
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * From Coreboot file cpu/intel/model_206ax/cache_as_ram.inc
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
+ * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/mtrr.h>
+#include <asm/post.h>
+#include <asm/processor-flags.h>
+
+#define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg))
+#define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1)
+
+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+
+/* Cache 4GB - MRC_SIZE_KB for MRC */
+#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
+#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES)
+#define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
+
+#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
+
+#define NOEVICTMOD_MSR 0x2e0
+
+ /*
+ * Note: ebp must not be touched in this code as it holds the BIST
+ * value (built-in self test). We preserve this value until it can
+ * be written to global_data when CAR is ready for use.
+ */
+.globl car_init
+car_init:
+ post_code(POST_CAR_START)
+
+ /* Send INIT IPI to all excluding ourself */
+ movl $0x000C4500, %eax
+ movl $0xFEE00300, %esi
+ movl %eax, (%esi)
+
+ post_code(POST_CAR_SIPI)
+ /* Zero out all fixed range and variable range MTRRs */
+ movl $mtrr_table, %esi
+ movl $((mtrr_table_end - mtrr_table) / 2), %edi
+ xorl %eax, %eax
+ xorl %edx, %edx
+clear_mtrrs:
+ movw (%esi), %bx
+ movzx %bx, %ecx
+ wrmsr
+ add $2, %esi
+ dec %edi
+ jnz clear_mtrrs
+
+ post_code(POST_CAR_MTRR)
+ /* Configure the default memory type to uncacheable */
+ movl $MTRRdefType_MSR, %ecx
+ rdmsr
+ andl $(~0x00000cff), %eax
+ wrmsr
+
+ post_code(POST_CAR_UNCACHEABLE)
+ /* Set Cache-as-RAM base address */
+ movl $(MTRR_PHYS_BASE_MSR(0)), %ecx
+ movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
+ xorl %edx, %edx
+ wrmsr
+
+ post_code(POST_CAR_BASE_ADDRESS)
+ /* Set Cache-as-RAM mask */
+ movl $(MTRR_PHYS_MASK_MSR(0)), %ecx
+ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $CPU_PHYSMASK_HI, %edx
+ wrmsr
+
+ post_code(POST_CAR_MASK)
+
+ /* Enable MTRR */
+ movl $MTRRdefType_MSR, %ecx
+ rdmsr
+ orl $MTRRdefTypeEn, %eax
+ wrmsr
+
+ /* Enable cache (CR0.CD = 0, CR0.NW = 0) */
+ movl %cr0, %eax
+ andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax
+ invd
+ movl %eax, %cr0
+
+ /* enable the 'no eviction' mode */
+ movl $NOEVICTMOD_MSR, %ecx
+ rdmsr
+ orl $1, %eax
+ andl $~2, %eax
+ wrmsr
+
+ /* Clear the cache memory region. This will also fill up the cache */
+ movl $CACHE_AS_RAM_BASE, %esi
+ movl %esi, %edi
+ movl $(CACHE_AS_RAM_SIZE / 4), %ecx
+ xorl %eax, %eax
+ rep stosl
+
+ /* enable the 'no eviction run' state */
+ movl $NOEVICTMOD_MSR, %ecx
+ rdmsr
+ orl $3, %eax
+ wrmsr
+
+ post_code(POST_CAR_FILL)
+ /* Enable Cache-as-RAM mode by disabling cache */
+ movl %cr0, %eax
+ orl $X86_CR0_CD, %eax
+ movl %eax, %cr0
+
+ /* Enable cache for our code in Flash because we do XIP here */
+ movl $MTRR_PHYS_BASE_MSR(1), %ecx
+ xorl %edx, %edx
+ movl $car_init_ret, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
+ orl $MTRR_TYPE_WRPROT, %eax
+ wrmsr
+
+ movl $MTRR_PHYS_MASK_MSR(1), %ecx
+ movl $CPU_PHYSMASK_HI, %edx
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ wrmsr
+
+ post_code(POST_CAR_ROM_CACHE)
+#ifdef CONFIG_CACHE_MRC_BIN
+ /* Enable caching for ram init code to run faster */
+ movl $MTRR_PHYS_BASE_MSR(2), %ecx
+ movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
+ xorl %edx, %edx
+ wrmsr
+ movl $MTRR_PHYS_MASK_MSR(2), %ecx
+ movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
+ movl $CPU_PHYSMASK_HI, %edx
+ wrmsr
+#endif
+
+ post_code(POST_CAR_MRC_CACHE)
+ /* Enable cache */
+ movl %cr0, %eax
+ andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax
+ movl %eax, %cr0
+
+ post_code(POST_CAR_CPU_CACHE)
+
+ /* All CPUs need to be in Wait for SIPI state */
+wait_for_sipi:
+ movl (%esi), %eax
+ bt $12, %eax
+ jc wait_for_sipi
+
+ /* return */
+ jmp car_init_ret
+
+mtrr_table:
+ /* Fixed MTRRs */
+ .word 0x250, 0x258, 0x259
+ .word 0x268, 0x269, 0x26A
+ .word 0x26B, 0x26C, 0x26D
+ .word 0x26E, 0x26F
+ /* Variable MTRRs */
+ .word 0x200, 0x201, 0x202, 0x203
+ .word 0x204, 0x205, 0x206, 0x207
+ .word 0x208, 0x209, 0x20A, 0x20B
+ .word 0x20C, 0x20D, 0x20E, 0x20F
+ .word 0x210, 0x211, 0x212, 0x213
+mtrr_table_end:
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
new file mode 100644
index 0000000..60976db
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -0,0 +1,357 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * Some portions from coreboot src/mainboard/google/link/romstage.c
+ * and src/cpu/intel/model_206ax/bootblock.c
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <asm/cpu.h>
+#include <asm/io.h>
+#include <asm/lapic.h>
+#include <asm/msr.h>
+#include <asm/mtrr.h>
+#include <asm/pci.h>
+#include <asm/post.h>
+#include <asm/processor.h>
+#include <asm/arch/model_206ax.h>
+#include <asm/arch/microcode.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/sandybridge.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void enable_port80_on_lpc(struct pci_controller *hose, pci_dev_t dev)
+{
+ /* Enable port 80 POST on LPC */
+ pci_hose_write_config_dword(hose, dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
+ clrbits_le32(RCB_REG(GCS), 4);
+}
+
+/*
+ * Enable Prefetching and Caching.
+ */
+static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev)
+{
+ u8 reg8;
+
+ pci_hose_read_config_byte(hose, dev, 0xdc, ®8);
+ reg8 &= ~(3 << 2);
+ reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+ pci_hose_write_config_byte(hose, dev, 0xdc, reg8);
+}
+
+static void set_var_mtrr(
+ unsigned reg, unsigned base, unsigned size, unsigned type)
+
+{
+ /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
+ /* FIXME: It only support 4G less range */
+ wrmsr(MTRRphysBase_MSR(reg), base | type, 0);
+ wrmsr(MTRRphysMask_MSR(reg), ~(size - 1) | MTRRphysMaskValid,
+ (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1);
+}
+
+static void enable_rom_caching(void)
+{
+ disable_caches();
+ set_var_mtrr(1, 0xffc00000, 4 << 20, MTRR_TYPE_WRPROT);
+ enable_caches();
+
+ /* Enable Variable MTRRs */
+ wrmsr(MTRRdefType_MSR, 0x800, 0);
+}
+
+static int set_flex_ratio_to_tdp_nominal(void)
+{
+ msr_t flex_ratio, msr;
+ u8 nominal_ratio;
+
+ /* Minimum CPU revision for configurable TDP support */
+ if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
+ return -EINVAL;
+
+ /* Check for Flex Ratio support */
+ flex_ratio = msr_read(MSR_FLEX_RATIO);
+ if (!(flex_ratio.lo & FLEX_RATIO_EN))
+ return -EINVAL;
+
+ /* Check for >0 configurable TDPs */
+ msr = msr_read(MSR_PLATFORM_INFO);
+ if (((msr.hi >> 1) & 3) == 0)
+ return -EINVAL;
+
+ /* Use nominal TDP ratio for flex ratio */
+ msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+ nominal_ratio = msr.lo & 0xff;
+
+ /* See if flex ratio is already set to nominal TDP ratio */
+ if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
+ return 0;
+
+ /* Set flex ratio to nominal TDP ratio */
+ flex_ratio.lo &= ~0xff00;
+ flex_ratio.lo |= nominal_ratio << 8;
+ flex_ratio.lo |= FLEX_RATIO_LOCK;
+ msr_write(MSR_FLEX_RATIO, flex_ratio);
+
+ /* Set flex ratio in soft reset data register bits 11:6 */
+ clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6,
+ (nominal_ratio & 0x3f) << 6);
+
+ /* Set soft reset control to use register value */
+ setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
+
+ /* Issue warm reset, will be "CPU only" due to soft reset data */
+ outb(0x0, PORT_RESET);
+ outb(0x6, PORT_RESET);
+ cpu_hlt();
+
+ /* Not reached */
+ return -EINVAL;
+}
+
+static void set_spi_speed(void)
+{
+ u32 fdod;
+
+ /* Observe SPI Descriptor Component Section 0 */
+ writel(0x1000, RCB_REG(SPI_DESC_COMP0));
+
+ /* Extract the1 Write/Erase SPI Frequency from descriptor */
+ fdod = readl(RCB_REG(SPI_FREQ_WR_ERA));
+ fdod >>= 24;
+ fdod &= 7;
+
+ /* Set Software Sequence frequency to match */
+ clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);
+}
+
+int arch_cpu_init(void)
+{
+ const void *blob = gd->fdt_blob;
+ struct pci_controller *hose;
+ int node;
+ int ret;
+
+ post_code(POST_CPU_INIT);
+ timer_set_base(rdtsc());
+
+ ret = x86_cpu_init_f();
+ if (ret)
+ return ret;
+
+ ret = pci_early_init_hose(&hose);
+ if (ret)
+ return ret;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
+ if (node < 0)
+ return -ENOENT;
+ ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV);
+ if (ret)
+ return ret;
+
+ enable_spi_prefetch(hose, PCH_LPC_DEV);
+
+ /* This is already done in start.S, but let's do it in C */
+ enable_port80_on_lpc(hose, PCH_LPC_DEV);
+
+ /* already done in car.S */
+ if (false)
+ enable_rom_caching();
+
+ set_spi_speed();
+
+ /*
+ * We should do as little as possible before the serial console is
+ * up. Perhaps this should move to later. Our next lot of init
+ * happens in print_cpuinfo() when we have a console
+ */
+ ret = set_flex_ratio_to_tdp_nominal();
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int enable_smbus(void)
+{
+ pci_dev_t dev;
+ uint16_t value;
+
+ /* Set the SMBus device statically. */
+ dev = PCI_BDF(0x0, 0x1f, 0x3);
+
+ /* Check to make sure we've got the right device. */
+ value = pci_read_config16(dev, 0x0);
+ if (value != 0x8086) {
+ printf("SMBus controller not found\n");
+ return -ENOSYS;
+ }
+
+ /* Set SMBus I/O base. */
+ pci_write_config32(dev, SMB_BASE,
+ SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+
+ /* Set SMBus enable. */
+ pci_write_config8(dev, HOSTC, HST_EN);
+
+ /* Set SMBus I/O space enable. */
+ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
+
+ /* Disable interrupt generation. */
+ outb(0, SMBUS_IO_BASE + SMBHSTCTL);
+
+ /* Clear any lingering errors, so transactions can run. */
+ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+ debug("SMBus controller enabled\n");
+
+ return 0;
+}
+
+#define PCH_EHCI0_TEMP_BAR0 0xe8000000
+#define PCH_EHCI1_TEMP_BAR0 0xe8000400
+#define PCH_XHCI_TEMP_BAR0 0xe8001000
+
+/*
+ * Setup USB controller MMIO BAR to prevent the reference code from
+ * resetting the controller.
+ *
+ * The BAR will be re-assigned during device enumeration so these are only
+ * temporary.
+ *
+ * This is used to speed up the resume path.
+ */
+static void enable_usb_bar(void)
+{
+ pci_dev_t usb0 = PCH_EHCI1_DEV;
+ pci_dev_t usb1 = PCH_EHCI2_DEV;
+ pci_dev_t usb3 = PCH_XHCI_DEV;
+ u32 cmd;
+
+ /* USB Controller 1 */
+ pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
+ PCH_EHCI0_TEMP_BAR0);
+ cmd = pci_read_config32(usb0, PCI_COMMAND);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config32(usb0, PCI_COMMAND, cmd);
+
+ /* USB Controller 1 */
+ pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
+ PCH_EHCI1_TEMP_BAR0);
+ cmd = pci_read_config32(usb1, PCI_COMMAND);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config32(usb1, PCI_COMMAND, cmd);
+
+ /* USB3 Controller */
+ pci_write_config32(usb3, PCI_BASE_ADDRESS_0,
+ PCH_XHCI_TEMP_BAR0);
+ cmd = pci_read_config32(usb3, PCI_COMMAND);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config32(usb3, PCI_COMMAND, cmd);
+}
+
+static int report_bist_failure(void)
+{
+ if (gd->arch.bist != 0) {
+ printf("BIST failed: %08x\n", gd->arch.bist);
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
+ char processor_name[CPU_MAX_NAME_LEN];
+ const char *name;
+ uint32_t pm1_cnt;
+ uint16_t pm1_sts;
+ int ret;
+
+ /* Halt if there was a built in self test failure */
+ ret = report_bist_failure();
+ if (ret)
+ return ret;
+
+ enable_lapic();
+
+ ret = microcode_update_intel();
+ if (ret && ret != -ENOENT && ret != -EEXIST)
+ return ret;
+
+ /* Enable upper 128bytes of CMOS */
+ writel(1 << 2, RCB_REG(RC));
+
+ /* TODO: cmos_post_init() */
+ if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) {
+ debug("soft reset detected\n");
+ boot_mode = PEI_BOOT_SOFT_RESET;
+
+ /* System is not happy after keyboard reset... */
+ debug("Issuing CF9 warm reset\n");
+ outb(0x6, 0xcf9);
+ cpu_hlt();
+ }
+
+ /* Early chipset init required before RAM init can work */
+ sandybridge_early_init(SANDYBRIDGE_MOBILE);
+
+ /* Check PM1_STS[15] to see if we are waking from Sx */
+ pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+
+ /* Read PM1_CNT[12:10] to determine which Sx state */
+ pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
+
+ if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+ debug("Resume from S3 detected.\n");
+ boot_mode = PEI_BOOT_RESUME;
+ /* Clear SLP_TYPE. This will break stage2 but
+ * we care for that when we get there.
+ */
+ outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
+#else
+ debug("Resume from S3 detected, but disabled.\n");
+#endif
+ } else {
+ /*
+ * TODO: An indication of life might be possible here (e.g.
+ * keyboard light)
+ */
+ }
+ post_code(POST_EARLY_INIT);
+
+ /* Enable SPD ROMs and DDR-III DRAM */
+ ret = enable_smbus();
+ if (ret)
+ return ret;
+
+ /* Prepare USB controller early in S3 resume */
+ if (boot_mode == PEI_BOOT_RESUME)
+ enable_usb_bar();
+
+ gd->arch.pei_boot_mode = boot_mode;
+
+ /* TODO: Move this to the board or driver */
+ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
+ pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+
+ /* Print processor name */
+ name = cpu_get_name(processor_name);
+ printf("CPU: %s\n", name);
+
+ post_code(POST_CPU_INFO);
+
+ return 0;
+}
diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c
new file mode 100644
index 0000000..eb8f613
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/early_init.c
@@ -0,0 +1,145 @@
+/*
+ * From Coreboot
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 Google Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/sandybridge.h>
+
+static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev)
+{
+ /* Setting up Southbridge. In the northbridge code. */
+ debug("Setting up static southbridge registers\n");
+ pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
+
+ pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1);
+ pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */
+
+ debug("Disabling watchdog reboot\n");
+ setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */
+ outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
+
+ /* Set up all hardcoded northbridge BARs */
+ debug("Setting up static registers\n");
+ pci_write_config32(pch_dev, EPBAR, DEFAULT_EPBAR | 1);
+ pci_write_config32(pch_dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
+ pci_write_config32(pch_dev, MCHBAR, DEFAULT_MCHBAR | 1);
+ pci_write_config32(pch_dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32);
+ /* 64MB - busses 0-63 */
+ pci_write_config32(pch_dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
+ pci_write_config32(pch_dev, PCIEXBAR + 4,
+ (0LL + DEFAULT_PCIEXBAR) >> 32);
+ pci_write_config32(pch_dev, DMIBAR, DEFAULT_DMIBAR | 1);
+ pci_write_config32(pch_dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);
+
+ /* Set C0000-FFFFF to access RAM on both reads and writes */
+ pci_write_config8(pch_dev, PAM0, 0x30);
+ pci_write_config8(pch_dev, PAM1, 0x33);
+ pci_write_config8(pch_dev, PAM2, 0x33);
+ pci_write_config8(pch_dev, PAM3, 0x33);
+ pci_write_config8(pch_dev, PAM4, 0x33);
+ pci_write_config8(pch_dev, PAM5, 0x33);
+ pci_write_config8(pch_dev, PAM6, 0x33);
+}
+
+static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
+{
+ u32 reg32;
+ u16 reg16;
+ u8 reg8;
+
+ reg16 = pci_read_config16(video_dev, PCI_DEVICE_ID);
+ switch (reg16) {
+ case 0x0102: /* GT1 Desktop */
+ case 0x0106: /* GT1 Mobile */
+ case 0x010a: /* GT1 Server */
+ case 0x0112: /* GT2 Desktop */
+ case 0x0116: /* GT2 Mobile */
+ case 0x0122: /* GT2 Desktop >=1.3GHz */
+ case 0x0126: /* GT2 Mobile >=1.3GHz */
+ case 0x0156: /* IvyBridge */
+ case 0x0166: /* IvyBridge */
+ break;
+ default:
+ debug("Graphics not supported by this CPU/chipset\n");
+ return;
+ }
+
+ debug("Initialising Graphics\n");
+
+ /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
+ reg16 = pci_read_config16(pch_dev, GGC);
+ reg16 &= ~0x00f8;
+ reg16 |= 1 << 3;
+ /* Program GTT memory by setting GGC[9:8] = 2MB */
+ reg16 &= ~0x0300;
+ reg16 |= 2 << 8;
+ /* Enable VGA decode */
+ reg16 &= ~0x0002;
+ pci_write_config16(pch_dev, GGC, reg16);
+
+ /* Enable 256MB aperture */
+ reg8 = pci_read_config8(video_dev, MSAC);
+ reg8 &= ~0x06;
+ reg8 |= 0x02;
+ pci_write_config8(video_dev, MSAC, reg8);
+
+ /* Erratum workarounds */
+ reg32 = readl(MCHBAR_REG(0x5f00));
+ reg32 |= (1 << 9) | (1 << 10);
+ writel(reg32, MCHBAR_REG(0x5f00));
+
+ /* Enable SA Clock Gating */
+ reg32 = readl(MCHBAR_REG(0x5f00));
+ writel(reg32 | 1, MCHBAR_REG(0x5f00));
+
+ /* GPU RC6 workaround for sighting 366252 */
+ reg32 = readl(MCHBAR_REG(0x5d14));
+ reg32 |= (1 << 31);
+ writel(reg32, MCHBAR_REG(0x5d14));
+
+ /* VLW */
+ reg32 = readl(MCHBAR_REG(0x6120));
+ reg32 &= ~(1 << 0);
+ writel(reg32, MCHBAR_REG(0x6120));
+
+ reg32 = readl(MCHBAR_REG(0x5418));
+ reg32 |= (1 << 4) | (1 << 5);
+ writel(reg32, MCHBAR_REG(0x5418));
+}
+
+void sandybridge_early_init(int chipset_type)
+{
+ pci_dev_t pch_dev = PCH_DEV;
+ pci_dev_t video_dev = PCH_VIDEO_DEV;
+ pci_dev_t lpc_dev = PCH_LPC_DEV;
+ u32 capid0_a;
+ u8 reg8;
+
+ /* Device ID Override Enable should be done very early */
+ capid0_a = pci_read_config32(pch_dev, 0xe4);
+ if (capid0_a & (1 << 10)) {
+ reg8 = pci_read_config8(pch_dev, 0xf3);
+ reg8 &= ~7; /* Clear 2:0 */
+
+ if (chipset_type == SANDYBRIDGE_MOBILE)
+ reg8 |= 1; /* Set bit 0 */
+
+ pci_write_config8(pch_dev, 0xf3, reg8);
+ }
+
+ /* Setup all BARs required for early PCIe and raminit */
+ sandybridge_setup_bars(pch_dev, lpc_dev);
+
+ /* Device Enable */
+ pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
+
+ sandybridge_setup_graphics(pch_dev, video_dev);
+}
diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c
new file mode 100644
index 0000000..b24dea1
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/early_me.c
@@ -0,0 +1,191 @@
+/*
+ * From Coreboot src/southbridge/intel/bd82x6x/early_me.c
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/pci.h>
+#include <asm/processor.h>
+#include <asm/arch/me.h>
+#include <asm/arch/pch.h>
+#include <asm/io.h>
+
+static const char *const me_ack_values[] = {
+ [ME_HFS_ACK_NO_DID] = "No DID Ack received",
+ [ME_HFS_ACK_RESET] = "Non-power cycle reset",
+ [ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset",
+ [ME_HFS_ACK_S3] = "Go to S3",
+ [ME_HFS_ACK_S4] = "Go to S4",
+ [ME_HFS_ACK_S5] = "Go to S5",
+ [ME_HFS_ACK_GBL_RESET] = "Global Reset",
+ [ME_HFS_ACK_CONTINUE] = "Continue to boot"
+};
+
+static inline void pci_read_dword_ptr(void *ptr, int offset)
+{
+ u32 dword;
+
+ dword = pci_read_config32(PCH_ME_DEV, offset);
+ memcpy(ptr, &dword, sizeof(dword));
+}
+
+static inline void pci_write_dword_ptr(void *ptr, int offset)
+{
+ u32 dword = 0;
+ memcpy(&dword, ptr, sizeof(dword));
+ pci_write_config32(PCH_ME_DEV, offset, dword);
+}
+
+void intel_early_me_status(void)
+{
+ struct me_hfs hfs;
+ struct me_gmes gmes;
+
+ pci_read_dword_ptr(&hfs, PCI_ME_HFS);
+ pci_read_dword_ptr(&gmes, PCI_ME_GMES);
+
+ intel_me_status(&hfs, &gmes);
+}
+
+int intel_early_me_init(void)
+{
+ int count;
+ struct me_uma uma;
+ struct me_hfs hfs;
+
+ debug("Intel ME early init\n");
+
+ /* Wait for ME UMA SIZE VALID bit to be set */
+ for (count = ME_RETRY; count > 0; --count) {
+ pci_read_dword_ptr(&uma, PCI_ME_UMA);
+ if (uma.valid)
+ break;
+ udelay(ME_DELAY);
+ }
+ if (!count) {
+ printf("ERROR: ME is not ready!\n");
+ return -EBUSY;
+ }
+
+ /* Check for valid firmware */
+ pci_read_dword_ptr(&hfs, PCI_ME_HFS);
+ if (hfs.fpt_bad) {
+ printf("WARNING: ME has bad firmware\n");
+ return -EBADF;
+ }
+
+ debug("Intel ME firmware is ready\n");
+
+ return 0;
+}
+
+int intel_early_me_uma_size(void)
+{
+ struct me_uma uma;
+
+ pci_read_dword_ptr(&uma, PCI_ME_UMA);
+ if (uma.valid) {
+ debug("ME: Requested %uMB UMA\n", uma.size);
+ return uma.size;
+ }
+
+ debug("ME: Invalid UMA size\n");
+ return -EINVAL;
+}
+
+static inline void set_global_reset(int enable)
+{
+ u32 etr3;
+
+ etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
+
+ /* Clear CF9 Without Resume Well Reset Enable */
+ etr3 &= ~ETR3_CWORWRE;
+
+ /* CF9GR indicates a Global Reset */
+ if (enable)
+ etr3 |= ETR3_CF9GR;
+ else
+ etr3 &= ~ETR3_CF9GR;
+
+ pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
+}
+
+int intel_early_me_init_done(u8 status)
+{
+ u8 reset;
+ int count;
+ u32 mebase_l, mebase_h;
+ struct me_hfs hfs;
+ struct me_did did = {
+ .init_done = ME_INIT_DONE,
+ .status = status
+ };
+
+ /* MEBASE from MESEG_BASE[35:20] */
+ mebase_l = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L);
+ mebase_h = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H);
+ mebase_h &= 0xf;
+ did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
+
+ /* Send message to ME */
+ debug("ME: Sending Init Done with status: %d, UMA base: 0x%04x\n",
+ status, did.uma_base);
+
+ pci_write_dword_ptr(&did, PCI_ME_H_GS);
+
+ /* Must wait for ME acknowledgement */
+ for (count = ME_RETRY; count > 0; --count) {
+ pci_read_dword_ptr(&hfs, PCI_ME_HFS);
+ if (hfs.bios_msg_ack)
+ break;
+ udelay(ME_DELAY);
+ }
+ if (!count) {
+ printf("ERROR: ME failed to respond\n");
+ return -1;
+ }
+
+ /* Return the requested BIOS action */
+ debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]);
+
+ /* Check status after acknowledgement */
+ intel_early_me_status();
+
+ reset = 0;
+ switch (hfs.ack_data) {
+ case ME_HFS_ACK_CONTINUE:
+ /* Continue to boot */
+ return 0;
+ case ME_HFS_ACK_RESET:
+ /* Non-power cycle reset */
+ set_global_reset(0);
+ reset = 0x06;
+ break;
+ case ME_HFS_ACK_PWR_CYCLE:
+ /* Power cycle reset */
+ set_global_reset(0);
+ reset = 0x0e;
+ break;
+ case ME_HFS_ACK_GBL_RESET:
+ /* Global reset */
+ set_global_reset(1);
+ reset = 0x0e;
+ break;
+ case ME_HFS_ACK_S3:
+ case ME_HFS_ACK_S4:
+ case ME_HFS_ACK_S5:
+ break;
+ }
+
+ /* Perform the requested reset */
+ if (reset) {
+ outb(reset, 0xcf9);
+ cpu_hlt();
+ }
+ return -1;
+}
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
new file mode 100644
index 0000000..621ef2c
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -0,0 +1,48 @@
+/*
+ * From coreboot southbridge/intel/bd82x6x/lpc.c
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <pci.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+
+int lpc_early_init(const void *blob, int node, pci_dev_t dev)
+{
+ struct reg_info {
+ u32 base;
+ u32 size;
+ } values[4], *ptr;
+ int count;
+ int i;
+
+ count = fdtdec_get_int_array_count(blob, node, "gen-dec",
+ (u32 *)values, sizeof(values) / sizeof(u32));
+ if (count < 0)
+ return -EINVAL;
+
+ /* Set COM1/COM2 decode range */
+ pci_write_config16(dev, LPC_IO_DEC, 0x0010);
+
+ /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
+ pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
+ GAMEL_LPC_EN | COMA_LPC_EN);
+
+ /* Write all registers but use 0 if we run out of data */
+ count = count * sizeof(u32) / sizeof(values[0]);
+ for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) {
+ u32 reg = 0;
+
+ if (i < count)
+ reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
+ pci_write_config32(dev, LPC_GENX_DEC(i), reg);
+ }
+
+ return 0;
+}
diff --git a/arch/x86/cpu/ivybridge/me_status.c b/arch/x86/cpu/ivybridge/me_status.c
new file mode 100644
index 0000000..15cf69f
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/me_status.c
@@ -0,0 +1,195 @@
+/*
+ * From Coreboot src/southbridge/intel/bd82x6x/me_status.c
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/arch/me.h>
+
+/* HFS1[3:0] Current Working State Values */
+static const char *const me_cws_values[] = {
+ [ME_HFS_CWS_RESET] = "Reset",
+ [ME_HFS_CWS_INIT] = "Initializing",
+ [ME_HFS_CWS_REC] = "Recovery",
+ [ME_HFS_CWS_NORMAL] = "Normal",
+ [ME_HFS_CWS_WAIT] = "Platform Disable Wait",
+ [ME_HFS_CWS_TRANS] = "OP State Transition",
+ [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In"
+};
+
+/* HFS1[8:6] Current Operation State Values */
+static const char *const me_opstate_values[] = {
+ [ME_HFS_STATE_PREBOOT] = "Preboot",
+ [ME_HFS_STATE_M0_UMA] = "M0 with UMA",
+ [ME_HFS_STATE_M3] = "M3 without UMA",
+ [ME_HFS_STATE_M0] = "M0 without UMA",
+ [ME_HFS_STATE_BRINGUP] = "Bring up",
+ [ME_HFS_STATE_ERROR] = "M0 without UMA but with error"
+};
+
+/* HFS[19:16] Current Operation Mode Values */
+static const char *const me_opmode_values[] = {
+ [ME_HFS_MODE_NORMAL] = "Normal",
+ [ME_HFS_MODE_DEBUG] = "Debug",
+ [ME_HFS_MODE_DIS] = "Soft Temporary Disable",
+ [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper",
+ [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message"
+};
+
+/* HFS[15:12] Error Code Values */
+static const char *const me_error_values[] = {
+ [ME_HFS_ERROR_NONE] = "No Error",
+ [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure",
+ [ME_HFS_ERROR_IMAGE] = "Image Failure",
+ [ME_HFS_ERROR_DEBUG] = "Debug Failure"
+};
+
+/* GMES[31:28] ME Progress Code */
+static const char *const me_progress_values[] = {
+ [ME_GMES_PHASE_ROM] = "ROM Phase",
+ [ME_GMES_PHASE_BUP] = "BUP Phase",
+ [ME_GMES_PHASE_UKERNEL] = "uKernel Phase",
+ [ME_GMES_PHASE_POLICY] = "Policy Module",
+ [ME_GMES_PHASE_MODULE] = "Module Loading",
+ [ME_GMES_PHASE_UNKNOWN] = "Unknown",
+ [ME_GMES_PHASE_HOST] = "Host Communication"
+};
+
+/* GMES[27:24] Power Management Event */
+static const char *const me_pmevent_values[] = {
+ [0x00] = "Clean Moff->Mx wake",
+ [0x01] = "Moff->Mx wake after an error",
+ [0x02] = "Clean global reset",
+ [0x03] = "Global reset after an error",
+ [0x04] = "Clean Intel ME reset",
+ [0x05] = "Intel ME reset due to exception",
+ [0x06] = "Pseudo-global reset",
+ [0x07] = "S0/M0->Sx/M3",
+ [0x08] = "Sx/M3->S0/M0",
+ [0x09] = "Non-power cycle reset",
+ [0x0a] = "Power cycle reset through M3",
+ [0x0b] = "Power cycle reset through Moff",
+ [0x0c] = "Sx/Mx->Sx/Moff"
+};
+
+/* Progress Code 0 states */
+static const char *const me_progress_rom_values[] = {
+ [0x00] = "BEGIN",
+ [0x06] = "DISABLE"
+};
+
+/* Progress Code 1 states */
+static const char *const me_progress_bup_values[] = {
+ [0x00] = "Initialization starts",
+ [0x01] = "Disable the host wake event",
+ [0x04] = "Flow determination start process",
+ [0x08] = "Error reading/matching the VSCC table in the descriptor",
+ [0x0a] = "Check to see if straps say ME DISABLED",
+ [0x0b] = "Timeout waiting for PWROK",
+ [0x0d] = "Possibly handle BUP manufacturing override strap",
+ [0x11] = "Bringup in M3",
+ [0x12] = "Bringup in M0",
+ [0x13] = "Flow detection error",
+ [0x15] = "M3 clock switching error",
+ [0x18] = "M3 kernel load",
+ [0x1c] = "T34 missing - cannot program ICC",
+ [0x1f] = "Waiting for DID BIOS message",
+ [0x20] = "Waiting for DID BIOS message failure",
+ [0x21] = "DID reported an error",
+ [0x22] = "Enabling UMA",
+ [0x23] = "Enabling UMA error",
+ [0x24] = "Sending DID Ack to BIOS",
+ [0x25] = "Sending DID Ack to BIOS error",
+ [0x26] = "Switching clocks in M0",
+ [0x27] = "Switching clocks in M0 error",
+ [0x28] = "ME in temp disable",
+ [0x32] = "M0 kernel load",
+};
+
+/* Progress Code 3 states */
+static const char *const me_progress_policy_values[] = {
+ [0x00] = "Entery into Policy Module",
+ [0x03] = "Received S3 entry",
+ [0x04] = "Received S4 entry",
+ [0x05] = "Received S5 entry",
+ [0x06] = "Received UPD entry",
+ [0x07] = "Received PCR entry",
+ [0x08] = "Received NPCR entry",
+ [0x09] = "Received host wake",
+ [0x0a] = "Received AC<>DC switch",
+ [0x0b] = "Received DRAM Init Done",
+ [0x0c] = "VSCC Data not found for flash device",
+ [0x0d] = "VSCC Table is not valid",
+ [0x0e] = "Flash Partition Boundary is outside address space",
+ [0x0f] = "ME cannot access the chipset descriptor region",
+ [0x10] = "Required VSCC values for flash parts do not match",
+};
+
+void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes)
+{
+ /* Check Current States */
+ debug("ME: FW Partition Table : %s\n",
+ hfs->fpt_bad ? "BAD" : "OK");
+ debug("ME: Bringup Loader Failure : %s\n",
+ hfs->ft_bup_ld_flr ? "YES" : "NO");
+ debug("ME: Firmware Init Complete : %s\n",
+ hfs->fw_init_complete ? "YES" : "NO");
+ debug("ME: Manufacturing Mode : %s\n",
+ hfs->mfg_mode ? "YES" : "NO");
+ debug("ME: Boot Options Present : %s\n",
+ hfs->boot_options_present ? "YES" : "NO");
+ debug("ME: Update In Progress : %s\n",
+ hfs->update_in_progress ? "YES" : "NO");
+ debug("ME: Current Working State : %s\n",
+ me_cws_values[hfs->working_state]);
+ debug("ME: Current Operation State : %s\n",
+ me_opstate_values[hfs->operation_state]);
+ debug("ME: Current Operation Mode : %s\n",
+ me_opmode_values[hfs->operation_mode]);
+ debug("ME: Error Code : %s\n",
+ me_error_values[hfs->error_code]);
+ debug("ME: Progress Phase : %s\n",
+ me_progress_values[gmes->progress_code]);
+ debug("ME: Power Management Event : %s\n",
+ me_pmevent_values[gmes->current_pmevent]);
+
+ debug("ME: Progress Phase State : ");
+ switch (gmes->progress_code) {
+ case ME_GMES_PHASE_ROM: /* ROM Phase */
+ debug("%s", me_progress_rom_values[gmes->current_state]);
+ break;
+
+ case ME_GMES_PHASE_BUP: /* Bringup Phase */
+ if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values) &&
+ me_progress_bup_values[gmes->current_state])
+ debug("%s",
+ me_progress_bup_values[gmes->current_state]);
+ else
+ debug("0x%02x", gmes->current_state);
+ break;
+
+ case ME_GMES_PHASE_POLICY: /* Policy Module Phase */
+ if (gmes->current_state <
+ ARRAY_SIZE(me_progress_policy_values) &&
+ me_progress_policy_values[gmes->current_state])
+ debug("%s",
+ me_progress_policy_values[gmes->current_state]);
+ else
+ debug("0x%02x", gmes->current_state);
+ break;
+
+ case ME_GMES_PHASE_HOST: /* Host Communication Phase */
+ if (!gmes->current_state)
+ debug("Host communication established");
+ else
+ debug("0x%02x", gmes->current_state);
+ break;
+
+ default:
+ debug("Unknown 0x%02x", gmes->current_state);
+ }
+ debug("\n");
+}
diff --git a/arch/x86/cpu/ivybridge/microcode_intel.c b/arch/x86/cpu/ivybridge/microcode_intel.c
new file mode 100644
index 0000000..8c11a63
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/microcode_intel.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ * Copyright (C) 2000 Ronald G. Minnich
+ *
+ * Microcode update for Intel PIII and later CPUs
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <asm/cpu.h>
+#include <asm/msr.h>
+#include <asm/processor.h>
+
+/**
+ * struct microcode_update - standard microcode header from Intel
+ *
+ * We read this information out of the device tree and use it to determine
+ * whether the update is applicable or not. We also use the same structure
+ * to read information from the CPU.
+ */
+struct microcode_update {
+ uint header_version;
+ uint update_revision;
+ uint date_code;
+ uint processor_signature;
+ uint checksum;
+ uint loader_revision;
+ uint processor_flags;
+ const void *data;
+ int size;
+};
+
+static int microcode_decode_node(const void *blob, int node,
+ struct microcode_update *update)
+{
+ update->data = fdt_getprop(blob, node, "data", &update->size);
+ if (!update->data)
+ return -EINVAL;
+
+ update->header_version = fdtdec_get_int(blob, node,
+ "intel,header-version", 0);
+ update->update_revision = fdtdec_get_int(blob, node,
+ "intel,update-revision", 0);
+ update->date_code = fdtdec_get_int(blob, node,
+ "intel,date-code", 0);
+ update->processor_signature = fdtdec_get_int(blob, node,
+ "intel.processor-signature", 0);
+ update->checksum = fdtdec_get_int(blob, node, "intel,checksum", 0);
+ update->loader_revision = fdtdec_get_int(blob, node,
+ "loader-revision", 0);
+ update->processor_flags = fdtdec_get_int(blob, node,
+ "processor-flags", 0);
+
+ return 0;
+}
+
+static uint32_t microcode_read_rev(void)
+{
+ /*
+ * Some Intel CPUs can be very finicky about the CPUID sequence used.
+ * So this is implemented in assembly so that it works reliably.
+ */
+ uint32_t low, high;
+
+ asm volatile (
+ "xorl %%eax, %%eax\n"
+ "xorl %%edx, %%edx\n"
+ "movl $0x8b, %%ecx\n"
+ "wrmsr\n"
+ "movl $0x01, %%eax\n"
+ "cpuid\n"
+ "movl $0x8b, %%ecx\n"
+ "rdmsr\n"
+ : /* outputs */
+ "=a" (low), "=d" (high)
+ : /* inputs */
+ : /* clobbers */
+ "ebx", "ecx"
+ );
+
+ return high;
+}
+
+static void microcode_read_cpu(struct microcode_update *cpu)
+{
+ /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */
+ unsigned int x86_model, x86_family;
+ struct cpuid_result result;
+ uint32_t low, high;
+
+ wrmsr(0x8b, 0, 0);
+ result = cpuid(1);
+ rdmsr(0x8b, low, cpu->update_revision);
+ x86_model = (result.eax >> 4) & 0x0f;
+ x86_family = (result.eax >> 8) & 0x0f;
+ cpu->processor_signature = result.eax;
+
+ cpu->processor_flags = 0;
+ if ((x86_model >= 5) || (x86_family > 6)) {
+ rdmsr(0x17, low, high);
+ cpu->processor_flags = 1 << ((high >> 18) & 7);
+ }
+ debug("microcode: sig=%#x pf=%#x revision=%#x\n",
+ cpu->processor_signature, cpu->processor_flags,
+ cpu->update_revision);
+}
+
+/* Get a microcode update from the device tree and apply it */
+int microcode_update_intel(void)
+{
+ struct microcode_update cpu, update;
+ const void *blob = gd->fdt_blob;
+ int count;
+ int node;
+ int ret;
+
+ microcode_read_cpu(&cpu);
+ node = 0;
+ count = 0;
+ do {
+ node = fdtdec_next_compatible(blob, node,
+ COMPAT_INTEL_MICROCODE);
+ if (node < 0) {
+ debug("%s: Found %d updates\n", __func__, count);
+ return count ? 0 : -ENOENT;
+ }
+
+ ret = microcode_decode_node(blob, node, &update);
+ if (ret) {
+ debug("%s: Unable to decode update: %d\n", __func__,
+ ret);
+ return ret;
+ }
+ if (update.processor_signature == cpu.processor_signature &&
+ (update.processor_flags & cpu.processor_flags)) {
+ debug("%s: Update already exists\n", __func__);
+ return -EEXIST;
+ }
+
+ wrmsr(0x79, (ulong)update.data, 0);
+ debug("microcode: updated to revision 0x%x date=%04x-%02x-%02x\n",
+ microcode_read_rev(), update.date_code & 0xffff,
+ (update.date_code >> 24) & 0xff,
+ (update.date_code >> 16) & 0xff);
+ count++;
+ } while (1);
+}
diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c
new file mode 100644
index 0000000..c1ae658
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/pci.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008,2009
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/pci.h>
+
+static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
+ struct pci_config_table *table)
+{
+ u8 secondary;
+
+ hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
+ if (secondary != 0)
+ pci_hose_scan_bus(hose, secondary);
+}
+
+static struct pci_config_table pci_ivybridge_config_table[] = {
+ /* vendor, device, class, bus, dev, func */
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
+ {}
+};
+
+void board_pci_setup_hose(struct pci_controller *hose)
+{
+ hose->config_table = pci_ivybridge_config_table;
+ hose->first_busno = 0;
+ hose->last_busno = 0;
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 0,
+ CONFIG_PCI_MEM_BUS,
+ CONFIG_PCI_MEM_PHYS,
+ CONFIG_PCI_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* PCI IO space */
+ pci_set_region(hose->regions + 1,
+ CONFIG_PCI_IO_BUS,
+ CONFIG_PCI_IO_PHYS,
+ CONFIG_PCI_IO_SIZE,
+ PCI_REGION_IO);
+
+ pci_set_region(hose->regions + 2,
+ CONFIG_PCI_PREF_BUS,
+ CONFIG_PCI_PREF_PHYS,
+ CONFIG_PCI_PREF_SIZE,
+ PCI_REGION_PREFETCH);
+
+ hose->region_count = 3;
+}
diff --git a/arch/x86/cpu/ivybridge/report_platform.c b/arch/x86/cpu/ivybridge/report_platform.c
new file mode 100644
index 0000000..69e31b3
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/report_platform.c
@@ -0,0 +1,89 @@
+/*
+ * From Coreboot src/northbridge/intel/sandybridge/report_platform.c
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/cpu.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+
+static void report_cpu_info(void)
+{
+ char cpu_string[CPU_MAX_NAME_LEN], *cpu_name;
+ const char *mode[] = {"NOT ", ""};
+ struct cpuid_result cpuidr;
+ int vt, txt, aes;
+ u32 index;
+
+ index = 0x80000000;
+ cpuidr = cpuid(index);
+ if (cpuidr.eax < 0x80000004) {
+ strcpy(cpu_string, "Platform info not available");
+ cpu_name = cpu_string;
+ } else {
+ cpu_name = cpu_get_name(cpu_string);
+ }
+
+ cpuidr = cpuid(1);
+ debug("CPU id(%x): %s\n", cpuidr.eax, cpu_name);
+ aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
+ txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
+ vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
+ debug("AES %ssupported, TXT %ssupported, VT %ssupported\n",
+ mode[aes], mode[txt], mode[vt]);
+}
+
+/* The PCI id name match comes from Intel document 472178 */
+static struct {
+ u16 dev_id;
+ const char *dev_name;
+} pch_table[] = {
+ {0x1E41, "Desktop Sample"},
+ {0x1E42, "Mobile Sample"},
+ {0x1E43, "SFF Sample"},
+ {0x1E44, "Z77"},
+ {0x1E45, "H71"},
+ {0x1E46, "Z75"},
+ {0x1E47, "Q77"},
+ {0x1E48, "Q75"},
+ {0x1E49, "B75"},
+ {0x1E4A, "H77"},
+ {0x1E53, "C216"},
+ {0x1E55, "QM77"},
+ {0x1E56, "QS77"},
+ {0x1E58, "UM77"},
+ {0x1E57, "HM77"},
+ {0x1E59, "HM76"},
+ {0x1E5D, "HM75"},
+ {0x1E5E, "HM70"},
+ {0x1E5F, "NM70"},
+};
+
+static void report_pch_info(void)
+{
+ const char *pch_type = "Unknown";
+ int i;
+ u16 dev_id;
+ uint8_t rev_id;
+
+ dev_id = pci_read_config16(PCH_LPC_DEV, 2);
+ for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
+ if (pch_table[i].dev_id == dev_id) {
+ pch_type = pch_table[i].dev_name;
+ break;
+ }
+ }
+ rev_id = pci_read_config8(PCH_LPC_DEV, 8);
+ debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id,
+ rev_id);
+}
+
+void report_platform_info(void)
+{
+ report_cpu_info();
+ report_pch_info();
+}
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
new file mode 100644
index 0000000..df2b990
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -0,0 +1,571 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010,2011
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * Portions from Coreboot mainboard/google/link/romstage.c
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/gpio.h>
+#include <asm/global_data.h>
+#include <asm/pci.h>
+#include <asm/arch/me.h>
+#include <asm/arch/pei_data.h>
+#include <asm/arch/pch.h>
+#include <asm/post.h>
+#include <asm/arch/sandybridge.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * This function looks for the highest region of memory lower than 4GB which
+ * has enough space for U-Boot where U-Boot is aligned on a page boundary.
+ * It overrides the default implementation found elsewhere which simply
+ * picks the end of ram, wherever that may be. The location of the stack,
+ * the relocation address, and how far U-Boot is moved by relocation are
+ * set in the global data structure.
+ */
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ struct memory_info *info = &gd->arch.meminfo;
+ uintptr_t dest_addr = 0;
+ struct memory_area *largest = NULL;
+ int i;
+
+ /* Find largest area of memory below 4GB */
+
+ for (i = 0; i < info->num_areas; i++) {
+ struct memory_area *area = &info->area[i];
+
+ if (area->start >= 1ULL << 32)
+ continue;
+ if (!largest || area->size > largest->size)
+ largest = area;
+ }
+
+ /* If no suitable area was found, return an error. */
+ assert(largest);
+ if (!largest || largest->size < (2 << 20))
+ panic("No available memory found for relocation");
+
+ dest_addr = largest->start + largest->size;
+
+ return (ulong)dest_addr;
+}
+
+void dram_init_banksize(void)
+{
+ struct memory_info *info = &gd->arch.meminfo;
+ int num_banks;
+ int i;
+
+ for (i = 0, num_banks = 0; i < info->num_areas; i++) {
+ struct memory_area *area = &info->area[i];
+
+ if (area->start >= 1ULL << 32)
+ continue;
+ gd->bd->bi_dram[num_banks].start = area->start;
+ gd->bd->bi_dram[num_banks].size = area->size;
+ num_banks++;
+ }
+}
+
+static const char *const ecc_decoder[] = {
+ "inactive",
+ "active on IO",
+ "disabled on IO",
+ "active"
+};
+
+/*
+ * Dump in the log memory controller configuration as read from the memory
+ * controller registers.
+ */
+static void report_memory_config(void)
+{
+ u32 addr_decoder_common, addr_decode_ch[2];
+ int i;
+
+ addr_decoder_common = readl(MCHBAR_REG(0x5000));
+ addr_decode_ch[0] = readl(MCHBAR_REG(0x5004));
+ addr_decode_ch[1] = readl(MCHBAR_REG(0x5008));
+
+ debug("memcfg DDR3 clock %d MHz\n",
+ (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100);
+ debug("memcfg channel assignment: A: %d, B % d, C % d\n",
+ addr_decoder_common & 3,
+ (addr_decoder_common >> 2) & 3,
+ (addr_decoder_common >> 4) & 3);
+
+ for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
+ u32 ch_conf = addr_decode_ch[i];
+ debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
+ debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
+ debug(" enhanced interleave mode %s\n",
+ ((ch_conf >> 22) & 1) ? "on" : "off");
+ debug(" rank interleave %s\n",
+ ((ch_conf >> 21) & 1) ? "on" : "off");
+ debug(" DIMMA %d MB width x%d %s rank%s\n",
+ ((ch_conf >> 0) & 0xff) * 256,
+ ((ch_conf >> 19) & 1) ? 16 : 8,
+ ((ch_conf >> 17) & 1) ? "dual" : "single",
+ ((ch_conf >> 16) & 1) ? "" : ", selected");
+ debug(" DIMMB %d MB width x%d %s rank%s\n",
+ ((ch_conf >> 8) & 0xff) * 256,
+ ((ch_conf >> 20) & 1) ? 16 : 8,
+ ((ch_conf >> 18) & 1) ? "dual" : "single",
+ ((ch_conf >> 16) & 1) ? ", selected" : "");
+ }
+}
+
+static void post_system_agent_init(struct pei_data *pei_data)
+{
+ /* If PCIe init is skipped, set the PEG clock gating */
+ if (!pei_data->pcie_init)
+ setbits_le32(MCHBAR_REG(0x7010), 1);
+}
+
+static asmlinkage void console_tx_byte(unsigned char byte)
+{
+#ifdef DEBUG
+ putc(byte);
+#endif
+}
+
+/**
+ * Find the PEI executable in the ROM and execute it.
+ *
+ * @param pei_data: configuration data for UEFI PEI reference code
+ */
+int sdram_initialise(struct pei_data *pei_data)
+{
+ unsigned version;
+ const char *data;
+ uint16_t done;
+ int ret;
+
+ report_platform_info();
+
+ /* Wait for ME to be ready */
+ ret = intel_early_me_init();
+ if (ret)
+ return ret;
+ ret = intel_early_me_uma_size();
+ if (ret < 0)
+ return ret;
+
+ debug("Starting UEFI PEI System Agent\n");
+
+ /* If MRC data is not found we cannot continue S3 resume. */
+ if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
+ debug("Giving up in sdram_initialize: No MRC data\n");
+ outb(0x6, PORT_RESET);
+ cpu_hlt();
+ }
+
+ /* Pass console handler in pei_data */
+ pei_data->tx_byte = console_tx_byte;
+
+ debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data));
+
+ data = (char *)CONFIG_X86_MRC_START;
+ if (data) {
+ int rv;
+ int (*func)(struct pei_data *);
+
+ debug("Calling MRC at %p\n", data);
+ post_code(POST_PRE_MRC);
+ func = (int (*)(struct pei_data *))data;
+ rv = func(pei_data);
+ post_code(POST_MRC);
+ if (rv) {
+ switch (rv) {
+ case -1:
+ printf("PEI version mismatch.\n");
+ break;
+ case -2:
+ printf("Invalid memory frequency.\n");
+ break;
+ default:
+ printf("MRC returned %x.\n", rv);
+ }
+ printf("Nonzero MRC return value.\n");
+ return -EFAULT;
+ }
+ } else {
+ printf("UEFI PEI System Agent not found.\n");
+ return -ENOSYS;
+ }
+
+#if CONFIG_USBDEBUG
+ /* mrc.bin reconfigures USB, so reinit it to have debug */
+ early_usbdebug_init();
+#endif
+
+ version = readl(MCHBAR_REG(0x5034));
+ debug("System Agent Version %d.%d.%d Build %d\n",
+ version >> 24 , (version >> 16) & 0xff,
+ (version >> 8) & 0xff, version & 0xff);
+
+ /*
+ * Send ME init done for SandyBridge here. This is done inside the
+ * SystemAgent binary on IvyBridge
+ */
+ done = pci_read_config32(PCH_DEV, PCI_DEVICE_ID);
+ done &= BASE_REV_MASK;
+ if (BASE_REV_SNB == done)
+ intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
+ else
+ intel_early_me_status();
+
+ post_system_agent_init(pei_data);
+ report_memory_config();
+
+ return 0;
+}
+
+static int copy_spd(struct pei_data *peid)
+{
+ const int gpio_vector[] = {41, 42, 43, 10, -1};
+ int spd_index;
+ const void *blob = gd->fdt_blob;
+ int node, spd_node;
+ int ret, i;
+
+ for (i = 0; ; i++) {
+ if (gpio_vector[i] == -1)
+ break;
+ ret = gpio_requestf(gpio_vector[i], "spd_id%d", i);
+ if (ret) {
+ debug("%s: Could not request gpio %d\n", __func__,
+ gpio_vector[i]);
+ return ret;
+ }
+ }
+ spd_index = gpio_get_values_as_int(gpio_vector);
+ debug("spd index %d\n", spd_index);
+ node = fdtdec_next_compatible(blob, 0, COMPAT_MEMORY_SPD);
+ if (node < 0) {
+ printf("SPD data not found.\n");
+ return -ENOENT;
+ }
+
+ for (spd_node = fdt_first_subnode(blob, node);
+ spd_node > 0;
+ spd_node = fdt_next_subnode(blob, spd_node)) {
+ const char *data;
+ int len;
+
+ if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index)
+ continue;
+ data = fdt_getprop(blob, spd_node, "data", &len);
+ if (len < sizeof(peid->spd_data[0])) {
+ printf("Missing SPD data\n");
+ return -EINVAL;
+ }
+
+ debug("Using SDRAM SPD data for '%s'\n",
+ fdt_get_name(blob, spd_node, NULL));
+ memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
+ break;
+ }
+
+ if (spd_node < 0) {
+ printf("No SPD data found for index %d\n", spd_index);
+ return -ENOENT;
+ }
+
+ return 0;
+}
+
+/**
+ * add_memory_area() - Add a new usable memory area to our list
+ *
+ * Note: @start and @end must not span the first 4GB boundary
+ *
+ * @info: Place to store memory info
+ * @start: Start of this memory area
+ * @end: End of this memory area + 1
+ */
+static int add_memory_area(struct memory_info *info,
+ uint64_t start, uint64_t end)
+{
+ struct memory_area *ptr;
+
+ if (info->num_areas == CONFIG_NR_DRAM_BANKS)
+ return -ENOSPC;
+
+ ptr = &info->area[info->num_areas];
+ ptr->start = start;
+ ptr->size = end - start;
+ info->total_memory += ptr->size;
+ if (ptr->start < (1ULL << 32))
+ info->total_32bit_memory += ptr->size;
+ debug("%d: memory %llx size %llx, total now %llx / %llx\n",
+ info->num_areas, ptr->start, ptr->size,
+ info->total_32bit_memory, info->total_memory);
+ info->num_areas++;
+
+ return 0;
+}
+
+/**
+ * sdram_find() - Find available memory
+ *
+ * This is a bit complicated since on x86 there are system memory holes all
+ * over the place. We create a list of available memory blocks
+ */
+static int sdram_find(pci_dev_t dev)
+{
+ struct memory_info *info = &gd->arch.meminfo;
+ uint32_t tseg_base, uma_size, tolud;
+ uint64_t tom, me_base, touud;
+ uint64_t uma_memory_base = 0;
+ uint64_t uma_memory_size;
+ unsigned long long tomk;
+ uint16_t ggc;
+
+ /* Total Memory 2GB example:
+ *
+ * 00000000 0000MB-1992MB 1992MB RAM (writeback)
+ * 7c800000 1992MB-2000MB 8MB TSEG (SMRR)
+ * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached)
+ * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached)
+ * 7f200000 2034MB TOLUD
+ * 7f800000 2040MB MEBASE
+ * 7f800000 2040MB-2048MB 8MB ME UMA (uncached)
+ * 80000000 2048MB TOM
+ * 100000000 4096MB-4102MB 6MB RAM (writeback)
+ *
+ * Total Memory 4GB example:
+ *
+ * 00000000 0000MB-2768MB 2768MB RAM (writeback)
+ * ad000000 2768MB-2776MB 8MB TSEG (SMRR)
+ * ad800000 2776MB-2778MB 2MB GFX GTT (uncached)
+ * ada00000 2778MB-2810MB 32MB GFX UMA (uncached)
+ * afa00000 2810MB TOLUD
+ * ff800000 4088MB MEBASE
+ * ff800000 4088MB-4096MB 8MB ME UMA (uncached)
+ * 100000000 4096MB TOM
+ * 100000000 4096MB-5374MB 1278MB RAM (writeback)
+ * 14fe00000 5368MB TOUUD
+ */
+
+ /* Top of Upper Usable DRAM, including remap */
+ touud = pci_read_config32(dev, TOUUD+4);
+ touud <<= 32;
+ touud |= pci_read_config32(dev, TOUUD);
+
+ /* Top of Lower Usable DRAM */
+ tolud = pci_read_config32(dev, TOLUD);
+
+ /* Top of Memory - does not account for any UMA */
+ tom = pci_read_config32(dev, 0xa4);
+ tom <<= 32;
+ tom |= pci_read_config32(dev, 0xa0);
+
+ debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom);
+
+ /* ME UMA needs excluding if total memory <4GB */
+ me_base = pci_read_config32(dev, 0x74);
+ me_base <<= 32;
+ me_base |= pci_read_config32(dev, 0x70);
+
+ debug("MEBASE %llx\n", me_base);
+
+ /* TODO: Get rid of all this shifting by 10 bits */
+ tomk = tolud >> 10;
+ if (me_base == tolud) {
+ /* ME is from MEBASE-TOM */
+ uma_size = (tom - me_base) >> 10;
+ /* Increment TOLUD to account for ME as RAM */
+ tolud += uma_size << 10;
+ /* UMA starts at old TOLUD */
+ uma_memory_base = tomk * 1024ULL;
+ uma_memory_size = uma_size * 1024ULL;
+ debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10);
+ }
+
+ /* Graphics memory comes next */
+ ggc = pci_read_config16(dev, GGC);
+ if (!(ggc & 2)) {
+ debug("IGD decoded, subtracting ");
+
+ /* Graphics memory */
+ uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL;
+ debug("%uM UMA", uma_size >> 10);
+ tomk -= uma_size;
+ uma_memory_base = tomk * 1024ULL;
+ uma_memory_size += uma_size * 1024ULL;
+
+ /* GTT Graphics Stolen Memory Size (GGMS) */
+ uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
+ tomk -= uma_size;
+ uma_memory_base = tomk * 1024ULL;
+ uma_memory_size += uma_size * 1024ULL;
+ debug(" and %uM GTT\n", uma_size >> 10);
+ }
+
+ /* Calculate TSEG size from its base which must be below GTT */
+ tseg_base = pci_read_config32(dev, 0xb8);
+ uma_size = (uma_memory_base - tseg_base) >> 10;
+ tomk -= uma_size;
+ uma_memory_base = tomk * 1024ULL;
+ uma_memory_size += uma_size * 1024ULL;
+ debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10);
+
+ debug("Available memory below 4GB: %lluM\n", tomk >> 10);
+
+ /* Report the memory regions */
+ add_memory_area(info, 1 << 20, 2 << 28);
+ add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28);
+ add_memory_area(info, (4 << 28) + (2 << 20), tseg_base);
+ add_memory_area(info, 1ULL << 32, touud);
+ /*
+ * If >= 4GB installed then memory from TOLUD to 4GB
+ * is remapped above TOM, TOUUD will account for both
+ */
+ if (touud > (1ULL << 32ULL)) {
+ debug("Available memory above 4GB: %lluM\n",
+ (touud >> 20) - 4096);
+ }
+
+ return 0;
+}
+
+static void rcba_config(void)
+{
+ /*
+ * GFX INTA -> PIRQA (MSI)
+ * D28IP_P3IP WLAN INTA -> PIRQB
+ * D29IP_E1P EHCI1 INTA -> PIRQD
+ * D26IP_E2P EHCI2 INTA -> PIRQF
+ * D31IP_SIP SATA INTA -> PIRQF (MSI)
+ * D31IP_SMIP SMBUS INTB -> PIRQH
+ * D31IP_TTIP THRT INTC -> PIRQA
+ * D27IP_ZIP HDA INTA -> PIRQA (MSI)
+ *
+ * TRACKPAD -> PIRQE (Edge Triggered)
+ * TOUCHSCREEN -> PIRQG (Edge Triggered)
+ */
+
+ /* Device interrupt pin register (board specific) */
+ writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+ (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP));
+ writel(NOINT << D30IP_PIP, RCB_REG(D30IP));
+ writel(INTA << D29IP_E1P, RCB_REG(D29IP));
+ writel(INTA << D28IP_P3IP, RCB_REG(D28IP));
+ writel(INTA << D27IP_ZIP, RCB_REG(D27IP));
+ writel(INTA << D26IP_E2P, RCB_REG(D26IP));
+ writel(NOINT << D25IP_LIP, RCB_REG(D25IP));
+ writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP));
+
+ /* Device interrupt route registers */
+ writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR));
+ writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR));
+ writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR));
+ writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR));
+ writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR));
+ writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR));
+ writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR));
+
+ /* Enable IOAPIC (generic) */
+ writew(0x0100, RCB_REG(OIC));
+ /* PCH BWG says to read back the IOAPIC enable register */
+ (void)readw(RCB_REG(OIC));
+
+ /* Disable unused devices (board specific) */
+ setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS);
+}
+
+int dram_init(void)
+{
+ struct pei_data pei_data __aligned(8) = {
+ .pei_version = PEI_VERSION,
+ .mchbar = DEFAULT_MCHBAR,
+ .dmibar = DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = CONFIG_HPET_ADDRESS,
+ .rcba = DEFAULT_RCBABASE,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .thermalbase = 0xfed08000,
+ .system_type = 0, /* 0 Mobile, 1 Desktop/Server */
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
+ .ec_present = 1,
+ .ddr3lv_support = 1,
+ /*
+ * 0 = leave channel enabled
+ * 1 = disable dimm 0 on channel
+ * 2 = disable dimm 1 on channel
+ * 3 = disable dimm 0+1 on channel
+ */
+ .dimm_channel0_disabled = 2,
+ .dimm_channel1_disabled = 2,
+ .max_ddr3_freq = 1600,
+ .usb_port_config = {
+ /*
+ * Empty and onboard Ports 0-7, set to un-used pin
+ * OC3
+ */
+ { 0, 3, 0x0000 }, /* P0= Empty */
+ { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */
+ { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */
+ { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */
+ { 0, 3, 0x0000 }, /* P4= Empty */
+ { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */
+ { 0, 3, 0x0000 }, /* P6= Empty */
+ { 0, 3, 0x0000 }, /* P7= Empty */
+ /*
+ * Empty and onboard Ports 8-13, set to un-used pin
+ * OC4
+ */
+ { 1, 4, 0x0040 }, /* P8= Camera (no OC) */
+ { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */
+ { 0, 4, 0x0000 }, /* P10= Empty */
+ { 0, 4, 0x0000 }, /* P11= Empty */
+ { 0, 4, 0x0000 }, /* P12= Empty */
+ { 0, 4, 0x0000 }, /* P13= Empty */
+ },
+ };
+ pci_dev_t dev = PCI_BDF(0, 0, 0);
+ int ret;
+
+ debug("Boot mode %d\n", gd->arch.pei_boot_mode);
+ debug("mcr_input %p\n", pei_data.mrc_input);
+ pei_data.boot_mode = gd->arch.pei_boot_mode;
+ ret = copy_spd(&pei_data);
+ if (!ret)
+ ret = sdram_initialise(&pei_data);
+ if (ret)
+ return ret;
+
+ rcba_config();
+ quick_ram_check();
+
+ writew(0xCAFE, MCHBAR_REG(SSKPD));
+
+ post_code(POST_DRAM);
+
+ ret = sdram_find(dev);
+ if (ret)
+ return ret;
+
+ gd->ram_size = gd->arch.meminfo.total_32bit_memory;
+
+ return 0;
+}
diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
new file mode 100644
index 0000000..e399388
--- /dev/null
+++ b/arch/x86/cpu/pci.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008,2009
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <pci.h>
+#include <asm/pci.h>
+
+static struct pci_controller x86_hose;
+
+int pci_early_init_hose(struct pci_controller **hosep)
+{
+ struct pci_controller *hose;
+
+ hose = calloc(1, sizeof(struct pci_controller));
+ if (!hose)
+ return -ENOMEM;
+
+ board_pci_setup_hose(hose);
+ pci_setup_type1(hose);
+ gd->arch.hose = hose;
+ *hosep = hose;
+
+ return 0;
+}
+
+void pci_init_board(void)
+{
+ struct pci_controller *hose = &x86_hose;
+
+ /* Stop using the early hose */
+ gd->arch.hose = NULL;
+
+ board_pci_setup_hose(hose);
+ pci_setup_type1(hose);
+ pci_register_hose(hose);
+
+ hose->last_busno = pci_hose_scan(hose);
+}
+
+static struct pci_controller *get_hose(void)
+{
+ if (gd->arch.hose)
+ return gd->arch.hose;
+
+ return pci_bus_to_hose(0);
+}
+
+unsigned int pci_read_config8(pci_dev_t dev, unsigned where)
+{
+ uint8_t value;
+
+ pci_hose_read_config_byte(get_hose(), dev, where, &value);
+
+ return value;
+}
+
+unsigned int pci_read_config16(pci_dev_t dev, unsigned where)
+{
+ uint16_t value;
+
+ pci_hose_read_config_word(get_hose(), dev, where, &value);
+
+ return value;
+}
+
+unsigned int pci_read_config32(pci_dev_t dev, unsigned where)
+{
+ uint32_t value;
+
+ pci_hose_read_config_dword(get_hose(), dev, where, &value);
+
+ return value;
+}
+
+void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value)
+{
+ pci_hose_write_config_byte(get_hose(), dev, where, value);
+}
+
+void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value)
+{
+ pci_hose_write_config_word(get_hose(), dev, where, value);
+}
+
+void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value)
+{
+ pci_hose_write_config_dword(get_hose(), dev, where, value);
+}
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 338bab1..b0d0ac0 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -13,6 +13,7 @@
#include <config.h>
#include <version.h>
#include <asm/global_data.h>
+#include <asm/post.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
#include <generated/generic-asm-offsets.h>
@@ -49,6 +50,8 @@
*/
movw $GD_FLG_COLD_BOOT, %bx
1:
+ /* Save BIST */
+ movl %eax, %ebp
/* Load the segement registes to match the gdt loaded in start16.S */
movl $(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax
@@ -65,6 +68,7 @@
jmp early_board_init
.globl early_board_init_ret
early_board_init_ret:
+ post_code(POST_START)
/* Initialise Cache-As-RAM */
jmp car_init
@@ -74,16 +78,29 @@
* We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM,
* or fully initialised SDRAM - we really don't care which)
* starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack
+ * and early malloc area. The MRC requires some space at the top.
+ *
+ * Stack grows down from top of CAR. We have:
+ *
+ * top-> CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE
+ * MRC area
+ * global_data
+ * x86 global descriptor table
+ * early malloc area
+ * stack
+ * bottom-> CONFIG_SYS_CAR_ADDR
*/
-
- /* Stack grows down from top of CAR */
- movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE), %esp
+ movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %esp
+#ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE
+ subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp
+#endif
/* Reserve space on stack for global data */
subl $GENERATED_GBL_DATA_SIZE, %esp
/* Align global data to 16-byte boundary */
andl $0xfffffff0, %esp
+ post_code(POST_START_STACK)
/* Zero the global data since it won't happen later */
xorl %eax, %eax
@@ -91,31 +108,36 @@
movl %esp, %edi
rep stosb
- /* Setup first parameter to setup_gdt */
+ /* Setup first parameter to setup_gdt, pointer to global_data */
movl %esp, %eax
/* Reserve space for global descriptor table */
subl $X86_GDT_SIZE, %esp
+ /* Align temporary global descriptor table to 16-byte boundary */
+ andl $0xfffffff0, %esp
+ movl %esp, %ecx
+
#if defined(CONFIG_SYS_MALLOC_F_LEN)
subl $CONFIG_SYS_MALLOC_F_LEN, %esp
movl %eax, %edx
addl $GD_MALLOC_BASE, %edx
movl %esp, (%edx)
#endif
-
- /* Align temporary global descriptor table to 16-byte boundary */
- andl $0xfffffff0, %esp
+ /* Store BIST */
+ movl %eax, %edx
+ addl $GD_BIST, %edx
+ movl %ebp, (%edx)
/* Set second parameter to setup_gdt */
- movl %esp, %edx
+ movl %ecx, %edx
/* Setup global descriptor table so gd->xyz works */
call setup_gdt
/* Set parameter to board_init_f() to boot flags */
+ post_code(POST_START_DONE)
xorl %eax, %eax
- movw %bx, %ax
/* Enter, U-boot! */
call board_init_f
diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S
index 6968fda..9550502 100644
--- a/arch/x86/cpu/start16.S
+++ b/arch/x86/cpu/start16.S
@@ -21,18 +21,16 @@
.code16
.globl start16
start16:
+ /* Save BIST */
+ movl %eax, %ecx
+
/* Set the Cold Boot / Hard Reset flag */
movl $GD_FLG_COLD_BOOT, %ebx
- /*
- * First we let the BSP do some early initialization
- * this code have to map the flash to its final position
- */
- jmp board_init16
-.globl board_init16_ret
-board_init16_ret:
+ xorl %eax, %eax
+ movl %eax, %cr3 /* Invalidate TLB */
- /* Turn of cache (this might require a 486-class CPU) */
+ /* Turn off cache (this might require a 486-class CPU) */
movl %cr0, %eax
orl $(X86_CR0_NW | X86_CR0_CD), %eax
movl %eax, %cr0
@@ -50,9 +48,11 @@
/* Flush the prefetch queue */
jmp ff
ff:
- /* Finally jump to the 32bit initialization code */
+
+ /* Finally restore BIST and jump to the 32bit initialization code */
movw $code32start, %ax
movw %ax, %bp
+ movl %ecx, %eax
o32 cs ljmp *(%bp)
/* 48-bit far pointer */
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 48265ef..bb3b116 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -1,4 +1,5 @@
dtb-y += link.dtb \
+ chromebook_link.dtb \
alex.dtb
targets += $(dtb-y)
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
new file mode 120000
index 0000000..6f8c5cd
--- /dev/null
+++ b/arch/x86/dts/chromebook_link.dts
@@ -0,0 +1 @@
+link.dts
\ No newline at end of file
diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
index f2fcb39..9329916 100644
--- a/arch/x86/dts/link.dts
+++ b/arch/x86/dts/link.dts
@@ -14,18 +14,21 @@
gpioa {
compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
reg = <0 0x10>;
bank-name = "A";
};
gpiob {
compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
reg = <0x30 0x10>;
bank-name = "B";
};
gpioc {
compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
reg = <0x40 0x10>;
bank-name = "C";
};
@@ -38,6 +41,117 @@
chosen { };
memory { device_type = "memory"; reg = <0 0>; };
+ spd {
+ compatible = "memory-spd";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ elpida_4Gb_1600_x16 {
+ reg = <0>;
+ data = [92 10 0b 03 04 19 02 02
+ 03 52 01 08 0a 00 fe 00
+ 69 78 69 3c 69 11 18 81
+ 20 08 3c 3c 01 40 83 81
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 0f 11 42 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 02 fe 00
+ 11 52 00 00 00 07 7f 37
+ 45 42 4a 32 30 55 47 36
+ 45 42 55 30 2d 47 4e 2d
+ 46 20 30 20 02 fe 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00];
+ };
+ samsung_4Gb_1600_1.35v_x16 {
+ reg = <1>;
+ data = [92 11 0b 03 04 19 02 02
+ 03 11 01 08 0a 00 fe 00
+ 69 78 69 3c 69 11 18 81
+ f0 0a 3c 3c 01 40 83 01
+ 00 80 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 0f 11 02 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 80 ce 01
+ 00 00 00 00 00 00 6a 04
+ 4d 34 37 31 42 35 36 37
+ 34 42 48 30 2d 59 4b 30
+ 20 20 00 00 80 ce 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00];
+ };
+ micron_4Gb_1600_1.35v_x16 {
+ reg = <2>;
+ data = [92 11 0b 03 04 19 02 02
+ 03 11 01 08 0a 00 fe 00
+ 69 78 69 3c 69 11 18 81
+ 20 08 3c 3c 01 40 83 05
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 0f 01 02 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 80 2c 00
+ 00 00 00 00 00 00 ad 75
+ 34 4b 54 46 32 35 36 36
+ 34 48 5a 2d 31 47 36 45
+ 31 20 45 31 80 2c 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff];
+ };
+ };
+
spi {
#address-cells = <1>;
#size-cells = <0>;
@@ -53,6 +167,7 @@
compatible = "intel,lpc";
#address-cells = <1>;
#size-cells = <1>;
+ gen-dec = <0x800 0xfc 0x900 0xfc>;
cros-ec@200 {
compatible = "google,cros-ec";
reg = <0x204 1 0x200 1 0x880 0x80>;
@@ -66,4 +181,14 @@
};
};
};
+
+ microcode {
+ update@0 {
+#include "m12206a7_00000028.dtsi"
+ };
+ update@1 {
+#include "m12306a9_00000017.dtsi"
+ };
+ };
+
};
diff --git a/arch/x86/dts/m12206a7_00000028.dtsi b/arch/x86/dts/m12206a7_00000028.dtsi
new file mode 100644
index 0000000..bcd5248
--- /dev/null
+++ b/arch/x86/dts/m12206a7_00000028.dtsi
@@ -0,0 +1,622 @@
+/*
+ * Copyright (c) <1995-2013>, Intel Corporation.
+ * All rights reserved.
+ *
+ * Redistribution. Redistribution and use in binary form, without modification, are
+ * permitted provided that the following conditions are met:
+ * .Redistributions must reproduce the above copyright notice and the following
+ * disclaimer in the documentation and/or other materials provided with the
+ * distribution.
+ * Neither the name of Intel Corporation nor the names of its suppliers may be used
+ * to endorse or promote products derived from this software without specific prior
+ * written permission.
+ * .No reverse engineering, decompilation, or disassembly of this software is
+ * permitted.
+ * ."Binary form" includes any format commonly used for electronic conveyance
+ * which is a reversible, bit-exact translation of binary representation to ASCII or
+ * ISO text, for example, "uuencode."
+ *
+ * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x28>;
+intel,date-code = <0x04242012>;
+intel,processor-signature = <0x000206a7>;
+intel,checksum = <0xf3e9935d>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The 48-byte public header is omitted. */
+data = <
+ 0x00000000 0x000000a1 0x00020001 0x00000028
+ 0x00000000 0x00000000 0x20120423 0x000008f1
+ 0x00000001 0x000206a7 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x000008f1 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x52b813ac 0xdb8994c7 0x70e9f6bb 0x9d6db2ff
+ 0xf4d70f5d 0x5b1eccf6 0xac59106f 0x0ae2e2c1
+ 0x1a7bbeb1 0x355a1d62 0x2e7eb594 0x09f8dea9
+ 0x432a49e4 0xbf520253 0xdafa4010 0x893a858a
+ 0x766e0efb 0xd91e196d 0x838bd2ef 0xe5146494
+ 0xd515f413 0x29704828 0xe85598b6 0xdcbe6c51
+ 0x88eabbfa 0xa1e8909f 0xd8931721 0x35386554
+ 0x089a78a7 0xd9914775 0xd4644748 0x1556a4dc
+ 0xf44448f6 0xd054d7db 0xf30f2b7d 0x5ae223d0
+ 0xcbbb48b0 0x5c8b0383 0x177de157 0x9c1e5f73
+ 0x2ec28289 0xd72a7b6c 0x823b6eb2 0x35e02171
+ 0xba8deae4 0x06f4d468 0x13dbafaa 0x72b419f1
+ 0x033385b5 0x05806920 0x4c6034cf 0x9bd117dc
+ 0x976e2d04 0x250330f0 0x7250b5e1 0x184980c2
+ 0x12a9d7d6 0x1bc808f9 0xae79994f 0xc6f87901
+ 0xc0e3132f 0x671491c5 0x236cad39 0x37889d9c
+ 0x67f7c3f3 0x964a6be5 0xbcced7da 0x57eeaa6e
+ 0x7bca1522 0x654fee4c 0x2a1ca5d9 0xa1803cf3
+ 0x00000011 0x8c316d2c 0x17603b7e 0x32e42981
+ 0xc26c1400 0xf0fbccb6 0xeab6b43a 0x11d456a5
+ 0x5b912d46 0x15195fe0 0x542f6db3 0x0b7f212e
+ 0x47718dd9 0x7c41b108 0x06c21111 0x4445d5ea
+ 0xb4fb8128 0xe07404a6 0x8d503da4 0x78fc7e44
+ 0xb9919656 0x9968c797 0x87f26ab0 0x23bb1af7
+ 0x1ec5d761 0x26f30d2c 0x7cdb747c 0xe4d42033
+ 0x8a5d4801 0x768aff57 0xbcfd5d11 0x7c853c2d
+ 0x231e6207 0x8b1988a6 0xd68fdb75 0x58dcb417
+ 0x44422ef9 0x2a186ebb 0x7d27e85f 0x36ac31f7
+ 0x1e487e77 0x2b0b8c37 0xd8ba682f 0x2cba791b
+ 0xe6d3dece 0x1b2c2a99 0x4e5decab 0xfbd313a3
+ 0xdbc78294 0x5a80cce7 0x2d8e0f0b 0xcf564f71
+ 0x073d1f37 0x25162870 0x96cdb85b 0x9c553048
+ 0x24eba740 0xfc0f352e 0x0c83be68 0x89b5076c
+ 0xc39c4355 0x6a4cf25c 0x2bbd2682 0xc524fdb9
+ 0x7ea19bae 0x191ad6f1 0xd3fbf3bf 0x21bf77fa
+ 0x8f77fec4 0x0f90f635 0xe55e165c 0x868d58c0
+ 0x966bc0ad 0x6c276364 0x9d8f7eff 0x4b7925d4
+ 0x8b2f9326 0x4ab7b47e 0x33a9087c 0xf31ab949
+ 0x69831dfb 0x4711a215 0x8128c1fa 0x8481c213
+ 0x7401b01b 0xfdcfdc50 0xd6b55266 0xae9b23ac
+ 0xfa2ad275 0xa225bb45 0x4dd720c4 0x760a20e6
+ 0x5f1223c9 0x2f334372 0x6e1dcdab 0xe8ee8638
+ 0x1c19ba8a 0xef9341c4 0x360aaa9d 0x90452ea9
+ 0x65852446 0xe9398fa3 0xbba6a631 0x1a3e90b9
+ 0xe2a73a56 0x6e8c0747 0x35c7c53d 0xcc1ac842
+ 0x183356af 0xb6e98608 0x987b43c2 0xa8a3cfd2
+ 0xc2c5fce0 0xcc3af64a 0xd6d3a291 0xe59ad1f5
+ 0x124ca513 0x9522b50a 0x25150477 0xa2eb5797
+ 0x7fc63626 0x648c48e3 0x9f5797ff 0x2307b84d
+ 0x980625a4 0xabc05983 0x24980807 0x773c4f99
+ 0x3407b872 0x07c3657a 0xa2cd9e48 0x49c1e6a8
+ 0xa881b84c 0xf804d72c 0xb5319d2a 0x3e39780f
+ 0x97518822 0x0acd54c2 0x0721a9ff 0x10e1d2fd
+ 0xa7b6db77 0x845b1a56 0xef00160e 0x6b41bfd5
+ 0xc994df0d 0xcf44a5ca 0x794b36a4 0xf9fdb127
+ 0x922a1366 0x822aa8a9 0x4b137bd5 0x5722a49f
+ 0x8933719a 0x17edc1a9 0x079d9538 0x21fae7d5
+ 0xe534fd73 0x9d3038d5 0x48c3a056 0x5b22d58a
+ 0x6f142866 0xf1d767cd 0xb51ad5a6 0x34a0ef85
+ 0x0111703e 0xca4b3a30 0xa0f3c34d 0x9d48775a
+ 0x3f2059f9 0xf2fe2c36 0x588861a9 0xed5bd9fe
+ 0x8231f7cb 0x8c115969 0x3f82ba00 0x21b3730c
+ 0xba757997 0x3ec0bb2c 0x16f11def 0x5d4356c6
+ 0xdc2e0bc2 0x58c1eb6e 0x313ede0c 0xb68fcc52
+ 0x84d3e1b5 0xcc6d9201 0x95046196 0x276b527b
+ 0x80a4a729 0xe782916d 0x5cf09e0b 0x98aaf9fa
+ 0x1de6dd43 0xab4f1962 0x49ece734 0x81455488
+ 0xc2597b61 0x5b22af85 0x646f7b94 0x09213a1f
+ 0x08edf7e4 0x963d343c 0x059ba888 0xb4e804ed
+ 0xe7cc826c 0xf87bafc7 0xeecaec10 0x8e60919c
+ 0xbf14c996 0xd3dcaee3 0xb8fa0b7e 0x81563c6e
+ 0x7f59a258 0x2f344446 0x374d8aa6 0x9b6de5c9
+ 0xbf992857 0xbc5b94fc 0x28adb080 0x17e41044
+ 0xb87b469e 0xda504d12 0xf21bef8b 0xce75c1e3
+ 0xdbd92c83 0x58bba0af 0x77b42977 0x506cfd75
+ 0x1139e875 0x6ce5fe43 0xc6a5d7b3 0x87f9e628
+ 0x7b5c500b 0x130066b3 0x789b611f 0xec8c1ba9
+ 0xb7e6872d 0xaf828cd6 0xc28d3316 0x2a91f6d0
+ 0xc725f063 0x065ac531 0x4f9ef4b8 0x2b9d927e
+ 0xaf54f3f9 0x7c924f72 0xda1d77ad 0xff00db67
+ 0xaf4f03c0 0xb4f4ee64 0x169e64e5 0x04653ac0
+ 0xed51cb70 0xfeaff0e5 0x51dbf346 0x072a2407
+ 0x23fb74f4 0x9a906eef 0x5d6fc3f0 0xbc3c374c
+ 0x1cf9f063 0x919015d9 0x5b3e9d07 0xd6209d8b
+ 0xa3710b3d 0x90ad23b8 0x420ceedc 0x58e8371f
+ 0x5d419d1f 0xb8acd13f 0x7d100d6d 0x210c10d1
+ 0xcd0a697e 0x5023db4b 0x33e6d8e7 0x44bbe6b4
+ 0x827e859f 0x6ca4cc81 0x661bb2c3 0x71209ee8
+ 0xb8c3ffaf 0xd1075f51 0xba1eae10 0x728b0a6a
+ 0xe4af7a2f 0xca9bcf2e 0xb249a631 0xdce6be47
+ 0x5c910321 0x425c3c27 0x33083e43 0xdea067ae
+ 0xea594a23 0x41b75c2c 0x3a401a95 0xd33cd88a
+ 0xc295cad0 0x67f48045 0x1dc9ad4c 0x4bc48864
+ 0x53991b6e 0x7aadde5f 0x2b0bf775 0x06ba5380
+ 0x9eb874be 0x2c4b967a 0x1bcc342f 0xe875001b
+ 0x15b5642d 0x5be99c9d 0xcb210ace 0x1b4924ad
+ 0x3793ed81 0x8b983114 0x3ec33981 0x75ec71e7
+ 0x8b5b7df3 0x834756f4 0x100fad01 0x70037fdf
+ 0x0cef9a36 0x3d9e3a2d 0x38b48efd 0xfc4034b6
+ 0xa32e29dd 0x388944bc 0xc1c15614 0x3877e9c7
+ 0xa5e733fa 0xa621bd53 0x4b651df6 0xce082970
+ 0x85f30d6f 0x729a5c87 0x31dd7ba9 0xdb495828
+ 0x7b12c698 0x953495c9 0x6b5f99e7 0x2cc42fa8
+ 0x697ac512 0x1be679de 0xc116d305 0x94a36606
+ 0x9e5e141e 0x874affed 0x58d40b0b 0x5e3cf5e5
+ 0x5d05e9a9 0x06840efc 0xd2f98b21 0xa1e83ab2
+ 0x4f726202 0xa6394535 0x62a02403 0x9f2167ec
+ 0x4f9fc77b 0x98073be4 0x2bc781fa 0xfc8e4c89
+ 0xc7179b97 0x692cf793 0x708ff7bb 0x12ecba93
+ 0xacd06e21 0x202bef76 0x03852241 0xe84e02a1
+ 0xf1f9ac8d 0xcee61aef 0x61a4f235 0xd22991eb
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+ 0x3d0a6fab 0x3e8523d6 0xd0688dee 0xe5c3865c
+ 0x838d72e4 0x6bb73a1d 0x497a59ca 0xf77c56de
+ 0x38ecb72e 0xa55e3565 0x04b12c92 0x1aec9997
+ 0x037c340a 0xef0d04c3 0x78f74bd6 0xdec9b9e8
+ 0xd95b61ea 0x5528e8f5 0x4ecd325c 0x88ffdc0b
+ 0xb337ac61 0x899d90e7 0xb5eeb978 0x8295d9ae
+ 0x1ed8978b 0xa8849eda 0x8633b4a3 0xb8c858b5
+ 0xbe3c4375 0x28b9e84e 0xb2a26def 0x22f8f66b
+ 0x3a4aed99 0x0c4914ea 0xad103249 0xba5a5eff
+ 0x8a052461 0x26938899 0x915c6ed7 0xe6268ad9
+ 0x246e8c74 0x75f3c196 0xc3e725d6 0x92e02549
+ 0x1f78a5cb 0xeada57e5 0x40f14906 0x0215e49c
+ 0x57c06bae 0xc1896b87 0x0cd40a63 0x60741d80
+ 0x11a69899 0x80fed942 0x0497e115 0x56697b55
+ 0xba89c3d4 0x27d6b7c5 0xddff87b0 0xd3b1ff2f
+ 0x3160e528 0x9cca1286 0x13b4fdf1 0x38cdd907
+ 0xb50c4597 0x4c151714 0x1cab86c7 0x23126a3e
+ 0xe26e9749 0x289a0d0e 0xc4004640 0x9d33928d
+ 0x33b691a2 0x15ed6e6b 0x6e773980 0xadd59678
+ 0x188ba49f 0x08da4c6d 0x6d150d0b 0x0c6c7b98
+ 0xc8e1df7e 0xb8b1e692 0x5e89fd35 0xcb253d24
+ 0xfc6ee27c 0x8013de3d 0x1d38012b 0xe50a8f7b
+ 0x7d410ff1 0xceee4e9f 0x0e8094b6 0xaa1a5f57
+ 0xb395a551 0xbd62b2ae 0x5d7b34c8 0xbd2d6195
+ 0x33af4109 0x0769ff18 0x9c6cc123 0x78ee6eb6
+ 0x412644e7 0x70e0c6f4 0xf45d8fc6 0x0435f5af
+ 0xd43622b7 0x27409d5b 0x6dd04e8f 0x9f02ecf5
+ 0xca415f7d 0xc9f439c2 0x7198e539 0x20476b75
+ 0x3cdd8dd8 0xce17fbb0 0xa5bc115e 0xb0ee52c1
+ 0x0b074cfa 0xd26d4f99 0x3b43320b 0x230b680b
+ 0x9908f2d2 0xcbcb1952 0xf45a2f53 0x7b4564c6
+ 0xcf2fd983 0x414fe4b2 0x55ea7f11 0x63e8117d
+ 0xe8954052 0x7c2ea344 0x97a02aaf 0x6ca874c3
+ 0x1ae5b4ee 0x41754eae 0x6954abe0 0x115ddcda
+ 0x9a27968b 0x32a53e65 0xffe47b2f 0x4fe7e5a7
+ 0x6016dedc 0xb3c0893e 0x9626776d 0x5ec773f9
+ 0x1104e01c 0x1473cfb3 0x43b2cedf 0x8ca9d119
+ 0x7f1bc844 0xd8bb7387 0xba90d2ef 0x2bb0dcf4
+ 0x2340f124 0xa5bd514c 0x50afab05 0x718f5ad5
+ 0x7c03fad9 0x71d00d2d 0x1c31fdc2 0x4a938809
+ 0x40945ded 0x437f2a0d 0x83c10d64 0xd224c6ab
+ 0x0cd44481 0xb0040966 0x27fd6e7f 0x6ff45d4c
+ 0xab057ad1 0x8fa4e5d4 0xac50270c 0x6e4926ca
+ 0xc5721498 0x2529b458 0x40ee2ad5 0xde5e21f2
+ 0xea8964ca 0x56766e60 0xdc3b8702 0xa93528d4
+ 0x28d7713d 0x42edf022 0x59774dd8 0x200ff942
+ 0xe7a4d769 0xd8c4ef5e 0xe177f715 0xe9d53cd6
+ 0xc11270bb 0xb25977e5 0xb80867b4 0xfb48468b
+ 0xdbf166a8 0x49700d85 0x0f85f98a 0xa7ca7a75
+ 0x109817ce 0xca243f19 0x8bed7688 0x9a1c8231
+ 0x94f0ce97 0xc36309ca 0x90ecac24 0x67e7e0de
+ 0x86b18d62 0x18c7b7a5 0x622f5d3a 0x47e1e067
+ 0xdc96b94d 0xe4a03beb 0x59d17692 0x040abc0d
+ 0x44a5ae50 0x3d3dab7d 0xc18dfd30 0x2802b9d9
+ 0x6818379f 0x56db41d7 0x97cbf039 0xe41d6a32
+ 0x64b5fb01 0x6506e0b4 0xd60a3234 0xdf3573d2
+ 0xac148579 0xe7f46ac0 0x05e1c763 0x904a5aa9
+ 0xc7ca1ee0 0xe0c3b047 0x5e36e1bc 0x447a9141
+ 0xe24654df 0x9853a49b 0x6a29cedb 0x022f00dc
+ 0x6df2a7a7 0x3636da02 0x72bb9c81 0x4f0e0918
+ 0xd649f4a5 0xbb0c81f9 0xc0ba93fd 0xc1b390f1
+ 0xda84e720 0x1aea0064 0xf3ee67e1 0xb874ef4a
+ 0x82467ce6 0x59abf506 0xafbf145a 0x9a4cf8a1
+ 0x17247c89 0xd8669398 0x1796eaf7 0xbc2d24a9
+ 0xcb486570 0x17a9db23 0x3e6504f0 0x08684517
+ 0x2723ab28 0x7081b814 0x8a265a04 0x697e6d8b
+ 0x69b146dc 0x6434c182 0x27ec8101 0x864405c5
+ 0xfff86c9e 0x3052d8a6 0x23d283db 0x492970e8
+ 0xbc6c64c3 0x46d8f98b 0xe16e7ff3 0x731e4f82
+ 0xbd26b1af 0x6b30e6c1 0xff192fce 0x097e0bba
+ 0x49df63a5 0x2fdc3f01 0x50aae053 0x60177b8f
+ 0x1949eb85 0xa46084ce 0x9658f694 0xcb951fbc
+ 0xc53806d9 0x63a17d30 0x3b3f86c2 0x8a37aa6c
+ 0xedf8fe5c 0x87aee1d3 0x8c680126 0xfd8b27a6
+ 0x231fa106 0x69358c25 0x4502c348 0xc107861c
+ 0x46280e70 0xcf6067ac 0xf6a04ff3 0x3e488677
+ 0x6f3fb4c1 0xeec1f758 0x560e1c48 0xb604c06b
+ 0x69e34b1e 0x8ef41dec 0x854cea22 0x726581d7
+ 0x55ea91f3 0x38ae4053 0x5ff7389d 0x6952cbf6
+ 0x09aa0fc1 0xcccb1d50 0x5c1a633a 0xde1eba46
+ 0x797212d8 0xa943fb3d 0x6063a1a8 0xbe68ef36
+ 0x6ba0d5ba 0x0dbe2061 0x47711712 0x62679807
+ 0x6f34009e 0xe6fe8f18 0x66a6a64b 0x3f80f472
+ 0xe953d5e0 0xbcd8196a 0x086faad0 0x49da7f16
+ 0x7f2199a5 0x55af4af2 0x085b4d38 0x22e634bd
+ 0x6cff0416 0x343466f4 0xd121a7a6 0x6caa3942
+ 0xe4f365a2 0xd832eb0c 0x616728e5 0xcca4c71a
+ 0x4010cdc2 0xd0f1d1cb 0x5e695f89 0x27719206
+ 0x0ec92854 0x76144a1b 0x49808021 0x12457a1b
+ 0xdde7aa5c 0x8f1a077f 0x110a4a5a 0xb3a5ad31
+ 0xaacebf8f 0x66ff7f33 0xa2340971 0xfb4c7e82
+ 0x8dd536d7 0xafd2021a 0x72aa9c6e 0x22df6952
+ 0x83c4b4fb 0xba515555 0x93eee8f0 0x22d0ed5a
+ 0xbec05586 0x83828f28 0xe0d7f930 0xac0f0199
+ 0xef6d76f9 0xf56ebdf8 0xf67323c9 0x8b805745
+ 0xce5902c0 0xfa2ce3da 0x10f836dd 0xe1ac6d97
+ 0xa0e415ea 0xbb7c32ad 0xc421f3b0 0x8166e898
+ 0x74e7a73c 0xf454b82a 0x631369b1 0xe30ed23f
+ 0xdaa1c75b 0xe7c9c6a7 0x5f33c375 0x99c05187
+ 0xf2d6e6ae 0xcd2045b8 0x92ff3009 0x15082015
+ 0xd1a1580e 0xdce25f9b 0x21984a75 0xa9be5388
+ 0x099a5372 0x3ab9bcfa 0xdb9069aa 0x49a99be6
+ 0x42a9ee0b 0xfe32d832 0x24e11ad3 0xd16f596b
+ 0xb95982cc 0x754ab1c8 0x42ffa128 0x539e823d
+ 0x28e0f976 0x262ddfc0 0x2a16e7ad 0x49b5acd9
+ 0x931f3def 0xdc419b84 0x8412cc3c 0x81056cd9
+ 0x91933e1f 0x57710b15 0xa55d2696 0x87d88724
+ 0xd4fedfdc 0xcc3825c6 0x397f382f 0x80f9b6ba
+ 0xcdd6d59f 0x24b984d8 0x8f1c5bcf 0x25bcef1d
+ 0x00dc603a 0x76fd94c2 0xa267a7dc 0xa6e90a6a
+ 0x5c5916d6 0x065a52cf 0xa28d3263 0x9b17b72d
+ 0xb8436b48 0x1b1c2391 0x1fda3395 0xa6cecbcb
+ 0xbc4ec502 0x1766b590 0x5945fbd6 0x6a124405
+ 0xf92d06f2 0xe24694b7 0xf6befd08 0x8266cf5c
+ 0x03ed670a 0x5f98be62 0xf27b7e2e 0x598cf22c
+ 0x2e855591 0x879815fb 0x153799c6 0x3820faf6
+ 0x3d3a2cc6 0xdbb6dece 0x1a3c46b2 0x5031bdda
+ 0x47894c03 0xe43661fe 0x7a6ee548 0xa5ca9779
+ 0x6aa9e105 0xbc8505a3 0xa03b860a 0x448faeb9
+ 0x367de4a9 0xc9779c7d 0x6535ad8c 0x4b7fcacc
+ 0xb2db5c10 0x0ab41ec6 0xe528ab90 0x5e6f03da
+ 0x98bc76d3 0xf38df42e 0xea59b039 0x1c2eaa28
+ 0xca30dac5 0xdb0eb8c6 0x60063860 0x18823f8d
+ 0x164e2f28 0x7cbbe080 0x70a12315 0xb08f44d9
+ 0x5fbb9453 0x4bc62738 0x9fa15ffc 0xe4033ca1
+ 0xc9dfbc13 0x58245d7d 0x588113aa 0x8f5a6ac8
+ 0x92588a60 0x26330c74 0xb2aaf0e3 0x24ada1ea
+ 0xa9e973ae 0x624b73e7 0x4ef961db 0x95ede155
+ 0xf2bb86ff 0x96bc79d9 0x95cd646b 0x1c3af453
+ 0xf60fa711 0x10905115 0x0e24b740 0x169bb227
+ 0x34cee6f0 0x990980db 0x18d8ace5 0xd4c87504
+ 0x29515d32 0x2e5d9c04 0x87dffa60 0x12e815d1
+ 0x021db8e9 0x2c5a42fd 0x6e3a1a13 0x88889ab5
+ 0x3bc915a6 0x608919c5 0xd310a970 0xea8f3218
+ 0x949f55bc 0x9ed7aadd 0x6d990157 0x181f1c2f
+ 0xa940df64 0xf3be8c39 0x7ca2e699 0x7b4f07f9
+ 0x89e83fee 0xe66b9493 0x54fc3d17 0xa63d2d46
+ 0xd5e835d5 0x910e0144 0xecf67025 0x1fa6a93a
+ 0xe692dbca 0x466af681 0xc2bc808c 0xbb4ebd60
+ 0x74d5c729 0xa283ad25 0x1e66fa23 0x6d372988
+ 0x753c9fcb 0x1742efdb 0x5b68cf15 0x372a0e33
+ 0xaa3a7ebd 0xa0e944d5 0x95d5cbb4 0x4fb6020b
+ 0xced927b0 0xb2afea78 0xd0646b72 0x1622fad4
+ 0x4672c6b6 0x736ae4f8 0x8d46a4db 0x0e6a432e
+ 0xe0a30a98 0x4c2bcf4f 0xd87acedd 0x19682d7a
+ 0xf97c025c 0x55d8feb3 0xbcd4d2ff 0x236c6f9f
+ 0x8ba0246d 0x42812f73 0x327636f5 0xc92cd30a
+ 0x08a69d9d 0xc735a946 0x82eca01f 0xda0753a0
+ 0x7077b1d1 0x17b05834 0xfa24bc02 0xf49f4473
+ 0x8f9ac6b4 0xa880c630 0xf7457b4d 0xd5f829e4
+ 0x25c49a99 0x1176a997 0xbb2d2009 0x61d35764
+ 0xa322c752 0x6ef3ae02 0x5faae6f8 0x9a52acf1
+ 0x19176f43 0x43843b07 0x14efc471 0xee474403
+ 0x319c4857 0xa19adcf0 0xc0a466e1 0x02db14ad
+ 0xb7f211f3 0x72aa6ca6 0x0eb9bffe 0x48a6d284
+ 0x9a93a2ee 0xac09fc5f 0x92a62c4f 0xd34f0271
+ 0xffb348c7 0xf229b6e2 0xc68ec1ca 0x19577dbc
+ 0x069a10bf 0xf64ac347 0xf7c3c848 0x81975294
+ 0x6376e550 0x93b53440 0x8bb17daa 0xc4c64c07
+ 0xcaeff293 0xd51497b0 0x33da3565 0xa73d5def
+ 0x4bf4dcde 0xfb470fcd 0xca7db864 0x7ef17022
+ 0x47567363 0xd8fb8d74 0xa68c3c72 0x8202e4f3
+ 0x75bf1798 0x16a70fd2 0xcc3b697f 0xab9a1075
+ 0x13f56ef3 0x269d0302 0xcb655a43 0xc9a4de88
+ 0xfb8363de 0xff40f36d 0xd2555489 0x647a7995
+ 0xfd8eda6e 0xa3958c9a 0x20e029b4 0xbed3e225
+ 0xa7df5f17 0x63bc3c1a 0x337ecc9d 0x6c329508
+ 0x786aa47e 0x1db5b093 0xc0acd73b 0xf9587237
+ 0x243e5d40 0xd3623c3a 0x338c4740 0xb672140e
+ 0x43640a9b 0xb7ef3f6a 0x44151074 0x749bcc46
+ 0xfa1f103b 0x0fefb19e 0x58855538 0x138ad276
+ 0x2641fd80 0x297d99d0 0xfaa63ba2 0x00b6f11a
+ 0x3793fb6b 0x124763a1 0x8b9419ac 0x56abf9eb
+ 0xdbf83419 0x43570571 0x37299cd8 0x8b201e62
+ 0xa4058fa5 0xb320e91b 0xbe7d40b7 0x4eca3b2d
+ 0x8519c155 0xf4b17021 0x9e4c572a 0xdc1f9e16
+ 0x39a589a3 0xa6cfc7a8 0x5b986910 0x64e150e7
+ 0x60b6f2c1 0x02bacd3f 0x2f3b5a5c 0xc6f453a8
+ 0x15a87a7e 0x76104a14 0xafa2ef63 0x2cd48dbe
+ 0x3c7abddc 0xd786ea5a 0x4f65867a 0x355cda38
+ 0x2ae03d9e 0x4f11f6be 0xfc0a0034 0xde4ea602
+ 0x21ff83ea 0x0f12d913 0xedf4da28 0xc96d8fd1
+ 0xd7e82c3c 0xfec63bdc 0x37a456d7 0x3007e18c
+ 0x091a47b6 0x82f1c641 0x82219cce 0x3e7e6993
+ 0x7b3a2115 0x0b8e1a02 0x40f88213 0xfa2f9c21
+ >;
diff --git a/arch/x86/dts/m12306a9_00000017.dtsi b/arch/x86/dts/m12306a9_00000017.dtsi
new file mode 100644
index 0000000..299d663
--- /dev/null
+++ b/arch/x86/dts/m12306a9_00000017.dtsi
@@ -0,0 +1,750 @@
+/*
+ * Copyright (c) <1995-2013>, Intel Corporation.
+ * All rights reserved.
+ *
+ * Redistribution. Redistribution and use in binary form, without modification, are
+ * permitted provided that the following conditions are met:
+ * .Redistributions must reproduce the above copyright notice and the following
+ * disclaimer in the documentation and/or other materials provided with the
+ * distribution.
+ * Neither the name of Intel Corporation nor the names of its suppliers may be used
+ * to endorse or promote products derived from this software without specific prior
+ * written permission.
+ * .No reverse engineering, decompilation, or disassembly of this software is
+ * permitted.
+ * ."Binary form" includes any format commonly used for electronic conveyance
+ * which is a reversible, bit-exact translation of binary representation to ASCII or
+ * ISO text, for example, "uuencode."
+ *
+ * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x17>;
+intel,date-code = <0x01092013>;
+intel,processor-signature = <0x000306a9>;
+intel,checksum = <0x3546450b>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The 48-byte public header is omitted. */
+data = <
+ 0x00000000 0x000000a1 0x00020001 0x00000017
+ 0x00000000 0x00000000 0x20130107 0x00000a61
+ 0x00000001 0x000306a9 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x86c5b0d4 0xf6978804 0x7f4f5870 0x6319dc3c
+ 0xbb3b7d61 0x33cf9075 0xe8424658 0xf611a357
+ 0x5a3401db 0x42caecce 0xb4d8e75e 0xe6dbaf24
+ 0x7861b35f 0x6bd717bc 0x23b9b731 0x82ec1ac8
+ 0x20337b64 0x5396dbf1 0x59973bff 0x724bc7e9
+ 0x5237193b 0x0b8647c1 0x6a0d0e16 0xbf9ddb5b
+ 0xace2cc1c 0xad707638 0x056f102f 0xa37e60f8
+ 0x76255642 0xfb86e030 0xb8069a40 0x367795f1
+ 0x653fb05e 0xab7f14ad 0xb6e8a8e1 0xd2598d20
+ 0x2eba3f68 0x78b372f1 0xba8d13f8 0x1f1de861
+ 0x97f951d5 0x8097c728 0x27dbf904 0xb97906a8
+ 0xffe7a4ac 0x4b947668 0xc1dbd726 0x2adcf777
+ 0x63b1bcf0 0x818e2a1b 0x49aa907b 0x2faf5e8d
+ 0xae842352 0x82707fae 0x0aa12b41 0xa0bae11c
+ 0xb4298c47 0xd2b4099c 0x4ff625f2 0xcd2630d4
+ 0x79850981 0x05dbf57d 0xb05b81a5 0x56e73ec7
+ 0x95cb3897 0xe262bda5 0xb2c6e288 0xcb7f8e77
+ 0x72b8bdd3 0x3f400494 0x63ade65b 0xbc4adc71
+ 0x00000011 0x06c0f8ff 0x0eb63d77 0xc54cdabf
+ 0x76bc8860 0xdd142643 0xe7bfc220 0x17aa0a91
+ 0x4fd676ba 0x4b6b1a15 0x2a1a1c16 0x4fed6de0
+ 0x8c3d6bcf 0xbb319bf6 0xa82532f1 0x7c8ce014
+ 0xb830a38b 0xec25bc6b 0x61c8a8a9 0x49a21dba
+ 0xfcf8bad0 0x7372f29c 0x1f7fbcdd 0xc2ff42f4
+ 0x780878f0 0xc967068e 0xe19cc3c9 0x155e6646
+ 0x75235c43 0x9aaf3741 0x9dfd116d 0x0f031b6a
+ 0x4963e039 0x6918daa8 0x7f0ca4ab 0xd77dad79
+ 0x2f8847e8 0xf79c82a4 0x6a6aaad4 0x24f07dbc
+ 0x895d3f6a 0xc96b2eb0 0xff50228f 0x573d364a
+ 0x5fca9d56 0x3c11c35b 0x3e90fb12 0xc4604067
+ 0x5c980234 0x7c42e0c7 0x60cca3de 0x637a4644
+ 0xedc43956 0xb0efb4e1 0xe94716fa 0xa6478f51
+ 0x33965654 0xdf6b40a3 0x48ac1b18 0xd6723c94
+ 0xf040d6d1 0xaf850470 0xe2bcde48 0xb90a4998
+ 0x8f620105 0x3d592878 0x2f697bad 0x9f7721d9
+ 0xec34444a 0xb0594770 0xd7180f9f 0xa510a168
+ 0x460563b0 0x5d4f34f4 0x21dfc16b 0x051de344
+ 0xa57bc344 0xff2c7863 0xf0bc063d 0xf5a89004
+ 0x79a81dab 0x9e8cb974 0x2309b0a4 0xa47a46de
+ 0xcf9c0c44 0xf761c817 0x67ab642c 0x0db4422f
+ 0xca3616fc 0x79e66c8a 0xd56a3332 0x5e0f338b
+ 0x5814cb3a 0xed1b9a4d 0x47d59f72 0x25b03786
+ 0x3edd1d42 0x8cd947cd 0x706e6ebd 0x82c2bada
+ 0x1bf6a96b 0x77dd859a 0xda35335f 0x22fab458
+ 0xd0661fd8 0x02bb4a42 0xe2a2bcdb 0x0616580e
+ 0xd35be23f 0xc206d16c 0x401218be 0x51107c3d
+ 0xba84b8be 0xace4d8f2 0x505b9b28 0xc517034b
+ 0xac5ba582 0x7419fe54 0x43493cb1 0x2fe0a66e
+ 0x206039b5 0x07569011 0x230ce53d 0x168d427f
+ 0xbfe0bd10 0x82bf11be 0x5b55475b 0x5490a0e9
+ 0x1c3c1e3c 0xacad77de 0x1666512f 0xfc3250d8
+ 0x930a6312 0xdd85c066 0x1b95c18f 0xc8bbd3b0
+ 0x1bb2a34e 0x642c7653 0x0f536213 0x1f7ab4eb
+ 0xaa5ef677 0xe6ac9581 0xd7a2fe73 0xd417dc79
+ 0x455a6877 0xae825a40 0xe0c98bec 0xac39ba49
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+ 0x6697cf37 0xc5d9661d 0x089eab85 0x7684a876
+ 0x018a81af 0x221a7fb2 0x31d80de0 0x9f18ae90
+ 0xa29c9af0 0xc3e2b00f 0xda0edbab 0x7ee9cd2a
+ 0x3ab0f88e 0x02c58228 0x606fa7aa 0x7776cb0a
+ 0x4e8ad99c 0x3b527469 0x58123d62 0x4ce428d2
+ 0xee91a210 0x466ba2cc 0x043c57b9 0xaf7bdd43
+ 0x98e76fee 0x8f3eac1b 0x00dffd6c 0x6fcb1c6a
+ 0x5cb90573 0x485d4505 0x0df5418a 0x26eafe35
+ 0x0faddf3e 0x4e972930 0xe113c823 0xe45944d1
+ 0xa646077f 0xc1708ae5 0x6ba07c20 0xc7e4e234
+ 0xc6754ed5 0xbd6e85aa 0x8cc1756e 0x02afda29
+ 0x72809597 0x75b6f5a1 0x61141874 0x1774047f
+ 0x7a10afed 0xfac2c4ad 0x42cf5c99 0x24f0350e
+ 0x042f2864 0xfab55b67 0xc8ead5bc 0x914e9512
+ 0x77c8ef6b 0x8369aeb1 0x71bc947f 0x0c6b49d8
+ 0x8ddd0513 0x028ad10d 0x99a1b28f 0xe6cfbdc8
+ 0x7978b4a6 0x3ebbade8 0x9985f5cf 0x431f42f1
+ 0x004372b2 0x18b67f68 0x20111c21 0xbb6f77ff
+ 0x1783b030 0xa045d7d1 0x0e9c7e09 0x3ccbd95f
+ 0x0b84a2ed 0xf0ee3325 0x63f2e126 0x5ec4c67b
+ 0x2ca782cc 0xcaf20d04 0x8b59d515 0x3212aa33
+ 0x335ca0c3 0x6f9e0cdd 0x4d4bf189 0x44d2fa0c
+ 0x5abe9396 0x492794ee 0x10dcfcb1 0x9acda9bd
+ 0xe8aa2803 0x3f1b9605 0x3e2ecb5a 0x971bfa8a
+ 0xcbf141d2 0x0afafe10 0x2fc906a6 0xefad20c0
+ 0x9e922581 0xe69142cc 0xc9c0ba82 0xc069e640
+ 0xb99c08b6 0x4b62ca1f 0xf3c5767a 0x6ab088c7
+ 0x8f0f0c0b 0x6726f64a 0x9711a3cd 0x46462571
+ 0x3a58350e 0xa2561911 0xe24dfdfe 0x97443fdc
+ 0xf80540be 0x069978bf 0xb38a359b 0x8e574f62
+ 0x69aea75c 0xdc753fcb 0x2a74002c 0xced027b4
+ 0xda993254 0x03409b83 0xf827331d 0x75fb3271
+ 0x01ad839d 0x68520842 0xca65c45c 0x1a3db5a0
+ 0x91d37dd3 0x6168c0fb 0x935f5a08 0x002007c3
+ 0x42eb4760 0xdab3a804 0x72a6297e 0x905c32d9
+ 0x81abcfa9 0x1b21d04a 0x5a1289ae 0x424e7183
+ 0xc207906c 0x31fe9134 0x5eb2e5af 0xc9253fc7
+ 0xc32be24f 0xe5474cbd 0xeff6e1b0 0x710e5e69
+ 0xe6c4c538 0x96b5f1de 0x2abc9c35 0xddbd1a92
+ 0x8aca40d7 0xe359c238 0x954718f4 0x18b157e5
+ 0xeeed790e 0x6948a963 0x24e70bfb 0x4d681547
+ 0xf68369a7 0x5b54409a 0x1f0b787a 0xc2610047
+ 0x0f8bd269 0xd7c8c154 0x9dee62d9 0xd4738ed8
+ 0x1a66c6b1 0x5bad5a5b 0xb110311a 0xfaec6802
+ 0x6b750f2d 0xcbf8d0e0 0x11edaf4b 0xf64a07bb
+ 0x422e7c15 0xb1732663 0x1ff404f0 0x2d5052b0
+ 0x6e45356c 0x7e2201e8 0x7c5ebcd1 0x1cb4425a
+ 0xb1539a64 0xa2e4459f 0xcf1ade8a 0xfc476473
+ 0xf4147deb 0x2afbdd77 0xff01fabc 0x6597408a
+ 0x0951220b 0x6750f3ec 0x0a242763 0xf3d71c05
+ 0x84cb1c26 0xdb7a81bd 0x7aea1a5d 0x7e719a48
+ 0xc5c12fe1 0x0ce2e988 0x29ecc6f0 0x5ede901a
+ 0xda8399b1 0x31c05d6b 0xe1956aff 0x59ed7c3d
+ 0x60832637 0x9bcb7cac 0x63c530d1 0x14c677de
+ 0x9225ed18 0x065327c9 0xd1ff6a0e 0x5516517e
+ 0x53c6f5c2 0xed5983cf 0xaa1d18b9 0xbe300d7f
+ 0xadc525a7 0x07ea81b6 0xfc517a09 0x4ead3f86
+ 0x45435f41 0x2efa58df 0x02348ebc 0x30ed6783
+ 0x190b4fb9 0x85c55d6e 0xc9ed8896 0x416ee113
+ 0x9b3536d9 0x30577cc0 0xbc4b88c8 0xcda59612
+ 0xdfe2bd89 0xd60cde71 0x98843881 0xcc1f32f2
+ 0x18b3f643 0x671a14ca 0xd6482a47 0xac6a7d38
+ 0x1897da16 0x91b6fcb3 0xf199bb35 0xd38c00ba
+ 0xa8c946b6 0x52a1ad37 0xd38ed2d4 0xa1d6f81d
+ 0x5af6865b 0xebdb858f 0xb844b110 0x53201ea2
+ 0x08870945 0x10c869de 0x19849613 0xdb35d3ed
+ 0xd68ebd6e 0x1056fd48 0xf1a0e305 0xe3982ebd
+ 0x6f7cc391 0x5956374a 0xf414a5a2 0x325119ab
+ 0x99ee1f96 0x6f044bd9 0x8374805b 0xb55c366c
+ 0xa2c77051 0x68f199e5 0xd36a9714 0x878f847b
+ 0xec0394ae 0x86d0584b 0xf4df66b9 0x451cd039
+ 0xf4de06ae 0x35dd0554 0x818a342f 0xeefdbfc9
+ 0x5b4e9edd 0x22d9313a 0x3b710d60 0x6deaeb4c
+ 0xa9e26512 0x98d31867 0x3c2c2d61 0x7eb5ce41
+ 0x40890db6 0x7a3aa660 0x3ef4f306 0x7322881f
+ 0x49dac4d5 0x96efe685 0x27bb7f49 0xbb955283
+ 0x79c5f2b7 0xff599c28 0x28ee7f5e 0x9f324b73
+ 0x45edb7cf 0x39a8b79c 0xd0919c6e 0xe149b29d
+ 0x62f5f82e 0xebcfa23e 0xd4d68937 0x54270090
+ 0x958af0d4 0xa1e4e799 0xaf68ac19 0x82a84f4e
+ 0x50f67b84 0xd5e59629 0xf5fdf24c 0xab1d63c5
+ 0x30835807 0x431fce5f 0xe5f96f4d 0x3f6b4802
+ 0x14010be8 0xdca45ae5 0xc82709af 0xff76ce2c
+ 0x8b222c22 0x73a2d948 0xa8d59cea 0x8c31849e
+ 0x469c2e5f 0x3777ee84 0x5fdfa5da 0x02ef9bb2
+ 0x792d3194 0xbed63f21 0x0b6dc5f1 0xc9d7fe08
+ 0x6df7883d 0x366566cf 0xef772769 0x37826465
+ 0x1cdc3086 0xa69ff7b6 0x235012ea 0x292f7e75
+ 0x30bdd0fd 0xffdc9df1 0x95c6d570 0xec206204
+ 0xc6cd42cb 0xc0d6dfd9 0xb7a16b71 0x17fa527e
+ 0x295f2c79 0x990f9820 0x8b8f447d 0x193f9ad1
+ 0xebddb2af 0x5dd532eb 0xf1bbd8e8 0x3444a3f4
+ 0x18ccce93 0x05edeb4f 0xc4a6b935 0xba37aab0
+ 0x96076ba4 0x250dc2f7 0xc4093548 0x030e777d
+ 0x7ea40933 0x8da7b1dd 0x59c0b79f 0x807d437c
+ 0xf5233ddf 0x54c1983f 0xfc18771b 0xe74b85f0
+ 0xdbd725b5 0x70cdd153 0x4ffe300c 0xfda4bdae
+ 0xf4ac75d2 0x91c4e15a 0x34d92b97 0x16356a79
+ >;
diff --git a/arch/x86/include/asm/arch-coreboot/gpio.h b/arch/x86/include/asm/arch-coreboot/gpio.h
index 3ec1816..4951a8c 100644
--- a/arch/x86/include/asm/arch-coreboot/gpio.h
+++ b/arch/x86/include/asm/arch-coreboot/gpio.h
@@ -7,9 +7,4 @@
#ifndef _X86_ARCH_GPIO_H_
#define _X86_ARCH_GPIO_H_
-struct ich6_bank_platdata {
- uint32_t base_addr;
- const char *bank_name;
-};
-
#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-ivybridge/gpio.h b/arch/x86/include/asm/arch-ivybridge/gpio.h
new file mode 100644
index 0000000..4951a8c
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/gpio.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2014, Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_GPIO_H_
+#define _X86_ARCH_GPIO_H_
+
+#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-ivybridge/me.h b/arch/x86/include/asm/arch-ivybridge/me.h
new file mode 100644
index 0000000..3a0809d
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/me.h
@@ -0,0 +1,356 @@
+/*
+ * From Coreboot src/southbridge/intel/bd82x6x/me.h
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ASM_INTEL_ME_H
+#define _ASM_INTEL_ME_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+#define ME_RETRY 100000 /* 1 second */
+#define ME_DELAY 10 /* 10 us */
+
+/*
+ * Management Engine PCI registers
+ */
+
+#define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */
+#define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */
+
+#define PCI_ME_HFS 0x40
+#define ME_HFS_CWS_RESET 0
+#define ME_HFS_CWS_INIT 1
+#define ME_HFS_CWS_REC 2
+#define ME_HFS_CWS_NORMAL 5
+#define ME_HFS_CWS_WAIT 6
+#define ME_HFS_CWS_TRANS 7
+#define ME_HFS_CWS_INVALID 8
+#define ME_HFS_STATE_PREBOOT 0
+#define ME_HFS_STATE_M0_UMA 1
+#define ME_HFS_STATE_M3 4
+#define ME_HFS_STATE_M0 5
+#define ME_HFS_STATE_BRINGUP 6
+#define ME_HFS_STATE_ERROR 7
+#define ME_HFS_ERROR_NONE 0
+#define ME_HFS_ERROR_UNCAT 1
+#define ME_HFS_ERROR_IMAGE 3
+#define ME_HFS_ERROR_DEBUG 4
+#define ME_HFS_MODE_NORMAL 0
+#define ME_HFS_MODE_DEBUG 2
+#define ME_HFS_MODE_DIS 3
+#define ME_HFS_MODE_OVER_JMPR 4
+#define ME_HFS_MODE_OVER_MEI 5
+#define ME_HFS_BIOS_DRAM_ACK 1
+#define ME_HFS_ACK_NO_DID 0
+#define ME_HFS_ACK_RESET 1
+#define ME_HFS_ACK_PWR_CYCLE 2
+#define ME_HFS_ACK_S3 3
+#define ME_HFS_ACK_S4 4
+#define ME_HFS_ACK_S5 5
+#define ME_HFS_ACK_GBL_RESET 6
+#define ME_HFS_ACK_CONTINUE 7
+
+struct me_hfs {
+ u32 working_state:4;
+ u32 mfg_mode:1;
+ u32 fpt_bad:1;
+ u32 operation_state:3;
+ u32 fw_init_complete:1;
+ u32 ft_bup_ld_flr:1;
+ u32 update_in_progress:1;
+ u32 error_code:4;
+ u32 operation_mode:4;
+ u32 reserved:4;
+ u32 boot_options_present:1;
+ u32 ack_data:3;
+ u32 bios_msg_ack:4;
+} __packed;
+
+#define PCI_ME_UMA 0x44
+
+struct me_uma {
+ u32 size:6;
+ u32 reserved_1:10;
+ u32 valid:1;
+ u32 reserved_0:14;
+ u32 set_to_one:1;
+} __packed;
+
+#define PCI_ME_H_GS 0x4c
+#define ME_INIT_DONE 1
+#define ME_INIT_STATUS_SUCCESS 0
+#define ME_INIT_STATUS_NOMEM 1
+#define ME_INIT_STATUS_ERROR 2
+
+struct me_did {
+ u32 uma_base:16;
+ u32 reserved:8;
+ u32 status:4;
+ u32 init_done:4;
+} __packed;
+
+#define PCI_ME_GMES 0x48
+#define ME_GMES_PHASE_ROM 0
+#define ME_GMES_PHASE_BUP 1
+#define ME_GMES_PHASE_UKERNEL 2
+#define ME_GMES_PHASE_POLICY 3
+#define ME_GMES_PHASE_MODULE 4
+#define ME_GMES_PHASE_UNKNOWN 5
+#define ME_GMES_PHASE_HOST 6
+
+struct me_gmes {
+ u32 bist_in_prog:1;
+ u32 icc_prog_sts:2;
+ u32 invoke_mebx:1;
+ u32 cpu_replaced_sts:1;
+ u32 mbp_rdy:1;
+ u32 mfs_failure:1;
+ u32 warm_rst_req_for_df:1;
+ u32 cpu_replaced_valid:1;
+ u32 reserved_1:2;
+ u32 fw_upd_ipu:1;
+ u32 reserved_2:4;
+ u32 current_state:8;
+ u32 current_pmevent:4;
+ u32 progress_code:4;
+} __packed;
+
+#define PCI_ME_HERES 0xbc
+#define PCI_ME_EXT_SHA1 0x00
+#define PCI_ME_EXT_SHA256 0x02
+#define PCI_ME_HER(x) (0xc0+(4*(x)))
+
+struct me_heres {
+ u32 extend_reg_algorithm:4;
+ u32 reserved:26;
+ u32 extend_feature_present:1;
+ u32 extend_reg_valid:1;
+} __packed;
+
+/*
+ * Management Engine MEI registers
+ */
+
+#define MEI_H_CB_WW 0x00
+#define MEI_H_CSR 0x04
+#define MEI_ME_CB_RW 0x08
+#define MEI_ME_CSR_HA 0x0c
+
+struct mei_csr {
+ u32 interrupt_enable:1;
+ u32 interrupt_status:1;
+ u32 interrupt_generate:1;
+ u32 ready:1;
+ u32 reset:1;
+ u32 reserved:3;
+ u32 buffer_read_ptr:8;
+ u32 buffer_write_ptr:8;
+ u32 buffer_depth:8;
+} __packed;
+
+#define MEI_ADDRESS_CORE 0x01
+#define MEI_ADDRESS_AMT 0x02
+#define MEI_ADDRESS_RESERVED 0x03
+#define MEI_ADDRESS_WDT 0x04
+#define MEI_ADDRESS_MKHI 0x07
+#define MEI_ADDRESS_ICC 0x08
+#define MEI_ADDRESS_THERMAL 0x09
+
+#define MEI_HOST_ADDRESS 0
+
+struct mei_header {
+ u32 client_address:8;
+ u32 host_address:8;
+ u32 length:9;
+ u32 reserved:6;
+ u32 is_complete:1;
+} __packed;
+
+#define MKHI_GROUP_ID_CBM 0x00
+#define MKHI_GROUP_ID_FWCAPS 0x03
+#define MKHI_GROUP_ID_MDES 0x08
+#define MKHI_GROUP_ID_GEN 0xff
+
+#define MKHI_GLOBAL_RESET 0x0b
+
+#define MKHI_FWCAPS_GET_RULE 0x02
+
+#define MKHI_MDES_ENABLE 0x09
+
+#define MKHI_GET_FW_VERSION 0x02
+#define MKHI_END_OF_POST 0x0c
+#define MKHI_FEATURE_OVERRIDE 0x14
+
+struct mkhi_header {
+ u32 group_id:8;
+ u32 command:7;
+ u32 is_response:1;
+ u32 reserved:8;
+ u32 result:8;
+} __packed;
+
+struct me_fw_version {
+ u16 code_minor;
+ u16 code_major;
+ u16 code_build_number;
+ u16 code_hot_fix;
+ u16 recovery_minor;
+ u16 recovery_major;
+ u16 recovery_build_number;
+ u16 recovery_hot_fix;
+} __packed;
+
+
+#define HECI_EOP_STATUS_SUCCESS 0x0
+#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
+
+#define CBM_RR_GLOBAL_RESET 0x01
+
+#define GLOBAL_RESET_BIOS_MRC 0x01
+#define GLOBAL_RESET_BIOS_POST 0x02
+#define GLOBAL_RESET_MEBX 0x03
+
+struct me_global_reset {
+ u8 request_origin;
+ u8 reset_type;
+} __packed;
+
+enum me_bios_path {
+ ME_NORMAL_BIOS_PATH,
+ ME_S3WAKE_BIOS_PATH,
+ ME_ERROR_BIOS_PATH,
+ ME_RECOVERY_BIOS_PATH,
+ ME_DISABLE_BIOS_PATH,
+ ME_FIRMWARE_UPDATE_BIOS_PATH,
+};
+
+struct __packed mbp_fw_version_name {
+ u32 major_version:16;
+ u32 minor_version:16;
+ u32 hotfix_version:16;
+ u32 build_version:16;
+};
+
+struct __packed mbp_icc_profile {
+ u8 num_icc_profiles;
+ u8 icc_profile_soft_strap;
+ u8 icc_profile_index;
+ u8 reserved;
+ u32 register_lock_mask[3];
+};
+
+struct __packed mefwcaps_sku {
+ u32 full_net:1;
+ u32 std_net:1;
+ u32 manageability:1;
+ u32 small_business:1;
+ u32 l3manageability:1;
+ u32 intel_at:1;
+ u32 intel_cls:1;
+ u32 reserved:3;
+ u32 intel_mpc:1;
+ u32 icc_over_clocking:1;
+ u32 pavp:1;
+ u32 reserved_1:4;
+ u32 ipv6:1;
+ u32 kvm:1;
+ u32 och:1;
+ u32 vlan:1;
+ u32 tls:1;
+ u32 reserved_4:1;
+ u32 wlan:1;
+ u32 reserved_5:8;
+};
+
+struct __packed tdt_state_flag {
+ u16 lock_state:1;
+ u16 authenticate_module:1;
+ u16 s3authentication:1;
+ u16 flash_wear_out:1;
+ u16 flash_variable_security:1;
+ u16 wwan3gpresent:1;
+ u16 wwan3goob:1;
+ u16 reserved:9;
+};
+
+struct __packed tdt_state_info {
+ u8 state;
+ u8 last_theft_trigger;
+ struct tdt_state_flag flags;
+};
+
+struct __packed platform_type_rule_data {
+ u32 platform_target_usage_type:4;
+ u32 platform_target_market_type:2;
+ u32 super_sku:1;
+ u32 reserved:1;
+ u32 intel_me_fw_image_type:4;
+ u32 platform_brand:4;
+ u32 reserved_1:16;
+};
+
+struct __packed mbp_fw_caps {
+ struct mefwcaps_sku fw_capabilities;
+ u8 available;
+};
+
+struct __packed mbp_rom_bist_data {
+ u16 device_id;
+ u16 fuse_test_flags;
+ u32 umchid[4];
+};
+
+struct __packed mbp_platform_key {
+ u32 key[8];
+};
+
+struct __packed mbp_plat_type {
+ struct platform_type_rule_data rule_data;
+ u8 available;
+};
+
+struct __packed me_bios_payload {
+ struct mbp_fw_version_name fw_version_name;
+ struct mbp_fw_caps fw_caps_sku;
+ struct mbp_rom_bist_data rom_bist_data;
+ struct mbp_platform_key platform_key;
+ struct mbp_plat_type fw_plat_type;
+ struct mbp_icc_profile icc_profile;
+ struct tdt_state_info at_state;
+ u32 mfsintegrity;
+};
+
+struct __packed mbp_header {
+ u32 mbp_size:8;
+ u32 num_entries:8;
+ u32 rsvd:16;
+};
+
+struct __packed mbp_item_header {
+ u32 app_id:8;
+ u32 item_id:8;
+ u32 length:8;
+ u32 rsvd:8;
+};
+
+struct __packed me_fwcaps {
+ u32 id;
+ u8 length;
+ struct mefwcaps_sku caps_sku;
+ u8 reserved[3];
+};
+
+/* Defined in me_status.c for both romstage and ramstage */
+void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
+
+void intel_early_me_status(void);
+int intel_early_me_init(void);
+int intel_early_me_uma_size(void);
+int intel_early_me_init_done(u8 status);
+
+#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/microcode.h b/arch/x86/include/asm/arch-ivybridge/microcode.h
new file mode 100644
index 0000000..bc9b87c
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/microcode.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MICROCODE_H
+#define __ASM_ARCH_MICROCODE_H
+
+/**
+ * microcode_update_intel() - Apply microcode updates
+ *
+ * Applies any microcode updates in the device tree.
+ *
+ * @return 0 if OK, -EEXIST if the updates were already applied, -ENOENT if
+ * not updates were found, -EINVAL if an update was invalid
+ */
+int microcode_update_intel(void);
+
+#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/model_206ax.h b/arch/x86/include/asm/arch-ivybridge/model_206ax.h
new file mode 100644
index 0000000..8281d7a
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/model_206ax.h
@@ -0,0 +1,82 @@
+/*
+ * From Coreboot file of the same name
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ASM_ARCH_MODEL_206AX_H
+#define _ASM_ARCH_MODEL_206AX_H
+
+/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
+#define SANDYBRIDGE_BCLK 100
+
+#define CPUID_VMX (1 << 5)
+#define CPUID_SMX (1 << 6)
+#define MSR_FEATURE_CONFIG 0x13c
+#define MSR_FLEX_RATIO 0x194
+#define FLEX_RATIO_LOCK (1 << 20)
+#define FLEX_RATIO_EN (1 << 16)
+#define IA32_PLATFORM_DCA_CAP 0x1f8
+#define IA32_MISC_ENABLE 0x1a0
+#define MSR_TEMPERATURE_TARGET 0x1a2
+#define IA32_PERF_CTL 0x199
+#define IA32_THERM_INTERRUPT 0x19b
+#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
+#define ENERGY_POLICY_PERFORMANCE 0
+#define ENERGY_POLICY_NORMAL 6
+#define ENERGY_POLICY_POWERSAVE 15
+#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
+#define MSR_LT_LOCK_MEMORY 0x2e7
+#define IA32_MC0_STATUS 0x401
+
+#define MSR_PIC_MSG_CONTROL 0x2e
+#define PLATFORM_INFO_SET_TDP (1 << 29)
+
+#define MSR_MISC_PWR_MGMT 0x1aa
+#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
+#define MSR_TURBO_RATIO_LIMIT 0x1ad
+#define MSR_POWER_CTL 0x1fc
+
+#define MSR_PKGC3_IRTL 0x60a
+#define MSR_PKGC6_IRTL 0x60b
+#define MSR_PKGC7_IRTL 0x60c
+#define IRTL_VALID (1 << 15)
+#define IRTL_1_NS (0 << 10)
+#define IRTL_32_NS (1 << 10)
+#define IRTL_1024_NS (2 << 10)
+#define IRTL_32768_NS (3 << 10)
+#define IRTL_1048576_NS (4 << 10)
+#define IRTL_33554432_NS (5 << 10)
+#define IRTL_RESPONSE_MASK (0x3ff)
+
+/* long duration in low dword, short duration in high dword */
+#define PKG_POWER_LIMIT_MASK 0x7fff
+#define PKG_POWER_LIMIT_EN (1 << 15)
+#define PKG_POWER_LIMIT_CLAMP (1 << 16)
+#define PKG_POWER_LIMIT_TIME_SHIFT 17
+#define PKG_POWER_LIMIT_TIME_MASK 0x7f
+
+#define MSR_PP0_CURRENT_CONFIG 0x601
+#define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */
+#define MSR_PP1_CURRENT_CONFIG 0x602
+#define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */
+#define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */
+#define MSR_PKG_POWER_SKU_UNIT 0x606
+#define MSR_PKG_POWER_SKU 0x614
+
+#define IVB_CONFIG_TDP_MIN_CPUID 0x306a2
+#define MSR_CONFIG_TDP_NOMINAL 0x648
+#define MSR_CONFIG_TDP_LEVEL1 0x649
+#define MSR_CONFIG_TDP_LEVEL2 0x64a
+#define MSR_CONFIG_TDP_CONTROL 0x64b
+#define MSR_TURBO_ACTIVATION_RATIO 0x64c
+
+/* P-state configuration */
+#define PSS_MAX_ENTRIES 8
+#define PSS_RATIO_STEP 2
+#define PSS_LATENCY_TRANSITION 10
+#define PSS_LATENCY_BUSMASTER 10
+
+#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
new file mode 100644
index 0000000..c6efdb8
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -0,0 +1,356 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * From Coreboot src/southbridge/intel/bd82x6x/pch.h
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ASM_ARCH_PCH_H
+#define _ASM_ARCH_PCH_H
+
+#include <pci.h>
+
+#define DEFAULT_GPIOBASE 0x0480
+#define DEFAULT_PMBASE 0x0500
+
+#define SMBUS_IO_BASE 0x0400
+
+#define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0)
+#define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0)
+#define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0)
+#define PCH_ME_DEV PCI_BDF(0, 0x16, 0)
+#define PCH_PCIE_DEV_SLOT 28
+
+#define PCH_DEV PCI_BDF(0, 0, 0)
+#define PCH_VIDEO_DEV PCI_BDF(0, 2, 0)
+
+/* PCI Configuration Space (D31:F0): LPC */
+#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
+
+#define GEN_PMCON_1 0xa0
+#define GEN_PMCON_2 0xa2
+#define GEN_PMCON_3 0xa4
+#define ETR3 0xac
+#define ETR3_CWORWRE (1 << 18)
+#define ETR3_CF9GR (1 << 20)
+
+#define PMBASE 0x40
+#define ACPI_CNTL 0x44
+#define BIOS_CNTL 0xDC
+#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
+#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
+#define GPIO_ROUT 0xb8
+
+#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
+#define LPC_EN 0x82 /* LPC IF Enables Register */
+#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
+#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
+#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */
+#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
+#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
+#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
+#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */
+#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
+#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
+#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */
+#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
+#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
+#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
+#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
+#define LPC_GENX_DEC(x) (0x84 + 4 * (x))
+
+/* PCI Configuration Space (D31:F3): SMBus */
+#define PCH_SMBUS_DEV PCI_BDF(0, 0x1f, 3)
+#define SMB_BASE 0x20
+#define HOSTC 0x40
+#define SMB_RCV_SLVA 0x09
+
+/* HOSTC bits */
+#define I2C_EN (1 << 2)
+#define SMB_SMI_EN (1 << 1)
+#define HST_EN (1 << 0)
+
+/* SMBus I/O bits. */
+#define SMBHSTSTAT 0x0
+#define SMBHSTCTL 0x2
+#define SMBHSTCMD 0x3
+#define SMBXMITADD 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBBLKDAT 0x7
+#define SMBTRNSADD 0x9
+#define SMBSLVDATA 0xa
+#define SMLINK_PIN_CTL 0xe
+#define SMBUS_PIN_CTL 0xf
+
+#define SMBUS_TIMEOUT (10 * 1000 * 100)
+
+
+/* Root Complex Register Block */
+#define DEFAULT_RCBA 0xfed1c000
+#define RCB_REG(reg) (DEFAULT_RCBA + (reg))
+
+#define PCH_RCBA_BASE 0xf0
+
+#define VCH 0x0000 /* 32bit */
+#define VCAP1 0x0004 /* 32bit */
+#define VCAP2 0x0008 /* 32bit */
+#define PVC 0x000c /* 16bit */
+#define PVS 0x000e /* 16bit */
+
+#define V0CAP 0x0010 /* 32bit */
+#define V0CTL 0x0014 /* 32bit */
+#define V0STS 0x001a /* 16bit */
+
+#define V1CAP 0x001c /* 32bit */
+#define V1CTL 0x0020 /* 32bit */
+#define V1STS 0x0026 /* 16bit */
+
+#define RCTCL 0x0100 /* 32bit */
+#define ESD 0x0104 /* 32bit */
+#define ULD 0x0110 /* 32bit */
+#define ULBA 0x0118 /* 64bit */
+
+#define RP1D 0x0120 /* 32bit */
+#define RP1BA 0x0128 /* 64bit */
+#define RP2D 0x0130 /* 32bit */
+#define RP2BA 0x0138 /* 64bit */
+#define RP3D 0x0140 /* 32bit */
+#define RP3BA 0x0148 /* 64bit */
+#define RP4D 0x0150 /* 32bit */
+#define RP4BA 0x0158 /* 64bit */
+#define HDD 0x0160 /* 32bit */
+#define HDBA 0x0168 /* 64bit */
+#define RP5D 0x0170 /* 32bit */
+#define RP5BA 0x0178 /* 64bit */
+#define RP6D 0x0180 /* 32bit */
+#define RP6BA 0x0188 /* 64bit */
+
+#define RPC 0x0400 /* 32bit */
+#define RPFN 0x0404 /* 32bit */
+
+#define TRSR 0x1e00 /* 8bit */
+#define TRCR 0x1e10 /* 64bit */
+#define TWDR 0x1e18 /* 64bit */
+
+#define IOTR0 0x1e80 /* 64bit */
+#define IOTR1 0x1e88 /* 64bit */
+#define IOTR2 0x1e90 /* 64bit */
+#define IOTR3 0x1e98 /* 64bit */
+
+#define TCTL 0x3000 /* 8bit */
+
+#define NOINT 0
+#define INTA 1
+#define INTB 2
+#define INTC 3
+#define INTD 4
+
+#define DIR_IDR 12 /* Interrupt D Pin Offset */
+#define DIR_ICR 8 /* Interrupt C Pin Offset */
+#define DIR_IBR 4 /* Interrupt B Pin Offset */
+#define DIR_IAR 0 /* Interrupt A Pin Offset */
+
+#define PIRQA 0
+#define PIRQB 1
+#define PIRQC 2
+#define PIRQD 3
+#define PIRQE 4
+#define PIRQF 5
+#define PIRQG 6
+#define PIRQH 7
+
+/* IO Buffer Programming */
+#define IOBPIRI 0x2330
+#define IOBPD 0x2334
+#define IOBPS 0x2338
+#define IOBPS_RW_BX ((1 << 9)|(1 << 10))
+#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10))
+#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
+
+#define D31IP 0x3100 /* 32bit */
+#define D31IP_TTIP 24 /* Thermal Throttle Pin */
+#define D31IP_SIP2 20 /* SATA Pin 2 */
+#define D31IP_SMIP 12 /* SMBUS Pin */
+#define D31IP_SIP 8 /* SATA Pin */
+#define D30IP 0x3104 /* 32bit */
+#define D30IP_PIP 0 /* PCI Bridge Pin */
+#define D29IP 0x3108 /* 32bit */
+#define D29IP_E1P 0 /* EHCI #1 Pin */
+#define D28IP 0x310c /* 32bit */
+#define D28IP_P8IP 28 /* PCI Express Port 8 */
+#define D28IP_P7IP 24 /* PCI Express Port 7 */
+#define D28IP_P6IP 20 /* PCI Express Port 6 */
+#define D28IP_P5IP 16 /* PCI Express Port 5 */
+#define D28IP_P4IP 12 /* PCI Express Port 4 */
+#define D28IP_P3IP 8 /* PCI Express Port 3 */
+#define D28IP_P2IP 4 /* PCI Express Port 2 */
+#define D28IP_P1IP 0 /* PCI Express Port 1 */
+#define D27IP 0x3110 /* 32bit */
+#define D27IP_ZIP 0 /* HD Audio Pin */
+#define D26IP 0x3114 /* 32bit */
+#define D26IP_E2P 0 /* EHCI #2 Pin */
+#define D25IP 0x3118 /* 32bit */
+#define D25IP_LIP 0 /* GbE LAN Pin */
+#define D22IP 0x3124 /* 32bit */
+#define D22IP_KTIP 12 /* KT Pin */
+#define D22IP_IDERIP 8 /* IDE-R Pin */
+#define D22IP_MEI2IP 4 /* MEI #2 Pin */
+#define D22IP_MEI1IP 0 /* MEI #1 Pin */
+#define D20IP 0x3128 /* 32bit */
+#define D20IP_XHCIIP 0
+#define D31IR 0x3140 /* 16bit */
+#define D30IR 0x3142 /* 16bit */
+#define D29IR 0x3144 /* 16bit */
+#define D28IR 0x3146 /* 16bit */
+#define D27IR 0x3148 /* 16bit */
+#define D26IR 0x314c /* 16bit */
+#define D25IR 0x3150 /* 16bit */
+#define D22IR 0x315c /* 16bit */
+#define D20IR 0x3160 /* 16bit */
+#define OIC 0x31fe /* 16bit */
+
+#define SPI_FREQ_SWSEQ 0x3893
+#define SPI_DESC_COMP0 0x38b0
+#define SPI_FREQ_WR_ERA 0x38b4
+#define SOFT_RESET_CTRL 0x38f4
+#define SOFT_RESET_DATA 0x38f8
+
+#define DIR_ROUTE(a, b, c, d) \
+ (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
+ ((b) << DIR_IBR) | ((a) << DIR_IAR))
+
+#define RC 0x3400 /* 32bit */
+#define HPTC 0x3404 /* 32bit */
+#define GCS 0x3410 /* 32bit */
+#define BUC 0x3414 /* 32bit */
+#define PCH_DISABLE_GBE (1 << 5)
+#define FD 0x3418 /* 32bit */
+#define DISPBDF 0x3424 /* 16bit */
+#define FD2 0x3428 /* 32bit */
+#define CG 0x341c /* 32bit */
+
+/* Function Disable 1 RCBA 0x3418 */
+#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))
+#define PCH_DISABLE_P2P (1 << 1)
+#define PCH_DISABLE_SATA1 (1 << 2)
+#define PCH_DISABLE_SMBUS (1 << 3)
+#define PCH_DISABLE_HD_AUDIO (1 << 4)
+#define PCH_DISABLE_EHCI2 (1 << 13)
+#define PCH_DISABLE_LPC (1 << 14)
+#define PCH_DISABLE_EHCI1 (1 << 15)
+#define PCH_DISABLE_PCIE(x) (1 << (16 + x))
+#define PCH_DISABLE_THERMAL (1 << 24)
+#define PCH_DISABLE_SATA2 (1 << 25)
+#define PCH_DISABLE_XHCI (1 << 27)
+
+/* Function Disable 2 RCBA 0x3428 */
+#define PCH_DISABLE_KT (1 << 4)
+#define PCH_DISABLE_IDER (1 << 3)
+#define PCH_DISABLE_MEI2 (1 << 2)
+#define PCH_DISABLE_MEI1 (1 << 1)
+#define PCH_ENABLE_DBDF (1 << 0)
+
+/* ICH7 GPIOBASE */
+#define GPIO_USE_SEL 0x00
+#define GP_IO_SEL 0x04
+#define GP_LVL 0x0c
+#define GPO_BLINK 0x18
+#define GPI_INV 0x2c
+#define GPIO_USE_SEL2 0x30
+#define GP_IO_SEL2 0x34
+#define GP_LVL2 0x38
+#define GPIO_USE_SEL3 0x40
+#define GP_IO_SEL3 0x44
+#define GP_LVL3 0x48
+#define GP_RST_SEL1 0x60
+#define GP_RST_SEL2 0x64
+#define GP_RST_SEL3 0x68
+
+/* ICH7 PMBASE */
+#define PM1_STS 0x00
+#define WAK_STS (1 << 15)
+#define PCIEXPWAK_STS (1 << 14)
+#define PRBTNOR_STS (1 << 11)
+#define RTC_STS (1 << 10)
+#define PWRBTN_STS (1 << 8)
+#define GBL_STS (1 << 5)
+#define BM_STS (1 << 4)
+#define TMROF_STS (1 << 0)
+#define PM1_EN 0x02
+#define PCIEXPWAK_DIS (1 << 14)
+#define RTC_EN (1 << 10)
+#define PWRBTN_EN (1 << 8)
+#define GBL_EN (1 << 5)
+#define TMROF_EN (1 << 0)
+#define PM1_CNT 0x04
+#define SLP_EN (1 << 13)
+#define SLP_TYP (7 << 10)
+#define SLP_TYP_S0 0
+#define SLP_TYP_S1 1
+#define SLP_TYP_S3 5
+#define SLP_TYP_S4 6
+#define SLP_TYP_S5 7
+#define GBL_RLS (1 << 2)
+#define BM_RLD (1 << 1)
+#define SCI_EN (1 << 0)
+#define PM1_TMR 0x08
+#define PROC_CNT 0x10
+#define LV2 0x14
+#define LV3 0x15
+#define LV4 0x16
+#define PM2_CNT 0x50 /* mobile only */
+#define GPE0_STS 0x20
+#define PME_B0_STS (1 << 13)
+#define PME_STS (1 << 11)
+#define BATLOW_STS (1 << 10)
+#define PCI_EXP_STS (1 << 9)
+#define RI_STS (1 << 8)
+#define SMB_WAK_STS (1 << 7)
+#define TCOSCI_STS (1 << 6)
+#define SWGPE_STS (1 << 2)
+#define HOT_PLUG_STS (1 << 1)
+#define GPE0_EN 0x28
+#define PME_B0_EN (1 << 13)
+#define PME_EN (1 << 11)
+#define TCOSCI_EN (1 << 6)
+#define SMI_EN 0x30
+#define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */
+#define LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */
+#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */
+#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */
+#define MCSMI_EN (1 << 11) /* Trap microcontroller range access */
+#define BIOS_RLS (1 << 7) /* asserts SCI on bit set */
+#define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */
+#define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */
+#define SLP_SMI_EN (1 << 4) /* Write SLP_EN in PM1_CNT asserts SMI# */
+#define LEGACY_USB_EN (1 << 3) /* Legacy USB circuit SMI logic */
+#define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */
+#define EOS (1 << 1) /* End of SMI (deassert SMI#) */
+#define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */
+#define SMI_STS 0x34
+#define ALT_GP_SMI_EN 0x38
+#define ALT_GP_SMI_STS 0x3a
+#define GPE_CNTL 0x42
+#define DEVACT_STS 0x44
+#define SS_CNT 0x50
+#define C3_RES 0x54
+#define TCO1_STS 0x64
+#define DMISCI_STS (1 << 9)
+#define TCO2_STS 0x66
+
+/**
+ * lpc_early_init() - set up LPC serial ports and other early things
+ *
+ * @blob: Device tree blob
+ * @node: Offset of LPC node
+ * @dev: PCH PCI device containing the LPC
+ * @return 0 if OK, -ve on error
+ */
+int lpc_early_init(const void *blob, int node, pci_dev_t dev);
+
+#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/pei_data.h b/arch/x86/include/asm/arch-ivybridge/pei_data.h
new file mode 100644
index 0000000..5026c8b
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/pei_data.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2011, Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef ASM_ARCH_PEI_DATA_H
+#define ASM_ARCH_PEI_DATA_H
+
+struct pch_usb3_controller_settings {
+ /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */
+ uint16_t mode;
+ /* 4 bit mask, 1: switchable, 0: not switchable */
+ uint16_t hs_port_switch_mask;
+ /* 0: No xHCI preOS driver, 1: xHCI preOS driver */
+ uint16_t preboot_support;
+ /* 0: Disable, 1: Enable */
+ uint16_t xhci_streams;
+};
+
+typedef asmlinkage void (*tx_byte_func)(unsigned char byte);
+
+#define PEI_VERSION 6
+
+struct __packed pei_data {
+ uint32_t pei_version;
+ uint32_t mchbar;
+ uint32_t dmibar;
+ uint32_t epbar;
+ uint32_t pciexbar;
+ uint16_t smbusbar;
+ uint32_t wdbbar;
+ uint32_t wdbsize;
+ uint32_t hpet_address;
+ uint32_t rcba;
+ uint32_t pmbase;
+ uint32_t gpiobase;
+ uint32_t thermalbase;
+ uint32_t system_type; /* 0 Mobile, 1 Desktop/Server */
+ uint32_t tseg_size;
+ uint8_t spd_addresses[4];
+ uint8_t ts_addresses[4];
+ int boot_mode;
+ int ec_present;
+ int gbe_enable;
+ /*
+ * 0 = leave channel enabled
+ * 1 = disable dimm 0 on channel
+ * 2 = disable dimm 1 on channel
+ * 3 = disable dimm 0+1 on channel
+ */
+ int dimm_channel0_disabled;
+ int dimm_channel1_disabled;
+ /* Seed values saved in CMOS */
+ uint32_t scrambler_seed;
+ uint32_t scrambler_seed_s3;
+ /* Data read from flash and passed into MRC */
+ unsigned char *mrc_input;
+ unsigned int mrc_input_len;
+ /* Data from MRC that should be saved to flash */
+ unsigned char *mrc_output;
+ unsigned int mrc_output_len;
+ /*
+ * Max frequency DDR3 could be ran at. Could be one of four values:
+ * 800, 1067, 1333, 1600
+ */
+ uint32_t max_ddr3_freq;
+ /*
+ * USB Port Configuration:
+ * [0] = enable
+ * [1] = overcurrent pin
+ * [2] = length
+ *
+ * Ports 0-7 can be mapped to OC0-OC3
+ * Ports 8-13 can be mapped to OC4-OC7
+ *
+ * Port Length
+ * MOBILE:
+ * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude)
+ * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude)
+ * DESKTOP:
+ * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude)
+ * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude)
+ * < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude)
+ */
+ uint16_t usb_port_config[16][3];
+ /* See the usb3 struct above for details */
+ struct pch_usb3_controller_settings usb3;
+ /*
+ * SPD data array for onboard RAM. Specify address 0xf0,
+ * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in
+ * spd_address for a given "DIMM".
+ */
+ uint8_t spd_data[4][256];
+ tx_byte_func tx_byte;
+ int ddr3lv_support;
+ /*
+ * pcie_init needs to be set to 1 to have the system agent initialise
+ * PCIe. Note: This should only be required if your system has Gen3
+ * devices and it will increase your boot time by at least 100ms.
+ */
+ int pcie_init;
+ /*
+ * N mode functionality. Leave this setting at 0.
+ * 0 Auto
+ * 1 1N
+ * 2 2N
+ */
+ int nmode;
+ /*
+ * DDR refresh rate config. JEDEC Standard No.21-C Annex K allows
+ * for DIMM SPD data to specify whether double-rate is required for
+ * extended operating temperature range.
+ * 0 Enable double rate based upon temperature thresholds
+ * 1 Normal rate
+ * 2 Always enable double rate
+ */
+ int ddr_refresh_rate_config;
+};
+
+#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
new file mode 100644
index 0000000..114ee19
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * From Coreboot file of the same name
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ACH_ASM_SANDYBRIDGE_H
+#define _ACH_ASM_SANDYBRIDGE_H
+
+/* Chipset types */
+#define SANDYBRIDGE_MOBILE 0
+#define SANDYBRIDGE_DESKTOP 1
+#define SANDYBRIDGE_SERVER 2
+
+/* Device ID for SandyBridge and IvyBridge */
+#define BASE_REV_SNB 0x00
+#define BASE_REV_IVB 0x50
+#define BASE_REV_MASK 0x50
+
+/* SandyBridge CPU stepping */
+#define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */
+#define SNB_STEP_D1 (BASE_REV_SNB + 6)
+#define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */
+
+/* IvyBridge CPU stepping */
+#define IVB_STEP_A0 (BASE_REV_IVB + 0)
+#define IVB_STEP_B0 (BASE_REV_IVB + 2)
+#define IVB_STEP_C0 (BASE_REV_IVB + 4)
+#define IVB_STEP_K0 (BASE_REV_IVB + 5)
+#define IVB_STEP_D0 (BASE_REV_IVB + 6)
+
+/* Intel Enhanced Debug region must be 4MB */
+#define IED_SIZE 0x400000
+
+/* Northbridge BARs */
+#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
+#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
+#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
+#define DEFAULT_RCBABASE 0xfed1c000
+/* 4 KB per PCIe device */
+#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
+
+/* Device 0:0.0 PCI configuration space (Host Bridge) */
+#define EPBAR 0x40
+#define MCHBAR 0x48
+#define PCIEXBAR 0x60
+#define DMIBAR 0x68
+#define X60BAR 0x60
+
+#define GGC 0x50 /* GMCH Graphics Control */
+
+#define DEVEN 0x54 /* Device Enable */
+#define DEVEN_PEG60 (1 << 13)
+#define DEVEN_IGD (1 << 4)
+#define DEVEN_PEG10 (1 << 3)
+#define DEVEN_PEG11 (1 << 2)
+#define DEVEN_PEG12 (1 << 1)
+#define DEVEN_HOST (1 << 0)
+
+#define PAM0 0x80
+#define PAM1 0x81
+#define PAM2 0x82
+#define PAM3 0x83
+#define PAM4 0x84
+#define PAM5 0x85
+#define PAM6 0x86
+
+#define LAC 0x87 /* Legacy Access Control */
+#define SMRAM 0x88 /* System Management RAM Control */
+#define D_OPEN (1 << 6)
+#define D_CLS (1 << 5)
+#define D_LCK (1 << 4)
+#define G_SMRAME (1 << 3)
+#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
+
+#define TOM 0xa0
+#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
+#define TSEG 0xb8 /* TSEG base */
+#define TOLUD 0xbc /* Top of Low Used Memory */
+
+#define SKPAD 0xdc /* Scratchpad Data */
+
+/* Device 0:1.0 PCI configuration space (PCI Express) */
+#define BCTRL1 0x3e /* 16bit */
+
+/* Device 0:2.0 PCI configuration space (Graphics Device) */
+
+#define MSAC 0x62 /* Multi Size Aperture Control */
+#define SWSCI 0xe8 /* SWSCI enable */
+#define ASLS 0xfc /* OpRegion Base */
+
+/*
+ * MCHBAR
+ */
+#define MCHBAR_REG(reg) (DEFAULT_RCBA + (reg))
+
+#define SSKPD 0x5d14 /* 16bit (scratchpad) */
+#define BIOS_RESET_CPL 0x5da8 /* 8bit */
+
+void report_platform_info(void);
+
+void sandybridge_early_init(int chipset_type);
+
+#endif
diff --git a/arch/x86/include/asm/config.h b/arch/x86/include/asm/config.h
index ff15828..c97d988 100644
--- a/arch/x86/include/asm/config.h
+++ b/arch/x86/include/asm/config.h
@@ -10,5 +10,6 @@
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+#define asmlinkage __attribute__((regparm(0)))
#endif
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 6c6774a..c839291 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -1,16 +1,160 @@
/*
* Copyright (c) 2014 The Chromium OS Authors.
*
+ * Part of this file is adapted from coreboot
+ * src/arch/x86/include/arch/cpu.h and
+ * src/arch/x86/lib/cpu.c
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
+
+#ifndef _ASM_CPU_H
+#define _ASM_CPU_H
+
+enum {
+ X86_VENDOR_INVALID = 0,
+ X86_VENDOR_INTEL,
+ X86_VENDOR_CYRIX,
+ X86_VENDOR_AMD,
+ X86_VENDOR_UMC,
+ X86_VENDOR_NEXGEN,
+ X86_VENDOR_CENTAUR,
+ X86_VENDOR_RISE,
+ X86_VENDOR_TRANSMETA,
+ X86_VENDOR_NSC,
+ X86_VENDOR_SIS,
+ X86_VENDOR_ANY = 0xfe,
+ X86_VENDOR_UNKNOWN = 0xff
+};
+
+struct cpuid_result {
+ uint32_t eax;
+ uint32_t ebx;
+ uint32_t ecx;
+ uint32_t edx;
+};
+
+/*
+ * Generic CPUID function
+ */
+static inline struct cpuid_result cpuid(int op)
+{
+ struct cpuid_result result;
+ asm volatile(
+ "mov %%ebx, %%edi;"
+ "cpuid;"
+ "mov %%ebx, %%esi;"
+ "mov %%edi, %%ebx;"
+ : "=a" (result.eax),
+ "=S" (result.ebx),
+ "=c" (result.ecx),
+ "=d" (result.edx)
+ : "0" (op)
+ : "edi");
+ return result;
+}
+
+/*
+ * Generic Extended CPUID function
+ */
+static inline struct cpuid_result cpuid_ext(int op, unsigned ecx)
+{
+ struct cpuid_result result;
+ asm volatile(
+ "mov %%ebx, %%edi;"
+ "cpuid;"
+ "mov %%ebx, %%esi;"
+ "mov %%edi, %%ebx;"
+ : "=a" (result.eax),
+ "=S" (result.ebx),
+ "=c" (result.ecx),
+ "=d" (result.edx)
+ : "0" (op), "2" (ecx)
+ : "edi");
+ return result;
+}
-#ifndef __X86_CPU_H
-#define __X86_CPU_H
+/*
+ * CPUID functions returning a single datum
+ */
+static inline unsigned int cpuid_eax(unsigned int op)
+{
+ unsigned int eax;
+
+ __asm__("mov %%ebx, %%edi;"
+ "cpuid;"
+ "mov %%edi, %%ebx;"
+ : "=a" (eax)
+ : "0" (op)
+ : "ecx", "edx", "edi");
+ return eax;
+}
+
+static inline unsigned int cpuid_ebx(unsigned int op)
+{
+ unsigned int eax, ebx;
+
+ __asm__("mov %%ebx, %%edi;"
+ "cpuid;"
+ "mov %%ebx, %%esi;"
+ "mov %%edi, %%ebx;"
+ : "=a" (eax), "=S" (ebx)
+ : "0" (op)
+ : "ecx", "edx", "edi");
+ return ebx;
+}
+
+static inline unsigned int cpuid_ecx(unsigned int op)
+{
+ unsigned int eax, ecx;
+
+ __asm__("mov %%ebx, %%edi;"
+ "cpuid;"
+ "mov %%edi, %%ebx;"
+ : "=a" (eax), "=c" (ecx)
+ : "0" (op)
+ : "edx", "edi");
+ return ecx;
+}
+
+static inline unsigned int cpuid_edx(unsigned int op)
+{
+ unsigned int eax, edx;
- /**
+ __asm__("mov %%ebx, %%edi;"
+ "cpuid;"
+ "mov %%edi, %%ebx;"
+ : "=a" (eax), "=d" (edx)
+ : "0" (op)
+ : "ecx", "edi");
+ return edx;
+}
+
+/* Standard macro to see if a specific flag is changeable */
+static inline int flag_is_changeable_p(uint32_t flag)
+{
+ uint32_t f1, f2;
+
+ asm(
+ "pushfl\n\t"
+ "pushfl\n\t"
+ "popl %0\n\t"
+ "movl %0,%1\n\t"
+ "xorl %2,%0\n\t"
+ "pushl %0\n\t"
+ "popfl\n\t"
+ "pushfl\n\t"
+ "popl %0\n\t"
+ "popfl\n\t"
+ : "=&r" (f1), "=&r" (f2)
+ : "ir" (flag));
+ return ((f1^f2) & flag) != 0;
+}
+
+/**
* cpu_enable_paging_pae() - Enable PAE-paging
*
- * @pdpt: Value to set in cr3 (PDPT or PML4T)
+ * @cr3: Value to set in cr3 (PDPT or PML4T)
*/
void cpu_enable_paging_pae(ulong cr3);
@@ -27,6 +171,27 @@
int cpu_has_64bit(void);
/**
+ * cpu_vendor_name() - Get CPU vendor name
+ *
+ * @vendor: CPU vendor enumeration number
+ *
+ * @return: Address to hold the CPU vendor name string
+ */
+const char *cpu_vendor_name(int vendor);
+
+#define CPU_MAX_NAME_LEN 49
+
+/**
+ * cpu_get_name() - Get the name of the current cpu
+ *
+ * @name: Place to put name, which must be CPU_MAX_NAME_LEN bytes including
+ * @return pointer to name, which will likely be a few bytes after the start
+ * of @name
+ * \0 terminator
+ */
+char *cpu_get_name(char *name);
+
+/**
* cpu_call64() - Jump to a 64-bit Linux kernel (internal function)
*
* The kernel is uncompressed and the 64-bit entry point is expected to be
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 3e8e2cd..48bbd1a 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -10,13 +10,43 @@
#ifndef __ASSEMBLY__
+enum pei_boot_mode_t {
+ PEI_BOOT_NONE = 0,
+ PEI_BOOT_SOFT_RESET,
+ PEI_BOOT_RESUME,
+
+};
+
+struct memory_area {
+ uint64_t start;
+ uint64_t size;
+};
+
+struct memory_info {
+ int num_areas;
+ uint64_t total_memory;
+ uint64_t total_32bit_memory;
+ struct memory_area area[CONFIG_NR_DRAM_BANKS];
+};
+
/* Architecture-specific global data */
struct arch_global_data {
struct global_data *gd_addr; /* Location of Global Data */
+ uint8_t x86; /* CPU family */
+ uint8_t x86_vendor; /* CPU vendor */
+ uint8_t x86_model;
+ uint8_t x86_mask;
+ uint32_t x86_device;
uint64_t tsc_base; /* Initial value returned by rdtsc() */
uint32_t tsc_base_kclocks; /* Initial tsc as a kclocks value */
uint32_t tsc_prev; /* For show_boot_progress() */
+ uint32_t tsc_mhz; /* TSC frequency in MHz */
void *new_fdt; /* Relocated FDT */
+ uint32_t bist; /* Built-in self test value */
+ struct pci_controller *hose; /* PCI hose for early use */
+ enum pei_boot_mode_t pei_boot_mode;
+ const struct pch_gpio_map *gpio_map; /* board GPIO map */
+ struct memory_info meminfo; /* Memory information */
};
#endif
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 8bda414..5540d42 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -1,12 +1,152 @@
/*
* Copyright (c) 2012, Google Inc. All rights reserved.
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _X86_GPIO_H_
#define _X86_GPIO_H_
+#include <linux/compiler.h>
#include <asm/arch/gpio.h>
#include <asm-generic/gpio.h>
+struct ich6_bank_platdata {
+ uint32_t base_addr;
+ const char *bank_name;
+};
+
+#define GPIO_MODE_NATIVE 0
+#define GPIO_MODE_GPIO 1
+#define GPIO_MODE_NONE 1
+
+#define GPIO_DIR_OUTPUT 0
+#define GPIO_DIR_INPUT 1
+
+#define GPIO_NO_INVERT 0
+#define GPIO_INVERT 1
+
+#define GPIO_LEVEL_LOW 0
+#define GPIO_LEVEL_HIGH 1
+
+#define GPIO_NO_BLINK 0
+#define GPIO_BLINK 1
+
+#define GPIO_RESET_PWROK 0
+#define GPIO_RESET_RSMRST 1
+
+struct pch_gpio_set1 {
+ u32 gpio0:1;
+ u32 gpio1:1;
+ u32 gpio2:1;
+ u32 gpio3:1;
+ u32 gpio4:1;
+ u32 gpio5:1;
+ u32 gpio6:1;
+ u32 gpio7:1;
+ u32 gpio8:1;
+ u32 gpio9:1;
+ u32 gpio10:1;
+ u32 gpio11:1;
+ u32 gpio12:1;
+ u32 gpio13:1;
+ u32 gpio14:1;
+ u32 gpio15:1;
+ u32 gpio16:1;
+ u32 gpio17:1;
+ u32 gpio18:1;
+ u32 gpio19:1;
+ u32 gpio20:1;
+ u32 gpio21:1;
+ u32 gpio22:1;
+ u32 gpio23:1;
+ u32 gpio24:1;
+ u32 gpio25:1;
+ u32 gpio26:1;
+ u32 gpio27:1;
+ u32 gpio28:1;
+ u32 gpio29:1;
+ u32 gpio30:1;
+ u32 gpio31:1;
+} __packed;
+
+struct pch_gpio_set2 {
+ u32 gpio32:1;
+ u32 gpio33:1;
+ u32 gpio34:1;
+ u32 gpio35:1;
+ u32 gpio36:1;
+ u32 gpio37:1;
+ u32 gpio38:1;
+ u32 gpio39:1;
+ u32 gpio40:1;
+ u32 gpio41:1;
+ u32 gpio42:1;
+ u32 gpio43:1;
+ u32 gpio44:1;
+ u32 gpio45:1;
+ u32 gpio46:1;
+ u32 gpio47:1;
+ u32 gpio48:1;
+ u32 gpio49:1;
+ u32 gpio50:1;
+ u32 gpio51:1;
+ u32 gpio52:1;
+ u32 gpio53:1;
+ u32 gpio54:1;
+ u32 gpio55:1;
+ u32 gpio56:1;
+ u32 gpio57:1;
+ u32 gpio58:1;
+ u32 gpio59:1;
+ u32 gpio60:1;
+ u32 gpio61:1;
+ u32 gpio62:1;
+ u32 gpio63:1;
+} __packed;
+
+struct pch_gpio_set3 {
+ u32 gpio64:1;
+ u32 gpio65:1;
+ u32 gpio66:1;
+ u32 gpio67:1;
+ u32 gpio68:1;
+ u32 gpio69:1;
+ u32 gpio70:1;
+ u32 gpio71:1;
+ u32 gpio72:1;
+ u32 gpio73:1;
+ u32 gpio74:1;
+ u32 gpio75:1;
+} __packed;
+
+/*
+ * This hilariously complex structure came from Coreboot. The
+ * setup_pch_gpios() function uses it. It could be move to device tree, or
+ * adjust to use masks instead of bitfields.
+ */
+struct pch_gpio_map {
+ struct {
+ const struct pch_gpio_set1 *mode;
+ const struct pch_gpio_set1 *direction;
+ const struct pch_gpio_set1 *level;
+ const struct pch_gpio_set1 *reset;
+ const struct pch_gpio_set1 *invert;
+ const struct pch_gpio_set1 *blink;
+ } set1;
+ struct {
+ const struct pch_gpio_set2 *mode;
+ const struct pch_gpio_set2 *direction;
+ const struct pch_gpio_set2 *level;
+ const struct pch_gpio_set2 *reset;
+ } set2;
+ struct {
+ const struct pch_gpio_set3 *mode;
+ const struct pch_gpio_set3 *direction;
+ const struct pch_gpio_set3 *level;
+ const struct pch_gpio_set3 *reset;
+ } set3;
+};
+
+void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
+
#endif /* _X86_GPIO_H_ */
diff --git a/arch/x86/include/asm/i8254.h b/arch/x86/include/asm/i8254.h
index c3ccd4f..4116de1 100644
--- a/arch/x86/include/asm/i8254.h
+++ b/arch/x86/include/asm/i8254.h
@@ -36,4 +36,7 @@
#define PIT_CMD_MODE4 0x08 /* Select mode 4 */
#define PIT_CMD_MODE5 0x0A /* Select mode 5 */
+/* The clock frequency of the i8253/i8254 PIT */
+#define PIT_TICK_RATE 1193182ul
+
#endif
diff --git a/arch/x86/include/asm/init_helpers.h b/arch/x86/include/asm/init_helpers.h
index b07887e..8cbe08e 100644
--- a/arch/x86/include/asm/init_helpers.h
+++ b/arch/x86/include/asm/init_helpers.h
@@ -13,7 +13,5 @@
int init_cache_f_r(void);
int init_bd_struct_r(void);
int init_func_spi(void);
-int find_fdt(void);
-int prepare_fdt(void);
#endif /* !_INIT_HELPERS_H_ */
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index 86bac90..fcd9aa9 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -69,6 +69,55 @@
#define memcpy_fromio(a,b,c) memcpy((a),(b),(c))
#define memcpy_toio(a,b,c) memcpy((a),(b),(c))
+#define write_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
+#define read_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
+
+#define write_le64(a, v) write_arch(q, le64, a, v)
+#define write_le32(a, v) write_arch(l, le32, a, v)
+#define write_le16(a, v) write_arch(w, le16, a, v)
+
+#define read_le64(a) read_arch(q, le64, a)
+#define read_le32(a) read_arch(l, le32, a)
+#define read_le16(a) read_arch(w, le16, a)
+
+#define write_be32(a, v) write_arch(l, be32, a, v)
+#define write_be16(a, v) write_arch(w, be16, a, v)
+
+#define read_be32(a) read_arch(l, be32, a)
+#define read_be16(a) read_arch(w, be16, a)
+
+#define write_8(a, v) __raw_writeb(v, a)
+#define read_8(a) __raw_readb(a)
+
+#define clrbits(type, addr, clear) \
+ write_##type((addr), read_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+ write_##type((addr), read_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+ write_##type((addr), (read_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
/*
* ISA space is 'always mapped' on a typical x86 system, no need to
* explicitly ioremap() it. The fact that the ISA IO space is mapped
diff --git a/arch/x86/include/asm/lapic.h b/arch/x86/include/asm/lapic.h
new file mode 100644
index 0000000..948e643
--- /dev/null
+++ b/arch/x86/include/asm/lapic.h
@@ -0,0 +1,59 @@
+/*
+ * From Coreboot file of same name
+ *
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ARCH_ASM_LAPIC_H
+#define _ARCH_ASM_LAPIC_H
+
+#include <asm/io.h>
+#include <asm/lapic_def.h>
+#include <asm/msr.h>
+#include <asm/processor.h>
+
+static inline __attribute__((always_inline))
+ unsigned long lapic_read(unsigned long reg)
+{
+ return readl(LAPIC_DEFAULT_BASE + reg);
+}
+
+static inline __attribute__((always_inline))
+ void lapic_write(unsigned long reg, unsigned long val)
+{
+ writel(val, LAPIC_DEFAULT_BASE + reg);
+}
+
+static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void)
+{
+ do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY);
+}
+
+static inline void enable_lapic(void)
+{
+ msr_t msr;
+
+ msr = msr_read(LAPIC_BASE_MSR);
+ msr.hi &= 0xffffff00;
+ msr.lo &= 0x000007ff;
+ msr.lo |= LAPIC_DEFAULT_BASE | (1 << 11);
+ msr_write(LAPIC_BASE_MSR, msr);
+}
+
+static inline void disable_lapic(void)
+{
+ msr_t msr;
+
+ msr = msr_read(LAPIC_BASE_MSR);
+ msr.lo &= ~(1 << 11);
+ msr_write(LAPIC_BASE_MSR, msr);
+}
+
+static inline __attribute__((always_inline)) unsigned long lapicid(void)
+{
+ return lapic_read(LAPIC_ID) >> 24;
+}
+
+#endif
diff --git a/arch/x86/include/asm/lapic_def.h b/arch/x86/include/asm/lapic_def.h
new file mode 100644
index 0000000..722cead
--- /dev/null
+++ b/arch/x86/include/asm/lapic_def.h
@@ -0,0 +1,101 @@
+/*
+ * Taken from the Coreboot file of the same name
+ *
+ * (C) Copyright 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ASM_LAPIC_DEF_H
+#define _ASM_LAPIC_DEF_H
+
+#define LAPIC_BASE_MSR 0x1B
+#define LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR (1 << 8)
+#define LAPIC_BASE_MSR_ENABLE (1 << 11)
+#define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000
+
+#define LOCAL_APIC_ADDR 0xfee00000
+#define LAPIC_DEFAULT_BASE LOCAL_APIC_ADDR
+
+#define LAPIC_ID 0x020
+#define LAPIC_LVR 0x030
+#define LAPIC_TASKPRI 0x80
+#define LAPIC_TPRI_MASK 0xFF
+#define LAPIC_ARBID 0x090
+#define LAPIC_RRR 0x0C0
+#define LAPIC_SVR 0x0f0
+#define LAPIC_SPIV 0x0f0
+#define LAPIC_SPIV_ENABLE 0x100
+#define LAPIC_ESR 0x280
+#define LAPIC_ESR_SEND_CS 0x00001
+#define LAPIC_ESR_RECV_CS 0x00002
+#define LAPIC_ESR_SEND_ACC 0x00004
+#define LAPIC_ESR_RECV_ACC 0x00008
+#define LAPIC_ESR_SENDILL 0x00020
+#define LAPIC_ESR_RECVILL 0x00040
+#define LAPIC_ESR_ILLREGA 0x00080
+#define LAPIC_ICR 0x300
+#define LAPIC_DEST_SELF 0x40000
+#define LAPIC_DEST_ALLINC 0x80000
+#define LAPIC_DEST_ALLBUT 0xC0000
+#define LAPIC_ICR_RR_MASK 0x30000
+#define LAPIC_ICR_RR_INVALID 0x00000
+#define LAPIC_ICR_RR_INPROG 0x10000
+#define LAPIC_ICR_RR_VALID 0x20000
+#define LAPIC_INT_LEVELTRIG 0x08000
+#define LAPIC_INT_ASSERT 0x04000
+#define LAPIC_ICR_BUSY 0x01000
+#define LAPIC_DEST_LOGICAL 0x00800
+#define LAPIC_DM_FIXED 0x00000
+#define LAPIC_DM_LOWEST 0x00100
+#define LAPIC_DM_SMI 0x00200
+#define LAPIC_DM_REMRD 0x00300
+#define LAPIC_DM_NMI 0x00400
+#define LAPIC_DM_INIT 0x00500
+#define LAPIC_DM_STARTUP 0x00600
+#define LAPIC_DM_EXTINT 0x00700
+#define LAPIC_VECTOR_MASK 0x000FF
+#define LAPIC_ICR2 0x310
+#define GET_LAPIC_DEST_FIELD(x) (((x) >> 24) & 0xFF)
+#define SET_LAPIC_DEST_FIELD(x) ((x) << 24)
+#define LAPIC_LVTT 0x320
+#define LAPIC_LVTPC 0x340
+#define LAPIC_LVT0 0x350
+#define LAPIC_LVT_TIMER_BASE_MASK (0x3 << 18)
+#define GET_LAPIC_TIMER_BASE(x) (((x) >> 18) & 0x3)
+#define SET_LAPIC_TIMER_BASE(x) (((x) << 18))
+#define LAPIC_TIMER_BASE_CLKIN 0x0
+#define LAPIC_TIMER_BASE_TMBASE 0x1
+#define LAPIC_TIMER_BASE_DIV 0x2
+#define LAPIC_LVT_TIMER_PERIODIC (1 << 17)
+#define LAPIC_LVT_MASKED (1 << 16)
+#define LAPIC_LVT_LEVEL_TRIGGER (1 << 15)
+#define LAPIC_LVT_REMOTE_IRR (1 << 14)
+#define LAPIC_INPUT_POLARITY (1 << 13)
+#define LAPIC_SEND_PENDING (1 << 12)
+#define LAPIC_LVT_RESERVED_1 (1 << 11)
+#define LAPIC_DELIVERY_MODE_MASK (7 << 8)
+#define LAPIC_DELIVERY_MODE_FIXED (0 << 8)
+#define LAPIC_DELIVERY_MODE_NMI (4 << 8)
+#define LAPIC_DELIVERY_MODE_EXTINT (7 << 8)
+#define GET_LAPIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7)
+#define SET_LAPIC_DELIVERY_MODE(x, y) (((x) & ~0x700)|((y) << 8))
+#define LAPIC_MODE_FIXED 0x0
+#define LAPIC_MODE_NMI 0x4
+#define LAPIC_MODE_EXINT 0x7
+#define LAPIC_LVT1 0x360
+#define LAPIC_LVTERR 0x370
+#define LAPIC_TMICT 0x380
+#define LAPIC_TMCCT 0x390
+#define LAPIC_TDCR 0x3E0
+#define LAPIC_TDR_DIV_TMBASE (1 << 2)
+#define LAPIC_TDR_DIV_1 0xB
+#define LAPIC_TDR_DIV_2 0x0
+#define LAPIC_TDR_DIV_4 0x1
+#define LAPIC_TDR_DIV_8 0x2
+#define LAPIC_TDR_DIV_16 0x3
+#define LAPIC_TDR_DIV_32 0x8
+#define LAPIC_TDR_DIV_64 0x9
+#define LAPIC_TDR_DIV_128 0xA
+
+#endif
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 3b5915d..df43983 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -175,6 +175,25 @@
return native_wrmsr_safe_regs(regs);
}
+typedef struct msr_t {
+ uint32_t lo;
+ uint32_t hi;
+} msr_t;
+
+static inline struct msr_t msr_read(unsigned msr_num)
+{
+ struct msr_t msr;
+
+ rdmsr(msr_num, msr.lo, msr.hi);
+
+ return msr;
+}
+
+static inline void msr_write(unsigned msr_num, msr_t msr)
+{
+ wrmsr(msr_num, msr.lo, msr.hi);
+}
+
#define rdtscl(low) \
((low) = (u32)__native_read_tsc())
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
new file mode 100644
index 0000000..5f05a48
--- /dev/null
+++ b/arch/x86/include/asm/mtrr.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * From Coreboot file of the same name
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_MTRR_H
+#define _ASM_MTRR_H
+
+/* These are the region types */
+#define MTRR_TYPE_UNCACHEABLE 0
+#define MTRR_TYPE_WRCOMB 1
+/*#define MTRR_TYPE_ 2*/
+/*#define MTRR_TYPE_ 3*/
+#define MTRR_TYPE_WRTHROUGH 4
+#define MTRR_TYPE_WRPROT 5
+#define MTRR_TYPE_WRBACK 6
+#define MTRR_NUM_TYPES 7
+
+#define MTRRcap_MSR 0x0fe
+#define MTRRdefType_MSR 0x2ff
+
+#define MTRRdefTypeEn (1 << 11)
+#define MTRRdefTypeFixEn (1 << 10)
+
+#define SMRRphysBase_MSR 0x1f2
+#define SMRRphysMask_MSR 0x1f3
+
+#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
+#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
+
+#define MTRRphysMaskValid (1 << 11)
+
+#define NUM_FIXED_RANGES 88
+#define RANGES_PER_FIXED_MTRR 8
+#define MTRRfix64K_00000_MSR 0x250
+#define MTRRfix16K_80000_MSR 0x258
+#define MTRRfix16K_A0000_MSR 0x259
+#define MTRRfix4K_C0000_MSR 0x268
+#define MTRRfix4K_C8000_MSR 0x269
+#define MTRRfix4K_D0000_MSR 0x26a
+#define MTRRfix4K_D8000_MSR 0x26b
+#define MTRRfix4K_E0000_MSR 0x26c
+#define MTRRfix4K_E8000_MSR 0x26d
+#define MTRRfix4K_F0000_MSR 0x26e
+#define MTRRfix4K_F8000_MSR 0x26f
+
+#if !defined(__ASSEMBLER__)
+
+/*
+ * The MTRR code has some side effects that the callers should be aware for.
+ * 1. The call sequence matters. x86_setup_mtrrs() calls
+ * x86_setup_fixed_mtrrs_no_enable() then enable_fixed_mtrrs() (equivalent
+ * of x86_setup_fixed_mtrrs()) then x86_setup_var_mtrrs(). If the callers
+ * want to call the components of x86_setup_mtrrs() because of other
+ * rquirements the ordering should still preserved.
+ * 2. enable_fixed_mtrr() will enable both variable and fixed MTRRs because
+ * of the nature of the global MTRR enable flag. Therefore, all direct
+ * or indirect callers of enable_fixed_mtrr() should ensure that the
+ * variable MTRR MSRs do not contain bad ranges.
+ * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling
+ * the caching of the ROM. However, it is set to uncacheable (UC). It
+ * is the responsiblity of the caller to enable it by calling
+ * x86_mtrr_enable_rom_caching().
+ */
+void x86_setup_mtrrs(void);
+/*
+ * x86_setup_var_mtrrs() parameters:
+ * address_bits - number of physical address bits supported by cpu
+ * above4gb - 2 means dynamically detect number of variable MTRRs available.
+ * non-zero means handle memory ranges above 4GiB.
+ * 0 means ignore memory ranges above 4GiB
+ */
+void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb);
+void enable_fixed_mtrr(void);
+void x86_setup_fixed_mtrrs(void);
+/* Set up fixed MTRRs but do not enable them. */
+void x86_setup_fixed_mtrrs_no_enable(void);
+int x86_mtrr_check(void);
+/* ROM caching can be used after variable MTRRs are set up. Beware that
+ * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on
+ * one's IO hole size and WRCOMB resources. Be sure to check the console
+ * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that
+ * on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the
+ * rom caching will be disabled if all threads run the MTRR code. Therefore,
+ * one needs to call x86_mtrr_enable_rom_caching() after all threads of the
+ * same core have run the MTRR code. */
+#if CONFIG_CACHE_ROM
+void x86_mtrr_enable_rom_caching(void);
+void x86_mtrr_disable_rom_caching(void);
+/* Return the variable range MTRR index of the ROM cache. */
+long x86_mtrr_rom_cache_var_index(void);
+#else
+static inline void x86_mtrr_enable_rom_caching(void) {}
+static inline void x86_mtrr_disable_rom_caching(void) {}
+static inline long x86_mtrr_rom_cache_var_index(void) { return -1; }
+#endif /* CONFIG_CACHE_ROM */
+
+#endif
+
+#if !defined(CONFIG_RAMTOP)
+# error "CONFIG_RAMTOP not defined"
+#endif
+
+#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
+# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
+#endif
+
+#if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0)
+# error "CONFIG_CACHE_ROM_SIZE is not a power of 2"
+#endif
+
+#define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12)
+
+#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
+# error "CONFIG_RAMTOP must be a power of 2"
+#endif
+
+#endif
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index 6b16188..98817aa 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -12,5 +12,38 @@
#define DEFINE_PCI_DEVICE_TABLE(_table) \
const struct pci_device_id _table[]
+struct pci_controller;
+
void pci_setup_type1(struct pci_controller *hose);
+
+/**
+ * board_pci_setup_hose() - Set up the PCI hose
+ *
+ * This is called by the common x86 PCI code to set up the PCI controller
+ * hose. It may be called when no memory/BSS is available so should just
+ * store things in 'hose' and not in BSS variables.
+ */
+void board_pci_setup_hose(struct pci_controller *hose);
+
+/**
+ * pci_early_init_hose() - Set up PCI host before relocation
+ *
+ * This allocates memory for, sets up and returns the PCI hose. It can be
+ * called before relocation. The hose will be stored in gd->arch.hose for
+ * later use, but will become invalid one DRAM is available.
+ */
+int pci_early_init_hose(struct pci_controller **hosep);
+
+/*
+ * Simple PCI access routines - these work from either the early PCI hose
+ * or the 'real' one, created after U-Boot has memory available
+ */
+unsigned int pci_read_config8(pci_dev_t dev, unsigned where);
+unsigned int pci_read_config16(pci_dev_t dev, unsigned where);
+unsigned int pci_read_config32(pci_dev_t dev, unsigned where);
+
+void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value);
+void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value);
+void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value);
+
#endif
diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h
new file mode 100644
index 0000000..ce68839
--- /dev/null
+++ b/arch/x86/include/asm/post.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _post_h
+#define _post_h
+
+/* port to use for post codes */
+#define POST_PORT 0x80
+
+/* post codes which represent various stages of init */
+#define POST_START 0x1e
+#define POST_CAR_START 0x1f
+#define POST_CAR_SIPI 0x20
+#define POST_CAR_MTRR 0x21
+#define POST_CAR_UNCACHEABLE 0x22
+#define POST_CAR_BASE_ADDRESS 0x23
+#define POST_CAR_MASK 0x24
+#define POST_CAR_FILL 0x25
+#define POST_CAR_ROM_CACHE 0x26
+#define POST_CAR_MRC_CACHE 0x27
+#define POST_CAR_CPU_CACHE 0x28
+#define POST_START_STACK 0x29
+#define POST_START_DONE 0x2a
+#define POST_CPU_INIT 0x2b
+#define POST_EARLY_INIT 0x2c
+#define POST_CPU_INFO 0x2d
+#define POST_PRE_MRC 0x2e
+#define POST_MRC 0x2f
+#define POST_DRAM 0x2f
+
+#define POST_RAM_FAILURE 0xea
+
+/* Output a post code using al - value must be 0 to 0xff */
+#ifdef __ASSEMBLY__
+#define post_code(value) \
+ movb $value, %al; \
+ outb %al, $POST_PORT
+#else
+#include <asm/io.h>
+
+static inline void post_code(int code)
+{
+ outb(code, POST_PORT);
+}
+#endif
+
+#endif
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index bb3172f..b9317cb 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -30,4 +30,25 @@
#define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE)
+#ifndef __ASSEMBLY__
+
+#define PORT_RESET 0xcf9
+
+static inline __attribute__((always_inline)) void cpu_hlt(void)
+{
+ asm("hlt");
+}
+
+static inline ulong cpu_get_sp(void)
+{
+ ulong result;
+
+ asm volatile(
+ "mov %%esp, %%eax"
+ : "=a" (result));
+ return result;
+}
+
+#endif /* __ASSEMBLY__ */
+
#endif
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index 9e525dd..98217dd 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -9,6 +9,7 @@
#define _U_BOOT_I386_H_ 1
/* cpu/.../cpu.c */
+int arch_cpu_init(void);
int x86_cpu_init_r(void);
int cpu_init_r(void);
int x86_cpu_init_f(void);
@@ -27,8 +28,8 @@
void timer_set_base(uint64_t base);
int pcat_timer_init(void);
-/* Architecture specific - can be in arch/x86/cpu/, arch/x86/lib/, or $(BOARD)/ */
-int dram_init_f(void);
+/* Architecture specific DRAM init */
+int dram_init(void);
/* cpu/.../interrupts.c */
int cpu_init_interrupts(void);
@@ -36,6 +37,16 @@
/* board/.../... */
int dram_init(void);
+int cleanup_before_linux(void);
+int x86_cleanup_before_linux(void);
+void x86_enable_caches(void);
+void x86_disable_caches(void);
+int x86_init_cache(void);
+void reset_cpu(ulong addr);
+ulong board_get_usable_ram_top(ulong total_size);
+void dram_init_banksize(void);
+int default_print_cpuinfo(void);
+
void setup_pcat_compatibility(void);
void isa_unmap_rom(u32 addr);
@@ -59,4 +70,6 @@
void timer_set_tsc_base(uint64_t new_base);
uint64_t timer_get_tsc(void);
+void quick_ram_check(void);
+
#endif /* _U_BOOT_I386_H_ */
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 25b672a..e146e64 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -15,6 +15,7 @@
obj-$(CONFIG_PCI) += pci_type1.o
obj-y += relocate.o
obj-y += physmem.o
+obj-$(CONFIG_X86_RAMTEST) += ramtest.o
obj-y += string.o
obj-$(CONFIG_SYS_X86_TSC_TIMER) += tsc_timer.o
obj-$(CONFIG_VIDEO_VGA) += video.o
diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index b5d937f..be4eb12 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -87,30 +87,3 @@
puts("ready\n");
return 0;
}
-
-int find_fdt(void)
-{
-#ifdef CONFIG_OF_EMBED
- /* Get a pointer to the FDT */
- gd->fdt_blob = __dtb_dt_begin;
-#elif defined CONFIG_OF_SEPARATE
- /* FDT is at end of image */
- gd->fdt_blob = (ulong *)&_end;
-#endif
- /* Allow the early environment to override the fdt address */
- gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
- (uintptr_t)gd->fdt_blob);
-
- return 0;
-}
-
-int prepare_fdt(void)
-{
- /* For now, put this check after the console is ready */
- if (fdtdec_prepare_fdt()) {
- panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
- "doc/README.fdt-control");
- }
-
- return 0;
-}
diff --git a/arch/x86/lib/ramtest.c b/arch/x86/lib/ramtest.c
new file mode 100644
index 0000000..c21be03
--- /dev/null
+++ b/arch/x86/lib/ramtest.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * From Coreboot src/lib/ramtest.c
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/post.h>
+
+static void write_phys(unsigned long addr, u32 value)
+{
+#if CONFIG_SSE2
+ asm volatile(
+ "movnti %1, (%0)"
+ : /* outputs */
+ : "r" (addr), "r" (value) /* inputs */
+ : /* clobbers */
+ );
+#else
+ writel(value, addr);
+#endif
+}
+
+static u32 read_phys(unsigned long addr)
+{
+ return readl(addr);
+}
+
+static void phys_memory_barrier(void)
+{
+#if CONFIG_SSE2
+ /* Needed for movnti */
+ asm volatile(
+ "sfence"
+ :
+ :
+ : "memory"
+ );
+#else
+ asm volatile(""
+ :
+ :
+ : "memory");
+#endif
+}
+
+void quick_ram_check(void)
+{
+ int fail = 0;
+ u32 backup;
+
+ backup = read_phys(CONFIG_RAMBASE);
+ write_phys(CONFIG_RAMBASE, 0x55555555);
+ phys_memory_barrier();
+ if (read_phys(CONFIG_RAMBASE) != 0x55555555)
+ fail = 1;
+ write_phys(CONFIG_RAMBASE, 0xaaaaaaaa);
+ phys_memory_barrier();
+ if (read_phys(CONFIG_RAMBASE) != 0xaaaaaaaa)
+ fail = 1;
+ write_phys(CONFIG_RAMBASE, 0x00000000);
+ phys_memory_barrier();
+ if (read_phys(CONFIG_RAMBASE) != 0x00000000)
+ fail = 1;
+ write_phys(CONFIG_RAMBASE, 0xffffffff);
+ phys_memory_barrier();
+ if (read_phys(CONFIG_RAMBASE) != 0xffffffff)
+ fail = 1;
+
+ write_phys(CONFIG_RAMBASE, backup);
+ if (fail) {
+ post_code(POST_RAM_FAILURE);
+ panic("RAM INIT FAILURE!\n");
+ }
+ phys_memory_barrier();
+}
diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c
index 8b38702..fb9afed 100644
--- a/arch/x86/lib/tsc_timer.c
+++ b/arch/x86/lib/tsc_timer.c
@@ -1,6 +1,9 @@
/*
* Copyright (c) 2012 The Chromium OS Authors.
*
+ * TSC calibration codes are adapted from Linux kernel
+ * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -12,8 +15,269 @@
#include <asm/msr.h>
#include <asm/u-boot-x86.h>
+/* CPU reference clock frequency: in KHz */
+#define FREQ_83 83200
+#define FREQ_100 99840
+#define FREQ_133 133200
+#define FREQ_166 166400
+
+#define MAX_NUM_FREQS 8
+
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * According to Intel 64 and IA-32 System Programming Guide,
+ * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
+ * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
+ * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
+ * so we need manually differentiate SoC families. This is what the
+ * field msr_plat does.
+ */
+struct freq_desc {
+ u8 x86_family; /* CPU family */
+ u8 x86_model; /* model */
+ /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
+ u8 msr_plat;
+ u32 freqs[MAX_NUM_FREQS];
+};
+
+static struct freq_desc freq_desc_tables[] = {
+ /* PNW */
+ { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
+ /* CLV+ */
+ { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
+ /* TNG */
+ { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
+ /* VLV2 */
+ { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
+ /* Ivybridge */
+ { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } },
+ /* ANN */
+ { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
+};
+
+static int match_cpu(u8 family, u8 model)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
+ if ((family == freq_desc_tables[i].x86_family) &&
+ (model == freq_desc_tables[i].x86_model))
+ return i;
+ }
+
+ return -1;
+}
+
+/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
+#define id_to_freq(cpu_index, freq_id) \
+ (freq_desc_tables[cpu_index].freqs[freq_id])
+
+/*
+ * Do MSR calibration only for known/supported CPUs.
+ *
+ * Returns the calibration value or 0 if MSR calibration failed.
+ */
+static unsigned long try_msr_calibrate_tsc(void)
+{
+ u32 lo, hi, ratio, freq_id, freq;
+ unsigned long res;
+ int cpu_index;
+
+ cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
+ if (cpu_index < 0)
+ return 0;
+
+ if (freq_desc_tables[cpu_index].msr_plat) {
+ rdmsr(MSR_PLATFORM_INFO, lo, hi);
+ ratio = (lo >> 8) & 0x1f;
+ } else {
+ rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
+ ratio = (hi >> 8) & 0x1f;
+ }
+ debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
+
+ if (!ratio)
+ goto fail;
+
+ if (freq_desc_tables[cpu_index].msr_plat == 2) {
+ /* TODO: Figure out how best to deal with this */
+ freq = FREQ_100;
+ debug("Using frequency: %u KHz\n", freq);
+ } else {
+ /* Get FSB FREQ ID */
+ rdmsr(MSR_FSB_FREQ, lo, hi);
+ freq_id = lo & 0x7;
+ freq = id_to_freq(cpu_index, freq_id);
+ debug("Resolved frequency ID: %u, frequency: %u KHz\n",
+ freq_id, freq);
+ }
+ if (!freq)
+ goto fail;
+
+ /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
+ res = freq * ratio / 1000;
+ debug("TSC runs at %lu MHz\n", res);
+
+ return res;
+
+fail:
+ debug("Fast TSC calibration using MSR failed\n");
+ return 0;
+}
+
+/*
+ * This reads the current MSB of the PIT counter, and
+ * checks if we are running on sufficiently fast and
+ * non-virtualized hardware.
+ *
+ * Our expectations are:
+ *
+ * - the PIT is running at roughly 1.19MHz
+ *
+ * - each IO is going to take about 1us on real hardware,
+ * but we allow it to be much faster (by a factor of 10) or
+ * _slightly_ slower (ie we allow up to a 2us read+counter
+ * update - anything else implies a unacceptably slow CPU
+ * or PIT for the fast calibration to work.
+ *
+ * - with 256 PIT ticks to read the value, we have 214us to
+ * see the same MSB (and overhead like doing a single TSC
+ * read per MSB value etc).
+ *
+ * - We're doing 2 reads per loop (LSB, MSB), and we expect
+ * them each to take about a microsecond on real hardware.
+ * So we expect a count value of around 100. But we'll be
+ * generous, and accept anything over 50.
+ *
+ * - if the PIT is stuck, and we see *many* more reads, we
+ * return early (and the next caller of pit_expect_msb()
+ * then consider it a failure when they don't see the
+ * next expected value).
+ *
+ * These expectations mean that we know that we have seen the
+ * transition from one expected value to another with a fairly
+ * high accuracy, and we didn't miss any events. We can thus
+ * use the TSC value at the transitions to calculate a pretty
+ * good value for the TSC frequencty.
+ */
+static inline int pit_verify_msb(unsigned char val)
+{
+ /* Ignore LSB */
+ inb(0x42);
+ return inb(0x42) == val;
+}
+
+static inline int pit_expect_msb(unsigned char val, u64 *tscp,
+ unsigned long *deltap)
+{
+ int count;
+ u64 tsc = 0, prev_tsc = 0;
+
+ for (count = 0; count < 50000; count++) {
+ if (!pit_verify_msb(val))
+ break;
+ prev_tsc = tsc;
+ tsc = rdtsc();
+ }
+ *deltap = rdtsc() - prev_tsc;
+ *tscp = tsc;
+
+ /*
+ * We require _some_ success, but the quality control
+ * will be based on the error terms on the TSC values.
+ */
+ return count > 5;
+}
+
+/*
+ * How many MSB values do we want to see? We aim for
+ * a maximum error rate of 500ppm (in practice the
+ * real error is much smaller), but refuse to spend
+ * more than 50ms on it.
+ */
+#define MAX_QUICK_PIT_MS 50
+#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
+
+static unsigned long quick_pit_calibrate(void)
+{
+ int i;
+ u64 tsc, delta;
+ unsigned long d1, d2;
+
+ /* Set the Gate high, disable speaker */
+ outb((inb(0x61) & ~0x02) | 0x01, 0x61);
+
+ /*
+ * Counter 2, mode 0 (one-shot), binary count
+ *
+ * NOTE! Mode 2 decrements by two (and then the
+ * output is flipped each time, giving the same
+ * final output frequency as a decrement-by-one),
+ * so mode 0 is much better when looking at the
+ * individual counts.
+ */
+ outb(0xb0, 0x43);
+
+ /* Start at 0xffff */
+ outb(0xff, 0x42);
+ outb(0xff, 0x42);
+
+ /*
+ * The PIT starts counting at the next edge, so we
+ * need to delay for a microsecond. The easiest way
+ * to do that is to just read back the 16-bit counter
+ * once from the PIT.
+ */
+ pit_verify_msb(0);
+
+ if (pit_expect_msb(0xff, &tsc, &d1)) {
+ for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
+ if (!pit_expect_msb(0xff-i, &delta, &d2))
+ break;
+
+ /*
+ * Iterate until the error is less than 500 ppm
+ */
+ delta -= tsc;
+ if (d1+d2 >= delta >> 11)
+ continue;
+
+ /*
+ * Check the PIT one more time to verify that
+ * all TSC reads were stable wrt the PIT.
+ *
+ * This also guarantees serialization of the
+ * last cycle read ('d2') in pit_expect_msb.
+ */
+ if (!pit_verify_msb(0xfe - i))
+ break;
+ goto success;
+ }
+ }
+ debug("Fast TSC calibration failed\n");
+ return 0;
+
+success:
+ /*
+ * Ok, if we get here, then we've seen the
+ * MSB of the PIT decrement 'i' times, and the
+ * error has shrunk to less than 500 ppm.
+ *
+ * As a result, we can depend on there not being
+ * any odd delays anywhere, and the TSC reads are
+ * reliable (within the error).
+ *
+ * kHz = ticks / time-in-seconds / 1000;
+ * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
+ * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
+ */
+ delta *= PIT_TICK_RATE;
+ delta /= (i*256*1000);
+ debug("Fast TSC calibration using PIT\n");
+ return delta / 1000;
+}
+
void timer_set_base(u64 base)
{
gd->arch.tsc_base = base;
@@ -34,17 +298,24 @@
return now_tick - gd->arch.tsc_base;
}
-#define PLATFORM_INFO_MSR 0xce
-
/* Get the speed of the TSC timer in MHz */
unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void)
{
- u32 ratio;
- u64 platform_info = native_read_msr(PLATFORM_INFO_MSR);
+ unsigned long fast_calibrate;
+
+ if (gd->arch.tsc_mhz)
+ return gd->arch.tsc_mhz;
+
+ fast_calibrate = try_msr_calibrate_tsc();
+ if (!fast_calibrate) {
+
+ fast_calibrate = quick_pit_calibrate();
+ if (!fast_calibrate)
+ panic("TSC frequency is ZERO");
+ }
- /* 100MHz times Max Non Turbo ratio */
- ratio = (platform_info >> 8) & 0xff;
- return 100 * ratio;
+ gd->arch.tsc_mhz = fast_calibrate;
+ return fast_calibrate;
}
unsigned long get_tbclk(void)
diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c
index b96ba81..ee1681b 100644
--- a/board/a3m071/a3m071.c
+++ b/board/a3m071/a3m071.c
@@ -392,9 +392,11 @@
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t * bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c
index d3d4c18..c5d161b 100644
--- a/board/a4m072/a4m072.c
+++ b/board/a4m072/a4m072.c
@@ -171,10 +171,11 @@
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index 79d4bab..c5cc4ff 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -490,9 +490,9 @@
#endif /* !defined(CONFIG_ARCHES) */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-extern void __ft_board_setup(void *blob, bd_t *bd);
+extern int __ft_board_setup(void *blob, bd_t *bd);
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
__ft_board_setup(blob, bd);
@@ -515,5 +515,7 @@
fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
"disabled", sizeof("disabled"), 1);
}
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 53f9b34..91c6cbf 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -10,6 +10,7 @@
*/
#include <common.h>
+#include <errno.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/ppc4xx.h>
@@ -363,7 +364,7 @@
* On NAND-booting sequoia, we need to patch the chips select numbers
* in the dtb (CS0 - NAND, CS3 - NOR)
*/
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int rc;
int len;
@@ -381,15 +382,14 @@
prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
if (prop == NULL) {
printf("Unable to update NOR chip select for NAND booting\n");
- return;
+ return -FDT_ERR_NOTFOUND;
}
reg = (u32 *)&prop->data[0];
reg[0] = 3;
rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
if (rc) {
- printf("Unable to update property NOR mappings, err=%s\n",
- fdt_strerror(rc));
- return;
+ printf("Unable to update property NOR mappings\n");
+ return rc;
}
/* And now configure NAND chip select to 0 instead of 3 */
@@ -398,15 +398,16 @@
prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
if (prop == NULL) {
printf("Unable to update NDFC chip select for NAND booting\n");
- return;
+ return len;
}
reg = (u32 *)&prop->data[0];
reg[0] = 0;
rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
if (rc) {
- printf("Unable to update property NDFC mappings, err=%s\n",
- fdt_strerror(rc));
- return;
+ printf("Unable to update property NDFC mapping\n");
+ return rc;
}
+
+ return 0;
}
#endif /* CONFIG_SYS_RAMBOOT */
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
index 007c1ef..93f3d65 100644
--- a/board/bachmann/ot1200/ot1200.c
+++ b/board/bachmann/ot1200/ot1200.c
@@ -173,7 +173,7 @@
int board_mmc_init(bd_t *bis)
{
- s32 status = 0;
+ int ret;
u32 index = 0;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
@@ -196,13 +196,15 @@
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
index + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return status;
+ return -EINVAL;
}
- status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ if (ret)
+ return ret;
}
- return status;
+ return 0;
}
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
diff --git a/board/bluewater/snapper9260/MAINTAINERS b/board/bluewater/snapper9260/MAINTAINERS
index ff1e997..1f8f4d6 100644
--- a/board/bluewater/snapper9260/MAINTAINERS
+++ b/board/bluewater/snapper9260/MAINTAINERS
@@ -1,5 +1,5 @@
SNAPPER9260 BOARD
-M: Ryan Mallon <ryan@bluewatersys.com>
+M: Simon Glass <sjg@chromium.org>
S: Maintained
F: board/bluewater/snapper9260/
F: include/configs/snapper9260.h
diff --git a/board/bluewater/snapper9260/snapper9260.c b/board/bluewater/snapper9260/snapper9260.c
index bfde129..95633b0 100644
--- a/board/bluewater/snapper9260/snapper9260.c
+++ b/board/bluewater/snapper9260/snapper9260.c
@@ -9,12 +9,15 @@
*/
#include <common.h>
+#include <dm.h>
#include <asm/io.h>
+#include <asm/gpio.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
+#include <asm/arch/atmel_serial.h>
#include <net.h>
#include <netdev.h>
#include <i2c.h>
@@ -95,10 +98,12 @@
&smc->cs[3].mode);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
+ gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
+ gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
int board_init(void)
@@ -140,3 +145,12 @@
void reset_phy(void)
{
}
+
+static struct atmel_serial_platdata at91sam9260_serial_plat = {
+ .base_addr = ATMEL_BASE_DBGU,
+};
+
+U_BOOT_DEVICE(at91sam9260_serial) = {
+ .name = "serial_atmel",
+ .platdata = &at91sam9260_serial_plat,
+};
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index fcd4d82..e8ea256 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -302,7 +302,7 @@
int board_mmc_init(bd_t *bis)
{
- s32 status = 0;
+ int ret;
u32 index = 0;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
@@ -325,13 +325,15 @@
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
index + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return status;
+ return -EINVAL;
}
- status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ if (ret)
+ return ret;
}
- return status;
+ return 0;
}
#endif
diff --git a/board/broadcom/bcm11130/MAINTAINERS b/board/broadcom/bcm11130/MAINTAINERS
new file mode 100644
index 0000000..b22e86f
--- /dev/null
+++ b/board/broadcom/bcm11130/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM11130 BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcm28155_ap/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm11130_defconfig
diff --git a/board/broadcom/bcm11130_nand/MAINTAINERS b/board/broadcom/bcm11130_nand/MAINTAINERS
new file mode 100644
index 0000000..881db5b
--- /dev/null
+++ b/board/broadcom/bcm11130_nand/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM11130_NAND BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcm28155_ap/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm11130_nand_defconfig
diff --git a/board/broadcom/bcm911360_entphn-ns/MAINTAINERS b/board/broadcom/bcm911360_entphn-ns/MAINTAINERS
new file mode 100644
index 0000000..b5f0207
--- /dev/null
+++ b/board/broadcom/bcm911360_entphn-ns/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM911360_ENTPHN-NS BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm911360_entphn-ns_defconfig
diff --git a/board/broadcom/bcm911360_entphn/MAINTAINERS b/board/broadcom/bcm911360_entphn/MAINTAINERS
new file mode 100644
index 0000000..fb7ee2b
--- /dev/null
+++ b/board/broadcom/bcm911360_entphn/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM911360_ENTPHN BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm911360_entphn_defconfig
diff --git a/board/broadcom/bcm911360k/MAINTAINERS b/board/broadcom/bcm911360k/MAINTAINERS
new file mode 100644
index 0000000..754a15f
--- /dev/null
+++ b/board/broadcom/bcm911360k/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM911360K BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm911360k_defconfig
diff --git a/board/broadcom/bcm958300k-ns/MAINTAINERS b/board/broadcom/bcm958300k-ns/MAINTAINERS
new file mode 100644
index 0000000..763401a
--- /dev/null
+++ b/board/broadcom/bcm958300k-ns/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM958300K-NS BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm958300k-ns_defconfig
diff --git a/board/broadcom/bcm958300k/MAINTAINERS b/board/broadcom/bcm958300k/MAINTAINERS
index f75ee6e..8afc728 100644
--- a/board/broadcom/bcm958300k/MAINTAINERS
+++ b/board/broadcom/bcm958300k/MAINTAINERS
@@ -1,6 +1,6 @@
-Broadcom: Cygnus
+BCM958300K BOARD
M: Steve Rae <srae@broadcom.com>
S: Maintained
-F: board/broadcom/bcm958300k/
+F: board/broadcom/bcmcygnus/
F: include/configs/bcm_ep_board.h
F: configs/bcm958300k_defconfig
diff --git a/board/broadcom/bcm958305k/MAINTAINERS b/board/broadcom/bcm958305k/MAINTAINERS
new file mode 100644
index 0000000..179fd4e
--- /dev/null
+++ b/board/broadcom/bcm958305k/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM958305K BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm958305k_defconfig
diff --git a/board/broadcom/bcm958622hr/MAINTAINERS b/board/broadcom/bcm958622hr/MAINTAINERS
index c34272f..d08aded 100644
--- a/board/broadcom/bcm958622hr/MAINTAINERS
+++ b/board/broadcom/bcm958622hr/MAINTAINERS
@@ -1,6 +1,6 @@
-Broadcom: Northstar Plus
+BCM958622HR BOARD
M: Steve Rae <srae@broadcom.com>
S: Maintained
-F: board/broadcom/bcm958622hr/
+F: board/broadcom/bcmnsp/
F: include/configs/bcm_ep_board.h
F: configs/bcm958622hr_defconfig
diff --git a/board/broadcom/bcm_ep/board.c b/board/broadcom/bcm_ep/board.c
index e48cd3f..6a70a2e 100644
--- a/board/broadcom/bcm_ep/board.c
+++ b/board/broadcom/bcm_ep/board.c
@@ -53,3 +53,17 @@
return status;
}
+
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+}
+
+void smp_kick_all_cpus(void)
+{
+}
+
+void smp_waitloop(unsigned previous_address)
+{
+}
+#endif
diff --git a/board/broadcom/bcm958300k/Kconfig b/board/broadcom/bcmcygnus/Kconfig
similarity index 88%
rename from board/broadcom/bcm958300k/Kconfig
rename to board/broadcom/bcmcygnus/Kconfig
index 9289288..faba4cf 100644
--- a/board/broadcom/bcm958300k/Kconfig
+++ b/board/broadcom/bcmcygnus/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_BCM958300K
+if TARGET_BCMCYGNUS
config SYS_BOARD
default "bcm_ep"
diff --git a/board/broadcom/bcm958622hr/Kconfig b/board/broadcom/bcmnsp/Kconfig
similarity index 87%
rename from board/broadcom/bcm958622hr/Kconfig
rename to board/broadcom/bcmnsp/Kconfig
index 861c559..a975082 100644
--- a/board/broadcom/bcm958622hr/Kconfig
+++ b/board/broadcom/bcmnsp/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_BCM958622HR
+if TARGET_BCMNSP
config SYS_BOARD
default "bcm_ep"
diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c
index 048aa6c..5276907 100644
--- a/board/cm5200/cm5200.c
+++ b/board/cm5200/cm5200.c
@@ -359,9 +359,11 @@
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
ft_blob_update(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index 0206ae8..84e3643 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -98,9 +98,6 @@
/* Make sure this gpio has logical 0 value */
gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
udelay(100);
-
- cm_fx6_sata_power(0);
- mdelay(250);
cm_fx6_sata_power(1);
for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
@@ -125,6 +122,15 @@
return err;
}
+
+int sata_stop(void)
+{
+ __sata_stop();
+ cm_fx6_sata_power(0);
+ mdelay(250);
+
+ return 0;
+}
#else
static int cm_fx6_setup_issd(void) { return 0; }
#endif
@@ -452,7 +458,7 @@
#endif
#ifdef CONFIG_OF_BOARD_SETUP
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
uint8_t enetaddr[6];
@@ -461,6 +467,8 @@
fdt_find_and_setprop(blob, "/fec", "local-mac-address",
enetaddr, 6, 1);
}
+
+ return 0;
}
#endif
diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c
index b1a067d..2c2530a 100644
--- a/board/compulab/cm_t54/cm_t54.c
+++ b/board/compulab/cm_t54/cm_t54.c
@@ -121,7 +121,7 @@
#ifdef CONFIG_USB_HOST_ETHER
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
uint8_t enetaddr[6];
@@ -130,6 +130,8 @@
fdt_find_and_setprop(blob, "/smsc95xx@0", "mac-address",
enetaddr, 6, 1);
}
+
+ return 0;
}
static void generate_mac_addr(uint8_t *enetaddr)
diff --git a/board/chromebook-x86/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig
similarity index 86%
rename from board/chromebook-x86/coreboot/Kconfig
rename to board/coreboot/coreboot/Kconfig
index 83385c7..6ca6ced 100644
--- a/board/chromebook-x86/coreboot/Kconfig
+++ b/board/coreboot/coreboot/Kconfig
@@ -4,7 +4,7 @@
default "coreboot"
config SYS_VENDOR
- default "chromebook-x86"
+ default "coreboot"
config SYS_SOC
default "coreboot"
diff --git a/board/chromebook-x86/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS
similarity index 78%
rename from board/chromebook-x86/coreboot/MAINTAINERS
rename to board/coreboot/coreboot/MAINTAINERS
index 3b2fb52..6ce66f5 100644
--- a/board/chromebook-x86/coreboot/MAINTAINERS
+++ b/board/coreboot/coreboot/MAINTAINERS
@@ -1,6 +1,6 @@
COREBOOT BOARD
M: Simon Glass <sjg@chromium.org>
S: Maintained
-F: board/chromebook-x86/coreboot/
+F: board/coreboot/coreboot/
F: include/configs/coreboot.h
F: configs/coreboot-x86_defconfig
diff --git a/board/chromebook-x86/coreboot/Makefile b/board/coreboot/coreboot/Makefile
similarity index 100%
rename from board/chromebook-x86/coreboot/Makefile
rename to board/coreboot/coreboot/Makefile
diff --git a/board/chromebook-x86/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c
similarity index 100%
rename from board/chromebook-x86/coreboot/coreboot.c
rename to board/coreboot/coreboot/coreboot.c
diff --git a/board/chromebook-x86/coreboot/coreboot_start.S b/board/coreboot/coreboot/coreboot_start.S
similarity index 100%
rename from board/chromebook-x86/coreboot/coreboot_start.S
rename to board/coreboot/coreboot/coreboot_start.S
diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c
index c740669..a15a9ed 100644
--- a/board/davedenx/aria/aria.c
+++ b/board/davedenx/aria/aria.c
@@ -107,8 +107,10 @@
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
index 682f268..5c629db 100644
--- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
@@ -20,7 +20,7 @@
{
*(.vectors)
arch/arm/cpu/arm926ejs/start.o (.text*)
- arch/arm/cpu/arm926ejs/davinci/built-in.o (.text*)
+ arch/arm/cpu/arm926ejs/built-in.o (.text*)
drivers/mtd/nand/built-in.o (.text*)
*(.text*)
diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c
index 02fb3fa..f8c7468 100644
--- a/board/embest/mx6boards/mx6boards.c
+++ b/board/embest/mx6boards/mx6boards.c
@@ -216,7 +216,7 @@
int board_mmc_init(bd_t *bis)
{
- s32 status = 0;
+ int ret;
int i;
/*
@@ -268,13 +268,15 @@
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
i + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return status;
+ return -EINVAL;
}
- status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
}
- return status;
+ return 0;
}
#endif
diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c
index b168074..f3f70ff 100644
--- a/board/esd/common/auto_update.c
+++ b/board/esd/common/auto_update.c
@@ -12,6 +12,7 @@
#include <image.h>
#include <asm/byteorder.h>
#include <fat.h>
+#include <flash.h>
#include <part.h>
#include "auto_update.h"
@@ -30,14 +31,8 @@
#define MAX_LOADSZ 0x1c00000
/* externals */
-extern int fat_register_device(block_dev_desc_t *, int);
-extern int file_fat_detectfs(void);
-extern long file_fat_read(const char *, void *, unsigned long);
long do_fat_read (const char *filename, void *buffer,
unsigned long maxsize, int dols);
-extern int flash_sect_erase(ulong, ulong);
-extern int flash_sect_protect (int, ulong, ulong);
-extern int flash_write (char *, ulong, ulong);
extern block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index 63cd862..e23ec55 100644
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -508,7 +508,7 @@
#endif /* defined(CONFIG_PCI) */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int rc;
@@ -526,6 +526,8 @@
fdt_strerror(rc));
}
}
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c
index 9700611..cda1d7b 100644
--- a/board/esd/mecp5123/mecp5123.c
+++ b/board/esd/mecp5123/mecp5123.c
@@ -199,8 +199,10 @@
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c
index 4409ea6..3e17132 100644
--- a/board/esd/pmc405de/pmc405de.c
+++ b/board/esd/pmc405de/pmc405de.c
@@ -300,7 +300,7 @@
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int rc;
@@ -318,6 +318,8 @@
fdt_strerror(rc));
}
}
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
index 062ae67..15c3151 100644
--- a/board/esd/pmc440/pmc440.c
+++ b/board/esd/pmc440/pmc440.c
@@ -882,7 +882,7 @@
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int rc;
@@ -899,5 +899,7 @@
printf("err=%s\n", fdt_strerror(rc));
}
}
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c
index 01365dc..f8f1834 100644
--- a/board/esd/vme8349/vme8349.c
+++ b/board/esd/vme8349/vme8349.c
@@ -74,13 +74,15 @@
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index 34d66d5..bed8f56 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -1110,7 +1110,7 @@
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -1136,6 +1136,8 @@
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
+
+ return 0;
}
/*
diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c
index 9146f49..75e1142 100644
--- a/board/freescale/bsc9131rdb/bsc9131rdb.c
+++ b/board/freescale/bsc9131rdb/bsc9131rdb.c
@@ -58,7 +58,7 @@
{ "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
};
#endif
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -74,5 +74,7 @@
#endif
fdt_fixup_dr_usb(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
index c88838b..36a68db 100644
--- a/board/freescale/bsc9132qds/bsc9132qds.c
+++ b/board/freescale/bsc9132qds/bsc9132qds.c
@@ -363,7 +363,7 @@
{ "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
};
#endif
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -423,5 +423,7 @@
printf("\nRemove sim from hwconfig and reset\n");
}
}
+
+ return 0;
}
#endif
diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c
index 534c6d1..d757709 100644
--- a/board/freescale/c29xpcie/c29xpcie.c
+++ b/board/freescale/c29xpcie/c29xpcie.c
@@ -128,7 +128,7 @@
}
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -150,5 +150,7 @@
fdt_del_sec(blob, 1);
else if (cpu->soc_ver == SVR_C292)
fdt_del_sec(blob, 2);
+
+ return 0;
}
#endif
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 32b5a3b..25a1bc1 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -53,6 +53,7 @@
obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
obj-$(CONFIG_ZM7300) += zm7300.o
+obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
# deal with common files for P-series corenet based devices
obj-$(CONFIG_P2041RDB) += p_corenet/
diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c
index 2e5dcdf..571dfbb 100644
--- a/board/freescale/common/cds_pci_ft.c
+++ b/board/freescale/common/cds_pci_ft.c
@@ -63,13 +63,14 @@
}
}
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
cds_pci_fixup(blob);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c
new file mode 100644
index 0000000..2cd1794
--- /dev/null
+++ b/board/freescale/common/pfuze.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+
+struct pmic *pfuze_common_init(unsigned char i2cbus)
+{
+ struct pmic *p;
+ int ret;
+ unsigned int reg;
+
+ ret = power_pfuze100_init(i2cbus);
+ if (ret)
+ return NULL;
+
+ p = pmic_get("PFUZE100");
+ ret = pmic_probe(p);
+ if (ret)
+ return NULL;
+
+ pmic_reg_read(p, PFUZE100_DEVICEID, ®);
+ printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+
+ /* Set SW1AB stanby volage to 0.975V */
+ pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
+ reg &= ~SW1x_STBY_MASK;
+ reg |= SW1x_0_975V;
+ pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+ /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(p, PUZE_100_SW1ABCONF, ®);
+ reg &= ~SW1xCONF_DVSSPEED_MASK;
+ reg |= SW1xCONF_DVSSPEED_4US;
+ pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+
+ /* Set SW1C standby voltage to 0.975V */
+ pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
+ reg &= ~SW1x_STBY_MASK;
+ reg |= SW1x_0_975V;
+ pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+ /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
+ reg &= ~SW1xCONF_DVSSPEED_MASK;
+ reg |= SW1xCONF_DVSSPEED_4US;
+ pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+ return p;
+}
diff --git a/board/freescale/common/pfuze.h b/board/freescale/common/pfuze.h
new file mode 100644
index 0000000..7a4126c
--- /dev/null
+++ b/board/freescale/common/pfuze.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PFUZE_BOARD_HELPER__
+#define __PFUZE_BOARD_HELPER__
+
+struct pmic *pfuze_common_init(unsigned char i2cbus);
+
+#endif
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index 3426b8a..5cb7570 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -114,7 +114,7 @@
e.date[3] & 0x80 ? "PM" : "");
/* Show MAC addresses */
- for (i = 0; i < min(e.mac_count, MAX_NUM_PORTS); i++) {
+ for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) {
u8 *p = e.mac[i];
@@ -223,7 +223,7 @@
*/
for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
- p, min((sizeof(e) - i), 8));
+ p, min((int)(sizeof(e) - i), 8));
if (ret)
break;
udelay(5000); /* 5ms write cycle timing */
@@ -461,7 +461,7 @@
memset(e.mac[8], 0xff, 6);
#endif
- for (i = 0; i < min(e.mac_count, MAX_NUM_PORTS); i++) {
+ for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) {
if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) &&
memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
char ethaddr[18];
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index 65b3867..6f0fea1 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -190,7 +190,7 @@
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -213,4 +213,6 @@
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
+
+ return 0;
}
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index d64b24c..0a7720a 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -254,9 +254,11 @@
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
u8 flash_read8(void *addr)
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 3f2dc1a..3e8c37b 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -303,9 +303,11 @@
}
#endif
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
u8 flash_read8(void *addr)
diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c
index 2c79a71..163a4c4 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -100,7 +100,7 @@
#endif
#ifdef CONFIG_OF_BOARD_SETUP
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -115,5 +115,7 @@
#ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(blob);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c
index 940978e..40bd55d 100644
--- a/board/freescale/mpc5121ads/mpc5121ads.c
+++ b/board/freescale/mpc5121ads/mpc5121ads.c
@@ -275,8 +275,10 @@
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/freescale/mpc7448hpc2/mpc7448hpc2.c b/board/freescale/mpc7448hpc2/mpc7448hpc2.c
index 71b760c..11747ca 100644
--- a/board/freescale/mpc7448hpc2/mpc7448hpc2.c
+++ b/board/freescale/mpc7448hpc2/mpc7448hpc2.c
@@ -70,11 +70,12 @@
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c
index fba41fe..93e1c50 100644
--- a/board/freescale/mpc8308rdb/mpc8308rdb.c
+++ b/board/freescale/mpc8308rdb/mpc8308rdb.c
@@ -161,11 +161,13 @@
return 0;
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
fdt_fixup_dr_usb(blob, bd);
fdt_fixup_esdhc(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
index 69e98a5..eac193e 100644
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ b/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -116,12 +116,14 @@
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+
+ return 0;
}
#endif
#else /* CONFIG_SPL_BUILD */
diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c
index e6f091f..ed611c5 100644
--- a/board/freescale/mpc8315erdb/mpc8315erdb.c
+++ b/board/freescale/mpc8315erdb/mpc8315erdb.c
@@ -188,7 +188,7 @@
do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
@@ -196,6 +196,8 @@
#endif
fdt_fixup_dr_usb(blob, bd);
fdt_tsec1_fixup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
index 3dce362..0a0152a 100644
--- a/board/freescale/mpc8323erdb/mpc8323erdb.c
+++ b/board/freescale/mpc8323erdb/mpc8323erdb.c
@@ -172,12 +172,14 @@
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c
index b7ea0e4..adf4254 100644
--- a/board/freescale/mpc832xemds/mpc832xemds.c
+++ b/board/freescale/mpc832xemds/mpc832xemds.c
@@ -154,11 +154,13 @@
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index d909220..02b5040 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -273,11 +273,13 @@
#endif /* CONFIG_HARD_SPI */
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index 803d722..22a1d99 100644
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -378,11 +378,13 @@
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index 5ff9dff..f0a55f8 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -402,7 +402,7 @@
"peripheral", sizeof("peripheral"), 1);
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
@@ -447,5 +447,7 @@
#endif
}
}
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c
index fef230b..478f820 100644
--- a/board/freescale/mpc8360erdk/mpc8360erdk.c
+++ b/board/freescale/mpc8360erdk/mpc8360erdk.c
@@ -340,9 +340,11 @@
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
ft_pci_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
index c749e55..572913c 100644
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -328,7 +328,7 @@
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
ft_tsec_fixup(blob, bd);
@@ -340,5 +340,7 @@
ft_pci_fixup(blob, bd);
ft_pcie_fixup(blob, bd);
#endif
+
+ return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index 9afdcaf..e0a1031 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -199,7 +199,7 @@
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
@@ -207,5 +207,7 @@
ft_cpu_setup(blob, bd);
fdt_fixup_dr_usb(blob, bd);
fdt_fixup_esdhc(blob, bd);
+
+ return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 93eed59..7b0f461 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -271,7 +271,7 @@
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
@@ -285,5 +285,6 @@
fdt_fixup_dr_usb(blob, bd);
#endif
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index 93288c7..1069e2c 100644
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -218,8 +218,7 @@
#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int node, tmp[2];
const char *path;
@@ -237,5 +236,7 @@
}
#endif
}
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 1b33db6..66fb228 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -305,7 +305,7 @@
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
@@ -314,5 +314,7 @@
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index 7104e33..f99d639 100644
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -438,8 +438,7 @@
#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int node, tmp[2];
const char *path;
@@ -457,5 +456,7 @@
}
#endif
}
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index a8fdcb5..a5c5d9d 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -345,10 +345,12 @@
#endif /* CONFIG_PCI */
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
FT_FSL_PCI_SETUP;
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index cb55e1c..836578f 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -514,7 +514,7 @@
#endif /* CONFIG_PCI */
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_SYS_UCC_RMII_MODE)
int nodeoff, off, err;
@@ -579,5 +579,7 @@
fdt_board_fixup_esdhc(blob, bd);
fdt_board_fixup_qe_uart(blob, bd);
fdt_board_fixup_qe_usb(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 1bbf832..3f68cf4 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -232,7 +232,7 @@
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -249,5 +249,7 @@
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index d8740dd..95e398c 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -258,12 +258,13 @@
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
FT_FSL_PCI_SETUP;
+
+ return 0;
}
#endif
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index a58b5f9..94633b5 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -119,12 +119,11 @@
#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int off;
u64 *tmp;
- u32 *addrcells;
+ int addrcells;
ft_cpu_setup(blob, bd);
@@ -136,12 +135,13 @@
* which is defined by the "reg" property in the soc node.
*/
off = fdt_path_offset(blob, "/soc8641");
- addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
+ addrcells = fdt_address_cells(blob, 0);
tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
if (tmp) {
u64 addr;
- if (addrcells && (*addrcells == 1))
+
+ if (addrcells == 1)
addr = *(u32 *)tmp;
else
addr = *tmp;
@@ -152,6 +152,8 @@
"in u-boot. This means your .dts might "
"be old.\n");
}
+
+ return 0;
}
#endif
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index 9b43c84..f1e5eb4 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -320,7 +320,7 @@
};
u32 index;
- s32 status = 0;
+ int ret;
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
@@ -340,11 +340,13 @@
printf("Warning: you configured more ESDHC controller"
"(%d) as supported by the board(2)\n",
CONFIG_SYS_FSL_ESDHC_NUM);
- return status;
+ return -EINVAL;
}
- status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ if (ret)
+ return ret;
}
- return status;
+ return 0;
}
#endif
diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c
index c960c44..8ba2728 100644
--- a/board/freescale/mx53ard/mx53ard.c
+++ b/board/freescale/mx53ard/mx53ard.c
@@ -166,7 +166,7 @@
};
u32 index;
- s32 status = 0;
+ int ret;
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
@@ -185,12 +185,14 @@
printf("Warning: you configured more ESDHC controller"
"(%d) as supported by the board(2)\n",
CONFIG_SYS_FSL_ESDHC_NUM);
- return status;
+ return -EINVAL;
}
- status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ if (ret)
+ return ret;
}
- return status;
+ return 0;
}
#endif
diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c
index 13519e2..6ee6d73 100644
--- a/board/freescale/mx53evk/mx53evk.c
+++ b/board/freescale/mx53evk/mx53evk.c
@@ -195,7 +195,7 @@
};
u32 index;
- s32 status = 0;
+ int ret;
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
@@ -214,12 +214,14 @@
printf("Warning: you configured more ESDHC controller"
"(%d) as supported by the board(2)\n",
CONFIG_SYS_FSL_ESDHC_NUM);
- return status;
+ return -EINVAL;
}
- status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ if (ret)
+ return ret;
}
- return status;
+ return 0;
}
#endif
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index 7569ded..efcf4b3 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -186,7 +186,7 @@
};
u32 index;
- s32 status = 0;
+ int ret;
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
@@ -205,12 +205,14 @@
printf("Warning: you configured more ESDHC controller"
"(%d) as supported by the board(2)\n",
CONFIG_SYS_FSL_ESDHC_NUM);
- return status;
+ return -EINVAL;
}
- status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ if (ret)
+ return ret;
}
- return status;
+ return 0;
}
#endif
diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c
index d64c674..0963fd7 100644
--- a/board/freescale/mx53smd/mx53smd.c
+++ b/board/freescale/mx53smd/mx53smd.c
@@ -106,7 +106,7 @@
};
u32 index;
- s32 status = 0;
+ int ret;
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
@@ -121,12 +121,14 @@
printf("Warning: you configured more ESDHC controller"
"(%d) as supported by the board(1)\n",
CONFIG_SYS_FSL_ESDHC_NUM);
- return status;
+ return -EINVAL;
}
- status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ if (ret)
+ return ret;
}
- return status;
+ return 0;
}
#endif
diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c
index 667dca5..3a5b26d 100644
--- a/board/freescale/mx6qarm2/mx6qarm2.c
+++ b/board/freescale/mx6qarm2/mx6qarm2.c
@@ -125,7 +125,7 @@
int board_mmc_init(bd_t *bis)
{
- s32 status = 0;
+ int ret;
u32 index = 0;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
@@ -145,13 +145,15 @@
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
index + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return status;
+ return -EINVAL;
}
- status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ if (ret)
+ return ret;
}
- return status;
+ return 0;
}
#endif
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index c35dcaf..59387ff 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -28,6 +28,8 @@
#include <asm/imx-common/video.h>
#include <asm/arch/crm_regs.h>
#include <pca953x.h>
+#include <power/pmic.h>
+#include "../common/pfuze.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -53,6 +55,12 @@
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PMIC 1
+
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -97,6 +105,7 @@
}
};
+#ifndef CONFIG_SYS_FLASH_CFI
/*
* I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
* Compass Sensor, Accelerometer, Res Touch
@@ -113,6 +122,7 @@
.gp = IMX_GPIO_NR(3, 18)
}
};
+#endif
static iomux_v3_cfg_t const i2c3_pads[] = {
MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
@@ -160,6 +170,75 @@
return 0;
}
+static iomux_v3_cfg_t const eimnor_pads[] = {
+ MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
+ MX6_PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void eimnor_cs_setup(void)
+{
+ struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+ writel(0x00020181, &weim_regs->cs0gcr1);
+ writel(0x00000001, &weim_regs->cs0gcr2);
+ writel(0x0a020000, &weim_regs->cs0rcr1);
+ writel(0x0000c000, &weim_regs->cs0rcr2);
+ writel(0x0804a240, &weim_regs->cs0wcr1);
+ writel(0x00000120, &weim_regs->wcr);
+
+ set_chipselect_size(CS0_128);
+}
+
+static void setup_iomux_eimnor(void)
+{
+ imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
+
+ gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
+
+ eimnor_cs_setup();
+}
+
static void setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
@@ -402,6 +481,7 @@
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand();
#endif
+
return 0;
}
@@ -415,11 +495,13 @@
/* I2C 3 Steer */
gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
+#ifndef CONFIG_SYS_FLASH_CFI
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-
+#endif
gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
+ setup_iomux_eimnor();
return 0;
}
@@ -430,6 +512,17 @@
}
#endif
+int power_init_board(void)
+{
+ struct pmic *p;
+
+ p = pfuze_common_init(I2C_PMIC);
+ if (!p)
+ return -ENODEV;
+
+ return 0;
+}
+
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
diff --git a/board/freescale/mx6sabresd/MAINTAINERS b/board/freescale/mx6sabresd/MAINTAINERS
index 69c0a30..0011ec7 100644
--- a/board/freescale/mx6sabresd/MAINTAINERS
+++ b/board/freescale/mx6sabresd/MAINTAINERS
@@ -5,3 +5,4 @@
F: include/configs/mx6sabresd.h
F: configs/mx6dlsabresd_defconfig
F: configs/mx6qsabresd_defconfig
+F: configs/mx6sabresd_spl_defconfig
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 1142e8a..ac3757f 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -27,12 +27,11 @@
#include <i2c.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
#include <asm/arch/mx6-ddr.h>
DECLARE_GLOBAL_DATA_PTR;
-#define BOOT_CFG 0x020D8004
-
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
@@ -300,7 +299,8 @@
return 0;
#else
- unsigned reg = readl(BOOT_CFG) >> 11;
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ unsigned reg = readl(&psrc->sbmr1) >> 11;
/*
* Upon reading BOOT_CFG register the following map is done:
* Bit 11 and 12 of BOOT_CFG register can determine the current
@@ -560,60 +560,27 @@
return 0;
}
-static int pfuze_init(void)
+int power_init_board(void)
{
struct pmic *p;
- int ret;
unsigned int reg;
- ret = power_pfuze100_init(I2C_PMIC);
- if (ret)
- return ret;
-
- p = pmic_get("PFUZE100");
- ret = pmic_probe(p);
- if (ret)
- return ret;
-
- pmic_reg_read(p, PFUZE100_DEVICEID, ®);
- printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+ p = pfuze_common_init(I2C_PMIC);
+ if (!p)
+ return -ENODEV;
/* Increase VGEN3 from 2.5 to 2.8V */
pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
- reg &= ~0xf;
- reg |= 0xa;
+ reg &= ~LDO_VOL_MASK;
+ reg |= LDOB_2_80V;
pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
/* Increase VGEN5 from 2.8 to 3V */
pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
- reg &= ~0xf;
- reg |= 0xc;
+ reg &= ~LDO_VOL_MASK;
+ reg |= LDOB_3_00V;
pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
- /* Set SW1AB stanby volage to 0.975V */
- pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
- reg &= ~0x3f;
- reg |= 0x1b;
- pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
-
- /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
- pmic_reg_read(p, PUZE_100_SW1ABCONF, ®);
- reg &= ~0xc0;
- reg |= 0x40;
- pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
-
- /* Set SW1C standby voltage to 0.975V */
- pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
- reg &= ~0x3f;
- reg |= 0x1b;
- pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
-
- /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
- pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
- reg &= ~0xc0;
- reg |= 0x40;
- pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
-
return 0;
}
@@ -640,8 +607,6 @@
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
- pfuze_init();
-
return 0;
}
@@ -729,11 +694,33 @@
.trasmin = 3500,
};
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xF00000CF, &iomux->gpr[4]);
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+}
+
/*
- * This section require the differentiation
- * between iMX6 Sabre Families.
- * But for now, it will configure only for
- * SabreSD.
+ * This section requires the differentiation between iMX6 Sabre boards, but
+ * for now, it will configure only for the mx6q variant.
*/
static void spl_dram_init(void)
{
@@ -768,6 +755,9 @@
/* setup AIPS and disable watchdog */
arch_cpu_init();
+ ccgr_init();
+ gpr_init();
+
/* iomux and setup of i2c */
board_early_init_f();
diff --git a/board/freescale/mx6sabresd/mx6sabresd_spl.cfg b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg
deleted file mode 100644
index 2bf4817..0000000
--- a/board/freescale/mx6sabresd/mx6sabresd_spl.cfg
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
- * Jason Liu <r64343@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-
-/* set the default clock gate to save power */
-DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC03
-DATA 4 0x020c4070 0x0FFFC000
-DATA 4 0x020c4074 0x3FF00000
-DATA 4 0x020c4078 0x00FFF300
-DATA 4 0x020c407c 0x0F0000C3
-DATA 4 0x020c4080 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4 0x020e0010 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4 0x020e0018 0x007F007F
-DATA 4 0x020e001c 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en = 1 --> CKO1 enabled
- * cko1_div = 111 --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4 0x020c4060 0x000000fb
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index e76c343..8111edf 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -230,16 +230,11 @@
static int setup_fec(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- int ret;
/* clear gpr1[14], gpr1[18:17] to select anatop clock */
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
- ret = enable_fec_anatop_clock(ENET_50MHz);
- if (ret)
- return ret;
-
- return 0;
+ return enable_fec_anatop_clock(ENET_50MHz);
}
#endif
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 68d3718..7aee074 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -25,6 +25,7 @@
#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -68,6 +69,34 @@
MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* CD pin */
+ MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+ /* RST_B, used for power reset cycle */
+ MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
static iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -119,7 +148,6 @@
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- int ret;
int reg;
/* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
@@ -140,11 +168,7 @@
reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
writel(reg, &anatop->pll_enet);
- ret = enable_fec_anatop_clock(ENET_125MHz);
- if (ret)
- return ret;
-
- return 0;
+ return enable_fec_anatop_clock(ENET_125MHz);
}
int board_eth_init(bd_t *bis)
@@ -170,52 +194,19 @@
},
};
-static int pfuze_init(void)
+int power_init_board(void)
{
struct pmic *p;
- int ret;
unsigned int reg;
- ret = power_pfuze100_init(I2C_PMIC);
- if (ret)
- return ret;
-
- p = pmic_get("PFUZE100");
- ret = pmic_probe(p);
- if (ret)
- return ret;
-
- pmic_reg_read(p, PFUZE100_DEVICEID, ®);
- printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
-
- /* Set SW1AB standby voltage to 0.975V */
- pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
- reg &= ~0x3f;
- reg |= 0x1b;
- pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
-
- /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
- pmic_reg_read(p, PUZE_100_SW1ABCONF, ®);
- reg &= ~0xc0;
- reg |= 0x40;
- pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
-
- /* Set SW1C standby voltage to 0.975V */
- pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
- reg &= ~0x3f;
- reg |= 0x1b;
- pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
-
- /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
- pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
- reg &= ~0xc0;
- reg |= 0x40;
- pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+ p = pfuze_common_init(I2C_PMIC);
+ if (!p)
+ return -ENODEV;
/* Enable power of VGEN5 3V3, needed for SD3 */
pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
- reg &= ~0x1F;
- reg |= 0x1F;
+ reg &= ~LDO_VOL_MASK;
+ reg |= (LDOB_3_30V | (1 << LDO_EN));
pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
return 0;
@@ -243,7 +234,6 @@
int board_early_init_f(void)
{
setup_iomux_uart();
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
/* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
@@ -255,35 +245,98 @@
return 0;
}
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+ {USDHC2_BASE_ADDR, 0, 4},
+ {USDHC3_BASE_ADDR},
{USDHC4_BASE_ADDR},
};
+#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
+#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
+
int board_mmc_getcd(struct mmc *mmc)
{
- return 1; /* Assume boot SD always present */
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ ret = 1; /* Assume uSDHC2 is always present */
+ break;
+ case USDHC3_BASE_ADDR:
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ case USDHC4_BASE_ADDR:
+ ret = !gpio_get_value(USDHC4_CD_GPIO);
+ break;
+ }
+
+ return ret;
}
int board_mmc_init(bd_t *bis)
{
- imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC2
+ * mmc1 USDHC3
+ * mmc2 USDHC4
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+ gpio_direction_output(USDHC3_PWR_GPIO, 1);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ case 2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ gpio_direction_input(USDHC4_CD_GPIO);
+ usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ return ret;
+ }
+ }
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+ return 0;
}
+
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+#ifdef CONFIG_SYS_I2C_MXC
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
return 0;
}
int board_late_init(void)
{
- pfuze_init();
-
return 0;
}
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index 491b576..1cf0ab7 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -444,7 +444,7 @@
}
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -496,6 +496,8 @@
fdt_del_flexcan(blob);
fdt_disable_uart1(blob);
}
+
+ return 0;
}
#endif
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index f5e1851..d7dd478 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -332,7 +332,7 @@
}
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -356,5 +356,7 @@
/* Update the WM8776 node's clock frequency property */
ft_codec_setup(blob, "wlf,wm8776");
+
+ return 0;
}
#endif
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
index d4d277b..56f561a 100644
--- a/board/freescale/p1023rdb/p1023rdb.c
+++ b/board/freescale/p1023rdb/p1023rdb.c
@@ -130,7 +130,7 @@
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -147,5 +147,7 @@
#endif
fdt_fixup_fman_ethernet(blob);
+
+ return 0;
}
#endif
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index aba4f53..61ed466 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -234,7 +234,7 @@
#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_pci_board_setup(void *blob);
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
const char *soc_usb_compat = "fsl-usb2-dr";
int err, usb1_off, usb2_off;
@@ -263,39 +263,41 @@
int off = fdt_node_offset_by_compatible(blob, -1,
soc_elbc_compat);
if (off < 0) {
- printf("WARNING: could not find compatible node"
- " %s: %s.\n", soc_elbc_compat,
- fdt_strerror(off));
- return;
+ printf("WARNING: could not find compatible node %s\n",
+ soc_elbc_compat);
+ return off;
}
err = fdt_del_node(blob, off);
if (err < 0) {
- printf("WARNING: could not remove %s: %s.\n",
- soc_elbc_compat, fdt_strerror(err));
+ printf("WARNING: could not remove %s\n",
+ soc_elbc_compat);
+ return err;
}
- return;
+ return 0;
}
#endif
/* Delete USB2 node as it is muxed with eLBC */
usb1_off = fdt_node_offset_by_compatible(blob, -1,
soc_usb_compat);
if (usb1_off < 0) {
- printf("WARNING: could not find compatible node"
- " %s: %s.\n", soc_usb_compat,
- fdt_strerror(usb1_off));
- return;
+ printf("WARNING: could not find compatible node %s\n",
+ soc_usb_compat);
+ return usb1_off;
}
usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
soc_usb_compat);
if (usb2_off < 0) {
- printf("WARNING: could not find compatible node"
- " %s: %s.\n", soc_usb_compat,
- fdt_strerror(usb2_off));
- return;
+ printf("WARNING: could not find compatible node %s\n",
+ soc_usb_compat);
+ return usb2_off;
}
err = fdt_del_node(blob, usb2_off);
- if (err < 0)
- printf("WARNING: could not remove %s: %s.\n",
- soc_usb_compat, fdt_strerror(err));
+ if (err < 0) {
+ printf("WARNING: could not remove %s\n", soc_usb_compat);
+ return err;
+ }
+
+ return 0;
}
+
#endif
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index a6756c6..3f47cfb 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -424,7 +424,7 @@
#endif
#ifdef CONFIG_OF_BOARD_SETUP
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -459,17 +459,17 @@
int off = fdt_node_offset_by_compatible(blob, -1,
soc_elbc_compat);
if (off < 0) {
- printf("WARNING: could not find compatible node %s: %s.\n",
- soc_elbc_compat,
- fdt_strerror(off));
- return;
+ printf("WARNING: could not find compatible node %s\n",
+ soc_elbc_compat);
+ return off;
}
err = fdt_del_node(blob, off);
if (err < 0) {
- printf("WARNING: could not remove %s: %s.\n",
- soc_elbc_compat, fdt_strerror(err));
+ printf("WARNING: could not remove %s\n",
+ soc_elbc_compat);
+ return err;
}
- return;
+ return 0;
}
#endif
@@ -477,24 +477,23 @@
usb1_off = fdt_node_offset_by_compatible(blob, -1,
soc_usb_compat);
if (usb1_off < 0) {
- printf("WARNING: could not find compatible node %s: %s.\n",
- soc_usb_compat,
- fdt_strerror(usb1_off));
- return;
+ printf("WARNING: could not find compatible node %s\n",
+ soc_usb_compat);
+ return usb1_off;
}
usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
soc_usb_compat);
if (usb2_off < 0) {
- printf("WARNING: could not find compatible node %s: %s.\n",
- soc_usb_compat,
- fdt_strerror(usb2_off));
- return;
+ printf("WARNING: could not find compatible node %s\n",
+ soc_usb_compat);
+ return usb2_off;
}
err = fdt_del_node(blob, usb2_off);
if (err < 0) {
- printf("WARNING: could not remove %s: %s.\n",
- soc_usb_compat, fdt_strerror(err));
+ printf("WARNING: could not remove %s\n", soc_usb_compat);
+ return err;
}
+ return 0;
}
#endif
diff --git a/board/freescale/p1_twr/p1_twr.c b/board/freescale/p1_twr/p1_twr.c
index a0a416ba..a40bea3 100644
--- a/board/freescale/p1_twr/p1_twr.c
+++ b/board/freescale/p1_twr/p1_twr.c
@@ -261,7 +261,7 @@
#endif
#ifdef CONFIG_OF_BOARD_SETUP
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -283,5 +283,7 @@
fdt_board_fixup_qe_pins(blob);
#endif
fdt_fixup_dr_usb(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c
index f777bb9..1db37e3 100644
--- a/board/freescale/p2020come/p2020come.c
+++ b/board/freescale/p2020come/p2020come.c
@@ -250,7 +250,7 @@
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -269,5 +269,7 @@
#ifdef CONFIG_HAS_FSL_DR_USB
fdt_fixup_dr_usb(blob, bd);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index b72fcff..5d18e8d 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -236,7 +236,7 @@
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -257,5 +257,7 @@
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif
+
+ return 0;
}
#endif
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index a14b43b..e600bdb 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -215,7 +215,7 @@
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -239,4 +239,6 @@
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
#endif
+
+ return 0;
}
diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/freescale/qemu-ppce500/qemu-ppce500.c
index 230870d..a0fca0d 100644
--- a/board/freescale/qemu-ppce500/qemu-ppce500.c
+++ b/board/freescale/qemu-ppce500/qemu-ppce500.c
@@ -235,9 +235,11 @@
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
+
+ return 0;
}
#endif
diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
index 19af46e..13285be 100644
--- a/board/freescale/t1040qds/t1040qds.c
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -233,7 +233,7 @@
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -259,6 +259,8 @@
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
+
+ return 0;
}
void qixis_dump_switch(void)
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
index ddb669f..4734f9d 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -85,7 +85,7 @@
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -110,6 +110,8 @@
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
#endif
+
+ return 0;
}
#ifdef CONFIG_DEEP_SLEEP
diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README
new file mode 100755
index 0000000..83060c1
--- /dev/null
+++ b/board/freescale/t208xqds/README
@@ -0,0 +1,274 @@
+The T2080QDS is a high-performance computing evaluation, development and
+test platform supporting the T2080 QorIQ Power Architecture processor.
+
+T2080 SoC Overview
+------------------
+The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
+Architecture processor cores with high-performance datapath acceleration
+logic and network and peripheral bus interfaces required for networking,
+telecom/datacom, wireless infrastructure, and mil/aerospace applications.
+
+T2080 includes the following functions and features:
+ - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
+ - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
+ - Hierarchical interconnect fabric
+ - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration
+ - 16 SerDes lanes up to 10.3125 GHz
+ - 8 Ethernet interfaces, supporting combinations of the following:
+ - Up to four 10 Gbps Ethernet MACs
+ - Up to eight 1 Gbps Ethernet MACs
+ - Up to four 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+ - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
+ - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
+ - Additional peripheral interfaces
+ - Two serial ATA (SATA 2.0) controllers
+ - Two high-speed USB 2.0 controllers with integrated PHY
+ - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
+ - Enhanced serial peripheral interface (eSPI)
+ - Four I2C controllers
+ - Four 2-pin UARTs or two 4-pin UARTs
+ - Integrated Flash Controller supporting NAND and NOR flash
+ - Three eight-channel DMA engines
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ Platform's Trust Architecture 2.0
+
+Differences between T2080 and T2081
+-----------------------------------
+ Feature T2080 T2081
+ 1G Ethernet numbers: 8 6
+ 10G Ethernet numbers: 4 2
+ SerDes lanes: 16 8
+ Serial RapidIO,RMan: 2 no
+ SATA Controller: 2 no
+ Aurora: yes no
+ SoC Package: 896-pins 780-pins
+
+
+T2080QDS feature overview
+-------------------------
+Processor:
+ - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
+Memory:
+ - Single memory controller capable of supporting DDR3 and DDR3-LV devices
+ - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
+Ethernet interfaces:
+ - Two 1Gbps RGMII on-board ports
+ - Four 10Gbps XFI on-board cages
+ - 1Gbps/2.5Gbps SGMII Riser card
+ - 10Gbps XAUI Riser card
+Accelerator:
+ - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
+SerDes:
+ - 16 lanes up to 10.3125GHz
+ - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
+IFC:
+ - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
+eSPI:
+ - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
+USB:
+ - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
+PCIE:
+ - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
+SATA:
+ - Two SATA 2.0 ports on-board
+SRIO:
+ - Two Serial RapidIO 2.0 ports up to 5 GHz
+eSDHC:
+ - Supports SD/SDHC/SDXC/eMMC Card
+I2C:
+ - Four I2C controllers.
+UART:
+ - Dual 4-pins UART serial ports
+System Logic:
+ - QIXIS-II FPGA system controll
+Debug Features:
+ - Support Legacy, COP/JTAG, Aurora, Event and EVT
+XFI:
+ - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
+ a on-board SFP+ cages, which to house optical module (fiber cable) or
+ direct attach cable(copper), the copper cable is used to emulate
+ 10GBASE-KR scenario.
+ So, for XFI usage, there are two scenarios, one will use fiber cable,
+ another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
+ introduced to indicate a XFI port will use copper cable, and U-boot
+ will fixup the dtb accordingly.
+ It's used as: fsl_10gkr_copper:<10g_mac_name>
+ The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they
+ do not have to be coexist in hwconfig. If a MAC is listed in the env
+ "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
+ will be used by default.
+ for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in
+ hwconfig, then both four XFI ports will use copper cable.
+ set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
+ XFI ports will use copper cable, the other two XFI ports will use fiber
+ cable.
+1000BASE-KX(1G-KX):
+ - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
+ runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
+ in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration
+ Register 1 (PCCR1), and U-boot fixup the dtb for kernel to do proper
+ initialization.
+ Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC
+ 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a
+ MAC to use 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1'
+ stands for MAC 1, 'fm1_1g2' stands for MAC 2, etc.
+ For ex. set "fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10" in
+ hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode.
+
+System Memory map
+----------------
+
+Start Address End Address Description Size
+0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
+0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
+0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
+0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
+0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
+0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
+0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
+0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
+0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
+0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
+0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
+0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB
+0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB
+0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB
+0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB
+0x0_0000_0000 0x0_ffff_ffff DDR 4GB
+
+
+128M NOR Flash memory Map
+-------------------------
+Start Address End Address Definition Max size
+0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
+0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
+0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
+0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
+0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
+0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
+0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
+0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
+0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
+0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
+0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
+0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
+0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
+0xE8000000 0xE801FFFF RCW (current bank) 128KB
+
+
+
+Software configurations and board settings
+------------------------------------------
+1. NOR boot:
+ a. build NOR boot image
+ $ make T2080QDS_config
+ $ make
+ b. program u-boot.bin image to NOR flash
+ => tftp 1000000 u-boot.bin
+ => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
+ set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
+
+ Switching between default bank0 and alternate bank4 on NOR flash
+ To change boot source to vbank4:
+ by software: run command 'qixis_reset altbank' in u-boot.
+ by DIP-switch: set SW6[1:4] = '0100'
+
+ To change boot source to vbank0:
+ by software: run command 'qixis_reset' in u-boot.
+ by DIP-Switch: set SW6[1:4] = '0000'
+
+2. NAND Boot:
+ a. build PBL image for NAND boot
+ $ make T2080QDS_NAND_config
+ $ make
+ b. program u-boot-with-spl-pbl.bin to NAND flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => nand erase 0 $filesize
+ => nand write 1000000 0 $filesize
+ set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
+
+3. SPI Boot:
+ a. build PBL image for SPI boot
+ $ make T2080QDS_SPIFLASH_config
+ $ make
+ b. program u-boot-with-spl-pbl.bin to SPI flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => sf probe 0
+ => sf erase 0 f0000
+ => sf write 1000000 0 $filesize
+ set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
+
+4. SD Boot:
+ a. build PBL image for SD boot
+ $ make T2080QDS_SDCARD_config
+ $ make
+ b. program u-boot-with-spl-pbl.bin to SD/MMC card
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => mmc write 1000000 8 0x800
+ => tftp 1000000 fsl_fman_ucode_T2080_xx.bin
+ => mmc write 1000000 0x820 80
+ set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
+
+
+2-stage NAND/SPI/SD boot loader
+-------------------------------
+PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
+SPL further initializes DDR using SPD and environment variables
+and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
+Finally SPL transers control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area | Address |
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000 (32KB) |
+-------------------------------------------------
+|GD, BD | 0xFFFC8000 (4KB) |
+-------------------------------------------------
+|ENV | 0xFFFC9000 (8KB) |
+-------------------------------------------------
+|HEAP | 0xFFFCB000 (50KB) |
+-------------------------------------------------
+|STACK | 0xFFFD8000 (22KB) |
+-------------------------------------------------
+|U-boot SPL | 0xFFFD8000 (160KB) |
+-------------------------------------------------
+
+NAND Flash memory Map on T2080QDS
+--------------------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot img 1MB (2 blocks)
+0x100000 0x17FFFF u-boot env 512KB (1 block)
+0x180000 0x1FFFFF FMAN ucode 512KB (1 block)
+
+
+Micro SD Card memory Map on T2080QDS
+----------------------------------------------------
+Block #blocks Definition Size
+0x008 2048 u-boot img 1MB
+0x800 0016 u-boot env 8KB
+0x820 0128 FMAN ucode 64KB
+
+
+SPI Flash memory Map on T2080QDS
+----------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot img 1MB
+0x100000 0x101FFF u-boot env 8KB
+0x110000 0x11FFFF FMAN ucode 64KB
+
+
+How to update the ucode of Freescale FMAN
+-----------------------------------------
+=> tftp 1000000 fsl_fman_ucode_t2080_xx.bin
+=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
+
+
+For more details, please refer to T2080QDS User Guide and access
+website www.freescale.com and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
index 5879198..b82e9e7 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -23,6 +23,7 @@
#include <phy.h>
#include <asm/fsl_dtsec.h>
#include <asm/fsl_serdes.h>
+#include <hwconfig.h>
#include "../common/qixis.h"
#include "../common/fman.h"
#include "t208xqds_qixis.h"
@@ -46,6 +47,15 @@
#define EMI2 8
#endif
+#define PCCR1_SGMIIA_KX_MASK 0x00008000
+#define PCCR1_SGMIIB_KX_MASK 0x00004000
+#define PCCR1_SGMIIC_KX_MASK 0x00002000
+#define PCCR1_SGMIID_KX_MASK 0x00001000
+#define PCCR1_SGMIIE_KX_MASK 0x00000800
+#define PCCR1_SGMIIF_KX_MASK 0x00000400
+#define PCCR1_SGMIIG_KX_MASK 0x00000200
+#define PCCR1_SGMIIH_KX_MASK 0x00000100
+
static int mdio_mux[NUM_FM_PORTS];
static const char * const mdio_names[] = {
@@ -187,8 +197,18 @@
{
int phy;
char alias[20];
+ char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"};
+ char buf[32] = "serdes-1,";
struct fixed_link f_link;
+ int media_type = 0;
+ int off;
+
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#ifdef CONFIG_T2080QDS
+ serdes_corenet_t *srds_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
+#endif
u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
@@ -199,9 +219,54 @@
switch (port) {
#if defined(CONFIG_T2080QDS)
case FM1_DTSEC1:
+ if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_1gkx1");
+ fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1");
+ sprintf(buf, "%s%s%s", buf, "lane-c,",
+ (char *)lane_mode[0]);
+ out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+ PCCR1_SGMIIH_KX_MASK);
+ break;
+ }
case FM1_DTSEC2:
+ if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) {
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_1gkx2");
+ fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2");
+ sprintf(buf, "%s%s%s", buf, "lane-d,",
+ (char *)lane_mode[0]);
+ out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+ PCCR1_SGMIIG_KX_MASK);
+ break;
+ }
case FM1_DTSEC9:
+ if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) {
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_1gkx9");
+ fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9");
+ sprintf(buf, "%s%s%s", buf, "lane-a,",
+ (char *)lane_mode[0]);
+ out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+ PCCR1_SGMIIE_KX_MASK);
+ break;
+ }
case FM1_DTSEC10:
+ if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) {
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_1gkx10");
+ fdt_status_okay_by_alias(fdt,
+ "1gkx_pcs_mdio10");
+ sprintf(buf, "%s%s%s", buf, "lane-b,",
+ (char *)lane_mode[0]);
+ out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+ PCCR1_SGMIIF_KX_MASK);
+ break;
+ }
if (mdio_mux[port] == EMI1_SLOT2) {
sprintf(alias, "phy_sgmii_s2_%x", phy);
fdt_set_phy_handle(fdt, compat, addr, alias);
@@ -213,7 +278,29 @@
}
break;
case FM1_DTSEC5:
+ if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) {
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_1gkx5");
+ fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5");
+ sprintf(buf, "%s%s%s", buf, "lane-g,",
+ (char *)lane_mode[0]);
+ out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+ PCCR1_SGMIIC_KX_MASK);
+ break;
+ }
case FM1_DTSEC6:
+ if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) {
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_1gkx6");
+ fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6");
+ sprintf(buf, "%s%s%s", buf, "lane-h,",
+ (char *)lane_mode[0]);
+ out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+ PCCR1_SGMIID_KX_MASK);
+ break;
+ }
if (mdio_mux[port] == EMI1_SLOT1) {
sprintf(alias, "phy_sgmii_s1_%x", phy);
fdt_set_phy_handle(fdt, compat, addr, alias);
@@ -257,6 +344,12 @@
default:
break;
}
+ if (media_type) {
+ /* set property for 1000BASE-KX in dtb */
+ off = fdt_node_offset_by_compat_reg(fdt,
+ "fsl,fman-memac-mdio", addr + 0x1000);
+ fdt_setprop_string(fdt, off, "lane-instance", buf);
+ }
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
switch (srds_s1) {
@@ -265,15 +358,77 @@
case 0x6c:
case 0x6d:
case 0x71:
- f_link.phy_id = port;
- f_link.duplex = 1;
- f_link.link_speed = 10000;
- f_link.pause = 0;
- f_link.asym_pause = 0;
- /* no PHY for XFI */
- fdt_delprop(fdt, offset, "phy-handle");
- fdt_setprop(fdt, offset, "fixed-link", &f_link,
- sizeof(f_link));
+ /*
+ * if the 10G is XFI, check hwconfig to see what is the
+ * media type, there are two types, fiber or copper,
+ * fix the dtb accordingly.
+ */
+ switch (port) {
+ case FM1_10GEC1:
+ if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
+ /* it's MAC9 */
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_xfi9");
+ fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9");
+ sprintf(buf, "%s%s%s", buf, "lane-a,",
+ (char *)lane_mode[1]);
+ }
+ break;
+ case FM1_10GEC2:
+ if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
+ /* it's MAC10 */
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_xfi10");
+ fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10");
+ sprintf(buf, "%s%s%s", buf, "lane-b,",
+ (char *)lane_mode[1]);
+ }
+ break;
+ case FM1_10GEC3:
+ if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) {
+ /* it's MAC1 */
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_xfi1");
+ fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1");
+ sprintf(buf, "%s%s%s", buf, "lane-c,",
+ (char *)lane_mode[1]);
+ }
+ break;
+ case FM1_10GEC4:
+ if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) {
+ /* it's MAC2 */
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_xfi2");
+ fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2");
+ sprintf(buf, "%s%s%s", buf, "lane-d,",
+ (char *)lane_mode[1]);
+ }
+ break;
+ default:
+ return;
+ }
+
+ if (!media_type) {
+ /* fixed-link is used for XFI fiber cable */
+ f_link.phy_id = port;
+ f_link.duplex = 1;
+ f_link.link_speed = 10000;
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+ fdt_delprop(fdt, offset, "phy-handle");
+ fdt_setprop(fdt, offset, "fixed-link", &f_link,
+ sizeof(f_link));
+ } else {
+ /* set property for copper cable */
+ off = fdt_node_offset_by_compat_reg(fdt,
+ "fsl,fman-memac-mdio", addr + 0x1000);
+ fdt_setprop_string(fdt, off,
+ "lane-instance", buf);
+ }
break;
default:
break;
diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
index fc6d256..5c470c3 100644
--- a/board/freescale/t208xqds/t208xqds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -437,7 +437,7 @@
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -460,4 +460,6 @@
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
+
+ return 0;
}
diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index be99fb8..341453b 100644
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -103,7 +103,7 @@
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -126,4 +126,6 @@
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
+
+ return 0;
}
diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c
index 479e124..5441094 100644
--- a/board/freescale/t4qds/t4240emu.c
+++ b/board/freescale/t4qds/t4240emu.c
@@ -69,7 +69,7 @@
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -83,4 +83,6 @@
fdt_fixup_liodn(blob);
fdt_fixup_dr_usb(blob, bd);
+
+ return 0;
}
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index 6205fea..4f2cccd 100644
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -683,7 +683,7 @@
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -706,6 +706,8 @@
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
+
+ return 0;
}
/*
diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c
index 2ff77b8..fac442b 100644
--- a/board/freescale/t4rdb/t4240rdb.c
+++ b/board/freescale/t4rdb/t4240rdb.c
@@ -88,7 +88,7 @@
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -111,6 +111,8 @@
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
+
+ return 0;
}
/*
diff --git a/board/galaxy5200/galaxy5200.c b/board/galaxy5200/galaxy5200.c
index 29e40eb..5d957b7 100644
--- a/board/galaxy5200/galaxy5200.c
+++ b/board/galaxy5200/galaxy5200.c
@@ -146,9 +146,11 @@
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t * bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/gateworks/gw_ventana/clocks.cfg b/board/gateworks/gw_ventana/clocks.cfg
deleted file mode 100644
index a8118a2..0000000
--- a/board/gateworks/gw_ventana/clocks.cfg
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2013 Gateworks Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF00000
-DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
-DATA 4, CCM_CCGR5, 0x0F0000C3
-DATA 4, CCM_CCGR6, 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en = 1 --> CKO1 enabled
- * cko1_div = 111 --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index df491a8..bb08cd2 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -1483,7 +1483,7 @@
* - board (full model from EEPROM)
* - peripherals removed from DTB if not loaded on board (per EEPROM config)
*/
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
struct ventana_board_info *info = &ventana_info;
struct ventana_eeprom_config *cfg;
@@ -1495,7 +1495,7 @@
if (getenv("fdt_noauto")) {
puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
- return;
+ return 0;
}
/* Update partition nodes using info from mtdparts env var */
@@ -1504,7 +1504,7 @@
if (!model) {
puts("invalid board info: Leaving FDT fully enabled\n");
- return;
+ return 0;
}
printf(" Adjusting FDT per EEPROM for %s...\n", model);
@@ -1523,7 +1523,7 @@
*/
if (getenv("fdt_noconfig")) {
puts(" Skiping periperhal config (fdt_noconfig defined)\n");
- return;
+ return 0;
}
cfg = econfig;
while (cfg->name) {
@@ -1533,6 +1533,8 @@
}
cfg++;
}
+
+ return 0;
}
#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/gateworks/gw_ventana/gw_ventana.cfg b/board/gateworks/gw_ventana/gw_ventana.cfg
deleted file mode 100644
index 9ab95f5..0000000
--- a/board/gateworks/gw_ventana/gw_ventana.cfg
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (C) 2013 Gateworks Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd, nand, sata
- */
-#ifdef CONFIG_SPI_FLASH
-BOOT_FROM spi
-#else
-BOOT_FROM nand
-#endif
-
-#define __ASSEMBLY__
-#include <config.h>
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-#include "clocks.cfg"
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index ca35b3c..d6a5847 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <i2c.h>
#include <asm/io.h>
+#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
@@ -392,6 +393,30 @@
mx6_dram_cfg(&sysinfo, calib, mem);
}
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xF00000CF, &iomux->gpr[4]);
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+}
+
/*
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM
@@ -405,6 +430,9 @@
/* setup AIPS and disable watchdog */
arch_cpu_init();
+ ccgr_init();
+ gpr_init();
+
/* iomux and setup of i2c */
board_early_init_f();
i2c_setup_iomux();
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index 1bac970..3a51d86 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -17,6 +17,7 @@
#include "../common/osd.h"
#include "../common/mclink.h"
+#include "../common/phy.h"
#include <i2c.h>
#include <pca953x.h>
@@ -98,8 +99,6 @@
unsigned int mclink_fpgacount;
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
-static int setup_88e1518(const char *bus, unsigned char addr);
-
int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
{
int res;
@@ -180,11 +179,11 @@
unsigned feature_carriers;
unsigned feature_video_channels;
- int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
+ int legacy = get_fpga_state(fpga) & FPGA_STATE_PLATFORM;
- FPGA_GET_REG(0, versions, &versions);
- FPGA_GET_REG(0, fpga_version, &fpga_version);
- FPGA_GET_REG(0, fpga_features, &fpga_features);
+ FPGA_GET_REG(fpga, versions, &versions);
+ FPGA_GET_REG(fpga, fpga_version, &fpga_version);
+ FPGA_GET_REG(fpga, fpga_features, &fpga_features);
unit_type = (versions & 0xf000) >> 12;
feature_compression = (fpga_features & 0xe000) >> 13;
@@ -369,10 +368,11 @@
unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
u16 fpga_features;
- int feature_carrier_speed = fpga_features & (1<<4);
+ int feature_carrier_speed;
bool ch0_rgmii2_present = false;
FPGA_GET_REG(0, fpga_features, &fpga_features);
+ feature_carrier_speed = fpga_features & (1<<4);
if (!legacy) {
/* Turn on Parade DP501 */
@@ -646,190 +646,3 @@
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
sizeof(bb_miiphy_buses[0]);
-
-enum {
- MIICMD_SET,
- MIICMD_MODIFY,
- MIICMD_VERIFY_VALUE,
- MIICMD_WAIT_FOR_VALUE,
-};
-
-struct mii_setupcmd {
- u8 token;
- u8 reg;
- u16 data;
- u16 mask;
- u32 timeout;
-};
-
-/*
- * verify we are talking to a 88e1518
- */
-struct mii_setupcmd verify_88e1518[] = {
- { MIICMD_SET, 22, 0x0000 },
- { MIICMD_VERIFY_VALUE, 2, 0x0141, 0xffff },
- { MIICMD_VERIFY_VALUE, 3, 0x0dd0, 0xfff0 },
-};
-
-/*
- * workaround for erratum mentioned in 88E1518 release notes
- */
-struct mii_setupcmd fixup_88e1518[] = {
- { MIICMD_SET, 22, 0x00ff },
- { MIICMD_SET, 17, 0x214b },
- { MIICMD_SET, 16, 0x2144 },
- { MIICMD_SET, 17, 0x0c28 },
- { MIICMD_SET, 16, 0x2146 },
- { MIICMD_SET, 17, 0xb233 },
- { MIICMD_SET, 16, 0x214d },
- { MIICMD_SET, 17, 0xcc0c },
- { MIICMD_SET, 16, 0x2159 },
- { MIICMD_SET, 22, 0x00fb },
- { MIICMD_SET, 7, 0xc00d },
- { MIICMD_SET, 22, 0x0000 },
-};
-
-/*
- * default initialization:
- * - set RGMII receive timing to "receive clock transition when data stable"
- * - set RGMII transmit timing to "transmit clock internally delayed"
- * - set RGMII output impedance target to 78,8 Ohm
- * - run output impedance calibration
- * - set autonegotiation advertise to 1000FD only
- */
-struct mii_setupcmd default_88e1518[] = {
- { MIICMD_SET, 22, 0x0002 },
- { MIICMD_MODIFY, 21, 0x0030, 0x0030 },
- { MIICMD_MODIFY, 25, 0x0000, 0x0003 },
- { MIICMD_MODIFY, 24, 0x8000, 0x8000 },
- { MIICMD_WAIT_FOR_VALUE, 24, 0x4000, 0x4000, 2000 },
- { MIICMD_SET, 22, 0x0000 },
- { MIICMD_MODIFY, 4, 0x0000, 0x01e0 },
- { MIICMD_MODIFY, 9, 0x0200, 0x0300 },
-};
-
-/*
- * turn off CLK125 for PHY daughterboard
- */
-struct mii_setupcmd ch1fix_88e1518[] = {
- { MIICMD_SET, 22, 0x0002 },
- { MIICMD_MODIFY, 16, 0x0006, 0x0006 },
- { MIICMD_SET, 22, 0x0000 },
-};
-
-/*
- * perform copper software reset
- */
-struct mii_setupcmd swreset_88e1518[] = {
- { MIICMD_SET, 22, 0x0000 },
- { MIICMD_MODIFY, 0, 0x8000, 0x8000 },
- { MIICMD_WAIT_FOR_VALUE, 0, 0x0000, 0x8000, 2000 },
-};
-
-static int process_setupcmd(const char *bus, unsigned char addr,
- struct mii_setupcmd *setupcmd)
-{
- int res;
- u8 reg = setupcmd->reg;
- u16 data = setupcmd->data;
- u16 mask = setupcmd->mask;
- u32 timeout = setupcmd->timeout;
- u16 orig_data;
- unsigned long start;
-
- debug("mii %s:%u reg %2u ", bus, addr, reg);
-
- switch (setupcmd->token) {
- case MIICMD_MODIFY:
- res = miiphy_read(bus, addr, reg, &orig_data);
- if (res)
- break;
- debug("is %04x. (value %04x mask %04x) ", orig_data, data,
- mask);
- data = (orig_data & ~mask) | (data & mask);
- case MIICMD_SET:
- debug("=> %04x\n", data);
- res = miiphy_write(bus, addr, reg, data);
- break;
- case MIICMD_VERIFY_VALUE:
- res = miiphy_read(bus, addr, reg, &orig_data);
- if (res)
- break;
- if ((orig_data & mask) != (data & mask))
- res = -1;
- debug("(value %04x mask %04x) == %04x? %s\n", data, mask,
- orig_data, res ? "FAIL" : "PASS");
- break;
- case MIICMD_WAIT_FOR_VALUE:
- res = -1;
- start = get_timer(0);
- while ((res != 0) && (get_timer(start) < timeout)) {
- res = miiphy_read(bus, addr, reg, &orig_data);
- if (res)
- continue;
- if ((orig_data & mask) != (data & mask))
- res = -1;
- }
- debug("(value %04x mask %04x) == %04x? %s after %lu ms\n", data,
- mask, orig_data, res ? "FAIL" : "PASS",
- get_timer(start));
- break;
- default:
- res = -1;
- break;
- }
-
- return res;
-}
-
-static int process_setup(const char *bus, unsigned char addr,
- struct mii_setupcmd *setupcmd, unsigned int count)
-{
- int res = 0;
- unsigned int k;
-
- for (k = 0; k < count; ++k) {
- res = process_setupcmd(bus, addr, &setupcmd[k]);
- if (res) {
- printf("mii cmd %u on bus %s addr %u failed, aborting setup",
- setupcmd[k].token, bus, addr);
- break;
- }
- }
-
- return res;
-}
-
-static int setup_88e1518(const char *bus, unsigned char addr)
-{
- int res;
-
- res = process_setup(bus, addr,
- verify_88e1518, ARRAY_SIZE(verify_88e1518));
- if (res)
- return res;
-
- res = process_setup(bus, addr,
- fixup_88e1518, ARRAY_SIZE(fixup_88e1518));
- if (res)
- return res;
-
- res = process_setup(bus, addr,
- default_88e1518, ARRAY_SIZE(default_88e1518));
- if (res)
- return res;
-
- if (addr) {
- res = process_setup(bus, addr,
- ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518));
- if (res)
- return res;
- }
-
- res = process_setup(bus, addr,
- swreset_88e1518, ARRAY_SIZE(swreset_88e1518));
- if (res)
- return res;
-
- return 0;
-}
diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
index 7f8b427..4957943 100644
--- a/board/gdsys/common/Makefile
+++ b/board/gdsys/common/Makefile
@@ -6,8 +6,10 @@
#
obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
+obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o
obj-$(CONFIG_IO) += miiphybb.o
obj-$(CONFIG_IO64) += miiphybb.o
-obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o
+obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o
obj-$(CONFIG_DLVISION_10G) += osd.o
obj-$(CONFIG_CONTROLCENTERD) += dp501.o
+obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o
diff --git a/board/gdsys/common/cmd_ioloop.c b/board/gdsys/common/cmd_ioloop.c
new file mode 100644
index 0000000..e0c74fe
--- /dev/null
+++ b/board/gdsys/common/cmd_ioloop.c
@@ -0,0 +1,295 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+
+#include <gdsys_fpga.h>
+
+enum {
+ STATE_TX_PACKET_BUILDING = 1<<0,
+ STATE_TX_TRANSMITTING = 1<<1,
+ STATE_TX_BUFFER_FULL = 1<<2,
+ STATE_TX_ERR = 1<<3,
+ STATE_RECEIVE_TIMEOUT = 1<<4,
+ STATE_PROC_RX_STORE_TIMEOUT = 1<<5,
+ STATE_PROC_RX_RECEIVE_TIMEOUT = 1<<6,
+ STATE_RX_DIST_ERR = 1<<7,
+ STATE_RX_LENGTH_ERR = 1<<8,
+ STATE_RX_FRAME_CTR_ERR = 1<<9,
+ STATE_RX_FCS_ERR = 1<<10,
+ STATE_RX_PACKET_DROPPED = 1<<11,
+ STATE_RX_DATA_LAST = 1<<12,
+ STATE_RX_DATA_FIRST = 1<<13,
+ STATE_RX_DATA_AVAILABLE = 1<<15,
+};
+
+enum {
+ CTRL_PROC_RECEIVE_ENABLE = 1<<12,
+ CTRL_FLUSH_TRANSMIT_BUFFER = 1<<15,
+};
+
+enum {
+ IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = 1<<5,
+ IRQ_CPU_PACKET_TRANSMITTED_EVENT = 1<<6,
+ IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = 1<<7,
+ IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = 1<<8,
+};
+
+struct io_generic_packet {
+ u16 target_address;
+ u16 source_address;
+ u8 packet_type;
+ u8 bc;
+ u16 packet_length;
+} __attribute__((__packed__));
+
+unsigned long long rx_ctr;
+unsigned long long tx_ctr;
+unsigned long long err_ctr;
+
+static void io_check_status(unsigned int fpga, u16 status, bool silent)
+{
+ u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR |
+ STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR |
+ STATE_RX_PACKET_DROPPED | STATE_TX_ERR;
+
+ if (!(status & mask)) {
+ FPGA_SET_REG(fpga, ep.rx_tx_status, status);
+ return;
+ }
+
+ err_ctr++;
+ FPGA_SET_REG(fpga, ep.rx_tx_status, status);
+
+ if (silent)
+ return;
+
+ if (status & STATE_RX_PACKET_DROPPED)
+ printf("RX_PACKET_DROPPED, status %04x\n", status);
+
+ if (status & STATE_RX_DIST_ERR)
+ printf("RX_DIST_ERR\n");
+ if (status & STATE_RX_LENGTH_ERR)
+ printf("RX_LENGTH_ERR\n");
+ if (status & STATE_RX_FRAME_CTR_ERR)
+ printf("RX_FRAME_CTR_ERR\n");
+ if (status & STATE_RX_FCS_ERR)
+ printf("RX_FCS_ERR\n");
+
+ if (status & STATE_TX_ERR)
+ printf("TX_ERR\n");
+}
+
+static void io_send(unsigned int fpga, unsigned int size)
+{
+ unsigned int k;
+ struct io_generic_packet packet = {
+ .source_address = 1,
+ .packet_type = 1,
+ .packet_length = size,
+ };
+ u16 *p = (u16 *)&packet;
+
+ for (k = 0; k < sizeof(packet) / 2; ++k)
+ FPGA_SET_REG(fpga, ep.transmit_data, *p++);
+
+ for (k = 0; k < (size + 1) / 2; ++k)
+ FPGA_SET_REG(fpga, ep.transmit_data, k);
+
+ FPGA_SET_REG(fpga, ep.rx_tx_control,
+ CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER);
+
+ tx_ctr++;
+}
+
+static void io_receive(unsigned int fpga)
+{
+ unsigned int k = 0;
+ u16 rx_tx_status;
+
+ FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+
+ while (rx_tx_status & STATE_RX_DATA_AVAILABLE) {
+ u16 rx;
+
+ if (rx_tx_status & STATE_RX_DATA_LAST)
+ rx_ctr++;
+
+ FPGA_GET_REG(fpga, ep.receive_data, &rx);
+
+ FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+
+ ++k;
+ }
+}
+
+static void io_reflect(unsigned int fpga)
+{
+ u16 buffer[128];
+
+ unsigned int k = 0;
+ unsigned int n;
+ u16 rx_tx_status;
+
+ FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+
+ while (rx_tx_status & STATE_RX_DATA_AVAILABLE) {
+ FPGA_GET_REG(fpga, ep.receive_data, &buffer[k++]);
+ if (rx_tx_status & STATE_RX_DATA_LAST)
+ break;
+
+ FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+ }
+
+ if (!k)
+ return;
+
+ for (n = 0; n < k; ++n)
+ FPGA_SET_REG(fpga, ep.transmit_data, buffer[n]);
+
+ FPGA_SET_REG(fpga, ep.rx_tx_control,
+ CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER);
+
+ tx_ctr++;
+}
+
+/*
+ * FPGA io-endpoint reflector
+ *
+ * Syntax:
+ * ioreflect {fpga} {reportrate}
+ */
+int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int fpga;
+ unsigned int rate = 0;
+ unsigned long long last_seen = 0;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ fpga = simple_strtoul(argv[1], NULL, 10);
+
+ /*
+ * If another parameter, it is the report rate in packets.
+ */
+ if (argc > 2)
+ rate = simple_strtoul(argv[2], NULL, 10);
+
+ /* enable receive path */
+ FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
+
+ /* set device address to dummy 1*/
+ FPGA_SET_REG(fpga, ep.device_address, 1);
+
+ rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
+
+ while (1) {
+ u16 top_int;
+ u16 rx_tx_status;
+
+ FPGA_GET_REG(fpga, top_interrupt, &top_int);
+ FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+
+ io_check_status(fpga, rx_tx_status, true);
+ if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
+ (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
+ io_reflect(fpga);
+
+ if (rate) {
+ if (!(tx_ctr % rate) && (tx_ctr != last_seen))
+ printf("refl %llu, err %llu\n", tx_ctr,
+ err_ctr);
+ last_seen = tx_ctr;
+ }
+
+ if (ctrlc())
+ break;
+ }
+
+ return 0;
+}
+
+/*
+ * FPGA io-endpoint looptest
+ *
+ * Syntax:
+ * ioloop {fpga} {size} {rate}
+ */
+#define DISP_LINE_LEN 16
+int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int fpga;
+ unsigned int size;
+ unsigned int rate = 0;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ /*
+ * FPGA is specified since argc > 2
+ */
+ fpga = simple_strtoul(argv[1], NULL, 10);
+
+ /*
+ * packet size is specified since argc > 2
+ */
+ size = simple_strtoul(argv[2], NULL, 10);
+
+ /*
+ * If another parameter, it is the test rate in packets per second.
+ */
+ if (argc > 3)
+ rate = simple_strtoul(argv[3], NULL, 10);
+
+ /* enable receive path */
+ FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
+
+ /* set device address to dummy 1*/
+ FPGA_SET_REG(fpga, ep.device_address, 1);
+
+ rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
+
+ while (1) {
+ u16 top_int;
+ u16 rx_tx_status;
+
+ FPGA_GET_REG(fpga, top_interrupt, &top_int);
+ FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+
+ io_check_status(fpga, rx_tx_status, false);
+ if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
+ io_send(fpga, size);
+ if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
+ io_receive(fpga);
+
+ if (rate) {
+ if (ctrlc())
+ break;
+ udelay(1000000 / rate);
+ if (!(tx_ctr % rate))
+ printf("d %lld, tx %llu, rx %llu, err %llu\n",
+ tx_ctr - rx_ctr, tx_ctr, rx_ctr,
+ err_ctr);
+ }
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ ioloop, 4, 0, do_ioloop,
+ "fpga io-endpoint looptest",
+ "fpga packetsize [packets/sec]"
+);
+
+U_BOOT_CMD(
+ ioreflect, 3, 0, do_ioreflect,
+ "fpga io-endpoint reflector",
+ "fpga reportrate"
+);
diff --git a/board/gdsys/common/ihs_mdio.c b/board/gdsys/common/ihs_mdio.c
new file mode 100644
index 0000000..1d6eb7b
--- /dev/null
+++ b/board/gdsys/common/ihs_mdio.c
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <gdsys_fpga.h>
+#include <miiphy.h>
+
+#include "ihs_mdio.h"
+
+static int ihs_mdio_idle(struct mii_dev *bus)
+{
+ struct ihs_mdio_info *info = bus->priv;
+ u16 val;
+ unsigned int ctr = 0;
+
+ do {
+ FPGA_GET_REG(info->fpga, mdio.control, &val);
+ udelay(100);
+ if (ctr++ > 10)
+ return -1;
+ } while (!(val & (1 << 12)));
+
+ return 0;
+}
+
+static int ihs_mdio_reset(struct mii_dev *bus)
+{
+ ihs_mdio_idle(bus);
+
+ return 0;
+}
+
+static int ihs_mdio_read(struct mii_dev *bus, int addr, int dev_addr,
+ int regnum)
+{
+ struct ihs_mdio_info *info = bus->priv;
+ u16 val;
+
+ ihs_mdio_idle(bus);
+
+ FPGA_SET_REG(info->fpga, mdio.control,
+ ((addr & 0x1f) << 5) | (regnum & 0x1f) | (2 << 10));
+
+ /* wait for rx data available */
+ udelay(100);
+
+ FPGA_GET_REG(info->fpga, mdio.rx_data, &val);
+
+ return val;
+}
+
+static int ihs_mdio_write(struct mii_dev *bus, int addr, int dev_addr,
+ int regnum, u16 value)
+{
+ struct ihs_mdio_info *info = bus->priv;
+
+ ihs_mdio_idle(bus);
+
+ FPGA_SET_REG(info->fpga, mdio.address_data, value);
+ FPGA_SET_REG(info->fpga, mdio.control,
+ ((addr & 0x1f) << 5) | (regnum & 0x1f) | (1 << 10));
+
+ return 0;
+}
+
+int ihs_mdio_init(struct ihs_mdio_info *info)
+{
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate FSL MDIO bus\n");
+ return -1;
+ }
+
+ bus->read = ihs_mdio_read;
+ bus->write = ihs_mdio_write;
+ bus->reset = ihs_mdio_reset;
+ sprintf(bus->name, info->name);
+
+ bus->priv = info;
+
+ return mdio_register(bus);
+}
diff --git a/board/gdsys/common/ihs_mdio.h b/board/gdsys/common/ihs_mdio.h
new file mode 100644
index 0000000..64b4049
--- /dev/null
+++ b/board/gdsys/common/ihs_mdio.h
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _IHS_MDIO_H_
+#define _IHS_MDIO_H_
+
+struct ihs_mdio_info {
+ u32 fpga;
+ char *name;
+};
+
+int ihs_mdio_init(struct ihs_mdio_info *info);
+
+#endif
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index 1c765e4..55ecdf1 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -289,7 +289,6 @@
{
u16 version;
u16 features;
- u8 value;
int old_bus = i2c_get_bus_num();
bool pixclock_present = false;
bool output_driver_present = false;
@@ -330,7 +329,8 @@
#ifdef CONFIG_SYS_CH7301_I2C
i2c_set_bus_num(ch7301_i2c[screen]);
if (!i2c_probe(CH7301_I2C_ADDR)) {
- value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
+ u8 value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
+
if (value == 0x17) {
i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
@@ -345,8 +345,7 @@
#ifdef CONFIG_SYS_SIL1178_I2C
i2c_set_bus_num(sil1178_i2c[screen]);
if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) {
- value = i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02);
- if (value == 0x06) {
+ if (i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02) == 0x06) {
/*
* magic initialization sequence,
* adapted from datasheet
diff --git a/board/gdsys/common/phy.c b/board/gdsys/common/phy.c
new file mode 100644
index 0000000..fb92658
--- /dev/null
+++ b/board/gdsys/common/phy.c
@@ -0,0 +1,280 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <miiphy.h>
+
+enum {
+ MIICMD_SET,
+ MIICMD_MODIFY,
+ MIICMD_VERIFY_VALUE,
+ MIICMD_WAIT_FOR_VALUE,
+};
+
+struct mii_setupcmd {
+ u8 token;
+ u8 reg;
+ u16 data;
+ u16 mask;
+ u32 timeout;
+};
+
+/*
+ * verify we are talking to a 88e1518
+ */
+struct mii_setupcmd verify_88e1518[] = {
+ { MIICMD_SET, 22, 0x0000 },
+ { MIICMD_VERIFY_VALUE, 2, 0x0141, 0xffff },
+ { MIICMD_VERIFY_VALUE, 3, 0x0dd0, 0xfff0 },
+};
+
+/*
+ * workaround for erratum mentioned in 88E1518 release notes
+ */
+struct mii_setupcmd fixup_88e1518[] = {
+ { MIICMD_SET, 22, 0x00ff },
+ { MIICMD_SET, 17, 0x214b },
+ { MIICMD_SET, 16, 0x2144 },
+ { MIICMD_SET, 17, 0x0c28 },
+ { MIICMD_SET, 16, 0x2146 },
+ { MIICMD_SET, 17, 0xb233 },
+ { MIICMD_SET, 16, 0x214d },
+ { MIICMD_SET, 17, 0xcc0c },
+ { MIICMD_SET, 16, 0x2159 },
+ { MIICMD_SET, 22, 0x00fb },
+ { MIICMD_SET, 7, 0xc00d },
+ { MIICMD_SET, 22, 0x0000 },
+};
+
+/*
+ * default initialization:
+ * - set RGMII receive timing to "receive clock transition when data stable"
+ * - set RGMII transmit timing to "transmit clock internally delayed"
+ * - set RGMII output impedance target to 78,8 Ohm
+ * - run output impedance calibration
+ * - set autonegotiation advertise to 1000FD only
+ */
+struct mii_setupcmd default_88e1518[] = {
+ { MIICMD_SET, 22, 0x0002 },
+ { MIICMD_MODIFY, 21, 0x0030, 0x0030 },
+ { MIICMD_MODIFY, 25, 0x0000, 0x0003 },
+ { MIICMD_MODIFY, 24, 0x8000, 0x8000 },
+ { MIICMD_WAIT_FOR_VALUE, 24, 0x4000, 0x4000, 2000 },
+ { MIICMD_SET, 22, 0x0000 },
+ { MIICMD_MODIFY, 4, 0x0000, 0x01e0 },
+ { MIICMD_MODIFY, 9, 0x0200, 0x0300 },
+};
+
+/*
+ * turn off CLK125 for PHY daughterboard
+ */
+struct mii_setupcmd ch1fix_88e1518[] = {
+ { MIICMD_SET, 22, 0x0002 },
+ { MIICMD_MODIFY, 16, 0x0006, 0x0006 },
+ { MIICMD_SET, 22, 0x0000 },
+};
+
+/*
+ * perform copper software reset
+ */
+struct mii_setupcmd swreset_88e1518[] = {
+ { MIICMD_SET, 22, 0x0000 },
+ { MIICMD_MODIFY, 0, 0x8000, 0x8000 },
+ { MIICMD_WAIT_FOR_VALUE, 0, 0x0000, 0x8000, 2000 },
+};
+
+/*
+ * special one for 88E1514:
+ * Force SGMII to Copper mode
+ */
+struct mii_setupcmd mii_to_copper_88e1514[] = {
+ { MIICMD_SET, 22, 0x0012 },
+ { MIICMD_MODIFY, 20, 0x0001, 0x0007 },
+ { MIICMD_MODIFY, 20, 0x8000, 0x8000 },
+ { MIICMD_SET, 22, 0x0000 },
+};
+
+/*
+ * turn off SGMII auto-negotiation
+ */
+struct mii_setupcmd sgmii_autoneg_off_88e1518[] = {
+ { MIICMD_SET, 22, 0x0001 },
+ { MIICMD_MODIFY, 0, 0x0000, 0x1000 },
+ { MIICMD_MODIFY, 0, 0x8000, 0x8000 },
+ { MIICMD_SET, 22, 0x0000 },
+};
+
+/*
+ * invert LED2 polarity
+ */
+struct mii_setupcmd invert_led2_88e1514[] = {
+ { MIICMD_SET, 22, 0x0003 },
+ { MIICMD_MODIFY, 17, 0x0030, 0x0010 },
+ { MIICMD_SET, 22, 0x0000 },
+};
+
+static int process_setupcmd(const char *bus, unsigned char addr,
+ struct mii_setupcmd *setupcmd)
+{
+ int res;
+ u8 reg = setupcmd->reg;
+ u16 data = setupcmd->data;
+ u16 mask = setupcmd->mask;
+ u32 timeout = setupcmd->timeout;
+ u16 orig_data;
+ unsigned long start;
+
+ debug("mii %s:%u reg %2u ", bus, addr, reg);
+
+ switch (setupcmd->token) {
+ case MIICMD_MODIFY:
+ res = miiphy_read(bus, addr, reg, &orig_data);
+ if (res)
+ break;
+ debug("is %04x. (value %04x mask %04x) ", orig_data, data,
+ mask);
+ data = (orig_data & ~mask) | (data & mask);
+ /* fallthrough */
+ case MIICMD_SET:
+ debug("=> %04x\n", data);
+ res = miiphy_write(bus, addr, reg, data);
+ break;
+ case MIICMD_VERIFY_VALUE:
+ res = miiphy_read(bus, addr, reg, &orig_data);
+ if (res)
+ break;
+ if ((orig_data & mask) != (data & mask))
+ res = -1;
+ debug("(value %04x mask %04x) == %04x? %s\n", data, mask,
+ orig_data, res ? "FAIL" : "PASS");
+ break;
+ case MIICMD_WAIT_FOR_VALUE:
+ res = -1;
+ start = get_timer(0);
+ while ((res != 0) && (get_timer(start) < timeout)) {
+ res = miiphy_read(bus, addr, reg, &orig_data);
+ if (res)
+ continue;
+ if ((orig_data & mask) != (data & mask))
+ res = -1;
+ }
+ debug("(value %04x mask %04x) == %04x? %s after %lu ms\n", data,
+ mask, orig_data, res ? "FAIL" : "PASS",
+ get_timer(start));
+ break;
+ default:
+ res = -1;
+ break;
+ }
+
+ return res;
+}
+
+static int process_setup(const char *bus, unsigned char addr,
+ struct mii_setupcmd *setupcmd, unsigned int count)
+{
+ int res = 0;
+ unsigned int k;
+
+ for (k = 0; k < count; ++k) {
+ res = process_setupcmd(bus, addr, &setupcmd[k]);
+ if (res) {
+ printf("mii cmd %u on bus %s addr %u failed, aborting setup\n",
+ setupcmd[k].token, bus, addr);
+ break;
+ }
+ }
+
+ return res;
+}
+
+int setup_88e1518(const char *bus, unsigned char addr)
+{
+ int res;
+
+ res = process_setup(bus, addr,
+ verify_88e1518, ARRAY_SIZE(verify_88e1518));
+ if (res)
+ return res;
+
+ res = process_setup(bus, addr,
+ fixup_88e1518, ARRAY_SIZE(fixup_88e1518));
+ if (res)
+ return res;
+
+ res = process_setup(bus, addr,
+ default_88e1518, ARRAY_SIZE(default_88e1518));
+ if (res)
+ return res;
+
+ if (addr) {
+ res = process_setup(bus, addr,
+ ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518));
+ if (res)
+ return res;
+ }
+
+ res = process_setup(bus, addr,
+ swreset_88e1518, ARRAY_SIZE(swreset_88e1518));
+ if (res)
+ return res;
+
+ return 0;
+}
+
+int setup_88e1514(const char *bus, unsigned char addr)
+{
+ int res;
+
+ res = process_setup(bus, addr,
+ verify_88e1518, ARRAY_SIZE(verify_88e1518));
+ if (res)
+ return res;
+
+ res = process_setup(bus, addr,
+ fixup_88e1518, ARRAY_SIZE(fixup_88e1518));
+ if (res)
+ return res;
+
+ res = process_setup(bus, addr,
+ mii_to_copper_88e1514,
+ ARRAY_SIZE(mii_to_copper_88e1514));
+ if (res)
+ return res;
+
+ res = process_setup(bus, addr,
+ sgmii_autoneg_off_88e1518,
+ ARRAY_SIZE(sgmii_autoneg_off_88e1518));
+ if (res)
+ return res;
+
+ res = process_setup(bus, addr,
+ invert_led2_88e1514,
+ ARRAY_SIZE(invert_led2_88e1514));
+ if (res)
+ return res;
+
+ res = process_setup(bus, addr,
+ default_88e1518, ARRAY_SIZE(default_88e1518));
+ if (res)
+ return res;
+
+ if (addr) {
+ res = process_setup(bus, addr,
+ ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518));
+ if (res)
+ return res;
+ }
+
+ res = process_setup(bus, addr,
+ swreset_88e1518, ARRAY_SIZE(swreset_88e1518));
+ if (res)
+ return res;
+
+ return 0;
+}
diff --git a/board/gdsys/common/phy.h b/board/gdsys/common/phy.h
new file mode 100644
index 0000000..afbdc65
--- /dev/null
+++ b/board/gdsys/common/phy.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PHY_H_
+#define _PHY_H_
+
+int setup_88e1514(const char *bus, unsigned char addr);
+int setup_88e1518(const char *bus, unsigned char addr);
+
+#endif
diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c
index ee6f9e0..8d01d8b 100644
--- a/board/gdsys/intip/intip.c
+++ b/board/gdsys/intip/intip.c
@@ -206,7 +206,7 @@
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
extern void __ft_board_setup(void *blob, bd_t *bd);
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
__ft_board_setup(blob, bd);
@@ -215,5 +215,7 @@
fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
"disabled", sizeof("disabled"), 1);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig
new file mode 100644
index 0000000..43e1663
--- /dev/null
+++ b/board/gdsys/mpc8308/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_HRCON
+
+config SYS_BOARD
+ default "mpc8308"
+
+config SYS_VENDOR
+ default "gdsys"
+
+config SYS_CONFIG_NAME
+ default "hrcon"
+
+endif
diff --git a/board/gdsys/mpc8308/MAINTAINERS b/board/gdsys/mpc8308/MAINTAINERS
new file mode 100644
index 0000000..a7853a5
--- /dev/null
+++ b/board/gdsys/mpc8308/MAINTAINERS
@@ -0,0 +1,6 @@
+MPC8308 BOARD
+M: Dirk Eibach <eibach@gdsys.de>
+S: Maintained
+F: board/gdsys/mpc8308/
+F: include/configs/hrcon.h
+F: configs/hrcon_defconfig
diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile
new file mode 100644
index 0000000..b5dfdbb
--- /dev/null
+++ b/board/gdsys/mpc8308/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2014
+# Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mpc8308.o sdram.o
+obj-$(CONFIG_HRCON) += hrcon.o
diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c
new file mode 100644
index 0000000..e4434b3
--- /dev/null
+++ b/board/gdsys/mpc8308/hrcon.c
@@ -0,0 +1,677 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <spi.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <fsl_esdhc.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+#include "mpc8308.h"
+
+#include <gdsys_fpga.h>
+
+#include "../common/osd.h"
+#include "../common/mclink.h"
+#include "../common/phy.h"
+
+#include <pca953x.h>
+#include <pca9698.h>
+
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MAX_MUX_CHANNELS 2
+
+enum {
+ UNITTYPE_MAIN_SERVER = 0,
+ UNITTYPE_MAIN_USER = 1,
+ UNITTYPE_VIDEO_SERVER = 2,
+ UNITTYPE_VIDEO_USER = 3,
+};
+
+enum {
+ UNITTYPEPCB_DVI = 0,
+ UNITTYPEPCB_DP_165 = 1,
+ UNITTYPEPCB_DP_300 = 2,
+ UNITTYPEPCB_HDMI = 3,
+};
+
+enum {
+ HWVER_100 = 0,
+ HWVER_110 = 1,
+};
+
+enum {
+ FPGA_HWVER_200 = 0,
+ FPGA_HWVER_210 = 1,
+};
+
+enum {
+ COMPRESSION_NONE = 0,
+ COMPRESSION_TYPE1_DELTA = 1,
+ COMPRESSION_TYPE1_TYPE2_DELTA = 3,
+};
+
+enum {
+ AUDIO_NONE = 0,
+ AUDIO_TX = 1,
+ AUDIO_RX = 2,
+ AUDIO_RXTX = 3,
+};
+
+enum {
+ SYSCLK_147456 = 0,
+};
+
+enum {
+ RAM_DDR2_32 = 0,
+ RAM_DDR3_32 = 1,
+};
+
+enum {
+ CARRIER_SPEED_1G = 0,
+ CARRIER_SPEED_2_5G = 1,
+};
+
+enum {
+ MCFPGA_DONE = 1 << 0,
+ MCFPGA_INIT_N = 1 << 1,
+ MCFPGA_PROGRAM_N = 1 << 2,
+ MCFPGA_UPDATE_ENABLE_N = 1 << 3,
+ MCFPGA_RESET_N = 1 << 4,
+};
+
+enum {
+ GPIO_MDC = 1 << 14,
+ GPIO_MDIO = 1 << 15,
+};
+
+unsigned int mclink_fpgacount;
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
+{
+ int res;
+
+ switch (fpga) {
+ case 0:
+ out_le16(reg, data);
+ break;
+ default:
+ res = mclink_send(fpga - 1, regoff, data);
+ if (res < 0) {
+ printf("mclink_send reg %02lx data %04x returned %d\n",
+ regoff, data, res);
+ return res;
+ }
+ break;
+ }
+
+ return 0;
+}
+
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
+{
+ int res;
+
+ switch (fpga) {
+ case 0:
+ *data = in_le16(reg);
+ break;
+ default:
+ if (fpga > mclink_fpgacount)
+ return -EINVAL;
+ res = mclink_receive(fpga - 1, regoff, data);
+ if (res < 0) {
+ printf("mclink_receive reg %02lx returned %d\n",
+ regoff, res);
+ return res;
+ }
+ }
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+ bool hw_type_cat = pca9698_get_value(0x20, 20);
+
+ puts("Board: ");
+
+ printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+
+ puts("\n");
+
+ return 0;
+}
+
+static void print_fpga_info(unsigned int fpga, bool rgmii2_present)
+{
+ u16 versions;
+ u16 fpga_version;
+ u16 fpga_features;
+ unsigned unit_type;
+ unsigned unit_type_pcb_video;
+ unsigned hardware_version;
+ unsigned feature_compression;
+ unsigned feature_osd;
+ unsigned feature_audio;
+ unsigned feature_sysclock;
+ unsigned feature_ramconfig;
+ unsigned feature_carrier_speed;
+ unsigned feature_carriers;
+ unsigned feature_video_channels;
+
+ FPGA_GET_REG(fpga, versions, &versions);
+ FPGA_GET_REG(fpga, fpga_version, &fpga_version);
+ FPGA_GET_REG(fpga, fpga_features, &fpga_features);
+
+ unit_type = (versions & 0xf000) >> 12;
+ unit_type_pcb_video = (versions & 0x01c0) >> 6;
+ feature_compression = (fpga_features & 0xe000) >> 13;
+ feature_osd = fpga_features & (1<<11);
+ feature_audio = (fpga_features & 0x0600) >> 9;
+ feature_sysclock = (fpga_features & 0x0180) >> 7;
+ feature_ramconfig = (fpga_features & 0x0060) >> 5;
+ feature_carrier_speed = fpga_features & (1<<4);
+ feature_carriers = (fpga_features & 0x000c) >> 2;
+ feature_video_channels = fpga_features & 0x0003;
+
+ switch (unit_type) {
+ case UNITTYPE_MAIN_USER:
+ printf("Mainchannel");
+ break;
+
+ case UNITTYPE_VIDEO_USER:
+ printf("Videochannel");
+ break;
+
+ default:
+ printf("UnitType %d(not supported)", unit_type);
+ break;
+ }
+
+ if (unit_type == UNITTYPE_MAIN_USER) {
+ hardware_version =
+ (!!pca9698_get_value(0x20, 24) << 0)
+ | (!!pca9698_get_value(0x20, 25) << 1)
+ | (!!pca9698_get_value(0x20, 26) << 2)
+ | (!!pca9698_get_value(0x20, 27) << 3)
+ | (!!pca9698_get_value(0x20, 28) << 4);
+ switch (hardware_version) {
+ case HWVER_100:
+ printf(" HW-Ver 1.00,");
+ break;
+
+ case HWVER_110:
+ printf(" HW-Ver 1.10,");
+ break;
+
+ default:
+ printf(" HW-Ver %d(not supported),",
+ hardware_version);
+ break;
+ }
+ if (rgmii2_present)
+ printf(" RGMII2,");
+ }
+
+ if (unit_type == UNITTYPE_VIDEO_USER) {
+ hardware_version = versions & 0x000f;
+ switch (hardware_version) {
+ case FPGA_HWVER_200:
+ printf(" HW-Ver 2.00,");
+ break;
+
+ case FPGA_HWVER_210:
+ printf(" HW-Ver 2.10,");
+ break;
+
+ default:
+ printf(" HW-Ver %d(not supported),",
+ hardware_version);
+ break;
+ }
+ }
+
+ switch (unit_type_pcb_video) {
+ case UNITTYPEPCB_DVI:
+ printf(" DVI,");
+ break;
+
+ case UNITTYPEPCB_DP_165:
+ printf(" DP 165MPix/s,");
+ break;
+
+ case UNITTYPEPCB_DP_300:
+ printf(" DP 300MPix/s,");
+ break;
+
+ case UNITTYPEPCB_HDMI:
+ printf(" HDMI,");
+ break;
+ }
+
+ printf(" FPGA V %d.%02d\n features:",
+ fpga_version / 100, fpga_version % 100);
+
+
+ switch (feature_compression) {
+ case COMPRESSION_NONE:
+ printf(" no compression");
+ break;
+
+ case COMPRESSION_TYPE1_DELTA:
+ printf(" type1-deltacompression");
+ break;
+
+ case COMPRESSION_TYPE1_TYPE2_DELTA:
+ printf(" type1-deltacompression, type2-inlinecompression");
+ break;
+
+ default:
+ printf(" compression %d(not supported)", feature_compression);
+ break;
+ }
+
+ printf(", %sosd", feature_osd ? "" : "no ");
+
+ switch (feature_audio) {
+ case AUDIO_NONE:
+ printf(", no audio");
+ break;
+
+ case AUDIO_TX:
+ printf(", audio tx");
+ break;
+
+ case AUDIO_RX:
+ printf(", audio rx");
+ break;
+
+ case AUDIO_RXTX:
+ printf(", audio rx+tx");
+ break;
+
+ default:
+ printf(", audio %d(not supported)", feature_audio);
+ break;
+ }
+
+ puts(",\n ");
+
+ switch (feature_sysclock) {
+ case SYSCLK_147456:
+ printf("clock 147.456 MHz");
+ break;
+
+ default:
+ printf("clock %d(not supported)", feature_sysclock);
+ break;
+ }
+
+ switch (feature_ramconfig) {
+ case RAM_DDR2_32:
+ printf(", RAM 32 bit DDR2");
+ break;
+
+ case RAM_DDR3_32:
+ printf(", RAM 32 bit DDR3");
+ break;
+
+ default:
+ printf(", RAM %d(not supported)", feature_ramconfig);
+ break;
+ }
+
+ printf(", %d carrier(s) %s", feature_carriers,
+ feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
+
+ printf(", %d video channel(s)\n", feature_video_channels);
+}
+
+int last_stage_init(void)
+{
+ int slaves;
+ unsigned int k;
+ unsigned int mux_ch;
+ unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
+ u16 fpga_features;
+ bool hw_type_cat = pca9698_get_value(0x20, 20);
+ bool ch0_rgmii2_present = false;
+
+ FPGA_GET_REG(0, fpga_features, &fpga_features);
+
+ /* Turn on Parade DP501 */
+ pca9698_direction_output(0x20, 10, 1);
+
+ ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
+
+ /* wait for FPGA done */
+ for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
+ unsigned int ctr = 0;
+
+ if (i2c_probe(mclink_controllers[k]))
+ continue;
+
+ while (!(pca953x_get_val(mclink_controllers[k])
+ & MCFPGA_DONE)) {
+ udelay(100000);
+ if (ctr++ > 5) {
+ printf("no done for mclink_controller %d\n", k);
+ break;
+ }
+ }
+ }
+
+ if (hw_type_cat) {
+ miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
+ bb_miiphy_write);
+ for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
+ if ((mux_ch == 1) && !ch0_rgmii2_present)
+ continue;
+
+ setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
+ }
+ }
+
+ /* give slave-PLLs and Parade DP501 some time to be up and running */
+ udelay(500000);
+
+ mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
+ slaves = mclink_probe();
+ mclink_fpgacount = 0;
+
+ print_fpga_info(0, ch0_rgmii2_present);
+ osd_probe(0);
+
+ if (slaves <= 0)
+ return 0;
+
+ mclink_fpgacount = slaves;
+
+ for (k = 1; k <= slaves; ++k) {
+ FPGA_GET_REG(k, fpga_features, &fpga_features);
+
+ print_fpga_info(k, false);
+ osd_probe(k);
+ if (hw_type_cat) {
+ miiphy_register(bb_miiphy_buses[k].name,
+ bb_miiphy_read, bb_miiphy_write);
+ setup_88e1514(bb_miiphy_buses[k].name, 0);
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * provide access to fpga gpios (for I2C bitbang)
+ * (these may look all too simple but make iocon.h much more readable)
+ */
+void fpga_gpio_set(unsigned int bus, int pin)
+{
+ FPGA_SET_REG(bus, gpio.set, pin);
+}
+
+void fpga_gpio_clear(unsigned int bus, int pin)
+{
+ FPGA_SET_REG(bus, gpio.clear, pin);
+}
+
+int fpga_gpio_get(unsigned int bus, int pin)
+{
+ u16 val;
+
+ FPGA_GET_REG(bus, gpio.read, &val);
+
+ return val & pin;
+}
+
+void mpc8308_init(void)
+{
+ pca9698_direction_output(0x20, 4, 1);
+}
+
+void mpc8308_set_fpga_reset(unsigned state)
+{
+ pca9698_set_value(0x20, 4, state ? 0 : 1);
+}
+
+void mpc8308_setup_hw(void)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ /*
+ * set "startup-finished"-gpios
+ */
+ setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
+ setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
+}
+
+int mpc8308_get_fpga_done(unsigned fpga)
+{
+ return pca9698_get_value(0x20, 19);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ sysconf83xx_t *sysconf = &immr->sysconf;
+
+ /* Enable cache snooping in eSDHC system configuration register */
+ out_be32(&sysconf->sdhccr, 0x02000000);
+
+ return fsl_esdhc_mmc_init(bd);
+}
+#endif
+
+static struct pci_region pcie_regions_0[] = {
+ {
+ .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+ .size = CONFIG_SYS_PCIE1_MEM_SIZE,
+ .flags = PCI_REGION_MEM,
+ },
+ {
+ .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+ .size = CONFIG_SYS_PCIE1_IO_SIZE,
+ .flags = PCI_REGION_IO,
+ },
+};
+
+void pci_init_board(void)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ sysconf83xx_t *sysconf = &immr->sysconf;
+ law83xx_t *pcie_law = sysconf->pcielaw;
+ struct pci_region *pcie_reg[] = { pcie_regions_0 };
+
+ fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
+ /* Deassert the resets in the control register */
+ out_be32(&sysconf->pecr1, 0xE0008000);
+ udelay(2000);
+
+ /* Configure PCI Express Local Access Windows */
+ out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+ out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+ mpc83xx_pcie_init(1, pcie_reg);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ info->portwidth = FLASH_CFI_16BIT;
+ info->chipwidth = FLASH_CFI_BY16;
+ info->interface = FLASH_CFI_X16;
+ return 1;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+ fdt_fixup_dr_usb(blob, bd);
+ fdt_fixup_esdhc(blob, bd);
+
+ return 0;
+}
+#endif
+
+/*
+ * FPGA MII bitbang implementation
+ */
+
+struct fpga_mii {
+ unsigned fpga;
+ int mdio;
+} fpga_mii[] = {
+ { 0, 1},
+ { 1, 1},
+ { 2, 1},
+ { 3, 1},
+};
+
+static int mii_dummy_init(struct bb_miiphy_bus *bus)
+{
+ return 0;
+}
+
+static int mii_mdio_active(struct bb_miiphy_bus *bus)
+{
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ if (fpga_mii->mdio)
+ FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+ else
+ FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
+
+ return 0;
+}
+
+static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+
+ return 0;
+}
+
+static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ if (v)
+ FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+ else
+ FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
+
+ fpga_mii->mdio = v;
+
+ return 0;
+}
+
+static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+ u16 gpio;
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
+
+ *v = ((gpio & GPIO_MDIO) != 0);
+
+ return 0;
+}
+
+static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ if (v)
+ FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
+ else
+ FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
+
+ return 0;
+}
+
+static int mii_delay(struct bb_miiphy_bus *bus)
+{
+ udelay(1);
+
+ return 0;
+}
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+ {
+ .name = "board0",
+ .init = mii_dummy_init,
+ .mdio_active = mii_mdio_active,
+ .mdio_tristate = mii_mdio_tristate,
+ .set_mdio = mii_set_mdio,
+ .get_mdio = mii_get_mdio,
+ .set_mdc = mii_set_mdc,
+ .delay = mii_delay,
+ .priv = &fpga_mii[0],
+ },
+ {
+ .name = "board1",
+ .init = mii_dummy_init,
+ .mdio_active = mii_mdio_active,
+ .mdio_tristate = mii_mdio_tristate,
+ .set_mdio = mii_set_mdio,
+ .get_mdio = mii_get_mdio,
+ .set_mdc = mii_set_mdc,
+ .delay = mii_delay,
+ .priv = &fpga_mii[1],
+ },
+ {
+ .name = "board2",
+ .init = mii_dummy_init,
+ .mdio_active = mii_mdio_active,
+ .mdio_tristate = mii_mdio_tristate,
+ .set_mdio = mii_set_mdio,
+ .get_mdio = mii_get_mdio,
+ .set_mdc = mii_set_mdc,
+ .delay = mii_delay,
+ .priv = &fpga_mii[2],
+ },
+ {
+ .name = "board3",
+ .init = mii_dummy_init,
+ .mdio_active = mii_mdio_active,
+ .mdio_tristate = mii_mdio_tristate,
+ .set_mdio = mii_set_mdio,
+ .get_mdio = mii_get_mdio,
+ .set_mdc = mii_set_mdc,
+ .delay = mii_delay,
+ .priv = &fpga_mii[3],
+ },
+};
+
+int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
+ sizeof(bb_miiphy_buses[0]);
diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c
new file mode 100644
index 0000000..4338a33
--- /dev/null
+++ b/board/gdsys/mpc8308/mpc8308.c
@@ -0,0 +1,109 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/global_data.h>
+
+#include "mpc8308.h"
+#include <gdsys_fpga.h>
+
+#define REFLECTION_TESTPATTERN 0xdede
+#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
+
+#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
+#define REFLECTION_TESTREG reflection_low
+#else
+#define REFLECTION_TESTREG reflection_high
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_fpga_state(unsigned dev)
+{
+ return gd->arch.fpga_state[dev];
+}
+
+void print_fpga_state(unsigned dev)
+{
+ if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+ puts(" Waiting for FPGA-DONE timed out.\n");
+ if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+ puts(" FPGA reflection test failed.\n");
+}
+
+int board_early_init_f(void)
+{
+ unsigned k;
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+ gd->arch.fpga_state[k] = 0;
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ unsigned k;
+ unsigned ctr;
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+ gd->arch.fpga_state[k] = 0;
+
+ /*
+ * reset FPGA
+ */
+ mpc8308_init();
+
+ mpc8308_set_fpga_reset(1);
+
+ mpc8308_setup_hw();
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+ ctr = 0;
+ while (!mpc8308_get_fpga_done(k)) {
+ udelay(100000);
+ if (ctr++ > 5) {
+ gd->arch.fpga_state[k] |=
+ FPGA_STATE_DONE_FAILED;
+ break;
+ }
+ }
+ }
+
+ udelay(10);
+
+ mpc8308_set_fpga_reset(0);
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+ /*
+ * wait for fpga out of reset
+ */
+ ctr = 0;
+ while (1) {
+ u16 val;
+
+ FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
+
+ FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
+ if (val == REFLECTION_TESTPATTERN_INV)
+ break;
+
+ udelay(100000);
+ if (ctr++ > 5) {
+ gd->arch.fpga_state[k] |=
+ FPGA_STATE_REFLECTION_FAILED;
+ break;
+ }
+ }
+ }
+
+ return 0;
+}
diff --git a/board/gdsys/mpc8308/mpc8308.h b/board/gdsys/mpc8308/mpc8308.h
new file mode 100644
index 0000000..dc07d56
--- /dev/null
+++ b/board/gdsys/mpc8308/mpc8308.h
@@ -0,0 +1,10 @@
+#ifndef __MPC8308_H_
+#define __MPC8308_H_
+
+/* functions to be provided by board implementation */
+void mpc8308_init(void);
+void mpc8308_set_fpga_reset(unsigned state);
+void mpc8308_setup_hw(void);
+int mpc8308_get_fpga_done(unsigned fpga);
+
+#endif /* __MPC8308_H_ */
diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c
new file mode 100644
index 0000000..0fce8cf
--- /dev/null
+++ b/board/gdsys/mpc8308/sdram.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * Authors: Nick.Spence@freescale.com
+ * Wilson.Lo@freescale.com
+ * scottwood@freescale.com
+ *
+ * This files is mostly identical to the original from
+ * board\freescale\mpc8315erdb\sdram.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <spd_sdram.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+ u32 msize_log2 = __ilog2(msize);
+
+ out_be32(&im->sysconf.ddrlaw[0].bar,
+ CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
+ out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+ out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+ out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+ out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+
+ /* Currently we use only one CS, so disable the other bank. */
+ out_be32(&im->ddr.cs_config[1], 0);
+
+ out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+ out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+ out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+ out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+ out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+ out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+ out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
+ out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+ out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+
+ out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+ sync();
+
+ /* enable DDR controller */
+ setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+ sync();
+
+ return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+}
+
+phys_size_t initdram(int board_type)
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize;
+
+ if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+ /* DDR SDRAM */
+ msize = fixed_sdram();
+
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return msize;
+}
diff --git a/board/gdsys/p1022/controlcenterd-id.c b/board/gdsys/p1022/controlcenterd-id.c
index 70eff91..11d075c 100644
--- a/board/gdsys/p1022/controlcenterd-id.c
+++ b/board/gdsys/p1022/controlcenterd-id.c
@@ -236,7 +236,7 @@
tmp_buf);
if (!n)
goto failure;
- result = min(size, blk_len - ofs);
+ result = min(size, (int)(blk_len - ofs));
memcpy(dst, tmp_buf + ofs, result);
dst += result;
size -= result;
@@ -736,7 +736,8 @@
src_buf = buf;
for (ptr = (uint8_t *)src_buf, i = 20; i > 0;
i -= data_size, ptr += data_size)
- memcpy(ptr, data, min(i, data_size));
+ memcpy(ptr, data,
+ min_t(size_t, i, data_size));
}
}
bin_func(dst_reg->digest, src_buf, 20);
@@ -931,11 +932,12 @@
struct key_program header;
uint32_t crc;
uint8_t buf[12];
- int i;
+ loff_t i;
if (fs_set_blk_dev(ifname, dev_part_str, fs_type))
goto failure;
+ if (fs_read(path, (ulong)buf, 0, 12, &i) < 0)
+ goto failure;
- i = fs_read(path, (ulong)buf, 0, 12);
if (i < 12)
goto failure;
header.magic = get_unaligned_be32(buf);
@@ -950,8 +952,9 @@
goto failure;
if (fs_set_blk_dev(ifname, dev_part_str, fs_type))
goto failure;
- i = fs_read(path, (ulong)result, 0,
- sizeof(struct key_program) + header.code_size);
+ if (fs_read(path, (ulong)result, 0,
+ sizeof(struct key_program) + header.code_size, &i) < 0)
+ goto failure;
if (i <= 0)
goto failure;
*result = header;
@@ -1042,7 +1045,7 @@
const char *image_path = "/ccdm.itb";
char *mac_path = NULL;
ulong image_addr;
- size_t image_size;
+ loff_t image_size;
uint32_t err;
printf("CCDM S2\n");
@@ -1084,10 +1087,11 @@
image_addr = (ulong)get_image_location();
if (fs_set_blk_dev("mmc", mmcdev, FS_TYPE_EXT))
goto failure;
- image_size = fs_read(image_path, image_addr, 0, 0);
+ if (fs_read(image_path, image_addr, 0, 0, &image_size) < 0)
+ goto failure;
if (image_size <= 0)
goto failure;
- printf("CCDM image found on %s, %d bytes\n", mmcdev, image_size);
+ printf("CCDM image found on %s, %lld bytes\n", mmcdev, image_size);
hmac_blob = load_key_chunk("mmc", mmcdev, FS_TYPE_EXT, mac_path);
if (!hmac_blob) {
diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c
index f76d968..64d90dd 100644
--- a/board/gdsys/p1022/controlcenterd.c
+++ b/board/gdsys/p1022/controlcenterd.c
@@ -326,7 +326,7 @@
}
#ifdef CONFIG_OF_BOARD_SETUP
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -343,6 +343,8 @@
#endif
FT_FSL_PCI_SETUP;
+
+ return 0;
}
#endif
diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
new file mode 100644
index 0000000..3a4f557
--- /dev/null
+++ b/board/google/chromebook_link/Kconfig
@@ -0,0 +1,31 @@
+if TARGET_CHROMEBOOK_LINK
+
+config SYS_BOARD
+ default "chromebook_link"
+
+config SYS_VENDOR
+ default "google"
+
+config SYS_SOC
+ default "ivybridge"
+
+config SYS_CONFIG_NAME
+ default "chromebook_link"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_INTEL_SOCKET_RPGA989
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select SOUTHBRIDGE_INTEL_C216
+ select HAVE_ACPI_RESUME
+ select MARK_GRAPHICS_MEM_WRCOMB
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+
+config EARLY_POST_CROS_EC
+ bool "Enable early post to Chrome OS EC"
+ default y
+
+endif
diff --git a/board/google/chromebook_link/MAINTAINERS b/board/google/chromebook_link/MAINTAINERS
new file mode 100644
index 0000000..bc253a2
--- /dev/null
+++ b/board/google/chromebook_link/MAINTAINERS
@@ -0,0 +1,6 @@
+CHROMEBOOK LINK BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/google/chromebook_link/
+F: include/configs/chromebook_link.h
+F: configs/chromebook_link_defconfig
diff --git a/board/google/chromebook_link/Makefile b/board/google/chromebook_link/Makefile
new file mode 100644
index 0000000..a133c2e
--- /dev/null
+++ b/board/google/chromebook_link/Makefile
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2011 The Chromium OS Authors.
+# (C) Copyright 2008
+# Graeme Russ, graeme.russ@gmail.com.
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += link.o
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
new file mode 100644
index 0000000..88cee05
--- /dev/null
+++ b/board/google/chromebook_link/link.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+
+int arch_early_init_r(void)
+{
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ return 0;
+}
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */
+ .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */
+ .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */
+ .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */
+ .gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */
+ .gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */
+ .gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */
+ .gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */
+ .gpio12 = GPIO_MODE_GPIO, /* TP_INT# */
+ .gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */
+ .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */
+ .gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */
+ .gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */
+ .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio1 = GPIO_LEVEL_HIGH,
+ .gpio6 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio7 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio12 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+ .gpio15 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */
+ .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */
+ .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */
+ .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */
+ .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */
+ .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio36 = GPIO_DIR_OUTPUT,
+ .gpio41 = GPIO_DIR_INPUT,
+ .gpio42 = GPIO_DIR_INPUT,
+ .gpio43 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio36 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_map link_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ },
+};
+
+int board_early_init_f(void)
+{
+ ich_gpio_set_gpio_map(&link_gpio_map);
+
+ return 0;
+}
diff --git a/board/google/common/Makefile b/board/google/common/Makefile
new file mode 100644
index 0000000..b38bc14
--- /dev/null
+++ b/board/google/common/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2014 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += early_init.o
diff --git a/board/google/common/early_init.S b/board/google/common/early_init.S
new file mode 100644
index 0000000..7017185
--- /dev/null
+++ b/board/google/common/early_init.S
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+ /* Enable post codes to EC */
+#ifdef CONFIG_EARLY_POST_CROS_EC
+ mov $0x1b, %ecx
+ rdmsr
+ and $0x100, %eax
+ test %eax, %eax
+ je 1f
+
+ mov $0x8000f8f0, %eax
+ mov $0xcf8, %dx
+ out %eax, (%dx)
+ mov $0xfed1c001, %eax
+ mov $0xcfc, %dx
+ out %eax, (%dx)
+ mov $0xfed1f410, %esp
+ mov (%esp), %eax
+ and $0xfffffffb, %eax
+ mov %eax, (%esp)
+1:
+#endif
+ jmp early_board_init_ret
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index a1b6749..fc2385c 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -94,7 +94,7 @@
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *fdt, bd_t *bd)
+int ft_board_setup(void *fdt, bd_t *bd)
{
static const char disabled[] = "disabled";
u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
@@ -106,6 +106,8 @@
if (!(reg & PWRDOM_STAT_EMMC))
do_fixup_by_compat(fdt, "calxeda,hb-sdhci", "status",
disabled, sizeof(disabled), 1);
+
+ return 0;
}
#endif
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
index a99416b..f0af24a 100644
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -311,10 +311,11 @@
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c
index f742143..e7838dc 100644
--- a/board/ids/ids8313/ids8313.c
+++ b/board/ids/ids8313/ids8313.c
@@ -138,9 +138,11 @@
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c
index 0fbdfdb..5d2ab2f 100644
--- a/board/ifm/ac14xx/ac14xx.c
+++ b/board/ifm/ac14xx/ac14xx.c
@@ -608,8 +608,10 @@
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/ifm/o2dnt2/o2dnt2.c b/board/ifm/o2dnt2/o2dnt2.c
index 6716ffc..ca09767 100644
--- a/board/ifm/o2dnt2/o2dnt2.c
+++ b/board/ifm/o2dnt2/o2dnt2.c
@@ -364,7 +364,7 @@
}
#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int phy_addr = CONFIG_PHY_ADDR;
char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
@@ -380,5 +380,7 @@
#endif
/* fix up the phy address */
do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index d363e49..78c4bd4 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -37,7 +37,7 @@
void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
/* print up to 8 characters of the string */
- for (i = 0; i < min(strlen(str), 8); i++) {
+ for (i = 0; i < min((int)strlen(str), 8); i++) {
__raw_writel(str[i], reg);
reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
}
diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c
index 5843725..4ab7160 100644
--- a/board/intercontrol/digsy_mtc/digsy_mtc.c
+++ b/board/intercontrol/digsy_mtc/digsy_mtc.c
@@ -454,7 +454,7 @@
}
#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int phy_addr = CONFIG_PHY_ADDR;
char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
@@ -478,5 +478,7 @@
#endif
/* fix up the phy address */
do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/ipek01/ipek01.c b/board/ipek01/ipek01.c
index d44c4bf..2078f53 100644
--- a/board/ipek01/ipek01.c
+++ b/board/ipek01/ipek01.c
@@ -196,10 +196,12 @@
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup (void *blob, bd_t * bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup (blob, bd);
fdt_fixup_memory (blob, (u64) bd->bi_memstart, (u64) bd->bi_memsize);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c
index 78e4b5d..8856393 100644
--- a/board/jupiter/jupiter.c
+++ b/board/jupiter/jupiter.c
@@ -283,9 +283,10 @@
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/keymile/km82xx/km82xx.c b/board/keymile/km82xx/km82xx.c
index dfbfab8..e200935 100644
--- a/board/keymile/km82xx/km82xx.c
+++ b/board/keymile/km82xx/km82xx.c
@@ -460,8 +460,10 @@
}
#endif
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index 0543483..1da0dcb 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -359,9 +359,11 @@
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
index 4a73613..a74f75b 100644
--- a/board/keymile/kmp204x/kmp204x.c
+++ b/board/keymile/kmp204x/kmp204x.c
@@ -261,7 +261,7 @@
}
#endif
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
@@ -286,6 +286,8 @@
fdt_fixup_fman_ethernet(blob);
fdt_fixup_fman_mac_addresses(blob);
#endif
+
+ return 0;
}
#if defined(CONFIG_POST)
diff --git a/board/korat/korat.c b/board/korat/korat.c
index 8b83000..d9ab2fd 100644
--- a/board/korat/korat.c
+++ b/board/korat/korat.c
@@ -610,7 +610,7 @@
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
u32 val[4];
int rc;
@@ -627,5 +627,7 @@
if (rc)
printf("Unable to update property NOR mapping, err=%s\n",
fdt_strerror(rc));
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c
index c4155dd..c07735a 100644
--- a/board/kosagi/novena/novena_spl.c
+++ b/board/kosagi/novena/novena_spl.c
@@ -17,6 +17,7 @@
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
+#include <asm/arch/crm_regs.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
@@ -533,6 +534,30 @@
.trasmin = 3590,
};
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0xFFFFF300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xF00000CF, &iomux->gpr[4]);
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+}
+
/*
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM
@@ -543,6 +568,9 @@
/* setup AIPS and disable watchdog */
arch_cpu_init();
+ ccgr_init();
+ gpr_init();
+
/* setup GP timer */
timer_init();
diff --git a/board/kosagi/novena/setup.cfg b/board/kosagi/novena/setup.cfg
deleted file mode 100644
index 18d139c..0000000
--- a/board/kosagi/novena/setup.cfg
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (C) 2014 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Refer docs/README.imxmage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/* Boot Device : sd */
-BOOT_FROM sd
-
-#define __ASSEMBLY__
-#include <config.h>
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF00000
-DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
-DATA 4, CCM_CCGR5, 0x0F0000C3
-DATA 4, CCM_CCGR6, 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en = 1 --> CKO1 enabled
- * cko1_div = 111 --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/kup/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c
index a4c1998..71c6a79 100644
--- a/board/kup/kup4k/kup4k.c
+++ b/board/kup/kup4k/kup4k.c
@@ -280,8 +280,10 @@
* Device Tree Support
*/
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/manroland/mucmc52/mucmc52.c b/board/manroland/mucmc52/mucmc52.c
index c3ce66d..c8ed5b7 100644
--- a/board/manroland/mucmc52/mucmc52.c
+++ b/board/manroland/mucmc52/mucmc52.c
@@ -385,8 +385,10 @@
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/manroland/uc101/uc101.c b/board/manroland/uc101/uc101.c
index 5c5afa2..e794c46 100644
--- a/board/manroland/uc101/uc101.c
+++ b/board/manroland/uc101/uc101.c
@@ -358,8 +358,10 @@
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
index a6235e5..4d0ebaa 100644
--- a/board/motionpro/motionpro.c
+++ b/board/motionpro/motionpro.c
@@ -185,9 +185,11 @@
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/mpc8308_p1m/mpc8308_p1m.c b/board/mpc8308_p1m/mpc8308_p1m.c
index 2009e62..688cc12 100644
--- a/board/mpc8308_p1m/mpc8308_p1m.c
+++ b/board/mpc8308_p1m/mpc8308_p1m.c
@@ -62,10 +62,12 @@
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
fdt_fixup_dr_usb(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/muas3001/muas3001.c b/board/muas3001/muas3001.c
index 08eb5e8..529a58c 100644
--- a/board/muas3001/muas3001.c
+++ b/board/muas3001/muas3001.c
@@ -329,9 +329,11 @@
}
}
-void ft_board_setup (void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup (blob, bd);
ft_blob_update (blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/munices/munices.c b/board/munices/munices.c
index 319fa8c..23d0f56 100644
--- a/board/munices/munices.c
+++ b/board/munices/munices.c
@@ -146,9 +146,10 @@
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 51125df..0e4a65a 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <dm.h>
#include <ns16550.h>
#include <linux/compiler.h>
#include <asm/io.h>
@@ -43,6 +44,13 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SPL_BUILD
+/* TODO(sjg@chromium.org): Remove once SPL supports device tree */
+U_BOOT_DEVICE(tegra_gpios) = {
+ "gpio_tegra"
+};
+#endif
+
const struct tegra_sysinfo sysinfo = {
CONFIG_TEGRA_BOARD_STRING
};
diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c
index 15f8f31..81f3024 100644
--- a/board/pdm360ng/pdm360ng.c
+++ b/board/pdm360ng/pdm360ng.c
@@ -477,7 +477,7 @@
};
#endif
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
u32 val[8];
int rc, i = 0;
@@ -526,6 +526,8 @@
if (rc)
printf("Unable to update flash reg property, err=%s\n",
fdt_strerror(rc));
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c
index ce515d8..ed41de1 100644
--- a/board/phytec/pcm030/pcm030.c
+++ b/board/phytec/pcm030/pcm030.c
@@ -164,9 +164,11 @@
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t * bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/raspberrypi/rpi_b/rpi_b.c b/board/raspberrypi/rpi_b/rpi_b.c
index 7445f53..db904a4 100644
--- a/board/raspberrypi/rpi_b/rpi_b.c
+++ b/board/raspberrypi/rpi_b/rpi_b.c
@@ -154,7 +154,7 @@
msg_clk->get_clock_rate.body.resp.rate_hz);
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
/*
* For now, we simply always add the simplefb DT node. Later, we
@@ -162,4 +162,6 @@
* node exists for the "real" graphics driver.
*/
lcd_dt_simplefb_add_node(blob);
+
+ return 0;
}
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
index 33003ee..b7d2381 100644
--- a/board/samsung/odroid/odroid.c
+++ b/board/samsung/odroid/odroid.c
@@ -382,6 +382,22 @@
gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
gpio_direction_input(EXYNOS4X12_GPIO_X31);
+
+ /* Blue LED (Odroid X2/U2/U3) */
+ gpio_request(EXYNOS4X12_GPIO_C10, "Blue LED");
+
+ gpio_direction_output(EXYNOS4X12_GPIO_C10, 0);
+
+#ifdef CONFIG_CMD_USB
+ /* USB3503A Reference frequency */
+ gpio_request(EXYNOS4X12_GPIO_X30, "USB3503A RefFreq");
+
+ /* USB3503A Connect */
+ gpio_request(EXYNOS4X12_GPIO_X34, "USB3503A Connect");
+
+ /* USB3503A Reset */
+ gpio_request(EXYNOS4X12_GPIO_X35, "USB3503A Reset");
+#endif
}
static int pmic_init_max77686(void)
@@ -462,9 +478,39 @@
.usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
.usb_flags = PHY0_SLEEP,
};
+#endif
+
+#if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
int board_usb_init(int index, enum usb_init_type init)
{
+#ifdef CONFIG_CMD_USB
+ struct pmic *p_pmic;
+
+ /* Set Ref freq 0 => 24MHz, 1 => 26MHz*/
+ /* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */
+ if (gd->board_type == ODROID_TYPE_U3)
+ gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
+ else
+ gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
+
+ /* Disconnect, Reset, Connect */
+ gpio_direction_output(EXYNOS4X12_GPIO_X34, 0);
+ gpio_direction_output(EXYNOS4X12_GPIO_X35, 0);
+ gpio_direction_output(EXYNOS4X12_GPIO_X35, 1);
+ gpio_direction_output(EXYNOS4X12_GPIO_X34, 1);
+
+ /* Power off and on BUCK8 for LAN9730 */
+ debug("LAN9730 - Turning power buck 8 OFF and ON.\n");
+
+ p_pmic = pmic_get("MAX77686_PMIC");
+ if (p_pmic && !pmic_probe(p_pmic)) {
+ max77686_set_buck_voltage(p_pmic, 8, 750000);
+ max77686_set_buck_voltage(p_pmic, 8, 3300000);
+ }
+
+#endif
+
debug("USB_udc_probe\n");
return s3c_udc_probe(&s5pc210_otg_data);
}
diff --git a/board/samsung/smdk5420/Kconfig b/board/samsung/smdk5420/Kconfig
index d3a5b7f..e7aafe5 100644
--- a/board/samsung/smdk5420/Kconfig
+++ b/board/samsung/smdk5420/Kconfig
@@ -1,3 +1,19 @@
+if TARGET_PEACH_PI
+
+config SYS_BOARD
+ string
+ default "smdk5420"
+
+config SYS_VENDOR
+ string
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ string
+ default "peach-pi"
+
+endif
+
if TARGET_PEACH_PIT
config SYS_BOARD
diff --git a/board/samsung/smdk5420/MAINTAINERS b/board/samsung/smdk5420/MAINTAINERS
index e0f5c7a..1423f83 100644
--- a/board/samsung/smdk5420/MAINTAINERS
+++ b/board/samsung/smdk5420/MAINTAINERS
@@ -6,3 +6,5 @@
F: configs/peach-pit_defconfig
F: include/configs/smdk5420.h
F: configs/smdk5420_defconfig
+F: include/configs/peach-pi.h
+F: configs/peach-pi_defconfig
diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index 89da47e..72786d2 100644
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -214,11 +214,13 @@
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+
+ return 0;
}
#endif
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index d584276..25329e4 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -301,12 +301,14 @@
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_FSL_PCI_INIT
FT_FSL_PCI_SETUP;
#endif
+
+ return 0;
}
#endif
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index 4906be4..6bdf1a2 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -173,11 +173,13 @@
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup (void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
FT_FSL_PCI_SETUP;
+
+ return 0;
}
#endif
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 2caefbb..953a43f 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -218,8 +218,7 @@
#endif /* CONFIG_BOARD_EARLY_INIT_R */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
u32 val[12];
int rc, i = 0;
@@ -251,6 +250,8 @@
if (rc)
printf("Unable to update localbus ranges, err=%s\n",
fdt_strerror(rc));
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c
index f5c3d75..6e4eed8 100644
--- a/board/stx/stxssa/stxssa.c
+++ b/board/stx/stxssa/stxssa.c
@@ -233,9 +233,11 @@
}
#ifdef CONFIG_OF_BOARD_SETUP
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup (blob, bd);
+
+ return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index c3f865d..246cd9a 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -21,7 +21,10 @@
config MACH_SUN7I
bool "sun7i (Allwinner A20)"
select CPU_V7
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
select SUPPORT_SPL
+ select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
config MACH_SUN8I
bool "sun8i (Allwinner A23)"
@@ -213,4 +216,18 @@
---help---
See USB1_VBUS_PIN help text.
+config VIDEO
+ boolean "Enable graphical uboot console on HDMI"
+ default y
+ ---help---
+ Say Y here to add support for using a cfb console on the HDMI output
+ found on most sunxi devices.
+
+config USB_KEYBOARD
+ boolean "Enable USB keyboard support"
+ default y
+ ---help---
+ Say Y here to add support for using a USB keyboard (typically used
+ in combination with a graphical console on HDMI).
+
endif
diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c
index 5e12328..b7f0dda 100644
--- a/board/sunxi/ahci.c
+++ b/board/sunxi/ahci.c
@@ -76,6 +76,8 @@
#ifdef CONFIG_SATAPWR
gpio_request(CONFIG_SATAPWR, "satapwr");
gpio_direction_output(CONFIG_SATAPWR, 1);
+ /* Give attached sata device time to power-up to avoid link timeouts */
+ mdelay(500);
#endif
if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index e6ec5b8..4c1c69a 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -24,6 +24,7 @@
#endif
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
+#include <asm/arch/display.h>
#include <asm/arch/dram.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
@@ -237,3 +238,12 @@
return 0;
}
#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_VIDEO_DT_SIMPLEFB
+ return sunxi_simplefb_setup(blob);
+#endif
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index 051aca0..571bc9e 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -13,7 +13,12 @@
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* Set up clock gating */
+#ifndef CONFIG_MACH_SUN6I
setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
+#else
+ setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
+ setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
+#endif
/* Set MII clock */
#ifdef CONFIG_RGMII
@@ -33,6 +38,7 @@
setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10);
#endif
+#ifndef CONFIG_MACH_SUN6I
/* Configure pin mux settings for GMAC */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
#ifdef CONFIG_RGMII
@@ -43,9 +49,48 @@
sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
+#elif defined CONFIG_RGMII
+ /* Configure sun6i RGMII mode pin mux settings */
+ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_drv(pin, 3);
+ }
+ for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_drv(pin, 3);
+ }
+ for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_drv(pin, 3);
+ }
+ for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_drv(pin, 3);
+ }
+#elif defined CONFIG_GMII
+ /* Configure sun6i GMII mode pin mux settings */
+ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+#else
+ /* Configure sun6i MII mode pin mux settings */
+ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+#endif
#ifdef CONFIG_RGMII
return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
+#elif defined CONFIG_GMII
+ return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII);
#else
return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
#endif
diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
index daf8ff4..dfa430e 100644
--- a/board/tbs/tbs2910/tbs2910.c
+++ b/board/tbs/tbs2910/tbs2910.c
@@ -219,15 +219,13 @@
int board_mmc_init(bd_t *bis)
{
- s32 status = 0;
- int i;
-
/*
* (U-boot device node) (Physical Port)
* mmc0 SD2
* mmc1 SD3
* mmc2 eMMC
*/
+ int i, ret;
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
@@ -251,12 +249,13 @@
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
i + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return status;
+ return -EINVAL;
}
-
- status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
}
- return status;
+ return 0;
}
#endif /* CONFIG_FSL_ESDHC */
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index ff7bc4b..04ec675 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -114,7 +114,7 @@
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int lpae;
char *env;
@@ -217,6 +217,8 @@
}
}
}
+
+ return 0;
}
void ft_board_setup_ex(void *blob, bd_t *bd)
diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c
index a1f56cd..e9363ea 100644
--- a/board/tqc/tqm5200/tqm5200.c
+++ b/board/tqc/tqm5200/tqm5200.c
@@ -863,12 +863,14 @@
#endif /* CONFIG_VIDEO_SM501 */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#if defined(CONFIG_VIDEO)
fdt_add_edid(blob, "smi,sm501", edid_buf);
#endif
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c
index 814fcb2..d891a38 100644
--- a/board/tqc/tqm834x/tqm834x.c
+++ b/board/tqc/tqm834x/tqm834x.c
@@ -414,12 +414,14 @@
}
#ifdef CONFIG_OF_BOARD_SETUP
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif /* CONFIG_PCI */
+
+ return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c
index 9ce2a57..3b5230a 100644
--- a/board/tqc/tqm8xx/tqm8xx.c
+++ b/board/tqc/tqm8xx/tqm8xx.c
@@ -674,10 +674,12 @@
}
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
ft_blob_update(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c
index fd1bd59..c9e163e 100644
--- a/board/tqc/tqma6/tqma6.c
+++ b/board/tqc/tqma6/tqma6.c
@@ -17,6 +17,7 @@
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/spi.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <libfdt.h>
@@ -50,7 +51,7 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+ gd->ram_size = imx_ddr_size();
return 0;
}
@@ -180,8 +181,14 @@
static void tqma6_setup_i2c(void)
{
- /* use logical index for bus, e.g. I2C1 -> 0 */
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
+ int ret;
+ /*
+ * use logical index for bus, e.g. I2C1 -> 0
+ * warn on error
+ */
+ ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
+ if (ret)
+ printf("setup I2C3 failed: %d\n", ret);
}
int board_early_init_f(void)
@@ -259,12 +266,14 @@
* Device Tree Support
*/
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
/* bring in eMMC dsr settings */
do_fixup_by_path_u32(blob,
"/soc/aips-bus@02100000/usdhc@02198000",
"dsr", tqma6_emmc_dsr, 2);
tqma6_bb_ft_board_setup(blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c
index fd59287..6f4cffd 100644
--- a/board/tqc/tqma6/tqma6_mba6.c
+++ b/board/tqc/tqma6/tqma6_mba6.c
@@ -224,8 +224,14 @@
static void mba6_setup_i2c(void)
{
- /* use logical index for bus, e.g. I2C1 -> 0 */
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads);
+ int ret;
+ /*
+ * use logical index for bus, e.g. I2C1 -> 0
+ * warn on error
+ */
+ ret = setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads);
+ if (ret)
+ printf("setup I2C1 failed: %d\n", ret);
}
diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
index c4feef8..7f24a30 100644
--- a/board/ve8313/ve8313.c
+++ b/board/ve8313/ve8313.c
@@ -192,11 +192,13 @@
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+
+ return 0;
}
#endif
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 3c8b7a5..1075c65 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -144,7 +144,7 @@
int board_mmc_init(bd_t *bis)
{
- s32 status = 0;
+ int ret;
u32 index = 0;
/*
@@ -173,13 +173,15 @@
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
index + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return status;
+ return -EINVAL;
}
- status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ if (ret)
+ return ret;
}
- return status;
+ return 0;
}
static int mx6_rgmii_rework(struct phy_device *phydev)
diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c
index b7ad349..0028870 100644
--- a/board/xes/xpedite517x/xpedite517x.c
+++ b/board/xes/xpedite517x/xpedite517x.c
@@ -69,11 +69,13 @@
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_PCI
ft_board_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/xes/xpedite520x/xpedite520x.c b/board/xes/xpedite520x/xpedite520x.c
index aa9e99d..6a3df52 100644
--- a/board/xes/xpedite520x/xpedite520x.c
+++ b/board/xes/xpedite520x/xpedite520x.c
@@ -70,11 +70,13 @@
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_PCI
ft_board_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/xes/xpedite537x/xpedite537x.c b/board/xes/xpedite537x/xpedite537x.c
index efd563b..41419fe 100644
--- a/board/xes/xpedite537x/xpedite537x.c
+++ b/board/xes/xpedite537x/xpedite537x.c
@@ -72,11 +72,13 @@
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_PCI
ft_board_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/board/xes/xpedite550x/xpedite550x.c b/board/xes/xpedite550x/xpedite550x.c
index e64d682..1f05150 100644
--- a/board/xes/xpedite550x/xpedite550x.c
+++ b/board/xes/xpedite550x/xpedite550x.c
@@ -72,11 +72,13 @@
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_PCI
ft_board_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
+
+ return 0;
}
#endif
diff --git a/common/Kconfig b/common/Kconfig
index 216a8de..fd84fa0 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -1,34 +1,316 @@
menu "Command line interface"
depends on !SPL_BUILD
+config HUSH_PARSER
+ bool "Use hush shell"
+ select SYS_HUSH_PARSER
+ help
+ This option enables the "hush" shell (from Busybox) as command line
+ interpreter, thus enabling powerful command line syntax like
+ if...then...else...fi conditionals or `&&' and '||'
+ constructs ("shell scripts").
+
+ If disabled, you get the old, much simpler behaviour with a somewhat
+ smaller memory footprint.
+
+config SYS_HUSH_PARSER
+ bool
+ help
+ Backward compatibility.
+
+comment "Commands"
+
+menu "Info commands"
+
+config CMD_BDI
+ bool "bdinfo"
+ help
+ Print board info
+
+config CMD_CONSOLE
+ bool "coninfo"
+ help
+ Print console devices and information.
+
+config CMD_LICENSE
+ bool "license"
+ help
+ Print GPL license text
+
+endmenu
+
+menu "Boot commands"
+
+config CMD_BOOTD
+ bool "bootd"
+ help
+ Run the command stored in the environment "bootcmd", i.e.
+ "bootd" does the same thing as "run bootcmd".
+
config CMD_BOOTM
- bool "Enable bootm command"
+ bool "bootm"
default y
help
Boot an application image from the memory.
-config CMD_CRC32
- bool "Enable crc32 command"
+config CMD_GO
+ bool "go"
default y
help
- Compute CRC32.
+ Start an application at a given address.
+
+config CMD_RUN
+ bool "run"
+ help
+ Run the command in the given environment variable.
+
+config CMD_IMI
+ bool "iminfo"
+ help
+ Print header information for application image.
+
+config CMD_IMLS
+ bool "imls"
+ help
+ List all images found in flash
+
+config CMD_XIMG
+ bool "imxtract"
+ help
+ Extract a part of a multi-image.
+
+endmenu
+
+menu "Environment commands"
config CMD_EXPORTENV
- bool "Enable env export command"
+ bool "env export"
default y
help
Export environments.
config CMD_IMPORTENV
- bool "Enable env import command"
+ bool "env import"
default y
help
Import environments.
-config CMD_GO
- bool "Enable go command"
+config CMD_EDITENV
+ bool "editenv"
+ help
+ Edit environment variable.
+
+config CMD_SAVEENV
+ bool "saveenv"
+ help
+ Run the command in the given environment variable.
+
+endmenu
+
+menu "Memory commands"
+
+config CMD_MEMORY
+ bool "md, mm, nm, mw, cp, cmp, base, loop"
+ help
+ Memeory commands.
+ md - memory display
+ mm - memory modify (auto-incrementing address)
+ nm - memory modify (constant address)
+ mw - memory write (fill)
+ cp - memory copy
+ cmp - memory compare
+ base - print or set address offset
+ loop - initinite loop on address range
+
+config CMD_CRC32
+ bool "crc32"
default y
help
- Start an application at a given address.
+ Compute CRC32.
+
+config LOOPW
+ bool "loopw"
+ help
+ Infinite write loop on address range
+
+config CMD_MEMTEST
+ bool "crc32"
+ help
+ Simple RAM read/write test.
+
+config CMD_MX_CYCLIC
+ bool "mdc, mwc"
+ help
+ mdc - memory display cyclic
+ mwc - memory write cyclic
+
+config CMD_MEMINFO
+ bool "meminfo"
+ help
+ Display memory information.
+
+endmenu
+
+menu "Device access commands"
+
+config CMD_LOADB
+ bool "loadb"
+ help
+ Load a binary file over serial line.
+
+config CMD_LOADS
+ bool "loads"
+ help
+ Load an S-Record file over serial line
+
+config CMD_FLASH
+ bool "flinfo, erase, protect"
+ help
+ NOR flash support.
+ flinfo - print FLASH memory information
+ erase - FLASH memory
+ protect - enable or disable FLASH write protection
+
+config CMD_NAND
+ bool "nand"
+ help
+ NAND support.
+
+config CMD_SPI
+ bool "sspi"
+ help
+ SPI utility command.
+
+config CMD_I2C
+ bool "i2c"
+ help
+ I2C support.
+
+config CMD_USB
+ bool "usb"
+ help
+ USB support.
+
+config CMD_FPGA
+ bool "fpga"
+ help
+ FPGA support.
+
+endmenu
+
+
+menu "Shell scripting commands"
+
+config CMD_ECHO
+ bool "echo"
+ help
+ Echo args to console
+
+config CMD_ITEST
+ bool "itest"
+ help
+ Return true/false on integer compare.
+
+config CMD_SOURCE
+ bool "source"
+ help
+ Run script from memory
+
+endmenu
+
+menu "Network commands"
+
+config CMD_NET
+ bool "bootp, tftpboot"
+ help
+ Network commands.
+ bootp - boot image via network using BOOTP/TFTP protocol
+ tftpboot - boot image via network using TFTP protocol
+
+config CMD_TFTPPUT
+ bool "tftp put"
+ help
+ TFTP put command, for uploading files to a server
+
+config CMD_TFTPSRV
+ bool "tftpsrv"
+ help
+ Act as a TFTP server and boot the first received file
+
+config CMD_RARP
+ bool "rarpboot"
+ help
+ Boot image via network using RARP/TFTP protocol
+
+config CMD_DHCP
+ bool "dhcp"
+ help
+ Boot image via network using DHCP/TFTP protocol
+
+config CMD_NFS
+ bool "nfs"
+ help
+ Boot image via network using NFS protocol.
+
+config CMD_PING
+ bool "ping"
+ help
+ Send ICMP ECHO_REQUEST to network host
+
+config CMD_CDP
+ bool "cdp"
+ help
+ Perform CDP network configuration
+
+config CMD_SNTP
+ bool "sntp"
+ help
+ Synchronize RTC via network
+
+config CMD_DNS
+ bool "dns"
+ help
+ Lookup the IP of a hostname
+
+config CMD_DNS
+ bool "dns"
+ help
+ Lookup the IP of a hostname
+
+config CMD_LINK_LOCAL
+ bool "linklocal"
+ help
+ Acquire a network IP address using the link-local protocol
+
+endmenu
+
+menu "Misc commands"
+
+config CMD_TIME
+ bool "time"
+ help
+ Run commands and summarize execution time.
+
+# TODO: rename to CMD_SLEEP
+config CMD_MISC
+ bool "sleep"
+ help
+ Delay execution for some time
+
+config CMD_TIMER
+ bool "timer"
+ help
+ Access the system timer.
+
+config CMD_SETGETDCR
+ bool "getdcr, setdcr, getidcr, setidcr"
+ depends on 4xx
+ help
+ getdcr - Get an AMCC PPC 4xx DCR's value
+ setdcr - Set an AMCC PPC 4xx DCR's value
+ getidcr - Get a register value via indirect DCR addressing
+ setidcr - Set a register value via indirect DCR addressing
+
+endmenu
endmenu
diff --git a/common/Makefile b/common/Makefile
index 6cc4de8..9c47e20 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -188,6 +188,7 @@
obj-$(CONFIG_USB_STORAGE) += usb_storage.o
endif
obj-$(CONFIG_CMD_FASTBOOT) += cmd_fastboot.o
+obj-$(CONFIG_CMD_FS_UUID) += cmd_fs_uuid.o
obj-$(CONFIG_CMD_USB_MASS_STORAGE) += cmd_usb_mass_storage.o
obj-$(CONFIG_CMD_THOR_DOWNLOAD) += cmd_thordown.o
@@ -251,6 +252,9 @@
obj-y += console.o
obj-$(CONFIG_CROS_EC) += cros_ec.o
obj-y += dlmalloc.o
+ifdef CONFIG_SYS_MALLOC_F_LEN
+obj-y += malloc_simple.o
+endif
obj-y += image.o
obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o
obj-$(CONFIG_OF_LIBFDT) += image-fdt.o
diff --git a/common/board_f.c b/common/board_f.c
index b5bebc9..98c9c72 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -142,17 +142,19 @@
static int display_text_info(void)
{
#ifndef CONFIG_SANDBOX
- ulong bss_start, bss_end;
+ ulong bss_start, bss_end, text_base;
bss_start = (ulong)&__bss_start;
bss_end = (ulong)&__bss_end;
- debug("U-Boot code: %08X -> %08lX BSS: -> %08lX\n",
#ifdef CONFIG_SYS_TEXT_BASE
- CONFIG_SYS_TEXT_BASE, bss_start, bss_end);
+ text_base = CONFIG_SYS_TEXT_BASE;
#else
- CONFIG_SYS_MONITOR_BASE, bss_start, bss_end);
+ text_base = CONFIG_SYS_MONITOR_BASE;
#endif
+
+ debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
+ text_base, bss_start, bss_end);
#endif
#ifdef CONFIG_MODEM_SUPPORT
@@ -285,7 +287,7 @@
struct sandbox_state *state = state_get_current();
const char *fname = state->fdt_fname;
void *blob;
- ssize_t size;
+ loff_t size;
int err;
int fd;
@@ -298,10 +300,10 @@
return -EINVAL;
}
- size = os_get_filesize(fname);
- if (size < 0) {
+ err = os_get_filesize(fname, &size);
+ if (err < 0) {
printf("Failed to file FDT file '%s'\n", fname);
- return -ENOENT;
+ return err;
}
fd = os_open(fname, OS_O_RDONLY);
if (fd < 0) {
@@ -812,22 +814,16 @@
setup_mon_len,
setup_fdt,
trace_early_init,
+ initf_malloc,
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
/* TODO: can this go into arch_cpu_init()? */
probecpu,
#endif
arch_cpu_init, /* basic arch cpu dependent setup */
-#ifdef CONFIG_X86
- cpu_init_f, /* TODO(sjg@chromium.org): remove */
-# ifdef CONFIG_OF_CONTROL
- find_fdt, /* TODO(sjg@chromium.org): remove */
-# endif
-#endif
mark_bootstage,
#ifdef CONFIG_OF_CONTROL
fdtdec_check_fdt,
#endif
- initf_malloc,
initf_dm,
#if defined(CONFIG_BOARD_EARLY_INIT_F)
board_early_init_f,
@@ -903,13 +899,9 @@
#if defined(CONFIG_HARD_SPI)
init_func_spi,
#endif
-#ifdef CONFIG_X86
- dram_init_f, /* configure available RAM banks */
- calculate_relocation_address,
-#endif
announce_dram_init,
/* TODO: unify all these dram functions? */
-#ifdef CONFIG_ARM
+#if defined(CONFIG_ARM) || defined(CONFIG_X86)
dram_init, /* configure available RAM banks */
#endif
#if defined(CONFIG_MIPS) || defined(CONFIG_PPC)
diff --git a/common/board_r.c b/common/board_r.c
index 7c33900..19c6427 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -99,7 +99,8 @@
static int initr_reloc(void)
{
- gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
+ /* tell others: relocation done */
+ gd->flags |= GD_FLG_RELOC | GD_FLG_FULL_MALLOC_INIT;
bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");
return 0;
diff --git a/common/cli_hush.c b/common/cli_hush.c
index d643912..296542f 100644
--- a/common/cli_hush.c
+++ b/common/cli_hush.c
@@ -3217,7 +3217,7 @@
}
b_free(&temp);
/* loop on syntax errors, return on EOF */
- } while (rcode != 1 && !(flag & FLAG_EXIT_FROM_LOOP) &&
+ } while (rcode != -1 && !(flag & FLAG_EXIT_FROM_LOOP) &&
(inp->peek != static_peek || b_peek(inp)));
#ifndef __U_BOOT__
return 0;
diff --git a/common/cmd_elf.c b/common/cmd_elf.c
index 42a5296..58b61c2 100644
--- a/common/cmd_elf.c
+++ b/common/cmd_elf.c
@@ -210,9 +210,9 @@
*/
bootline = getenv("bootargs");
if (bootline) {
- memcpy((void *) bootaddr, bootline,
- max(strlen(bootline), 255));
- flush_cache(bootaddr, max(strlen(bootline), 255));
+ memcpy((void *)bootaddr, bootline,
+ max(strlen(bootline), (size_t)255));
+ flush_cache(bootaddr, max(strlen(bootline), (size_t)255));
} else {
sprintf(build_buf, CONFIG_SYS_VXWORKS_BOOT_DEVICE);
tmp = getenv("bootfile");
@@ -240,9 +240,9 @@
CONFIG_SYS_VXWORKS_ADD_PARAMS);
#endif
- memcpy((void *) bootaddr, build_buf,
- max(strlen(build_buf), 255));
- flush_cache(bootaddr, max(strlen(build_buf), 255));
+ memcpy((void *)bootaddr, build_buf,
+ max(strlen(build_buf), (size_t)255));
+ flush_cache(bootaddr, max(strlen(build_buf), (size_t)255));
}
/*
diff --git a/common/cmd_ext4.c b/common/cmd_ext4.c
index ecfc6d3..19423d1 100644
--- a/common/cmd_ext4.c
+++ b/common/cmd_ext4.c
@@ -61,61 +61,16 @@
#if defined(CONFIG_CMD_EXT4_WRITE)
int do_ext4_write(cmd_tbl_t *cmdtp, int flag, int argc,
- char *const argv[])
+ char *const argv[])
{
- const char *filename = "/";
- int dev, part;
- unsigned long ram_address;
- unsigned long file_size;
- disk_partition_t info;
- block_dev_desc_t *dev_desc;
-
- if (argc < 6)
- return cmd_usage(cmdtp);
-
- part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1);
- if (part < 0)
- return 1;
-
- dev = dev_desc->dev;
-
- /* get the filename */
- filename = argv[4];
-
- /* get the address in hexadecimal format (string to int) */
- ram_address = simple_strtoul(argv[3], NULL, 16);
-
- /* get the filesize in hexadecimal format */
- file_size = simple_strtoul(argv[5], NULL, 16);
-
- /* set the device as block device */
- ext4fs_set_blk_dev(dev_desc, &info);
-
- /* mount the filesystem */
- if (!ext4fs_mount(info.size)) {
- printf("Bad ext4 partition %s %d:%d\n", argv[1], dev, part);
- goto fail;
- }
-
- /* start write */
- if (ext4fs_write(filename, (unsigned char *)ram_address, file_size)) {
- printf("** Error ext4fs_write() **\n");
- goto fail;
- }
- ext4fs_close();
-
- return 0;
-
-fail:
- ext4fs_close();
-
- return 1;
+ return do_save(cmdtp, flag, argc, argv, FS_TYPE_EXT);
}
-U_BOOT_CMD(ext4write, 6, 1, do_ext4_write,
- "create a file in the root directory",
- "<interface> <dev[:part]> <addr> <absolute filename path> [sizebytes]\n"
- " - create a file in / directory");
+U_BOOT_CMD(ext4write, 7, 1, do_ext4_write,
+ "create a file in the root directory",
+ "<interface> <dev[:part]> <addr> <absolute filename path>\n"
+ " [sizebytes] [file offset]\n"
+ " - create a file in / directory");
#endif
@@ -132,7 +87,7 @@
"<interface> <dev[:part]> [directory]\n"
" - list files from 'dev' on 'interface' in a 'directory'");
-U_BOOT_CMD(ext4load, 6, 0, do_ext4_load,
+U_BOOT_CMD(ext4load, 7, 0, do_ext4_load,
"load binary file from a Ext4 filesystem",
"<interface> [<dev[:part]> [addr [filename [bytes [pos]]]]]\n"
" - load binary file 'filename' from 'dev' on 'interface'\n"
diff --git a/common/cmd_fat.c b/common/cmd_fat.c
index 633fbf1..c00fb28 100644
--- a/common/cmd_fat.c
+++ b/common/cmd_fat.c
@@ -100,7 +100,8 @@
static int do_fat_fswrite(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
- long size;
+ loff_t size;
+ int ret;
unsigned long addr;
unsigned long count;
block_dev_desc_t *dev_desc = NULL;
@@ -127,15 +128,15 @@
count = simple_strtoul(argv[5], NULL, 16);
buf = map_sysmem(addr, count);
- size = file_fat_write(argv[4], buf, count);
+ ret = file_fat_write(argv[4], buf, 0, count, &size);
unmap_sysmem(buf);
- if (size == -1) {
+ if (ret < 0) {
printf("\n** Unable to write \"%s\" from %s %d:%d **\n",
argv[4], argv[1], dev, part);
return 1;
}
- printf("%ld bytes written\n", size);
+ printf("%llu bytes written\n", size);
return 0;
}
diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c
index 5640ded..25b4675 100644
--- a/common/cmd_fdt.c
+++ b/common/cmd_fdt.c
@@ -566,8 +566,27 @@
}
#ifdef CONFIG_OF_BOARD_SETUP
/* Call the board-specific fixup routine */
- else if (strncmp(argv[1], "boa", 3) == 0)
- ft_board_setup(working_fdt, gd->bd);
+ else if (strncmp(argv[1], "boa", 3) == 0) {
+ int err = ft_board_setup(working_fdt, gd->bd);
+
+ if (err) {
+ printf("Failed to update board information in FDT: %s\n",
+ fdt_strerror(err));
+ return CMD_RET_FAILURE;
+ }
+ }
+#endif
+#ifdef CONFIG_OF_SYSTEM_SETUP
+ /* Call the board-specific fixup routine */
+ else if (strncmp(argv[1], "sys", 3) == 0) {
+ int err = ft_system_setup(working_fdt, gd->bd);
+
+ if (err) {
+ printf("Failed to add system information to FDT: %s\n",
+ fdt_strerror(err));
+ return CMD_RET_FAILURE;
+ }
+ }
#endif
/* Create a chosen node */
else if (strncmp(argv[1], "cho", 3) == 0) {
@@ -1008,6 +1027,9 @@
#ifdef CONFIG_OF_BOARD_SETUP
"fdt boardsetup - Do board-specific set up\n"
#endif
+#ifdef CONFIG_OF_SYSTEM_SETUP
+ "fdt systemsetup - Do system-specific set up\n"
+#endif
"fdt move <fdt> <newaddr> <length> - Copy the fdt to <addr> and make it active\n"
"fdt resize - Resize fdt to size + padding to 4k addr\n"
"fdt print <path> [<prop>] - Recursive print starting at <path>\n"
diff --git a/common/cmd_fpgad.c b/common/cmd_fpgad.c
index 1b25ed8..1f1d00f 100644
--- a/common/cmd_fpgad.c
+++ b/common/cmd_fpgad.c
@@ -31,7 +31,8 @@
unsigned int fpga;
ulong addr, length;
int rc = 0;
- u16 linebuf[DISP_LINE_LEN/sizeof(u16)];
+ u16 linebuf[DISP_LINE_LEN/sizeof(u16)];
+ ulong nbytes;
/*
* We use the last specified parameters, unless new ones are
@@ -63,13 +64,28 @@
length = simple_strtoul(argv[3], NULL, 16);
}
- /* Print the lines. */
- for (k = 0; k < DISP_LINE_LEN / sizeof(u16); ++k)
- fpga_get_reg(fpga, (u16 *)fpga_ptr[fpga] + k, k * sizeof(u16),
- &linebuf[k]);
- print_buffer(addr, (void *)linebuf, sizeof(u16),
- length, DISP_LINE_LEN / sizeof(u16));
- addr += sizeof(u16)*length;
+ nbytes = length * sizeof(u16);
+ do {
+ ulong linebytes = (nbytes > DISP_LINE_LEN) ?
+ DISP_LINE_LEN : nbytes;
+
+ for (k = 0; k < linebytes / sizeof(u16); ++k)
+ fpga_get_reg(fpga,
+ (u16 *)fpga_ptr[fpga] + addr
+ / sizeof(u16) + k,
+ addr + k * sizeof(u16),
+ &linebuf[k]);
+ print_buffer(addr, (void *)linebuf, sizeof(u16),
+ linebytes / sizeof(u16),
+ DISP_LINE_LEN / sizeof(u16));
+
+ nbytes -= linebytes;
+ addr += linebytes;
+ if (ctrlc()) {
+ rc = 1;
+ break;
+ }
+ } while (nbytes > 0);
dp_last_fpga = fpga;
dp_last_addr = addr;
diff --git a/common/cmd_fs.c b/common/cmd_fs.c
index 6754340..0d9da11 100644
--- a/common/cmd_fs.c
+++ b/common/cmd_fs.c
@@ -51,6 +51,23 @@
" If 'pos' is 0 or omitted, the file is read from the start."
)
+static int do_save_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ return do_save(cmdtp, flag, argc, argv, FS_TYPE_ANY);
+}
+
+U_BOOT_CMD(
+ save, 7, 0, do_save_wrapper,
+ "save file to a filesystem",
+ "<interface> <dev[:part]> <addr> <filename> bytes [pos]\n"
+ " - Save binary file 'filename' to partition 'part' on device\n"
+ " type 'interface' instance 'dev' from addr 'addr' in memory.\n"
+ " 'bytes' gives the size to save in bytes and is mandatory.\n"
+ " 'pos' gives the file byte position to start writing to.\n"
+ " If 'pos' is 0 or omitted, the file is written from the start."
+)
+
static int do_ls_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
diff --git a/common/cmd_fs_uuid.c b/common/cmd_fs_uuid.c
new file mode 100644
index 0000000..613f3a4
--- /dev/null
+++ b/common/cmd_fs_uuid.c
@@ -0,0 +1,26 @@
+/*
+ * cmd_fs_uuid.c -- fsuuid command
+ *
+ * Copyright (C) 2014, Bachmann electronic GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fs.h>
+
+static int do_fs_uuid_wrapper(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ return do_fs_uuid(cmdtp, flag, argc, argv, FS_TYPE_ANY);
+}
+
+U_BOOT_CMD(
+ fsuuid, 4, 1, do_fs_uuid_wrapper,
+ "Look up a filesystem UUID",
+ "<interface> <dev>:<part>\n"
+ " - print filesystem UUID\n"
+ "fsuuid <interface> <dev>:<part> <varname>\n"
+ " - set environment variable to filesystem UUID\n"
+);
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index 3a75f94..c266b88 100644
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@@ -198,6 +198,19 @@
return alen;
}
+enum i2c_err_op {
+ I2C_ERR_READ,
+ I2C_ERR_WRITE,
+};
+
+static int i2c_report_err(int ret, enum i2c_err_op op)
+{
+ printf("Error %s the chip: %d\n",
+ op == I2C_ERR_READ ? "reading" : "writing", ret);
+
+ return CMD_RET_FAILURE;
+}
+
/**
* do_i2c_read() - Handle the "i2c read" command-line command
* @cmdtp: Command data struct pointer
@@ -245,7 +258,7 @@
memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
if (i2c_read(chip, devaddr, alen, memaddr, length) != 0) {
- puts ("Error reading the chip.\n");
+ i2c_report_err(-1, I2C_ERR_READ);
return 1;
}
return 0;
@@ -286,8 +299,7 @@
while (length-- > 0) {
if (i2c_write(chip, devaddr++, alen, memaddr++, 1) != 0) {
- puts("Error writing to the chip.\n");
- return 1;
+ return i2c_report_err(-1, I2C_ERR_WRITE);
}
/*
* No write delay with FRAM devices.
@@ -370,7 +382,7 @@
linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0)
- puts ("Error reading the chip.\n");
+ i2c_report_err(-1, I2C_ERR_READ);
else {
printf("%04x:", addr);
cp = linebuf;
@@ -452,7 +464,7 @@
while (count-- > 0) {
if (i2c_write(chip, addr++, alen, &byte, 1) != 0)
- puts ("Error writing the chip.\n");
+ i2c_report_err(-1, I2C_ERR_WRITE);
/*
* Wait for the write to complete. The write can take
* up to 10mSec (we allow a little more time).
@@ -528,7 +540,7 @@
addr++;
}
if (err > 0)
- puts ("Error reading the chip,\n");
+ i2c_report_err(-1, I2C_ERR_READ);
else
printf ("%08lx\n", crc);
@@ -601,7 +613,7 @@
do {
printf("%08lx:", addr);
if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0)
- puts ("\nError reading the chip,\n");
+ i2c_report_err(-1, I2C_ERR_READ);
else {
data = cpu_to_be32(data);
if (size == 1)
@@ -644,7 +656,7 @@
*/
bootretry_reset_cmd_timeout();
if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0)
- puts ("Error writing the chip.\n");
+ i2c_report_err(-1, I2C_ERR_WRITE);
#ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
#endif
@@ -783,7 +795,7 @@
*/
while (1) {
if (i2c_read(chip, addr, alen, bytes, length) != 0)
- puts ("Error reading the chip.\n");
+ i2c_report_err(-1, I2C_ERR_READ);
udelay(delay);
}
@@ -1341,7 +1353,7 @@
chip = simple_strtoul(argv[1], NULL, 16);
if (i2c_read(chip, 0, 1, (uchar *)&edid, sizeof(edid)) != 0) {
- puts("Error reading EDID content.\n");
+ i2c_report_err(-1, I2C_ERR_READ);
return 1;
}
diff --git a/common/cmd_md5sum.c b/common/cmd_md5sum.c
index 3ac8cc4..d22ace5 100644
--- a/common/cmd_md5sum.c
+++ b/common/cmd_md5sum.c
@@ -11,6 +11,7 @@
#include <common.h>
#include <command.h>
#include <u-boot/md5.h>
+#include <asm/io.h>
/*
* Store the resulting sum to an address or variable
@@ -79,6 +80,7 @@
int verify = 0;
int ac;
char * const *av;
+ void *buf;
if (argc < 3)
return CMD_RET_USAGE;
@@ -96,7 +98,9 @@
addr = simple_strtoul(*av++, NULL, 16);
len = simple_strtoul(*av++, NULL, 16);
- md5_wd((unsigned char *) addr, len, output, CHUNKSZ_MD5);
+ buf = map_sysmem(addr, len);
+ md5_wd(buf, len, output, CHUNKSZ_MD5);
+ unmap_sysmem(buf);
if (!verify) {
printf("md5 for %08lx ... %08lx ==> ", addr, addr + len - 1);
@@ -135,6 +139,7 @@
unsigned long addr, len;
unsigned int i;
u8 output[16];
+ void *buf;
if (argc < 3)
return CMD_RET_USAGE;
@@ -142,7 +147,10 @@
addr = simple_strtoul(argv[1], NULL, 16);
len = simple_strtoul(argv[2], NULL, 16);
- md5_wd((unsigned char *) addr, len, output, CHUNKSZ_MD5);
+ buf = map_sysmem(addr, len);
+ md5_wd(buf, len, output, CHUNKSZ_MD5);
+ unmap_sysmem(buf);
+
printf("md5 for %08lx ... %08lx ==> ", addr, addr + len - 1);
for (i = 0; i < 16; i++)
printf("%02x", output[i]);
diff --git a/common/cmd_pci.c b/common/cmd_pci.c
index a1ba42e..e3a77e3 100644
--- a/common/cmd_pci.c
+++ b/common/cmd_pci.c
@@ -42,12 +42,16 @@
*/
void pciinfo(int BusNum, int ShortPCIListing)
{
+ struct pci_controller *hose = pci_bus_to_hose(BusNum);
int Device;
int Function;
unsigned char HeaderType;
unsigned short VendorID;
pci_dev_t dev;
+ if (!hose)
+ return;
+
printf("Scanning PCI devices on bus %d\n", BusNum);
if (ShortPCIListing) {
@@ -67,6 +71,9 @@
dev = PCI_BDF(BusNum, Device, Function);
+ if (pci_skip_dev(hose, dev))
+ continue;
+
pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
continue;
diff --git a/common/cmd_sata.c b/common/cmd_sata.c
index fc92131..51f6703 100644
--- a/common/cmd_sata.c
+++ b/common/cmd_sata.c
@@ -48,6 +48,20 @@
}
int sata_initialize(void) __attribute__((weak,alias("__sata_initialize")));
+__weak int __sata_stop(void)
+{
+ int i, err = 0;
+
+ for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++)
+ err |= reset_sata(i);
+
+ if (err)
+ printf("Could not reset some SATA devices\n");
+
+ return err;
+}
+int sata_stop(void) __attribute__((weak, alias("__sata_stop")));
+
#ifdef CONFIG_PARTITIONS
block_dev_desc_t *sata_get_dev(int dev)
{
@@ -59,8 +73,15 @@
{
int rc = 0;
+ if (argc == 2 && strcmp(argv[1], "stop") == 0)
+ return sata_stop();
+
- if (argc == 2 && strcmp(argv[1], "init") == 0)
+ if (argc == 2 && strcmp(argv[1], "init") == 0) {
+ if (sata_curr_device != -1)
+ sata_stop();
+
return sata_initialize();
+ }
/* If the user has not yet run `sata init`, do it now */
if (sata_curr_device == -1)
@@ -185,6 +206,7 @@
sata, 5, 1, do_sata,
"SATA sub system",
"init - init SATA sub system\n"
+ "sata stop - disable SATA sub system\n"
"sata info - show available SATA devices\n"
"sata device [dev] - show or set current device\n"
"sata part [dev] - print partition table\n"
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 95a6f89..5c788e9 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -18,7 +18,6 @@
static struct spi_flash *flash;
-
/*
* This function computes the length argument for the erase command.
* The length on which the command is to operate can be given in two forms:
@@ -71,9 +70,9 @@
{
/* less accurate but avoids overflow */
if (len >= ((unsigned int) -1) / 1024)
- return len / (max(get_timer(start_ms) / 1024, 1));
+ return len / (max(get_timer(start_ms) / 1024, 1UL));
else
- return 1024 * len / max(get_timer(start_ms), 1);
+ return 1024 * len / max(get_timer(start_ms), 1UL);
}
static int do_spi_flash_probe(int argc, char * const argv[])
@@ -223,7 +222,7 @@
ulong last_update = get_timer(0);
for (; buf < end && !err_oper; buf += todo, offset += todo) {
- todo = min(end - buf, flash->sector_size);
+ todo = min_t(size_t, end - buf, flash->sector_size);
if (get_timer(last_update) > 100) {
printf(" \rUpdating, %zu%% %lu B/s",
100 - (end - buf) / scale,
@@ -421,7 +420,8 @@
for (i = 0; i < len; i++) {
if (vbuf[i] != 0xff) {
printf("Check failed at %d\n", i);
- print_buffer(i, vbuf + i, 1, min(len - i, 0x40), 0);
+ print_buffer(i, vbuf + i, 1,
+ min_t(uint, len - i, 0x40), 0);
return -1;
}
}
@@ -443,9 +443,11 @@
for (i = 0; i < len; i++) {
if (buf[i] != vbuf[i]) {
printf("Verify failed at %d, good data:\n", i);
- print_buffer(i, buf + i, 1, min(len - i, 0x40), 0);
+ print_buffer(i, buf + i, 1,
+ min_t(uint, len - i, 0x40), 0);
printf("Bad data:\n");
- print_buffer(i, vbuf + i, 1, min(len - i, 0x40), 0);
+ print_buffer(i, vbuf + i, 1,
+ min_t(uint, len - i, 0x40), 0);
return -1;
}
}
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index 991229d..6453ee9 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -2184,17 +2184,8 @@
INTERNAL_SIZE_T nb;
#ifdef CONFIG_SYS_MALLOC_F_LEN
- if (gd && !(gd->flags & GD_FLG_RELOC)) {
- ulong new_ptr;
- void *ptr;
-
- new_ptr = gd->malloc_ptr + bytes;
- if (new_ptr > gd->malloc_limit)
- panic("Out of pre-reloc memory");
- ptr = map_sysmem(gd->malloc_base + gd->malloc_ptr, bytes);
- gd->malloc_ptr = ALIGN(new_ptr, sizeof(new_ptr));
- return ptr;
- }
+ if (gd && !(gd->flags & GD_FLG_FULL_MALLOC_INIT))
+ return malloc_simple(bytes);
#endif
/* check if mem_malloc_init() was run */
@@ -2462,7 +2453,7 @@
#ifdef CONFIG_SYS_MALLOC_F_LEN
/* free() is a no-op - all the memory will be freed on relocation */
- if (!(gd->flags & GD_FLG_RELOC))
+ if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT))
return;
#endif
@@ -2618,7 +2609,7 @@
if (oldmem == NULL) return mALLOc(bytes);
#ifdef CONFIG_SYS_MALLOC_F_LEN
- if (!(gd->flags & GD_FLG_RELOC)) {
+ if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) {
/* This is harder to support and should not be needed */
panic("pre-reloc realloc() is not supported");
}
@@ -2970,7 +2961,7 @@
else
{
#ifdef CONFIG_SYS_MALLOC_F_LEN
- if (!(gd->flags & GD_FLG_RELOC)) {
+ if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) {
MALLOC_ZERO(mem, sz);
return mem;
}
diff --git a/common/env_fat.c b/common/env_fat.c
index 8db0160..e4c8489 100644
--- a/common/env_fat.c
+++ b/common/env_fat.c
@@ -41,6 +41,7 @@
disk_partition_t info;
int dev, part;
int err;
+ loff_t size;
err = env_export(&env_new);
if (err)
@@ -59,7 +60,8 @@
return 1;
}
- err = file_fat_write(FAT_ENV_FILE, (void *)&env_new, sizeof(env_t));
+ err = file_fat_write(FAT_ENV_FILE, (void *)&env_new, 0, sizeof(env_t),
+ &size);
if (err == -1) {
printf("\n** Unable to write \"%s\" from %s%d:%d **\n",
FAT_ENV_FILE, FAT_ENV_INTERFACE, dev, part);
diff --git a/common/env_nand.c b/common/env_nand.c
index 749605f..9c9bb82 100644
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -132,7 +132,7 @@
u_char *char_ptr;
blocksize = nand_info[0].erasesize;
- len = min(blocksize, CONFIG_ENV_SIZE);
+ len = min(blocksize, (size_t)CONFIG_ENV_SIZE);
while (amount_saved < CONFIG_ENV_SIZE && offset < end) {
if (nand_block_isbad(&nand_info[0], offset)) {
@@ -244,7 +244,7 @@
if (!blocksize)
return 1;
- len = min(blocksize, CONFIG_ENV_SIZE);
+ len = min(blocksize, (size_t)CONFIG_ENV_SIZE);
while (amount_loaded < CONFIG_ENV_SIZE && offset < end) {
if (nand_block_isbad(&nand_info[0], offset)) {
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 3f64156..ea42c63 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -16,22 +16,6 @@
#include <fdt_support.h>
#include <exports.h>
-/*
- * Get cells len in bytes
- * if #NNNN-cells property is 2 then len is 8
- * otherwise len is 4
- */
-static int get_cells_len(const void *fdt, const char *nr_cells_name)
-{
- const fdt32_t *cell;
-
- cell = fdt_getprop(fdt, 0, nr_cells_name, NULL);
- if (cell && fdt32_to_cpu(*cell) == 2)
- return 8;
-
- return 4;
-}
-
/**
* fdt_getprop_u32_default_node - Return a node's property or a default
*
@@ -113,7 +97,8 @@
}
/**
- * fdt_find_or_add_subnode - find or possibly add a subnode of a given node
+ * fdt_find_or_add_subnode() - find or possibly add a subnode of a given node
+ *
* @fdt: pointer to the device tree blob
* @parentoffset: structure block offset of a node
* @name: name of the subnode to locate
@@ -121,8 +106,7 @@
* fdt_subnode_offset() finds a subnode of the node with a given name.
* If the subnode does not exist, it will be created.
*/
-static int fdt_find_or_add_subnode(void *fdt, int parentoffset,
- const char *name)
+int fdt_find_or_add_subnode(void *fdt, int parentoffset, const char *name)
{
int offset;
@@ -246,7 +230,7 @@
return err;
}
- is_u64 = (get_cells_len(fdt, "#address-cells") == 8);
+ is_u64 = (fdt_address_cells(fdt, 0) == 2);
err = fdt_setprop_uxx(fdt, nodeoffset, "linux,initrd-start",
(uint64_t)initrd_start, is_u64);
@@ -382,22 +366,22 @@
/*
* fdt_pack_reg - pack address and size array into the "reg"-suitable stream
*/
-static int fdt_pack_reg(const void *fdt, void *buf, uint64_t *address,
- uint64_t *size, int n)
+static int fdt_pack_reg(const void *fdt, void *buf, u64 *address, u64 *size,
+ int n)
{
int i;
- int address_len = get_cells_len(fdt, "#address-cells");
- int size_len = get_cells_len(fdt, "#size-cells");
+ int address_len = fdt_address_cells(fdt, 0);
+ int size_len = fdt_size_cells(fdt, 0);
char *p = buf;
for (i = 0; i < n; i++) {
- if (address_len == 8)
+ if (address_len == 2)
*(fdt64_t *)p = cpu_to_fdt64(address[i]);
else
*(fdt32_t *)p = cpu_to_fdt32(address[i]);
p += address_len;
- if (size_len == 8)
+ if (size_len == 2)
*(fdt64_t *)p = cpu_to_fdt64(size[i]);
else
*(fdt32_t *)p = cpu_to_fdt32(size[i]);
@@ -968,13 +952,8 @@
{
const fdt32_t *prop;
- if (addrc) {
- prop = fdt_getprop(blob, parentoffset, "#address-cells", NULL);
- if (prop)
- *addrc = be32_to_cpup(prop);
- else
- *addrc = 2;
- }
+ if (addrc)
+ *addrc = fdt_address_cells(blob, parentoffset);
if (sizec) {
prop = fdt_getprop(blob, parentoffset, "#size-cells", NULL);
@@ -1199,7 +1178,8 @@
*/
int fdt_alloc_phandle(void *blob)
{
- int offset, phandle = 0;
+ int offset;
+ uint32_t phandle = 0;
for (offset = fdt_next_node(blob, -1, NULL); offset >= 0;
offset = fdt_next_node(blob, offset, NULL)) {
@@ -1419,11 +1399,7 @@
u32 naddr;
const fdt32_t *prop;
- prop = fdt_getprop(fdt, node, "#address-cells", &size);
- if (prop && size == 4)
- naddr = be32_to_cpup(prop);
- else
- naddr = 2;
+ naddr = fdt_address_cells(fdt, node);
prop = fdt_getprop(fdt, node, "ranges", &size);
@@ -1523,3 +1499,65 @@
return 0;
}
+
+/**
+ * fdt_setup_simplefb_node - Fill and enable a simplefb node
+ *
+ * @fdt: ptr to device tree
+ * @node: offset of the simplefb node
+ * @base_address: framebuffer base address
+ * @width: width in pixels
+ * @height: height in pixels
+ * @stride: bytes per line
+ * @format: pixel format string
+ *
+ * Convenience function to fill and enable a simplefb node.
+ */
+int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width,
+ u32 height, u32 stride, const char *format)
+{
+ char name[32];
+ fdt32_t cells[4];
+ int i, addrc, sizec, ret;
+
+ of_bus_default_count_cells(fdt, fdt_parent_offset(fdt, node),
+ &addrc, &sizec);
+ i = 0;
+ if (addrc == 2)
+ cells[i++] = cpu_to_fdt32(base_address >> 32);
+ cells[i++] = cpu_to_fdt32(base_address);
+ if (sizec == 2)
+ cells[i++] = 0;
+ cells[i++] = cpu_to_fdt32(height * stride);
+
+ ret = fdt_setprop(fdt, node, "reg", cells, sizeof(cells[0]) * i);
+ if (ret < 0)
+ return ret;
+
+ snprintf(name, sizeof(name), "framebuffer@%llx", base_address);
+ ret = fdt_set_name(fdt, node, name);
+ if (ret < 0)
+ return ret;
+
+ ret = fdt_setprop_u32(fdt, node, "width", width);
+ if (ret < 0)
+ return ret;
+
+ ret = fdt_setprop_u32(fdt, node, "height", height);
+ if (ret < 0)
+ return ret;
+
+ ret = fdt_setprop_u32(fdt, node, "stride", stride);
+ if (ret < 0)
+ return ret;
+
+ ret = fdt_setprop_string(fdt, node, "format", format);
+ if (ret < 0)
+ return ret;
+
+ ret = fdt_setprop_string(fdt, node, "status", "okay");
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
diff --git a/common/image-fdt.c b/common/image-fdt.c
index a39ae1b..1d76bd6 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -460,19 +460,32 @@
{
ulong *initrd_start = &images->initrd_start;
ulong *initrd_end = &images->initrd_end;
- int ret;
+ int ret = -EPERM;
+ int fdt_ret;
if (fdt_chosen(blob) < 0) {
- puts("ERROR: /chosen node create failed");
- puts(" - must RESET the board to recover.\n");
- return -1;
+ printf("ERROR: /chosen node create failed\n");
+ goto err;
}
if (arch_fixup_fdt(blob) < 0) {
- puts("ERROR: arch specific fdt fixup failed");
- return -1;
+ printf("ERROR: arch-specific fdt fixup failed\n");
+ goto err;
}
- if (IMAGE_OF_BOARD_SETUP)
- ft_board_setup(blob, gd->bd);
+ if (IMAGE_OF_BOARD_SETUP) {
+ fdt_ret = ft_board_setup(blob, gd->bd);
+ if (fdt_ret) {
+ printf("ERROR: board-specific fdt fixup failed: %s\n",
+ fdt_strerror(fdt_ret));
+ goto err;
+ }
+ }
+ if (IMAGE_OF_SYSTEM_SETUP) {
+ if (ft_system_setup(blob, gd->bd)) {
+ printf("ERROR: system-specific fdt fixup failed: %s\n",
+ fdt_strerror(fdt_ret));
+ goto err;
+ }
+ }
fdt_fixup_ethernet(blob);
/* Delete the old LMB reservation */
@@ -481,7 +494,7 @@
ret = fdt_shrink_to_minimum(blob);
if (ret < 0)
- return ret;
+ goto err;
of_size = ret;
if (*initrd_start && *initrd_end) {
@@ -493,7 +506,7 @@
fdt_initrd(blob, *initrd_start, *initrd_end);
if (!ft_verify_fdt(blob))
- return -1;
+ goto err;
#if defined(CONFIG_SOC_KEYSTONE)
if (IMAGE_OF_BOARD_SETUP)
@@ -501,4 +514,8 @@
#endif
return 0;
+err:
+ printf(" - must RESET the board to recover.\n\n");
+
+ return ret;
}
diff --git a/common/lcd.c b/common/lcd.c
index 37147af..28b3fe7 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -30,6 +30,7 @@
#include <splash.h>
#include <asm/io.h>
#include <asm/unaligned.h>
+#include <fdt_support.h>
#if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
defined(CONFIG_CPU_MONAHANS)
@@ -746,7 +747,7 @@
else
return;
- *axis = max(0, axis_alignment);
+ *axis = max(0, (int)axis_alignment);
}
#endif
@@ -1145,8 +1146,8 @@
void lcd_position_cursor(unsigned col, unsigned row)
{
- console_col = min(col, CONSOLE_COLS - 1);
- console_row = min(row, CONSOLE_ROWS - 1);
+ console_col = min_t(short, col, CONSOLE_COLS - 1);
+ console_row = min_t(short, row, CONSOLE_ROWS - 1);
}
int lcd_get_pixel_width(void)
@@ -1172,51 +1173,13 @@
#if defined(CONFIG_LCD_DT_SIMPLEFB)
static int lcd_dt_simplefb_configure_node(void *blob, int off)
{
- u32 stride;
- fdt32_t cells[2];
- int ret;
- static const char format[] =
#if LCD_BPP == LCD_COLOR16
- "r5g6b5";
+ return fdt_setup_simplefb_node(blob, off, gd->fb_base,
+ panel_info.vl_col, panel_info.vl_row,
+ panel_info.vl_col * 2, "r5g6b5");
#else
- "";
+ return -1;
#endif
-
- if (!format[0])
- return -1;
-
- stride = panel_info.vl_col * 2;
-
- cells[0] = cpu_to_fdt32(gd->fb_base);
- cells[1] = cpu_to_fdt32(stride * panel_info.vl_row);
- ret = fdt_setprop(blob, off, "reg", cells, sizeof(cells[0]) * 2);
- if (ret < 0)
- return -1;
-
- cells[0] = cpu_to_fdt32(panel_info.vl_col);
- ret = fdt_setprop(blob, off, "width", cells, sizeof(cells[0]));
- if (ret < 0)
- return -1;
-
- cells[0] = cpu_to_fdt32(panel_info.vl_row);
- ret = fdt_setprop(blob, off, "height", cells, sizeof(cells[0]));
- if (ret < 0)
- return -1;
-
- cells[0] = cpu_to_fdt32(stride);
- ret = fdt_setprop(blob, off, "stride", cells, sizeof(cells[0]));
- if (ret < 0)
- return -1;
-
- ret = fdt_setprop(blob, off, "format", format, strlen(format) + 1);
- if (ret < 0)
- return -1;
-
- ret = fdt_delprop(blob, off, "status");
- if (ret < 0)
- return -1;
-
- return 0;
}
int lcd_dt_simplefb_add_node(void *blob)
diff --git a/common/malloc_simple.c b/common/malloc_simple.c
new file mode 100644
index 0000000..afdacff
--- /dev/null
+++ b/common/malloc_simple.c
@@ -0,0 +1,39 @@
+/*
+ * Simple malloc implementation
+ *
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void *malloc_simple(size_t bytes)
+{
+ ulong new_ptr;
+ void *ptr;
+
+ new_ptr = gd->malloc_ptr + bytes;
+ if (new_ptr > gd->malloc_limit)
+ panic("Out of pre-reloc memory");
+ ptr = map_sysmem(gd->malloc_base + gd->malloc_ptr, bytes);
+ gd->malloc_ptr = ALIGN(new_ptr, sizeof(new_ptr));
+ return ptr;
+}
+
+#ifdef CONFIG_SYS_MALLOC_SIMPLE
+void *calloc(size_t nmemb, size_t elem_size)
+{
+ size_t size = nmemb * elem_size;
+ void *ptr;
+
+ ptr = malloc(size);
+ memset(ptr, '\0', size);
+
+ return ptr;
+}
+#endif
diff --git a/common/spl/spl.c b/common/spl/spl.c
index f01a21c..1826c47 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -7,6 +7,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <dm.h>
#include <spl.h>
#include <asm/u-boot.h>
#include <nand.h>
@@ -15,6 +16,7 @@
#include <i2c.h>
#include <image.h>
#include <malloc.h>
+#include <dm/root.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -139,9 +141,16 @@
u32 boot_device;
debug(">>spl:board_init_r()\n");
-#ifdef CONFIG_SYS_SPL_MALLOC_START
+#if defined(CONFIG_SYS_SPL_MALLOC_START)
mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
CONFIG_SYS_SPL_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
+#elif defined(CONFIG_SYS_MALLOC_F_LEN)
+ gd->malloc_limit = gd->malloc_base + CONFIG_SYS_MALLOC_F_LEN;
+ gd->malloc_ptr = 0;
+#endif
+#ifdef CONFIG_SPL_DM
+ dm_init_and_scan(true);
#endif
#ifndef CONFIG_PPC
@@ -221,7 +230,9 @@
break;
#endif
default:
- debug("SPL: Un-supported Boot Device\n");
+#if defined(CONFIG_SPL_SERIAL_SUPPORT) && defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+ printf("SPL: Unsupported Boot Device %d\n", boot_device);
+#endif
hang();
}
@@ -238,6 +249,11 @@
default:
debug("Unsupported OS image.. Jumping nevertheless..\n");
}
+#if defined(CONFIG_SYS_MALLOC_F_LEN) && !defined(CONFIG_SYS_SPL_MALLOC_SIZE)
+ debug("SPL malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr,
+ gd->malloc_ptr / 1024);
+#endif
+
jump_to_image_no_args(&spl_image);
}
diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index d9eba5a..9d37fd3 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -15,7 +15,7 @@
{
s32 err;
struct image_header *header;
- int filelen;
+ loff_t filelen, actlen;
disk_partition_t part_info = {};
header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
@@ -37,36 +37,36 @@
goto end;
}
- filelen = err = ext4fs_open(filename);
+ err = ext4fs_open(filename, &filelen);
if (err < 0) {
puts("spl: ext4fs_open failed\n");
goto end;
}
- err = ext4fs_read((char *)header, sizeof(struct image_header));
- if (err <= 0) {
+ err = ext4fs_read((char *)header, sizeof(struct image_header), &actlen);
+ if (err < 0) {
puts("spl: ext4fs_read failed\n");
goto end;
}
spl_parse_image_header(header);
- err = ext4fs_read((char *)spl_image.load_addr, filelen);
+ err = ext4fs_read((char *)spl_image.load_addr, filelen, &actlen);
end:
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- if (err <= 0)
+ if (err < 0)
printf("%s: error reading image %s, err - %d\n",
__func__, filename, err);
#endif
- return err <= 0;
+ return err < 0;
}
#ifdef CONFIG_SPL_OS_BOOT
int spl_load_image_ext_os(block_dev_desc_t *block_dev, int partition)
{
int err;
- int filelen;
+ __maybe_unused loff_t filelen, actlen;
disk_partition_t part_info = {};
__maybe_unused char *file;
@@ -89,13 +89,13 @@
#if defined(CONFIG_SPL_ENV_SUPPORT) && defined(CONFIG_SPL_OS_BOOT)
file = getenv("falcon_args_file");
if (file) {
- filelen = err = ext4fs_open(file);
+ err = ext4fs_open(file, &filelen);
if (err < 0) {
puts("spl: ext4fs_open failed\n");
goto defaults;
}
- err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen);
- if (err <= 0) {
+ err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen, &actlen);
+ if (err < 0) {
printf("spl: error reading image %s, err - %d, falling back to default\n",
file, err);
goto defaults;
@@ -119,12 +119,12 @@
defaults:
#endif
- filelen = err = ext4fs_open(CONFIG_SPL_FS_LOAD_ARGS_NAME);
+ err = ext4fs_open(CONFIG_SPL_FS_LOAD_ARGS_NAME, &filelen);
if (err < 0)
puts("spl: ext4fs_open failed\n");
- err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen);
- if (err <= 0) {
+ err = ext4fs_read((void *)CONFIG_SYS_SPL_ARGS_ADDR, filelen, &actlen);
+ if (err < 0) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: error reading image %s, err - %d\n",
__func__, CONFIG_SPL_FS_LOAD_ARGS_NAME, err);
diff --git a/common/usb_hub.c b/common/usb_hub.c
index 0f1eab4..66b4a72 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -300,7 +300,8 @@
}
descriptor = (struct usb_hub_descriptor *)buffer;
- length = min(descriptor->bLength, sizeof(struct usb_hub_descriptor));
+ length = min_t(int, descriptor->bLength,
+ sizeof(struct usb_hub_descriptor));
if (usb_get_hub_descriptor(dev, buffer, length) < 0) {
debug("usb_hub_configure: failed to get hub " \
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index 8517203..be8652b 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -2,6 +2,8 @@
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,USB_EHCI"
CONFIG_FDTFILE="sun5i-a13-olinuxino-micro.dtb"
CONFIG_USB1_VBUS_PIN="PG11"
+CONFIG_VIDEO=n
+CONFIG_USB_KEYBOARD=n
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN5I=y
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index 61f5466..654e12a 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -2,6 +2,8 @@
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER,USB_EHCI"
CONFIG_FDTFILE="sun5i-a13-olinuxino.dtb"
CONFIG_USB1_VBUS_PIN="PG11"
+CONFIG_VIDEO=n
+CONFIG_USB_KEYBOARD=n
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN5I=y
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index bef568d..de78a01 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -1,5 +1,6 @@
CONFIG_SPL=y
CONFIG_FDTFILE="sun6i-a31-colombus.dtb"
+CONFIG_USB_KEYBOARD=n
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN6I=y
diff --git a/configs/Ippo_q8h_v5_defconfig b/configs/Ippo_q8h_v5_defconfig
index fc67bd9..50c2f93 100644
--- a/configs/Ippo_q8h_v5_defconfig
+++ b/configs/Ippo_q8h_v5_defconfig
@@ -4,3 +4,5 @@
CONFIG_MACH_SUN8I=y
CONFIG_TARGET_IPPO_Q8H_V5=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v5.dtb"
+CONFIG_VIDEO=n
+CONFIG_USB_KEYBOARD=n
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index f46439f..ac3cd36 100644
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -1,5 +1,5 @@
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
CONFIG_FDTFILE="sun6i-a31-m9.dtb"
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
@@ -14,5 +14,7 @@
# HDMI power ?
+S:CONFIG_AXP221_ALDO2_VOLT=1800
+S:CONFIG_AXP221_ALDO3_VOLT=3000
-# No Vbus gpio for usb1
-+S:CONFIG_USB1_VBUS_PIN=""
+# Vbus gpio for usb1
++S:CONFIG_USB1_VBUS_PIN="PC27"
+# No Vbus gpio for usb2
++S:CONFIG_USB2_VBUS_PIN=""
diff --git a/configs/bcm11130_defconfig b/configs/bcm11130_defconfig
new file mode 100644
index 0000000..f8c9f03
--- /dev/null
+++ b/configs/bcm11130_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_MMC_ENV_DEV=0"
+CONFIG_ARM=y
+CONFIG_TARGET_BCM28155_AP=y
diff --git a/configs/bcm11130_nand_defconfig b/configs/bcm11130_nand_defconfig
new file mode 100644
index 0000000..39cb709
--- /dev/null
+++ b/configs/bcm11130_nand_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_ARM=y
+CONFIG_TARGET_BCM28155_AP=y
diff --git a/configs/bcm911360_entphn-ns_defconfig b/configs/bcm911360_entphn-ns_defconfig
new file mode 100644
index 0000000..6f5c154
--- /dev/null
+++ b/configs/bcm911360_entphn-ns_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000,ARMV7_NONSEC"
+CONFIG_ARM=y
+CONFIG_TARGET_BCMCYGNUS=y
diff --git a/configs/bcm911360_entphn_defconfig b/configs/bcm911360_entphn_defconfig
new file mode 100644
index 0000000..37b5846
--- /dev/null
+++ b/configs/bcm911360_entphn_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000"
+CONFIG_ARM=y
+CONFIG_TARGET_BCMCYGNUS=y
diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig
new file mode 100644
index 0000000..527e407
--- /dev/null
+++ b/configs/bcm911360k_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
+CONFIG_ARM=y
+CONFIG_TARGET_BCMCYGNUS=y
diff --git a/configs/bcm958300k-ns_defconfig b/configs/bcm958300k-ns_defconfig
new file mode 100644
index 0000000..0e3aaa7
--- /dev/null
+++ b/configs/bcm958300k-ns_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000,ARMV7_NONSEC"
+CONFIG_ARM=y
+CONFIG_TARGET_BCMCYGNUS=y
diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig
index 066739d..527e407 100644
--- a/configs/bcm958300k_defconfig
+++ b/configs/bcm958300k_defconfig
@@ -1,3 +1,3 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
CONFIG_ARM=y
-CONFIG_TARGET_BCM958300K=y
+CONFIG_TARGET_BCMCYGNUS=y
diff --git a/configs/bcm958305k_defconfig b/configs/bcm958305k_defconfig
new file mode 100644
index 0000000..527e407
--- /dev/null
+++ b/configs/bcm958305k_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
+CONFIG_ARM=y
+CONFIG_TARGET_BCMCYGNUS=y
diff --git a/configs/bcm958622hr_defconfig b/configs/bcm958622hr_defconfig
index 8a45e51..7c86300 100644
--- a/configs/bcm958622hr_defconfig
+++ b/configs/bcm958622hr_defconfig
@@ -1,3 +1,3 @@
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x01000000"
CONFIG_ARM=y
-CONFIG_TARGET_BCM958622HR=y
+CONFIG_TARGET_BCMNSP=y
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
new file mode 100644
index 0000000..b83803e
--- /dev/null
+++ b/configs/chromebook_link_defconfig
@@ -0,0 +1,10 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
+CONFIG_X86=y
+CONFIG_TARGET_CHROMEBOOK_LINK=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_SEPARATE=y
+CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
+CONFIG_HAVE_MRC=y
+CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index 50c06f7..3c0d64f 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -1,4 +1,4 @@
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/compulab/cm_fx6/imximage.cfg,MX6QDL,SPL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_CM_FX6=y
diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig
index f185329..4cddbdd 100644
--- a/configs/gwventana_defconfig
+++ b/configs/gwventana_defconfig
@@ -1,4 +1,4 @@
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_GW_VENTANA=y
diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig
new file mode 100644
index 0000000..69c65ba
--- /dev/null
+++ b/configs/hrcon_defconfig
@@ -0,0 +1,3 @@
+CONFIG_PPC=y
+CONFIG_MPC83xx=y
+CONFIG_TARGET_HRCON=y
diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig
index b7b26df..12e7844 100644
--- a/configs/mx6sabresd_spl_defconfig
+++ b/configs/mx6sabresd_spl_defconfig
@@ -1,5 +1,5 @@
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6sabresd_spl.cfg,SPL,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_MX6SABRESD=y
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index cadf461..b8fd97f 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -1,4 +1,4 @@
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/kosagi/novena/setup.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_KOSAGI_NOVENA=y
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
new file mode 100644
index 0000000..8ada0db
--- /dev/null
+++ b/configs/peach-pi_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_EXYNOS=y
++S:CONFIG_TARGET_PEACH_PI=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi"
diff --git a/doc/README.mxsimage b/doc/README.mxsimage
index 0d31cba..c3975ee 100644
--- a/doc/README.mxsimage
+++ b/doc/README.mxsimage
@@ -27,7 +27,7 @@
- Each line of the configuration file contains exactly one instruction.
- Every numeric value must be encoded in hexadecimal and in format 0xabcdef12 .
- The configuration file is a concatenation of blocks called "sections" and
- optionally "DCD blocks" (see below).
+ optionally "DCD blocks" (see below), and optional flags lines.
- Each "section" is started by the "SECTION" instruction.
- The "SECTION" instruction has the following semantics:
@@ -139,9 +139,14 @@
NOOP
- This instruction does nothing.
-- If the verbose output from the BootROM is enabled, the BootROM will produce a
- letter on the Debug UART for each instruction it started processing. Here is a
- mapping between the above instructions and the BootROM verbose output:
+ - An optional flags lines can be one of the following:
+
+ DISPLAYPROGRESS
+ - Enable boot progress output form the BootROM.
+
+- If the boot progress output from the BootROM is enabled, the BootROM will
+ produce a letter on the Debug UART for each instruction it started processing.
+ Here is a mapping between the above instructions and the BootROM output:
H -- SB Image header loaded
T -- TAG instruction
diff --git a/doc/README.odroid b/doc/README.odroid
index 528bb95..25b962b 100644
--- a/doc/README.odroid
+++ b/doc/README.odroid
@@ -141,3 +141,172 @@
- boot_fit - if "Image.itb" exists
- boot_zimg - if "zImage" exists
- boot_uimg - if "uImage" exists
+
+11. USB host support
+====================
+
+The ethernet can be accessed after starting the USB subsystem in U-Boot.
+The adapter does not come with a preconfigured MAC address, and hence it needs
+to be set before starting USB.
+setenv usbethaddr 02:DE:AD:BE:EF:FF
+
+Note that in this example a locally managed MAC address is chosen. Care should
+be taken to make these MAC addresses unique within the same subnet.
+
+Start the USB subsystem:
+Odroid # setenv usbethaddr 02:DE:AD:BE:EF:FF
+Odroid # usb start
+(Re)start USB...
+USB0: USB EHCI 1.00
+scanning bus 0 for devices... 4 USB Device(s) found
+ scanning usb for storage devices... 1 Storage Device(s) found
+ scanning usb for ethernet devices... 1 Ethernet Device(s) found
+Odroid #
+
+Automatic IP assignment:
+------------------------
+If the ethernet is connected to a DHCP server (router maybe with DHCP enabled),
+then the below will automatically assign an ip address through DHCP.
+setenv autoload no
+dhcp
+
+Odroid # setenv autoload no
+Odroid # dhcp
+Waiting for Ethernet connection... done.
+BOOTP broadcast 1
+DHCP client bound to address 192.168.1.10 (524 ms)
+Odroid #
+
+Note that this automatically sets the many IP address related variables in
+U-Boot that is obtained from the DHCP server.
+
+Odroid # printenv ipaddr netmask gatewayip dnsip
+ipaddr=192.168.1.10
+netmask=255.255.255.0
+gatewayip=192.168.1.1
+dnsip=192.168.1.1
+
+Ping example:
+The ping command can be used a test to check connectivity. In this example,
+192.168.1.27 is a pingable server in the network.
+Odroid # ping 192.168.1.27
+Waiting for Ethernet connection... done.
+Using sms0 device
+host 192.168.1.27 is alive
+Odroid #
+
+Static IP assignment:
+---------------------
+In the case where there are no DHCP servers in the network, or you want to
+set the IP address statically, it can be done by:
+Odroid # setenv ipaddr 192.168.1.10
+Odroid # ping 192.168.1.27
+Waiting for Ethernet connection... done.
+Using sms0 device
+host 192.168.1.27 is alive
+
+TFTP booting:
+-------------
+Say there exists a tftp server in the network with address 192.168.1.27 and
+it serves a kernel image (zImage.3.17) and a DTB blob (exynos4412-odroidu3.dtb)
+that needs to be loaded and booted. It can be accomplished as below:
+(Assumes that you have setenv usbethaddr, and have not set autoload to no)
+
+Odroid # setenv serverip 192.168.1.27
+Odroid # tftpboot 0x40080000 zImage.3.17
+Waiting for Ethernet connection... done.
+Using sms0 device
+TFTP from server 192.168.1.27; our IP address is 192.168.1.10
+Filename 'zImage.3.17'.
+Load address: 0x40080000
+Loading: #################################################################
+ #################################################################
+ #################################################################
+ #######################
+ 52.7 KiB/s
+done
+Bytes transferred = 3194200 (30bd58 hex)
+Odroid # tftpboot 0x42000000 exynos4412-odroidu3.dtb
+Waiting for Ethernet connection... done.
+Using sms0 device
+TFTP from server 192.168.1.27; our IP address is 192.168.1.10
+Filename 'exynos4412-odroidu3.dtb'.
+Load address: 0x42000000
+Loading: ####
+ 40 KiB/s
+done
+Bytes transferred = 46935 (b757 hex)
+Odroid # printenv bootargs
+bootargs=Please use defined boot
+Odroid # setenv bootargs console=ttySAC1,115200n8 root=/dev/mmcblk0p2 rootwait
+Odroid # bootz 40080000 - 42000000
+Kernel image @ 0x40080000 [ 0x000000 - 0x30bd58 ]
+## Flattened Device Tree blob at 42000000
+ Booting using the fdt blob at 0x42000000
+ Loading Device Tree to 4fff1000, end 4ffff756 ... OK
+
+Starting kernel ...
+
+[ 0.000000] Booting Linux on physical CPU 0xa00
+... etc ...
+
+In the above example you can substitute 'dhcp' for 'tftpboot' as well.
+
+USB Storage booting:
+--------------------
+Similarly we can use the USB storage to load the kernel image/initrd/fdt etc
+and boot. For this example, there is a USB drive plugged in. It has a FAT
+1st partition and an EXT 2nd partition. Using the generic FS (ls/load) makes
+it even easier to work with FAT/EXT file systems.
+For this example the second EXT partition is used for booting and as rootfs.
+The boot files - kernel and the dtb are present in the /boot directory of the
+second partition.
+
+Odroid # usb start
+(Re)start USB...
+USB0: USB EHCI 1.00
+scanning bus 0 for devices... 4 USB Device(s) found
+ scanning usb for storage devices... 1 Storage Device(s) found
+ scanning usb for ethernet devices...
+Error: sms0 address not set. <----- Note the error as usbethaddr
+Warning: failed to set MAC address <----- is not set.
+1 Ethernet Device(s) found
+Odroid # usb part 0
+
+Partition Map for USB device 0 -- Partition Type: DOS
+
+Part Start Sector Num Sectors UUID Type
+ 1 3072 263168 000c4046-01 06
+ 2 266240 13457408 000c4046-02 83
+
+Odroid # ls usb 0:2 /boot
+<DIR> 4096 .
+<DIR> 4096 ..
+ 353 boot.scr
+ 281 boot.txt
+ 101420 config-3.8.13.23
+ 2127254 initrd.img-3.8.13.23
+ 2194825 uInitrd
+ 2194825 uInitrd-3.8.13.23
+ 2453112 zImage
+ 101448 config-3.8.13.26
+ 2127670 uInitrd-3.8.13.26
+ 2127606 initrd.img-3.8.13.26
+ 3194200 zImage.3.17 <--- Kernel
+ 46935 exynos4412-odroidu3.dtb <--- DTB
+Odroid # load usb 0:2 40080000 /boot/zImage.3.17
+3194200 bytes read in 471 ms (6.5 MiB/s)
+Odroid # load usb 0:2 42000000 /boot/exynos4412-odroidu3.dtb
+46935 bytes read in 233 ms (196.3 KiB/s)
+Odroid # setenv bootargs console=ttySAC1,115200n8 root=/dev/sda2 rootwait
+Odroid # bootz 40080000 - 42000000
+Kernel image @ 0x40080000 [ 0x000000 - 0x30bd58 ]
+## Flattened Device Tree blob at 42000000
+ Booting using the fdt blob at 0x42000000
+ Loading Device Tree to 4fff1000, end 4ffff756 ... OK
+
+Starting kernel ...
+
+[ 0.000000] Booting Linux on physical CPU 0xa00
+
+Please refer to README.usb for additional information.
diff --git a/doc/device-tree-bindings/misc/intel-lpc.txt b/doc/device-tree-bindings/misc/intel-lpc.txt
new file mode 100644
index 0000000..7e1b389
--- /dev/null
+++ b/doc/device-tree-bindings/misc/intel-lpc.txt
@@ -0,0 +1,23 @@
+Intel LPC Device Binding
+========================
+
+The device tree node which describes the operation of the Intel Low Pin
+Count device is as follows:
+
+Required properties :
+- compatible = "intel,lpc"
+- gen-dec : Specifies the values for the gen-dec registers. Up to four cell
+ pairs can be provided - the first of each pair is the base address and
+ the second is the size. These are written into the GENx_DEC registers of
+ the LPC device
+
+
+Example
+-------
+
+lpc {
+ compatible = "intel,lpc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ gen-dec = <0x800 0xfc 0x900 0xfc>;
+};
diff --git a/doc/driver-model/README.txt b/doc/driver-model/README.txt
index 0278dda..3e2f622 100644
--- a/doc/driver-model/README.txt
+++ b/doc/driver-model/README.txt
@@ -750,19 +750,43 @@
pointer is saved but not made available through the driver model API).
-Things to punt for later
-------------------------
+SPL Support
+-----------
+
+Driver model can operate in SPL. Its efficient implementation and small code
+size provide for a small overhead which is acceptable for all but the most
+constrained systems.
-- SPL support - this will have to be present before many drivers can be
-converted, but it seems like we can add it once we are happy with the
-core implementation.
+To enable driver model in SPL, define CONFIG_SPL_DM. You might want to
+consider the following option also. See the main README for more details.
-That is not to say that no thinking has gone into this - in fact there
-is quite a lot there. However, getting these right is non-trivial and
-there is a high cost associated with going down the wrong path.
+ - CONFIG_SYS_MALLOC_SIMPLE
+ - CONFIG_DM_WARN
+ - CONFIG_DM_DEVICE_REMOVE
+ - CONFIG_DM_STDIO
-For SPL, it may be possible to fit in a simplified driver model with only
-bind and probe methods, to reduce size.
+
+Enabling Driver Model
+---------------------
+
+Driver model is being brought into U-Boot gradually. As each subsystems gets
+support, a uclass is created and a CONFIG to enable use of driver model for
+that subsystem.
+
+For example CONFIG_DM_SERIAL enables driver model for serial. With that
+defined, the old serial support is not enabled, and your serial driver must
+conform to driver model. With that undefined, the old serial support is
+enabled and driver model is not available for serial. This means that when
+you convert a driver, you must either convert all its boards, or provide for
+the driver to be compiled both with and without driver model (generally this
+is not very hard).
+
+See the main README for full details of the available driver model CONFIG
+options.
+
+
+Things to punt for later
+------------------------
Uclasses are statically numbered at compile time. It would be possible to
change this to dynamic numbering, but then we would require some sort of
diff --git a/drivers/Makefile b/drivers/Makefile
index 3c96524..5ef58c0 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -22,3 +22,4 @@
obj-y += input/
# SOC specific infrastructure drivers.
obj-y += soc/
+obj-y += thermal/
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index a93a8e1..c9a3beb 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -730,7 +730,7 @@
u16 now_blocks; /* number of blocks per iteration */
u32 transfer_size; /* number of bytes per iteration */
- now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);
+ now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
transfer_size = ATA_SECT_SIZE * now_blocks;
if (transfer_size > user_buffer_size) {
diff --git a/drivers/block/ata_piix.c b/drivers/block/ata_piix.c
index 5cf91ad..3042684 100644
--- a/drivers/block/ata_piix.c
+++ b/drivers/block/ata_piix.c
@@ -192,6 +192,11 @@
return 0;
}
+int reset_sata(int dev)
+{
+ return 0;
+}
+
static inline u8 sata_inb(unsigned long ioaddr)
{
return inb(ioaddr);
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index c68fd2f..9a2b547 100644
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -592,6 +592,27 @@
return 0;
}
+int reset_sata(int dev)
+{
+ struct ahci_probe_ent *probe_ent =
+ (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+ struct sata_host_regs *host_mmio =
+ (struct sata_host_regs *)probe_ent->mmio_base;
+
+ if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
+ printf("The sata index %d is out of ranges\n\r", dev);
+ return -1;
+ }
+
+ setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
+ while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
+ udelay(100);
+
+ disable_sata_clock();
+
+ return 0;
+}
+
static void dwc_ahsata_print_info(int dev)
{
block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c
index ebd6261..71d7cec 100644
--- a/drivers/block/fsl_sata.c
+++ b/drivers/block/fsl_sata.c
@@ -255,6 +255,11 @@
return 0;
}
+int reset_sata(int dev)
+{
+ return 0;
+}
+
static void fsl_sata_dump_regs(fsl_sata_reg_t __iomem *reg)
{
printf("\n\rSATA: %08x\n\r", (u32)reg);
diff --git a/drivers/block/pata_bfin.c b/drivers/block/pata_bfin.c
index b7fd1cd..c2673bd 100644
--- a/drivers/block/pata_bfin.c
+++ b/drivers/block/pata_bfin.c
@@ -1009,6 +1009,11 @@
return res;
}
+int reset_sata(int dev)
+{
+ return 0;
+}
+
/* Read up to 255 sectors
*
* Returns sectors read
diff --git a/drivers/block/sata_dwc.c b/drivers/block/sata_dwc.c
index efca5ea..9e8b067 100644
--- a/drivers/block/sata_dwc.c
+++ b/drivers/block/sata_dwc.c
@@ -423,6 +423,11 @@
return rc;
}
+int reset_sata(int dev)
+{
+ return 0;
+}
+
static u8 ata_check_altstatus(struct ata_port *ap)
{
u8 val = 0;
diff --git a/drivers/block/sata_sil.c b/drivers/block/sata_sil.c
index 1f510cd..daff7d4 100644
--- a/drivers/block/sata_sil.c
+++ b/drivers/block/sata_sil.c
@@ -519,7 +519,7 @@
u16 word;
if (init_done == 1 && dev < sata_info.maxport)
- return 1;
+ return 0;
init_done = 1;
@@ -571,6 +571,11 @@
return 0;
}
+int reset_sata(int dev)
+{
+ return 0;
+}
+
/*
* SATA interface between low level driver and command layer
*/
diff --git a/drivers/block/sata_sil3114.c b/drivers/block/sata_sil3114.c
index 3aa6fc9..61ffb66 100644
--- a/drivers/block/sata_sil3114.c
+++ b/drivers/block/sata_sil3114.c
@@ -702,6 +702,11 @@
return res;
}
+int reset_sata(int dev)
+{
+ return 0;
+}
+
/* Check if device is connected to port */
int sata_bus_probe (int portno)
{
diff --git a/drivers/core/Makefile b/drivers/core/Makefile
index 151c239..f14695b 100644
--- a/drivers/core/Makefile
+++ b/drivers/core/Makefile
@@ -4,5 +4,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := device.o lists.o root.o uclass.o util.o
+obj-$(CONFIG_DM) += device.o lists.o root.o uclass.o util.o
obj-$(CONFIG_OF_CONTROL) += simple-bus.o
+obj-$(CONFIG_DM_DEVICE_REMOVE) += device-remove.o
diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
new file mode 100644
index 0000000..8fc6b71
--- /dev/null
+++ b/drivers/core/device-remove.c
@@ -0,0 +1,187 @@
+/*
+ * Device manager
+ *
+ * Copyright (c) 2014 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <dm/device.h>
+#include <dm/device-internal.h>
+#include <dm/uclass.h>
+#include <dm/uclass-internal.h>
+#include <dm/util.h>
+
+/**
+ * device_chld_unbind() - Unbind all device's children from the device
+ *
+ * On error, the function continues to unbind all children, and reports the
+ * first error.
+ *
+ * @dev: The device that is to be stripped of its children
+ * @return 0 on success, -ve on error
+ */
+static int device_chld_unbind(struct udevice *dev)
+{
+ struct udevice *pos, *n;
+ int ret, saved_ret = 0;
+
+ assert(dev);
+
+ list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) {
+ ret = device_unbind(pos);
+ if (ret && !saved_ret)
+ saved_ret = ret;
+ }
+
+ return saved_ret;
+}
+
+/**
+ * device_chld_remove() - Stop all device's children
+ * @dev: The device whose children are to be removed
+ * @return 0 on success, -ve on error
+ */
+static int device_chld_remove(struct udevice *dev)
+{
+ struct udevice *pos, *n;
+ int ret;
+
+ assert(dev);
+
+ list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) {
+ ret = device_remove(pos);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int device_unbind(struct udevice *dev)
+{
+ struct driver *drv;
+ int ret;
+
+ if (!dev)
+ return -EINVAL;
+
+ if (dev->flags & DM_FLAG_ACTIVATED)
+ return -EINVAL;
+
+ drv = dev->driver;
+ assert(drv);
+
+ if (drv->unbind) {
+ ret = drv->unbind(dev);
+ if (ret)
+ return ret;
+ }
+
+ ret = device_chld_unbind(dev);
+ if (ret)
+ return ret;
+
+ ret = uclass_unbind_device(dev);
+ if (ret)
+ return ret;
+
+ if (dev->parent)
+ list_del(&dev->sibling_node);
+ free(dev);
+
+ return 0;
+}
+
+/**
+ * device_free() - Free memory buffers allocated by a device
+ * @dev: Device that is to be started
+ */
+void device_free(struct udevice *dev)
+{
+ int size;
+
+ if (dev->driver->priv_auto_alloc_size) {
+ free(dev->priv);
+ dev->priv = NULL;
+ }
+ if (dev->flags & DM_FLAG_ALLOC_PDATA) {
+ free(dev->platdata);
+ dev->platdata = NULL;
+ }
+ size = dev->uclass->uc_drv->per_device_auto_alloc_size;
+ if (size) {
+ free(dev->uclass_priv);
+ dev->uclass_priv = NULL;
+ }
+ if (dev->parent) {
+ size = dev->parent->driver->per_child_auto_alloc_size;
+ if (size) {
+ free(dev->parent_priv);
+ dev->parent_priv = NULL;
+ }
+ }
+}
+
+int device_remove(struct udevice *dev)
+{
+ struct driver *drv;
+ int ret;
+
+ if (!dev)
+ return -EINVAL;
+
+ if (!(dev->flags & DM_FLAG_ACTIVATED))
+ return 0;
+
+ drv = dev->driver;
+ assert(drv);
+
+ ret = uclass_pre_remove_device(dev);
+ if (ret)
+ return ret;
+
+ ret = device_chld_remove(dev);
+ if (ret)
+ goto err;
+
+ if (drv->remove) {
+ ret = drv->remove(dev);
+ if (ret)
+ goto err_remove;
+ }
+
+ if (dev->parent && dev->parent->driver->child_post_remove) {
+ ret = dev->parent->driver->child_post_remove(dev);
+ if (ret) {
+ dm_warn("%s: Device '%s' failed child_post_remove()",
+ __func__, dev->name);
+ }
+ }
+
+ device_free(dev);
+
+ dev->seq = -1;
+ dev->flags &= ~DM_FLAG_ACTIVATED;
+
+ return ret;
+
+err_remove:
+ /* We can't put the children back */
+ dm_warn("%s: Device '%s' failed to remove, but children are gone\n",
+ __func__, dev->name);
+err:
+ ret = uclass_post_probe_device(dev);
+ if (ret) {
+ dm_warn("%s: Device '%s' failed to post_probe on error path\n",
+ __func__, dev->name);
+ }
+
+ return ret;
+}
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 49faa29..6793e1c 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -24,52 +24,6 @@
DECLARE_GLOBAL_DATA_PTR;
-/**
- * device_chld_unbind() - Unbind all device's children from the device
- *
- * On error, the function continues to unbind all children, and reports the
- * first error.
- *
- * @dev: The device that is to be stripped of its children
- * @return 0 on success, -ve on error
- */
-static int device_chld_unbind(struct udevice *dev)
-{
- struct udevice *pos, *n;
- int ret, saved_ret = 0;
-
- assert(dev);
-
- list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) {
- ret = device_unbind(pos);
- if (ret && !saved_ret)
- saved_ret = ret;
- }
-
- return saved_ret;
-}
-
-/**
- * device_chld_remove() - Stop all device's children
- * @dev: The device whose children are to be removed
- * @return 0 on success, -ve on error
- */
-static int device_chld_remove(struct udevice *dev)
-{
- struct udevice *pos, *n;
- int ret;
-
- assert(dev);
-
- list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) {
- ret = device_remove(pos);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
int device_bind(struct udevice *parent, struct driver *drv, const char *name,
void *platdata, int of_offset, struct udevice **devp)
{
@@ -167,71 +121,6 @@
-1, devp);
}
-int device_unbind(struct udevice *dev)
-{
- struct driver *drv;
- int ret;
-
- if (!dev)
- return -EINVAL;
-
- if (dev->flags & DM_FLAG_ACTIVATED)
- return -EINVAL;
-
- drv = dev->driver;
- assert(drv);
-
- if (drv->unbind) {
- ret = drv->unbind(dev);
- if (ret)
- return ret;
- }
-
- ret = device_chld_unbind(dev);
- if (ret)
- return ret;
-
- ret = uclass_unbind_device(dev);
- if (ret)
- return ret;
-
- if (dev->parent)
- list_del(&dev->sibling_node);
- free(dev);
-
- return 0;
-}
-
-/**
- * device_free() - Free memory buffers allocated by a device
- * @dev: Device that is to be started
- */
-static void device_free(struct udevice *dev)
-{
- int size;
-
- if (dev->driver->priv_auto_alloc_size) {
- free(dev->priv);
- dev->priv = NULL;
- }
- if (dev->flags & DM_FLAG_ALLOC_PDATA) {
- free(dev->platdata);
- dev->platdata = NULL;
- }
- size = dev->uclass->uc_drv->per_device_auto_alloc_size;
- if (size) {
- free(dev->uclass_priv);
- dev->uclass_priv = NULL;
- }
- if (dev->parent) {
- size = dev->parent->driver->per_child_auto_alloc_size;
- if (size) {
- free(dev->parent_priv);
- dev->parent_priv = NULL;
- }
- }
-}
-
int device_probe_child(struct udevice *dev, void *parent_priv)
{
struct driver *drv;
@@ -342,63 +231,6 @@
return device_probe_child(dev, NULL);
}
-int device_remove(struct udevice *dev)
-{
- struct driver *drv;
- int ret;
-
- if (!dev)
- return -EINVAL;
-
- if (!(dev->flags & DM_FLAG_ACTIVATED))
- return 0;
-
- drv = dev->driver;
- assert(drv);
-
- ret = uclass_pre_remove_device(dev);
- if (ret)
- return ret;
-
- ret = device_chld_remove(dev);
- if (ret)
- goto err;
-
- if (drv->remove) {
- ret = drv->remove(dev);
- if (ret)
- goto err_remove;
- }
-
- if (dev->parent && dev->parent->driver->child_post_remove) {
- ret = dev->parent->driver->child_post_remove(dev);
- if (ret) {
- dm_warn("%s: Device '%s' failed child_post_remove()",
- __func__, dev->name);
- }
- }
-
- device_free(dev);
-
- dev->seq = -1;
- dev->flags &= ~DM_FLAG_ACTIVATED;
-
- return ret;
-
-err_remove:
- /* We can't put the children back */
- dm_warn("%s: Device '%s' failed to remove, but children are gone\n",
- __func__, dev->name);
-err:
- ret = uclass_post_probe_device(dev);
- if (ret) {
- dm_warn("%s: Device '%s' failed to post_probe on error path\n",
- __func__, dev->name);
- }
-
- return ret;
-}
-
void *dev_get_platdata(struct udevice *dev)
{
if (!dev) {
@@ -548,3 +380,13 @@
return 0;
}
+
+struct udevice *dev_get_parent(struct udevice *child)
+{
+ return child->parent;
+}
+
+ulong dev_get_of_data(struct udevice *dev)
+{
+ return dev->of_id->data;
+}
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index 3a1ea85..ff115c4 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -25,9 +25,6 @@
const int n_ents = ll_entry_count(struct driver, driver);
struct driver *entry;
- if (!drv || !n_ents)
- return NULL;
-
for (entry = drv; entry != drv + n_ents; entry++) {
if (!strcmp(name, entry->name))
return entry;
@@ -44,9 +41,6 @@
const int n_ents = ll_entry_count(struct uclass_driver, uclass);
struct uclass_driver *entry;
- if ((id == UCLASS_INVALID) || !uclass)
- return NULL;
-
for (entry = uclass; entry != uclass + n_ents; entry++) {
if (entry->id == id)
return entry;
@@ -77,34 +71,60 @@
return result;
}
+int device_bind_driver(struct udevice *parent, const char *drv_name,
+ const char *dev_name, struct udevice **devp)
+{
+ struct driver *drv;
+ int ret;
+
+ drv = lists_driver_lookup_name(drv_name);
+ if (!drv) {
+ printf("Cannot find driver '%s'\n", drv_name);
+ return -ENOENT;
+ }
+ ret = device_bind(parent, drv, dev_name, NULL, -1, devp);
+ if (ret) {
+ printf("Cannot create device named '%s' (err=%d)\n",
+ dev_name, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
#ifdef CONFIG_OF_CONTROL
/**
* driver_check_compatible() - Check if a driver is compatible with this node
*
* @param blob: Device tree pointer
* @param offset: Offset of node in device tree
- * @param of_matchL List of compatible strings to match
+ * @param of_match: List of compatible strings to match
+ * @param of_idp: Returns the match that was found
* @return 0 if there is a match, -ENOENT if no match, -ENODEV if the node
* does not have a compatible string, other error <0 if there is a device
* tree error
*/
static int driver_check_compatible(const void *blob, int offset,
- const struct udevice_id *of_match)
+ const struct udevice_id *of_match,
+ const struct udevice_id **of_idp)
{
int ret;
+ *of_idp = NULL;
if (!of_match)
return -ENOENT;
while (of_match->compatible) {
ret = fdt_node_check_compatible(blob, offset,
of_match->compatible);
- if (!ret)
+ if (!ret) {
+ *of_idp = of_match;
return 0;
- else if (ret == -FDT_ERR_NOTFOUND)
+ } else if (ret == -FDT_ERR_NOTFOUND) {
return -ENODEV;
- else if (ret < 0)
+ } else if (ret < 0) {
return -EINVAL;
+ }
of_match++;
}
@@ -116,6 +136,7 @@
{
struct driver *driver = ll_entry_start(struct driver, driver);
const int n_ents = ll_entry_count(struct driver, driver);
+ const struct udevice_id *id;
struct driver *entry;
struct udevice *dev;
bool found = false;
@@ -127,7 +148,8 @@
if (devp)
*devp = NULL;
for (entry = driver; entry != driver + n_ents; entry++) {
- ret = driver_check_compatible(blob, offset, entry->of_match);
+ ret = driver_check_compatible(blob, offset, entry->of_match,
+ &id);
name = fdt_get_name(blob, offset, NULL);
if (ret == -ENOENT) {
continue;
@@ -136,8 +158,7 @@
break;
} else if (ret) {
dm_warn("Device tree error at offset %d\n", offset);
- if (!result || ret != -ENOENT)
- result = ret;
+ result = ret;
break;
}
@@ -147,6 +168,7 @@
dm_warn("Error binding driver '%s'\n", entry->name);
return ret;
} else {
+ dev->of_id = id;
found = true;
if (devp)
*devp = dev;
diff --git a/drivers/core/root.c b/drivers/core/root.c
index a328a48..47b3acf 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -73,10 +73,8 @@
dm_warn("Some drivers were not found\n");
ret = 0;
}
- if (ret)
- return ret;
- return 0;
+ return ret;
}
#ifdef CONFIG_OF_CONTROL
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 9a156bf..9e2a4d2 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -303,7 +303,7 @@
#ifdef CONFIG_SYS_FSL_DDR4
/* tXP=max(4nCK, 6ns) */
- int txp = max(mclk_ps * 4, 6000); /* unit=ps */
+ int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
trwt_mclk = 2;
twrt_mclk = 1;
act_pd_exit_mclk = picos_to_mclk(txp);
@@ -312,7 +312,7 @@
* MRS_CYC = max(tMRD, tMOD)
* tMRD = 8nCK, tMOD = max(24nCK, 15ns)
*/
- tmrd_mclk = max(24, picos_to_mclk(15000));
+ tmrd_mclk = max(24U, picos_to_mclk(15000));
#elif defined(CONFIG_SYS_FSL_DDR3)
unsigned int data_rate = get_ddr_freq(0);
int txp;
@@ -325,7 +325,7 @@
* spec has not the tAXPD, we use
* tAXPD=1, need design to confirm.
*/
- txp = max(mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
+ txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
tmrd_mclk = 4;
/* set the turnaround time */
@@ -511,8 +511,8 @@
#ifdef CONFIG_SYS_FSL_DDR4
refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8;
wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
- acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4);
- wrtord_mclk = max(2, picos_to_mclk(2500));
+ acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4U);
+ wrtord_mclk = max(2U, picos_to_mclk(2500));
if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
else
@@ -627,14 +627,14 @@
wr_data_delay = popts->write_data_delay;
#ifdef CONFIG_SYS_FSL_DDR4
cpo = 0;
- cke_pls = max(3, picos_to_mclk(5000));
+ cke_pls = max(3U, picos_to_mclk(5000));
#elif defined(CONFIG_SYS_FSL_DDR3)
/*
* cke pulse = max(3nCK, 7.5ns) for DDR3-800
* max(3nCK, 5.625ns) for DDR3-1066, 1333
* max(3nCK, 5ns) for DDR3-1600, 1866, 2133
*/
- cke_pls = max(3, picos_to_mclk(mclk_ps > 1870 ? 7500 :
+ cke_pls = max(3U, picos_to_mclk(mclk_ps > 1870 ? 7500 :
(mclk_ps > 1245 ? 5625 : 5000)));
#else
cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
@@ -1810,9 +1810,9 @@
unsigned int txpr, tcksre, tcksrx;
unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
- txpr = max(5, picos_to_mclk(common_dimm->trfc1_ps + 10000));
- tcksre = max(5, picos_to_mclk(10000));
- tcksrx = max(5, picos_to_mclk(10000));
+ txpr = max(5U, picos_to_mclk(common_dimm->trfc1_ps + 10000));
+ tcksre = max(5U, picos_to_mclk(10000));
+ tcksrx = max(5U, picos_to_mclk(10000));
par_lat = 0;
cs_to_cmd = 0;
@@ -1877,7 +1877,7 @@
}
acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
- wrtord_bg = max(4, picos_to_mclk(7500));
+ wrtord_bg = max(4U, picos_to_mclk(7500));
if (popts->otf_burst_chop_en)
wrtord_bg += 2;
diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c
index 05a24dd..73db444 100644
--- a/drivers/ddr/fsl/lc_common_dimm_params.c
+++ b/drivers/ddr/fsl/lc_common_dimm_params.c
@@ -289,48 +289,58 @@
* Find minimum tckmax_ps to find fastest slow speed,
* i.e., this is the slowest the whole system can go.
*/
- tckmax_ps = min(tckmax_ps, dimm_params[i].tckmax_ps);
+ tckmax_ps = min(tckmax_ps,
+ (unsigned int)dimm_params[i].tckmax_ps);
#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
- taamin_ps = max(taamin_ps, dimm_params[i].taa_ps);
+ taamin_ps = max(taamin_ps,
+ (unsigned int)dimm_params[i].taa_ps);
#endif
- tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps);
- trcd_ps = max(trcd_ps, dimm_params[i].trcd_ps);
- trp_ps = max(trp_ps, dimm_params[i].trp_ps);
- tras_ps = max(tras_ps, dimm_params[i].tras_ps);
+ tckmin_x_ps = max(tckmin_x_ps,
+ (unsigned int)dimm_params[i].tckmin_x_ps);
+ trcd_ps = max(trcd_ps, (unsigned int)dimm_params[i].trcd_ps);
+ trp_ps = max(trp_ps, (unsigned int)dimm_params[i].trp_ps);
+ tras_ps = max(tras_ps, (unsigned int)dimm_params[i].tras_ps);
#ifdef CONFIG_SYS_FSL_DDR4
- trfc1_ps = max(trfc1_ps, dimm_params[i].trfc1_ps);
- trfc2_ps = max(trfc2_ps, dimm_params[i].trfc2_ps);
- trfc4_ps = max(trfc4_ps, dimm_params[i].trfc4_ps);
- trrds_ps = max(trrds_ps, dimm_params[i].trrds_ps);
- trrdl_ps = max(trrdl_ps, dimm_params[i].trrdl_ps);
- tccdl_ps = max(tccdl_ps, dimm_params[i].tccdl_ps);
+ trfc1_ps = max(trfc1_ps,
+ (unsigned int)dimm_params[i].trfc1_ps);
+ trfc2_ps = max(trfc2_ps,
+ (unsigned int)dimm_params[i].trfc2_ps);
+ trfc4_ps = max(trfc4_ps,
+ (unsigned int)dimm_params[i].trfc4_ps);
+ trrds_ps = max(trrds_ps,
+ (unsigned int)dimm_params[i].trrds_ps);
+ trrdl_ps = max(trrdl_ps,
+ (unsigned int)dimm_params[i].trrdl_ps);
+ tccdl_ps = max(tccdl_ps,
+ (unsigned int)dimm_params[i].tccdl_ps);
#else
- twr_ps = max(twr_ps, dimm_params[i].twr_ps);
- twtr_ps = max(twtr_ps, dimm_params[i].twtr_ps);
- trfc_ps = max(trfc_ps, dimm_params[i].trfc_ps);
- trrd_ps = max(trrd_ps, dimm_params[i].trrd_ps);
- trtp_ps = max(trtp_ps, dimm_params[i].trtp_ps);
+ twr_ps = max(twr_ps, (unsigned int)dimm_params[i].twr_ps);
+ twtr_ps = max(twtr_ps, (unsigned int)dimm_params[i].twtr_ps);
+ trfc_ps = max(trfc_ps, (unsigned int)dimm_params[i].trfc_ps);
+ trrd_ps = max(trrd_ps, (unsigned int)dimm_params[i].trrd_ps);
+ trtp_ps = max(trtp_ps, (unsigned int)dimm_params[i].trtp_ps);
#endif
- trc_ps = max(trc_ps, dimm_params[i].trc_ps);
+ trc_ps = max(trc_ps, (unsigned int)dimm_params[i].trc_ps);
#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
- tis_ps = max(tis_ps, dimm_params[i].tis_ps);
- tih_ps = max(tih_ps, dimm_params[i].tih_ps);
- tds_ps = max(tds_ps, dimm_params[i].tds_ps);
- tdh_ps = max(tdh_ps, dimm_params[i].tdh_ps);
- tqhs_ps = max(tqhs_ps, dimm_params[i].tqhs_ps);
+ tis_ps = max(tis_ps, (unsigned int)dimm_params[i].tis_ps);
+ tih_ps = max(tih_ps, (unsigned int)dimm_params[i].tih_ps);
+ tds_ps = max(tds_ps, (unsigned int)dimm_params[i].tds_ps);
+ tdh_ps = max(tdh_ps, (unsigned int)dimm_params[i].tdh_ps);
+ tqhs_ps = max(tqhs_ps, (unsigned int)dimm_params[i].tqhs_ps);
/*
* Find maximum tdqsq_max_ps to find slowest.
*
* FIXME: is finding the slowest value the correct
* strategy for this parameter?
*/
- tdqsq_max_ps = max(tdqsq_max_ps, dimm_params[i].tdqsq_max_ps);
+ tdqsq_max_ps = max(tdqsq_max_ps,
+ (unsigned int)dimm_params[i].tdqsq_max_ps);
#endif
refresh_rate_ps = max(refresh_rate_ps,
- dimm_params[i].refresh_rate_ps);
+ (unsigned int)dimm_params[i].refresh_rate_ps);
/* extended_op_srt is either 0 or 1, 0 having priority */
extended_op_srt = min(extended_op_srt,
- dimm_params[i].extended_op_srt);
+ (unsigned int)dimm_params[i].extended_op_srt);
}
outpdimm->ndimms_present = number_of_dimms - temp1;
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index b43b669..6f291eb 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -106,7 +106,8 @@
i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1);
ret = i2c_read(i2c_address, 0, 1,
(uchar *)((ulong)spd + 256),
- min(256, sizeof(generic_spd_eeprom_t) - 256));
+ min(256,
+ (int)sizeof(generic_spd_eeprom_t) - 256));
}
#else
ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c
index 55e6a83..c0aba6e 100644
--- a/drivers/dfu/dfu.c
+++ b/drivers/dfu/dfu.c
@@ -289,7 +289,7 @@
readn = 0;
while (size > 0) {
/* get chunk that can be read */
- chunk = min(size, dfu->b_left);
+ chunk = min((long)size, dfu->b_left);
/* consume */
if (chunk > 0) {
memcpy(buf, dfu->i_buf, chunk);
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 68fe0f3..6a74f89 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -406,8 +406,8 @@
unsigned long ts; /* Timestamp */
u32 isr_status, swap;
u32 partialbit = 0;
- u32 blocksize;
- u32 pos = 0;
+ loff_t blocksize, actread;
+ loff_t pos = 0;
int fstype;
char *interface, *dev_part, *filename;
@@ -420,7 +420,7 @@
if (fs_set_blk_dev(interface, dev_part, fstype))
return FPGA_FAIL;
- if (fs_read(filename, (u32) buf, pos, blocksize) < 0)
+ if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
return FPGA_FAIL;
if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap,
@@ -443,10 +443,10 @@
return FPGA_FAIL;
if (bsize > blocksize) {
- if (fs_read(filename, (u32) buf, pos, blocksize) < 0)
+ if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
return FPGA_FAIL;
} else {
- if (fs_read(filename, (u32) buf, pos, bsize) < 0)
+ if (fs_read(filename, (u32) buf, pos, bsize, &actread) < 0)
return FPGA_FAIL;
}
} while (bsize > blocksize);
diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c
index 6517af1..6129c02 100644
--- a/drivers/gpio/at91_gpio.c
+++ b/drivers/gpio/at91_gpio.c
@@ -10,11 +10,14 @@
#include <config.h>
#include <common.h>
+#include <dm.h>
#include <asm/io.h>
#include <linux/sizes.h>
+#include <asm/gpio.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pio.h>
-#include <asm/arch/gpio.h>
+
+#define GPIO_PER_BANK 32
static struct at91_port *at91_pio_get_port(unsigned port)
{
@@ -39,19 +42,25 @@
}
}
+static void at91_set_port_pullup(struct at91_port *at91_port, unsigned offset,
+ int use_pullup)
+{
+ u32 mask;
+
+ mask = 1 << offset;
+ if (use_pullup)
+ writel(mask, &at91_port->puer);
+ else
+ writel(mask, &at91_port->pudr);
+ writel(mask, &at91_port->per);
+}
+
int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
{
struct at91_port *at91_port = at91_pio_get_port(port);
- u32 mask;
- if (at91_port && (pin < 32)) {
- mask = 1 << pin;
- if (use_pullup)
- writel(1 << pin, &at91_port->puer);
- else
- writel(1 << pin, &at91_port->pudr);
- writel(mask, &at91_port->per);
- }
+ if (at91_port && (pin < GPIO_PER_BANK))
+ at91_set_port_pullup(at91_port, pin, use_pullup);
return 0;
}
@@ -64,7 +73,7 @@
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
- if (at91_port && (pin < 32)) {
+ if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
@@ -82,7 +91,7 @@
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
- if (at91_port && (pin < 32)) {
+ if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
@@ -108,7 +117,7 @@
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
- if (at91_port && (pin < 32)) {
+ if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
@@ -135,7 +144,7 @@
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
- if (at91_port && (pin < 32)) {
+ if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
@@ -157,7 +166,7 @@
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
- if (at91_port && (pin < 32)) {
+ if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
@@ -172,6 +181,29 @@
}
#endif
+#ifdef CONFIG_DM_GPIO
+static bool at91_get_port_output(struct at91_port *at91_port, int offset)
+{
+ u32 mask, val;
+
+ mask = 1 << offset;
+ val = readl(&at91_port->osr);
+ return val & mask;
+}
+#endif
+
+static void at91_set_port_input(struct at91_port *at91_port, int offset,
+ int use_pullup)
+{
+ u32 mask;
+
+ mask = 1 << offset;
+ writel(mask, &at91_port->idr);
+ at91_set_port_pullup(at91_port, offset, use_pullup);
+ writel(mask, &at91_port->odr);
+ writel(mask, &at91_port->per);
+}
+
/*
* mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
* configure it for an input.
@@ -179,19 +211,29 @@
int at91_set_pio_input(unsigned port, u32 pin, int use_pullup)
{
struct at91_port *at91_port = at91_pio_get_port(port);
- u32 mask;
- if (at91_port && (pin < 32)) {
- mask = 1 << pin;
- writel(mask, &at91_port->idr);
- at91_set_pio_pullup(port, pin, use_pullup);
- writel(mask, &at91_port->odr);
- writel(mask, &at91_port->per);
- }
+ if (at91_port && (pin < GPIO_PER_BANK))
+ at91_set_port_input(at91_port, pin, use_pullup);
return 0;
}
+static void at91_set_port_output(struct at91_port *at91_port, int offset,
+ int value)
+{
+ u32 mask;
+
+ mask = 1 << offset;
+ writel(mask, &at91_port->idr);
+ writel(mask, &at91_port->pudr);
+ if (value)
+ writel(mask, &at91_port->sodr);
+ else
+ writel(mask, &at91_port->codr);
+ writel(mask, &at91_port->oer);
+ writel(mask, &at91_port->per);
+}
+
/*
* mux the pin to the gpio controller (instead of "A" or "B" peripheral),
* and configure it for an output.
@@ -199,19 +241,9 @@
int at91_set_pio_output(unsigned port, u32 pin, int value)
{
struct at91_port *at91_port = at91_pio_get_port(port);
- u32 mask;
- if (at91_port && (port < ATMEL_PIO_PORTS) && (pin < 32)) {
- mask = 1 << pin;
- writel(mask, &at91_port->idr);
- writel(mask, &at91_port->pudr);
- if (value)
- writel(mask, &at91_port->sodr);
- else
- writel(mask, &at91_port->codr);
- writel(mask, &at91_port->oer);
- writel(mask, &at91_port->per);
- }
+ if (at91_port && (pin < GPIO_PER_BANK))
+ at91_set_port_output(at91_port, pin, value);
return 0;
}
@@ -224,7 +256,7 @@
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
- if (at91_port && (pin < 32)) {
+ if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
if (is_on) {
#if defined(CPU_HAS_PIO3)
@@ -248,7 +280,7 @@
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
- if (at91_port && (pin < 32)) {
+ if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
if (is_on) {
writel(mask, &at91_port->ifscer);
@@ -271,7 +303,7 @@
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
- if (at91_port && (pin < 32)) {
+ if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
writel(mask, &at91_port->pudr);
if (is_on)
@@ -291,7 +323,7 @@
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
- if (at91_port && (pin < 32)) {
+ if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
writel(readl(&at91_port->schmitt) | mask,
&at91_port->schmitt);
@@ -310,7 +342,7 @@
struct at91_port *at91_port = at91_pio_get_port(port);
u32 mask;
- if (at91_port && (pin < 32)) {
+ if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
if (is_on)
writel(mask, &at91_port->mder);
@@ -321,41 +353,54 @@
return 0;
}
+static void at91_set_port_value(struct at91_port *at91_port, int offset,
+ int value)
+{
+ u32 mask;
+
+ mask = 1 << offset;
+ if (value)
+ writel(mask, &at91_port->sodr);
+ else
+ writel(mask, &at91_port->codr);
+}
+
/*
* assuming the pin is muxed as a gpio output, set its value.
*/
int at91_set_pio_value(unsigned port, unsigned pin, int value)
{
struct at91_port *at91_port = at91_pio_get_port(port);
- u32 mask;
- if (at91_port && (pin < 32)) {
- mask = 1 << pin;
- if (value)
- writel(mask, &at91_port->sodr);
- else
- writel(mask, &at91_port->codr);
- }
+ if (at91_port && (pin < GPIO_PER_BANK))
+ at91_set_port_value(at91_port, pin, value);
return 0;
}
+static int at91_get_port_value(struct at91_port *at91_port, int offset)
+{
+ u32 pdsr = 0, mask;
+
+ mask = 1 << offset;
+ pdsr = readl(&at91_port->pdsr) & mask;
+
+ return pdsr != 0;
+}
/*
* read the pin's value (works even if it's not muxed as a gpio).
*/
int at91_get_pio_value(unsigned port, unsigned pin)
{
struct at91_port *at91_port = at91_pio_get_port(port);
- u32 pdsr = 0, mask;
- if (at91_port && (pin < 32)) {
- mask = 1 << pin;
- pdsr = readl(&at91_port->pdsr) & mask;
- }
+ if (at91_port && (pin < GPIO_PER_BANK))
+ return at91_get_port_value(at91_port, pin);
- return pdsr != 0;
+ return 0;
}
+#ifndef CONFIG_DM_GPIO
/* Common GPIO API */
int gpio_request(unsigned gpio, const char *label)
@@ -395,3 +440,91 @@
return 0;
}
+#endif
+
+#ifdef CONFIG_DM_GPIO
+
+struct at91_port_priv {
+ struct at91_port *regs;
+};
+
+/* set GPIO pin 'gpio' as an input */
+static int at91_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+ struct at91_port_priv *port = dev_get_platdata(dev);
+
+ at91_set_port_input(port->regs, offset, 0);
+
+ return 0;
+}
+
+/* set GPIO pin 'gpio' as an output, with polarity 'value' */
+static int at91_gpio_direction_output(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct at91_port_priv *port = dev_get_platdata(dev);
+
+ at91_set_port_output(port->regs, offset, value);
+
+ return 0;
+}
+
+/* read GPIO IN value of pin 'gpio' */
+static int at91_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+ struct at91_port_priv *port = dev_get_platdata(dev);
+
+ return at91_get_port_value(port->regs, offset);
+}
+
+/* write GPIO OUT value to pin 'gpio' */
+static int at91_gpio_set_value(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct at91_port_priv *port = dev_get_platdata(dev);
+
+ at91_set_port_value(port->regs, offset, value);
+
+ return 0;
+}
+
+static int at91_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+ struct at91_port_priv *port = dev_get_platdata(dev);
+
+ /* GPIOF_FUNC is not implemented yet */
+ if (at91_get_port_output(port->regs, offset))
+ return GPIOF_OUTPUT;
+ else
+ return GPIOF_INPUT;
+}
+
+static const struct dm_gpio_ops gpio_at91_ops = {
+ .direction_input = at91_gpio_direction_input,
+ .direction_output = at91_gpio_direction_output,
+ .get_value = at91_gpio_get_value,
+ .set_value = at91_gpio_set_value,
+ .get_function = at91_gpio_get_function,
+};
+
+static int at91_gpio_probe(struct udevice *dev)
+{
+ struct at91_port_priv *port = dev_get_priv(dev);
+ struct at91_port_platdata *plat = dev_get_platdata(dev);
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+
+ uc_priv->bank_name = plat->bank_name;
+ uc_priv->gpio_count = GPIO_PER_BANK;
+ port->regs = (struct at91_port *)plat->base_addr;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(gpio_at91) = {
+ .name = "gpio_at91",
+ .id = UCLASS_GPIO,
+ .ops = &gpio_at91_ops,
+ .probe = at91_gpio_probe,
+ .priv_auto_alloc_size = sizeof(struct at91_port_priv),
+};
+#endif
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index 45e9a5a..255700a 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -390,6 +390,25 @@
return 0;
}
+/*
+ * get a number comprised of multiple GPIO values. gpio_num_array points to
+ * the array of gpio pin numbers to scan, terminated by -1.
+ */
+unsigned gpio_get_values_as_int(const int *gpio_num_array)
+{
+ int gpio;
+ unsigned bitmask = 1;
+ unsigned vector = 0;
+
+ while (bitmask &&
+ ((gpio = *gpio_num_array++) != -1)) {
+ if (gpio_get_value(gpio))
+ vector |= bitmask;
+ bitmask <<= 1;
+ }
+ return vector;
+}
+
/* We need to renumber the GPIOs when any driver is probed/removed */
static int gpio_renumber(struct udevice *removed_dev)
{
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index d3381b0..b095d17 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -33,6 +33,11 @@
#include <pci.h>
#include <asm/gpio.h>
#include <asm/io.h>
+#include <asm/pci.h>
+#ifdef CONFIG_X86_RESET_VECTOR
+#include <asm/arch/pch.h>
+#define SUPPORT_GPIO_SETUP
+#endif
#define GPIO_PER_BANK 32
@@ -46,6 +51,53 @@
uint32_t lvl;
};
+#ifdef SUPPORT_GPIO_SETUP
+static void setup_pch_gpios(const struct pch_gpio_map *gpio)
+{
+ u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
+
+ /* GPIO Set 1 */
+ if (gpio->set1.level)
+ outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
+ if (gpio->set1.mode)
+ outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
+ if (gpio->set1.direction)
+ outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL);
+ if (gpio->set1.reset)
+ outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1);
+ if (gpio->set1.invert)
+ outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV);
+ if (gpio->set1.blink)
+ outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK);
+
+ /* GPIO Set 2 */
+ if (gpio->set2.level)
+ outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
+ if (gpio->set2.mode)
+ outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
+ if (gpio->set2.direction)
+ outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2);
+ if (gpio->set2.reset)
+ outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2);
+
+ /* GPIO Set 3 */
+ if (gpio->set3.level)
+ outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
+ if (gpio->set3.mode)
+ outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
+ if (gpio->set3.direction)
+ outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3);
+ if (gpio->set3.reset)
+ outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3);
+}
+
+/* TODO: Move this to device tree, or platform data */
+void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
+{
+ gd->arch.gpio_map = map;
+}
+#endif /* SUPPORT_GPIO_SETUP */
+
static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
{
struct ich6_bank_platdata *plat = dev_get_platdata(dev);
@@ -60,13 +112,13 @@
pci_dev = PCI_BDF(0, 0x1f, 0);
/* Is the device present? */
- pci_read_config_word(pci_dev, PCI_VENDOR_ID, &tmpword);
+ tmpword = pci_read_config16(pci_dev, PCI_VENDOR_ID);
if (tmpword != PCI_VENDOR_ID_INTEL) {
debug("%s: wrong VendorID\n", __func__);
return -ENODEV;
}
- pci_read_config_word(pci_dev, PCI_DEVICE_ID, &tmpword);
+ tmpword = pci_read_config16(pci_dev, PCI_DEVICE_ID);
debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword);
/*
* We'd like to validate the Device ID too, but pretty much any
@@ -76,34 +128,34 @@
*/
/* I/O should already be enabled (it's a RO bit). */
- pci_read_config_word(pci_dev, PCI_COMMAND, &tmpword);
+ tmpword = pci_read_config16(pci_dev, PCI_COMMAND);
if (!(tmpword & PCI_COMMAND_IO)) {
debug("%s: device IO not enabled\n", __func__);
return -ENODEV;
}
/* Header Type must be normal (bits 6-0 only; see spec.) */
- pci_read_config_byte(pci_dev, PCI_HEADER_TYPE, &tmpbyte);
+ tmpbyte = pci_read_config8(pci_dev, PCI_HEADER_TYPE);
if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) {
debug("%s: invalid Header type\n", __func__);
return -ENODEV;
}
/* Base Class must be a bridge device */
- pci_read_config_byte(pci_dev, PCI_CLASS_CODE, &tmpbyte);
+ tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_CODE);
if (tmpbyte != PCI_CLASS_CODE_BRIDGE) {
debug("%s: invalid class\n", __func__);
return -ENODEV;
}
/* Sub Class must be ISA */
- pci_read_config_byte(pci_dev, PCI_CLASS_SUB_CODE, &tmpbyte);
+ tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_SUB_CODE);
if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) {
debug("%s: invalid subclass\n", __func__);
return -ENODEV;
}
/* Programming Interface must be 0x00 (no others exist) */
- pci_read_config_byte(pci_dev, PCI_CLASS_PROG, &tmpbyte);
+ tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_PROG);
if (tmpbyte != 0x00) {
debug("%s: invalid interface type\n", __func__);
return -ENODEV;
@@ -114,7 +166,7 @@
* that it was unused (or undocumented). Check that it looks
* okay: not all ones or zeros, and mapped to I/O space (bit 0).
*/
- pci_read_config_dword(pci_dev, PCI_CFG_GPIOBASE, &tmplong);
+ tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
if (tmplong == 0x00000000 || tmplong == 0xffffffff ||
!(tmplong & 0x00000001)) {
debug("%s: unexpected GPIOBASE value\n", __func__);
@@ -140,12 +192,18 @@
return 0;
}
-int ich6_gpio_probe(struct udevice *dev)
+static int ich6_gpio_probe(struct udevice *dev)
{
struct ich6_bank_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev->uclass_priv;
struct ich6_bank_priv *bank = dev_get_priv(dev);
+#ifdef SUPPORT_GPIO_SETUP
+ if (gd->arch.gpio_map) {
+ setup_pch_gpios(gd->arch.gpio_map);
+ gd->arch.gpio_map = NULL;
+ }
+#endif
uc_priv->gpio_count = GPIO_PER_BANK;
uc_priv->bank_name = plat->bank_name;
bank->use_sel = plat->base_addr;
@@ -155,7 +213,8 @@
return 0;
}
-int ich6_gpio_request(struct udevice *dev, unsigned offset, const char *label)
+static int ich6_gpio_request(struct udevice *dev, unsigned offset,
+ const char *label)
{
struct ich6_bank_priv *bank = dev_get_priv(dev);
u32 tmplong;
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index d067897..dae3d71 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -5,7 +5,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
+obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
diff --git a/drivers/i2c/adi_i2c.c b/drivers/i2c/adi_i2c.c
new file mode 100644
index 0000000..20495b1
--- /dev/null
+++ b/drivers/i2c/adi_i2c.c
@@ -0,0 +1,305 @@
+/*
+ * i2c.c - driver for ADI TWI/I2C
+ *
+ * Copyright (c) 2006-2014 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/clock.h>
+#include <asm/twi.h>
+#include <asm/io.h>
+
+static struct twi_regs *i2c_get_base(struct i2c_adapter *adap);
+
+/* Every register is 32bit aligned, but only 16bits in size */
+#define ureg(name) u16 name; u16 __pad_##name;
+struct twi_regs {
+ ureg(clkdiv);
+ ureg(control);
+ ureg(slave_ctl);
+ ureg(slave_stat);
+ ureg(slave_addr);
+ ureg(master_ctl);
+ ureg(master_stat);
+ ureg(master_addr);
+ ureg(int_stat);
+ ureg(int_mask);
+ ureg(fifo_ctl);
+ ureg(fifo_stat);
+ char __pad[0x50];
+ ureg(xmt_data8);
+ ureg(xmt_data16);
+ ureg(rcv_data8);
+ ureg(rcv_data16);
+};
+#undef ureg
+
+#ifdef TWI_CLKDIV
+#define TWI0_CLKDIV TWI_CLKDIV
+# ifdef CONFIG_SYS_MAX_I2C_BUS
+# undef CONFIG_SYS_MAX_I2C_BUS
+# endif
+#define CONFIG_SYS_MAX_I2C_BUS 1
+#endif
+
+/*
+ * The way speed is changed into duty often results in integer truncation
+ * with 50% duty, so we'll force rounding up to the next duty by adding 1
+ * to the max. In practice this will get us a speed of something like
+ * 385 KHz. The other limit is easy to handle as it is only 8 bits.
+ */
+#define I2C_SPEED_MAX 400000
+#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed))
+#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
+#define I2C_DUTY_MIN 0xff /* 8 bit limited */
+#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
+/* Note: duty is inverse of speed, so the comparisons below are correct */
+#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN
+# error "The I2C hardware can only operate 20KHz - 400KHz"
+#endif
+
+/* All transfers are described by this data structure */
+struct i2c_msg {
+ u8 flags;
+#define I2C_M_COMBO 0x4
+#define I2C_M_STOP 0x2
+#define I2C_M_READ 0x1
+ int len; /* msg length */
+ u8 *buf; /* pointer to msg data */
+ int alen; /* addr length */
+ u8 *abuf; /* addr buffer */
+};
+
+/* Allow msec timeout per ~byte transfer */
+#define I2C_TIMEOUT 10
+
+/**
+ * wait_for_completion - manage the actual i2c transfer
+ * @msg: the i2c msg
+ */
+static int wait_for_completion(struct twi_regs *twi, struct i2c_msg *msg)
+{
+ u16 int_stat, ctl;
+ ulong timebase = get_timer(0);
+
+ do {
+ int_stat = readw(&twi->int_stat);
+
+ if (int_stat & XMTSERV) {
+ writew(XMTSERV, &twi->int_stat);
+ if (msg->alen) {
+ writew(*(msg->abuf++), &twi->xmt_data8);
+ --msg->alen;
+ } else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
+ writew(*(msg->buf++), &twi->xmt_data8);
+ --msg->len;
+ } else {
+ ctl = readw(&twi->master_ctl);
+ if (msg->flags & I2C_M_COMBO)
+ writew(ctl | RSTART | MDIR,
+ &twi->master_ctl);
+ else
+ writew(ctl | STOP, &twi->master_ctl);
+ }
+ }
+ if (int_stat & RCVSERV) {
+ writew(RCVSERV, &twi->int_stat);
+ if (msg->len) {
+ *(msg->buf++) = readw(&twi->rcv_data8);
+ --msg->len;
+ } else if (msg->flags & I2C_M_STOP) {
+ ctl = readw(&twi->master_ctl);
+ writew(ctl | STOP, &twi->master_ctl);
+ }
+ }
+ if (int_stat & MERR) {
+ writew(MERR, &twi->int_stat);
+ return msg->len;
+ }
+ if (int_stat & MCOMP) {
+ writew(MCOMP, &twi->int_stat);
+ if (msg->flags & I2C_M_COMBO && msg->len) {
+ ctl = readw(&twi->master_ctl);
+ ctl = (ctl & ~RSTART) |
+ (min(msg->len, 0xff) << 6) | MEN | MDIR;
+ writew(ctl, &twi->master_ctl);
+ } else
+ break;
+ }
+
+ /* If we were able to do something, reset timeout */
+ if (int_stat)
+ timebase = get_timer(0);
+
+ } while (get_timer(timebase) < I2C_TIMEOUT);
+
+ return msg->len;
+}
+
+static int i2c_transfer(struct i2c_adapter *adap, uint8_t chip, uint addr,
+ int alen, uint8_t *buffer, int len, uint8_t flags)
+{
+ struct twi_regs *twi = i2c_get_base(adap);
+ int ret;
+ u16 ctl;
+ uchar addr_buffer[] = {
+ (addr >> 0),
+ (addr >> 8),
+ (addr >> 16),
+ };
+ struct i2c_msg msg = {
+ .flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
+ .buf = buffer,
+ .len = len,
+ .abuf = addr_buffer,
+ .alen = alen,
+ };
+
+ /* wait for things to settle */
+ while (readw(&twi->master_stat) & BUSBUSY)
+ if (ctrlc())
+ return 1;
+
+ /* Set Transmit device address */
+ writew(chip, &twi->master_addr);
+
+ /* Clear the FIFO before starting things */
+ writew(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl);
+ writew(0, &twi->fifo_ctl);
+
+ /* prime the pump */
+ if (msg.alen) {
+ len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
+ writew(*(msg.abuf++), &twi->xmt_data8);
+ --msg.alen;
+ } else if (!(msg.flags & I2C_M_READ) && msg.len) {
+ writew(*(msg.buf++), &twi->xmt_data8);
+ --msg.len;
+ }
+
+ /* clear int stat */
+ writew(-1, &twi->master_stat);
+ writew(-1, &twi->int_stat);
+ writew(0, &twi->int_mask);
+
+ /* Master enable */
+ ctl = readw(&twi->master_ctl);
+ ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN |
+ ((msg.flags & I2C_M_READ) ? MDIR : 0);
+ writew(ctl, &twi->master_ctl);
+
+ /* process the rest */
+ ret = wait_for_completion(twi, &msg);
+
+ if (ret) {
+ ctl = readw(&twi->master_ctl) & ~MEN;
+ writew(ctl, &twi->master_ctl);
+ ctl = readw(&twi->control) & ~TWI_ENA;
+ writew(ctl, &twi->control);
+ ctl = readw(&twi->control) | TWI_ENA;
+ writew(ctl, &twi->control);
+ }
+
+ return ret;
+}
+
+static uint adi_i2c_setspeed(struct i2c_adapter *adap, uint speed)
+{
+ struct twi_regs *twi = i2c_get_base(adap);
+ u16 clkdiv = I2C_SPEED_TO_DUTY(speed);
+
+ /* Set TWI interface clock */
+ if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN)
+ return -1;
+ clkdiv = (clkdiv << 8) | (clkdiv & 0xff);
+ writew(clkdiv, &twi->clkdiv);
+
+ /* Don't turn it on */
+ writew(speed > 100000 ? FAST : 0, &twi->master_ctl);
+
+ return 0;
+}
+
+static void adi_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
+{
+ struct twi_regs *twi = i2c_get_base(adap);
+ u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;
+
+ /* Set TWI internal clock as 10MHz */
+ writew(prescale, &twi->control);
+
+ /* Set TWI interface clock as specified */
+ i2c_set_bus_speed(speed);
+
+ /* Enable it */
+ writew(TWI_ENA | prescale, &twi->control);
+}
+
+static int adi_i2c_read(struct i2c_adapter *adap, uint8_t chip,
+ uint addr, int alen, uint8_t *buffer, int len)
+{
+ return i2c_transfer(adap, chip, addr, alen, buffer,
+ len, alen ? I2C_M_COMBO : I2C_M_READ);
+}
+
+static int adi_i2c_write(struct i2c_adapter *adap, uint8_t chip,
+ uint addr, int alen, uint8_t *buffer, int len)
+{
+ return i2c_transfer(adap, chip, addr, alen, buffer, len, 0);
+}
+
+static int adi_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
+{
+ u8 byte;
+ return adi_i2c_read(adap, chip, 0, 0, &byte, 1);
+}
+
+static struct twi_regs *i2c_get_base(struct i2c_adapter *adap)
+{
+ switch (adap->hwadapnr) {
+#if CONFIG_SYS_MAX_I2C_BUS > 2
+ case 2:
+ return (struct twi_regs *)TWI2_CLKDIV;
+#endif
+#if CONFIG_SYS_MAX_I2C_BUS > 1
+ case 1:
+ return (struct twi_regs *)TWI1_CLKDIV;
+#endif
+ case 0:
+ return (struct twi_regs *)TWI0_CLKDIV;
+
+ default:
+ printf("wrong hwadapnr: %d\n", adap->hwadapnr);
+ }
+
+ return NULL;
+}
+
+U_BOOT_I2C_ADAP_COMPLETE(adi_i2c0, adi_i2c_init, adi_i2c_probe,
+ adi_i2c_read, adi_i2c_write,
+ adi_i2c_setspeed,
+ CONFIG_SYS_I2C_SPEED,
+ 0,
+ 0)
+
+#if CONFIG_SYS_MAX_I2C_BUS > 1
+U_BOOT_I2C_ADAP_COMPLETE(adi_i2c1, adi_i2c_init, adi_i2c_probe,
+ adi_i2c_read, adi_i2c_write,
+ adi_i2c_setspeed,
+ CONFIG_SYS_I2C_SPEED,
+ 0,
+ 1)
+#endif
+
+#if CONFIG_SYS_MAX_I2C_BUS > 2
+U_BOOT_I2C_ADAP_COMPLETE(adi_i2c2, adi_i2c_init, adi_i2c_probe,
+ adi_i2c_read, adi_i2c_write,
+ adi_i2c_setspeed,
+ CONFIG_SYS_I2C_SPEED,
+ 0,
+ 2)
+#endif
diff --git a/drivers/i2c/bfin-twi_i2c.c b/drivers/i2c/bfin-twi_i2c.c
deleted file mode 100644
index cfab064..0000000
--- a/drivers/i2c/bfin-twi_i2c.c
+++ /dev/null
@@ -1,379 +0,0 @@
-/*
- * i2c.c - driver for Blackfin on-chip TWI/I2C
- *
- * Copyright (c) 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <i2c.h>
-
-#include <asm/blackfin.h>
-#include <asm/clock.h>
-#include <asm/mach-common/bits/twi.h>
-
-/* Every register is 32bit aligned, but only 16bits in size */
-#define ureg(name) u16 name; u16 __pad_##name;
-struct twi_regs {
- ureg(clkdiv);
- ureg(control);
- ureg(slave_ctl);
- ureg(slave_stat);
- ureg(slave_addr);
- ureg(master_ctl);
- ureg(master_stat);
- ureg(master_addr);
- ureg(int_stat);
- ureg(int_mask);
- ureg(fifo_ctl);
- ureg(fifo_stat);
- char __pad[0x50];
- ureg(xmt_data8);
- ureg(xmt_data16);
- ureg(rcv_data8);
- ureg(rcv_data16);
-};
-#undef ureg
-
-/* U-Boot I2C framework allows only one active device at a time. */
-#ifdef TWI_CLKDIV
-#define TWI0_CLKDIV TWI_CLKDIV
-#endif
-static volatile struct twi_regs *twi = (void *)TWI0_CLKDIV;
-
-#ifdef DEBUG
-# define dmemset(s, c, n) memset(s, c, n)
-#else
-# define dmemset(s, c, n)
-#endif
-#define debugi(fmt, args...) \
- debug( \
- "MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t%-20s:%-3i: " fmt "\n", \
- twi->master_stat, twi->fifo_stat, twi->int_stat, \
- __func__, __LINE__, ## args)
-
-#ifdef CONFIG_TWICLK_KHZ
-# error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED
-#endif
-
-/*
- * The way speed is changed into duty often results in integer truncation
- * with 50% duty, so we'll force rounding up to the next duty by adding 1
- * to the max. In practice this will get us a speed of something like
- * 385 KHz. The other limit is easy to handle as it is only 8 bits.
- */
-#define I2C_SPEED_MAX 400000
-#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed))
-#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
-#define I2C_DUTY_MIN 0xff /* 8 bit limited */
-#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
-/* Note: duty is inverse of speed, so the comparisons below are correct */
-#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN
-# error "The Blackfin I2C hardware can only operate 20KHz - 400KHz"
-#endif
-
-/* All transfers are described by this data structure */
-struct i2c_msg {
- u8 flags;
-#define I2C_M_COMBO 0x4
-#define I2C_M_STOP 0x2
-#define I2C_M_READ 0x1
- int len; /* msg length */
- u8 *buf; /* pointer to msg data */
- int alen; /* addr length */
- u8 *abuf; /* addr buffer */
-};
-
-/* Allow msec timeout per ~byte transfer */
-#define I2C_TIMEOUT 10
-
-/**
- * wait_for_completion - manage the actual i2c transfer
- * @msg: the i2c msg
- */
-static int wait_for_completion(struct i2c_msg *msg)
-{
- uint16_t int_stat;
- ulong timebase = get_timer(0);
-
- do {
- int_stat = twi->int_stat;
-
- if (int_stat & XMTSERV) {
- debugi("processing XMTSERV");
- twi->int_stat = XMTSERV;
- SSYNC();
- if (msg->alen) {
- twi->xmt_data8 = *(msg->abuf++);
- --msg->alen;
- } else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
- twi->xmt_data8 = *(msg->buf++);
- --msg->len;
- } else {
- twi->master_ctl |= (msg->flags & I2C_M_COMBO) ? RSTART | MDIR : STOP;
- SSYNC();
- }
- }
- if (int_stat & RCVSERV) {
- debugi("processing RCVSERV");
- twi->int_stat = RCVSERV;
- SSYNC();
- if (msg->len) {
- *(msg->buf++) = twi->rcv_data8;
- --msg->len;
- } else if (msg->flags & I2C_M_STOP) {
- twi->master_ctl |= STOP;
- SSYNC();
- }
- }
- if (int_stat & MERR) {
- debugi("processing MERR");
- twi->int_stat = MERR;
- SSYNC();
- return msg->len;
- }
- if (int_stat & MCOMP) {
- debugi("processing MCOMP");
- twi->int_stat = MCOMP;
- SSYNC();
- if (msg->flags & I2C_M_COMBO && msg->len) {
- twi->master_ctl = (twi->master_ctl & ~RSTART) |
- (min(msg->len, 0xff) << 6) | MEN | MDIR;
- SSYNC();
- } else
- break;
- }
-
- /* If we were able to do something, reset timeout */
- if (int_stat)
- timebase = get_timer(0);
-
- } while (get_timer(timebase) < I2C_TIMEOUT);
-
- return msg->len;
-}
-
-/**
- * i2c_transfer - setup an i2c transfer
- * @return: 0 if things worked, non-0 if things failed
- *
- * Here we just get the i2c stuff all prepped and ready, and then tail off
- * into wait_for_completion() for all the bits to go.
- */
-static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, u8 flags)
-{
- uchar addr_buffer[] = {
- (addr >> 0),
- (addr >> 8),
- (addr >> 16),
- };
- struct i2c_msg msg = {
- .flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
- .buf = buffer,
- .len = len,
- .abuf = addr_buffer,
- .alen = alen,
- };
- int ret;
-
- dmemset(buffer, 0xff, len);
- debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i flags=0x%02x[%s] ",
- chip, addr, alen, buffer[0], len, flags, (flags & I2C_M_READ ? "rd" : "wr"));
-
- /* wait for things to settle */
- while (twi->master_stat & BUSBUSY)
- if (ctrlc())
- return 1;
-
- /* Set Transmit device address */
- twi->master_addr = chip;
-
- /* Clear the FIFO before starting things */
- twi->fifo_ctl = XMTFLUSH | RCVFLUSH;
- SSYNC();
- twi->fifo_ctl = 0;
- SSYNC();
-
- /* prime the pump */
- if (msg.alen) {
- len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
- debugi("first byte=0x%02x", *msg.abuf);
- twi->xmt_data8 = *(msg.abuf++);
- --msg.alen;
- } else if (!(msg.flags & I2C_M_READ) && msg.len) {
- debugi("first byte=0x%02x", *msg.buf);
- twi->xmt_data8 = *(msg.buf++);
- --msg.len;
- }
-
- /* clear int stat */
- twi->master_stat = -1;
- twi->int_stat = -1;
- twi->int_mask = 0;
- SSYNC();
-
- /* Master enable */
- twi->master_ctl =
- (twi->master_ctl & FAST) |
- (min(len, 0xff) << 6) | MEN |
- ((msg.flags & I2C_M_READ) ? MDIR : 0);
- SSYNC();
- debugi("CTL=0x%04x", twi->master_ctl);
-
- /* process the rest */
- ret = wait_for_completion(&msg);
- debugi("ret=%d", ret);
-
- if (ret) {
- twi->master_ctl &= ~MEN;
- twi->control &= ~TWI_ENA;
- SSYNC();
- twi->control |= TWI_ENA;
- SSYNC();
- }
-
- return ret;
-}
-
-/**
- * i2c_set_bus_speed - set i2c bus speed
- * @speed: bus speed (in HZ)
- */
-int i2c_set_bus_speed(unsigned int speed)
-{
- u16 clkdiv = I2C_SPEED_TO_DUTY(speed);
-
- /* Set TWI interface clock */
- if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN)
- return -1;
- twi->clkdiv = (clkdiv << 8) | (clkdiv & 0xff);
-
- /* Don't turn it on */
- twi->master_ctl = (speed > 100000 ? FAST : 0);
-
- return 0;
-}
-
-/**
- * i2c_get_bus_speed - get i2c bus speed
- * @speed: bus speed (in HZ)
- */
-unsigned int i2c_get_bus_speed(void)
-{
- /* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */
- return 5000000 / (twi->clkdiv & 0xff);
-}
-
-/**
- * i2c_init - initialize the i2c bus
- * @speed: bus speed (in HZ)
- * @slaveaddr: address of device in slave mode (0 - not slave)
- *
- * Slave mode isn't actually implemented. It'll stay that way until
- * we get a real request for it.
- */
-void i2c_init(int speed, int slaveaddr)
-{
- uint8_t prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;
-
- /* Set TWI internal clock as 10MHz */
- twi->control = prescale;
-
- /* Set TWI interface clock as specified */
- i2c_set_bus_speed(speed);
-
- /* Enable it */
- twi->control = TWI_ENA | prescale;
- SSYNC();
-
- debugi("CONTROL:0x%04x CLKDIV:0x%04x", twi->control, twi->clkdiv);
-
-#if CONFIG_SYS_I2C_SLAVE
-# error I2C slave support not tested/supported
- /* If they want us as a slave, do it */
- if (slaveaddr) {
- twi->slave_addr = slaveaddr;
- twi->slave_ctl = SEN;
- }
-#endif
-}
-
-/**
- * i2c_probe - test if a chip exists at a given i2c address
- * @chip: i2c chip addr to search for
- * @return: 0 if found, non-0 if not found
- */
-int i2c_probe(uchar chip)
-{
- u8 byte;
- return i2c_read(chip, 0, 0, &byte, 1);
-}
-
-/**
- * i2c_read - read data from an i2c device
- * @chip: i2c chip addr
- * @addr: memory (register) address in the chip
- * @alen: byte size of address
- * @buffer: buffer to store data read from chip
- * @len: how many bytes to read
- * @return: 0 on success, non-0 on failure
- */
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
- return i2c_transfer(chip, addr, alen, buffer, len, (alen ? I2C_M_COMBO : I2C_M_READ));
-}
-
-/**
- * i2c_write - write data to an i2c device
- * @chip: i2c chip addr
- * @addr: memory (register) address in the chip
- * @alen: byte size of address
- * @buffer: buffer holding data to write to chip
- * @len: how many bytes to write
- * @return: 0 on success, non-0 on failure
- */
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
- return i2c_transfer(chip, addr, alen, buffer, len, 0);
-}
-
-/**
- * i2c_set_bus_num - change active I2C bus
- * @bus: bus index, zero based
- * @returns: 0 on success, non-0 on failure
- */
-int i2c_set_bus_num(unsigned int bus)
-{
- switch (bus) {
-#if CONFIG_SYS_MAX_I2C_BUS > 0
- case 0: twi = (void *)TWI0_CLKDIV; return 0;
-#endif
-#if CONFIG_SYS_MAX_I2C_BUS > 1
- case 1: twi = (void *)TWI1_CLKDIV; return 0;
-#endif
-#if CONFIG_SYS_MAX_I2C_BUS > 2
- case 2: twi = (void *)TWI2_CLKDIV; return 0;
-#endif
- default: return -1;
- }
-}
-
-/**
- * i2c_get_bus_num - returns index of active I2C bus
- */
-unsigned int i2c_get_bus_num(void)
-{
- switch ((unsigned long)twi) {
-#if CONFIG_SYS_MAX_I2C_BUS > 0
- case TWI0_CLKDIV: return 0;
-#endif
-#if CONFIG_SYS_MAX_I2C_BUS > 1
- case TWI1_CLKDIV: return 1;
-#endif
-#if CONFIG_SYS_MAX_I2C_BUS > 2
- case TWI2_CLKDIV: return 2;
-#endif
- default: return -1;
- }
-}
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 7bb1702..ff7f25a 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -127,7 +127,7 @@
static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
unsigned int i2c_clk, unsigned int speed)
{
- unsigned short divider = min(i2c_clk / speed, (unsigned short) -1);
+ unsigned short divider = min(i2c_clk / speed, (unsigned int)USHRT_MAX);
/*
* We want to choose an FDR/DFSR that generates an I2C bus speed that
diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index 521edfd..9b4effb 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -701,6 +701,7 @@
/* Try sending a version 3 packet */
dev->protocol_version = 3;
+ req.in_data = 0;
if (ec_command_inptr(dev, EC_CMD_HELLO, 0, &req, sizeof(req),
(uint8_t **)&resp, sizeof(*resp)) > 0) {
return 0;
diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c
index e403664..e6dba29 100644
--- a/drivers/misc/cros_ec_spi.c
+++ b/drivers/misc/cros_ec_spi.c
@@ -143,7 +143,7 @@
return -1;
}
- len = min(p[1], din_len);
+ len = min((int)p[1], din_len);
cros_ec_dump_data("in", -1, p, len + 3);
/* Response code is first byte of message */
diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 3de1245..89737af 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -122,8 +122,8 @@
relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
1000000000) + 2 * (relax + 1) - 1;
- strobe_prog = DIV_ROUND(ipg_clk * BV_TIMING_STROBE_PROG_US, 1000000) +
- 2 * (relax + 1) - 1;
+ strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US,
+ 1000000) + 2 * (relax + 1) - 1;
timing = BF(strobe_read, TIMING_STROBE_READ) |
BF(relax, TIMING_RELAX) |
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 26406072..c55eb28 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -23,6 +23,13 @@
DECLARE_GLOBAL_DATA_PTR;
+#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
+ IRQSTATEN_CINT | \
+ IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
+ IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
+ IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
+ IRQSTATEN_DINT)
+
struct fsl_esdhc {
uint dsaddr; /* SDMA system address register */
uint blkattr; /* Block attributes register */
@@ -558,6 +565,7 @@
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
| SYSCTL_IPGEN | SYSCTL_CKEN);
+ writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
memset(&cfg->cfg, 0, sizeof(cfg->cfg));
voltage_caps = 0;
@@ -610,7 +618,7 @@
#endif
cfg->cfg.f_min = 400000;
- cfg->cfg.f_max = min(gd->arch.sdhc_clk, 52000000);
+ cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000);
cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
diff --git a/drivers/mmc/pxa_mmc_gen.c b/drivers/mmc/pxa_mmc_gen.c
index 1f29757..25ab0b1 100644
--- a/drivers/mmc/pxa_mmc_gen.c
+++ b/drivers/mmc/pxa_mmc_gen.c
@@ -197,7 +197,7 @@
while (len) {
/* The controller has data ready */
if (readl(®s->i_reg) & MMC_I_REG_RXFIFO_RD_REQ) {
- size = min(len, PXAMMC_FIFO_SIZE);
+ size = min(len, (uint32_t)PXAMMC_FIFO_SIZE);
len -= size;
size /= 4;
@@ -233,14 +233,14 @@
while (len) {
/* The controller is ready to receive data */
if (readl(®s->i_reg) & MMC_I_REG_TXFIFO_WR_REQ) {
- size = min(len, PXAMMC_FIFO_SIZE);
+ size = min(len, (uint32_t)PXAMMC_FIFO_SIZE);
len -= size;
size /= 4;
while (size--)
writel(*buf++, ®s->txfifo);
- if (min(len, PXAMMC_FIFO_SIZE) < 32)
+ if (min(len, (uint32_t)PXAMMC_FIFO_SIZE) < 32)
writel(MMC_PRTBUF_BUF_PART_FULL, ®s->prtbuf);
}
diff --git a/drivers/mtd/cfi_mtd.c b/drivers/mtd/cfi_mtd.c
index ac805ff..709a486 100644
--- a/drivers/mtd/cfi_mtd.c
+++ b/drivers/mtd/cfi_mtd.c
@@ -226,6 +226,7 @@
mtd->flags = MTD_CAP_NORFLASH;
mtd->size = fi->size;
mtd->writesize = 1;
+ mtd->writebufsize = mtd->writesize;
mtd->_erase = cfi_mtd_erase;
mtd->_read = cfi_mtd_read;
diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c
index 593b9b8..ce9af8f 100644
--- a/drivers/mtd/jedec_flash.c
+++ b/drivers/mtd/jedec_flash.c
@@ -333,6 +333,57 @@
}
},
{
+ .mfr_id = (u16)AMD_MANUFACT,
+ .dev_id = AM29LV800BT,
+ .name = "AMD AM29LV800BT",
+ .uaddr = {
+ [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
+ },
+ .DevSize = SIZE_1MiB,
+ .CmdSet = CFI_CMDSET_AMD_LEGACY,
+ .NumEraseRegions= 4,
+ .regions = {
+ ERASEINFO(0x10000, 15),
+ ERASEINFO(0x08000, 1),
+ ERASEINFO(0x02000, 2),
+ ERASEINFO(0x04000, 1),
+ }
+ },
+ {
+ .mfr_id = (u16)MX_MANUFACT,
+ .dev_id = AM29LV800BT,
+ .name = "MXIC MX29LV800BT",
+ .uaddr = {
+ [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
+ },
+ .DevSize = SIZE_1MiB,
+ .CmdSet = CFI_CMDSET_AMD_LEGACY,
+ .NumEraseRegions= 4,
+ .regions = {
+ ERASEINFO(0x10000, 15),
+ ERASEINFO(0x08000, 1),
+ ERASEINFO(0x02000, 2),
+ ERASEINFO(0x04000, 1),
+ }
+ },
+ {
+ .mfr_id = (u16)EON_ALT_MANU,
+ .dev_id = AM29LV800BT,
+ .name = "EON EN29LV800BT",
+ .uaddr = {
+ [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
+ },
+ .DevSize = SIZE_1MiB,
+ .CmdSet = CFI_CMDSET_AMD_LEGACY,
+ .NumEraseRegions= 4,
+ .regions = {
+ ERASEINFO(0x10000, 15),
+ ERASEINFO(0x08000, 1),
+ ERASEINFO(0x02000, 2),
+ ERASEINFO(0x04000, 1),
+ }
+ },
+ {
.mfr_id = (u16)STM_MANUFACT,
.dev_id = STM29F400BB,
.name = "ST Micro M29F400BB",
diff --git a/drivers/mtd/nand/denali_spl.c b/drivers/mtd/nand/denali_spl.c
index 65fdde8..e98f537 100644
--- a/drivers/mtd/nand/denali_spl.c
+++ b/drivers/mtd/nand/denali_spl.c
@@ -203,7 +203,7 @@
if (ret < 0)
return ret;
- readlen = min(page_size - column, size);
+ readlen = min(page_size - column, (int)size);
memcpy(dst, page_buffer, readlen);
column = 0;
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index 1cf2f98..3024b98 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -315,7 +315,7 @@
int ret;
while (size > 0) {
- todo = min(size, sizeof(sandbox_sf_0xff));
+ todo = min(size, (int)sizeof(sandbox_sf_0xff));
ret = os_write(sbsf->fd, sandbox_sf_0xff, todo);
if (ret != todo)
return ret;
@@ -602,14 +602,14 @@
spec, ret);
return ret;
}
- ret = device_find_child_by_seq(bus, cs, true, &slave);
+ ret = spi_find_chip_select(bus, cs, &slave);
if (!ret) {
printf("Chip select %d already exists for spec '%s'\n", cs,
spec);
return -EEXIST;
}
- ret = spi_bind_device(bus, cs, "spi_flash_std", spec, &slave);
+ ret = device_bind_driver(bus, "spi_flash_std", spec, &slave);
if (ret)
return ret;
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 85cf22d..759231f 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -313,10 +313,11 @@
return ret;
#endif
byte_addr = offset % page_size;
- chunk_len = min(len - actual, page_size - byte_addr);
+ chunk_len = min(len - actual, (size_t)(page_size - byte_addr));
if (flash->spi->max_write_size)
- chunk_len = min(chunk_len, flash->spi->max_write_size);
+ chunk_len = min(chunk_len,
+ (size_t)flash->spi->max_write_size);
spi_flash_addr(write_addr, cmd);
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 218a5ed..137886c 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -39,9 +39,14 @@
u32 value;
struct mii_dev bus;
bus.priv = priv->mac->phyregs;
+ bool sgmii_2500 = (priv->enet_if ==
+ PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
- /* SGMII IF mode + AN enable */
- value = PHY_SGMII_IF_MODE_AN | PHY_SGMII_IF_MODE_SGMII;
+ /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
+ value = PHY_SGMII_IF_MODE_SGMII;
+ if (!sgmii_2500)
+ value |= PHY_SGMII_IF_MODE_AN;
+
memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
/* Dev ability according to SGMII specification */
@@ -54,7 +59,9 @@
memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
/* Restart AN */
- value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
+ value = PHY_SGMII_CR_DEF_VAL;
+ if (!sgmii_2500)
+ value |= PHY_SGMII_CR_RESET_AN;
memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
#else
struct dtsec *regs = priv->mac->base;
@@ -83,7 +90,8 @@
out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
#endif
- if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII)
+ if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
+ fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
dtsec_configure_serdes(fm_eth);
}
diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c
index 623f749..677c89f 100644
--- a/drivers/net/netconsole.c
+++ b/drivers/net/netconsole.c
@@ -256,7 +256,7 @@
len = strlen(s);
while (len) {
- int send_len = min(len, sizeof(input_buffer));
+ int send_len = min(len, (int)sizeof(input_buffer));
nc_send_packet(s, send_len);
len -= send_len;
s += send_len;
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 60c333e..7ee21d1 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -195,6 +195,9 @@
bdf < PCI_BDF(bus + 1, 0, 0);
#endif
bdf += PCI_BDF(0, 0, 1)) {
+ if (pci_skip_dev(hose, bdf))
+ continue;
+
if (!PCI_FUNC(bdf)) {
pci_read_config_byte(bdf,
PCI_HEADER_TYPE,
@@ -662,13 +665,15 @@
#endif
#ifdef CONFIG_PCI_PNP
- sub_bus = max(pciauto_config_device(hose, dev), sub_bus);
+ sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
+ sub_bus);
#else
cfg = pci_find_config(hose, class, vendor, device,
PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
if (cfg) {
cfg->config_device(hose, dev, cfg);
- sub_bus = max(sub_bus, hose->current_busno);
+ sub_bus = max(sub_bus,
+ (unsigned int)hose->current_busno);
}
#endif
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 86ba6b5..44470fa 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -387,7 +387,7 @@
n = pci_hose_scan_bus(hose, hose->current_busno);
/* figure out the deepest we've gone for this leg */
- sub_bus = max(n, sub_bus);
+ sub_bus = max((unsigned int)n, sub_bus);
pciauto_postscan_setup_bridge(hose, dev, sub_bus);
sub_bus = hose->current_busno;
diff --git a/drivers/power/pmic/pmic_max77686.c b/drivers/power/pmic/pmic_max77686.c
index df1fd91..95b1a57 100644
--- a/drivers/power/pmic/pmic_max77686.c
+++ b/drivers/power/pmic/pmic_max77686.c
@@ -42,11 +42,30 @@
return 0;
}
+static int max77686_buck_volt2hex(int buck, ulong uV)
+{
+ int hex = 0;
+
+ if (buck < 5 || buck > 9) {
+ debug("%s: buck %d is not supported\n", __func__, buck);
+ return -EINVAL;
+ }
+
+ hex = (uV - 750000) / 50000;
+
+ if (hex >= 0 && hex <= MAX77686_BUCK_VOLT_MAX_HEX)
+ return hex;
+
+ debug("%s: %ld is wrong voltage value for BUCK%d\n",
+ __func__, uV, buck);
+ return -EINVAL;
+}
+
int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
{
unsigned int val, ret, hex, adr;
- if (ldo < 1 && ldo > 26) {
+ if (ldo < 1 || ldo > 26) {
printf("%s: %d is wrong ldo number\n", __func__, ldo);
return -1;
}
@@ -68,11 +87,38 @@
return ret;
}
+int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV)
+{
+ unsigned int val, adr;
+ int hex, ret;
+
+ if (buck < 5 || buck > 9) {
+ printf("%s: %d is an unsupported bucket number\n",
+ __func__, buck);
+ return -EINVAL;
+ }
+
+ adr = max77686_buck_addr[buck] + 1;
+ hex = max77686_buck_volt2hex(buck, uV);
+
+ if (hex < 0)
+ return hex;
+
+ ret = pmic_reg_read(p, adr, &val);
+ if (ret)
+ return ret;
+
+ val &= ~MAX77686_BUCK_VOLT_MASK;
+ ret |= pmic_reg_write(p, adr, val | hex);
+
+ return ret;
+}
+
int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode)
{
unsigned int val, ret, adr, mode;
- if (ldo < 1 && 26 < ldo) {
+ if (ldo < 1 || 26 < ldo) {
printf("%s: %d is wrong ldo number\n", __func__, ldo);
return -1;
}
@@ -157,7 +203,7 @@
/* mode */
switch (opmode) {
case OPMODE_OFF:
- mode = MAX77686_BUCK_MODE_OFF;
+ mode = MAX77686_BUCK_MODE_OFF << mode_shift;
break;
case OPMODE_STANDBY:
switch (buck) {
diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
index 8f0e348..4fe992b 100644
--- a/drivers/serial/atmel_usart.c
+++ b/drivers/serial/atmel_usart.c
@@ -7,11 +7,16 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <dm.h>
+#include <errno.h>
#include <watchdog.h>
#include <serial.h>
#include <linux/compiler.h>
#include <asm/io.h>
+#ifdef CONFIG_DM_SERIAL
+#include <asm/arch/atmel_serial.h>
+#endif
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
@@ -19,9 +24,9 @@
DECLARE_GLOBAL_DATA_PTR;
-static void atmel_serial_setbrg(void)
+static void atmel_serial_setbrg_internal(atmel_usart3_t *usart, int id,
+ int baudrate)
{
- atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
unsigned long divisor;
unsigned long usart_hz;
@@ -30,15 +35,13 @@
* Baud Rate = --------------
* 16 * CD
*/
- usart_hz = get_usart_clk_rate(CONFIG_USART_ID);
- divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate;
+ usart_hz = get_usart_clk_rate(id);
+ divisor = (usart_hz / 16 + baudrate / 2) / baudrate;
writel(USART3_BF(CD, divisor), &usart->brgr);
}
-static int atmel_serial_init(void)
+static void atmel_serial_init_internal(atmel_usart3_t *usart)
{
- atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
-
/*
* Just in case: drain transmitter register
* 1000us is enough for baudrate >= 9600
@@ -47,9 +50,10 @@
__udelay(1000);
writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
-
- serial_setbrg();
+}
+static void atmel_serial_activate(atmel_usart3_t *usart)
+{
writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
| USART3_BF(USCLKS, USART3_USCLKS_MCK)
| USART3_BF(CHRL, USART3_CHRL_8)
@@ -59,6 +63,22 @@
writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
/* 100us is enough for the new settings to be settled */
__udelay(100);
+}
+
+#ifndef CONFIG_DM_SERIAL
+static void atmel_serial_setbrg(void)
+{
+ atmel_serial_setbrg_internal((atmel_usart3_t *)CONFIG_USART_BASE,
+ CONFIG_USART_ID, gd->baudrate);
+}
+
+static int atmel_serial_init(void)
+{
+ atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
+
+ atmel_serial_init_internal(usart);
+ serial_setbrg();
+ atmel_serial_activate(usart);
return 0;
}
@@ -109,3 +129,81 @@
{
return &atmel_serial_drv;
}
+#endif
+
+#ifdef CONFIG_DM_SERIAL
+
+struct atmel_serial_priv {
+ atmel_usart3_t *usart;
+};
+
+int atmel_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct atmel_serial_priv *priv = dev_get_priv(dev);
+
+ atmel_serial_setbrg_internal(priv->usart, 0 /* ignored */, baudrate);
+ atmel_serial_activate(priv->usart);
+
+ return 0;
+}
+
+static int atmel_serial_getc(struct udevice *dev)
+{
+ struct atmel_serial_priv *priv = dev_get_priv(dev);
+
+ if (!(readl(&priv->usart->csr) & USART3_BIT(RXRDY)))
+ return -EAGAIN;
+
+ return readl(&priv->usart->rhr);
+}
+
+static int atmel_serial_putc(struct udevice *dev, const char ch)
+{
+ struct atmel_serial_priv *priv = dev_get_priv(dev);
+
+ if (!(readl(&priv->usart->csr) & USART3_BIT(TXRDY)))
+ return -EAGAIN;
+
+ writel(ch, &priv->usart->thr);
+
+ return 0;
+}
+
+static int atmel_serial_pending(struct udevice *dev, bool input)
+{
+ struct atmel_serial_priv *priv = dev_get_priv(dev);
+ uint32_t csr = readl(&priv->usart->csr);
+
+ if (input)
+ return csr & USART3_BIT(RXRDY) ? 1 : 0;
+ else
+ return csr & USART3_BIT(TXEMPTY) ? 0 : 1;
+}
+
+static const struct dm_serial_ops atmel_serial_ops = {
+ .putc = atmel_serial_putc,
+ .pending = atmel_serial_pending,
+ .getc = atmel_serial_getc,
+ .setbrg = atmel_serial_setbrg,
+};
+
+static int atmel_serial_probe(struct udevice *dev)
+{
+ struct atmel_serial_platdata *plat = dev->platdata;
+ struct atmel_serial_priv *priv = dev_get_priv(dev);
+
+ priv->usart = (atmel_usart3_t *)plat->base_addr;
+ atmel_serial_init_internal(priv->usart);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(serial_atmel) = {
+ .name = "serial_atmel",
+ .id = UCLASS_SERIAL,
+ .probe = atmel_serial_probe,
+ .ops = &atmel_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+ .priv_auto_alloc_size = sizeof(struct atmel_serial_priv),
+};
+#endif
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 71f1a5c..b09053f 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <dm.h>
+#include <environment.h>
#include <errno.h>
#include <fdtdec.h>
#include <os.h>
@@ -19,8 +20,10 @@
DECLARE_GLOBAL_DATA_PTR;
-/* The currently-selected console serial device */
-struct udevice *cur_dev __attribute__ ((section(".data")));
+/*
+ * Table with supported baudrates (defined in config_xyz.h)
+ */
+static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
#ifndef CONFIG_SYS_MALLOC_F_LEN
#error "Serial is required before relocation - define CONFIG_SYS_MALLOC_F_LEN to make this work"
@@ -28,6 +31,8 @@
static void serial_find_console_or_panic(void)
{
+ struct udevice *dev;
+
#ifdef CONFIG_OF_CONTROL
int node;
@@ -35,18 +40,21 @@
node = fdtdec_get_chosen_node(gd->fdt_blob, "stdout-path");
if (node < 0)
node = fdtdec_get_alias_node(gd->fdt_blob, "console");
- if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &cur_dev))
+ if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &dev)) {
+ gd->cur_serial_dev = dev;
return;
+ }
/*
* If the console is not marked to be bound before relocation, bind
* it anyway.
*/
if (node > 0 &&
- !lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &cur_dev)) {
- if (!device_probe(cur_dev))
+ !lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &dev)) {
+ if (!device_probe(dev)) {
+ gd->cur_serial_dev = dev;
return;
- cur_dev = NULL;
+ }
}
#endif
/*
@@ -61,11 +69,12 @@
#else
#define INDEX 0
#endif
- if (uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &cur_dev) &&
- uclass_get_device(UCLASS_SERIAL, INDEX, &cur_dev) &&
- (uclass_first_device(UCLASS_SERIAL, &cur_dev) || !cur_dev))
+ if (uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &dev) &&
+ uclass_get_device(UCLASS_SERIAL, INDEX, &dev) &&
+ (uclass_first_device(UCLASS_SERIAL, &dev) || !dev))
panic("No serial driver found");
#undef INDEX
+ gd->cur_serial_dev = dev;
}
/* Called prior to relocation */
@@ -127,40 +136,42 @@
void serial_putc(char ch)
{
- _serial_putc(cur_dev, ch);
+ _serial_putc(gd->cur_serial_dev, ch);
}
void serial_puts(const char *str)
{
- _serial_puts(cur_dev, str);
+ _serial_puts(gd->cur_serial_dev, str);
}
int serial_getc(void)
{
- return _serial_getc(cur_dev);
+ return _serial_getc(gd->cur_serial_dev);
}
int serial_tstc(void)
{
- return _serial_tstc(cur_dev);
+ return _serial_tstc(gd->cur_serial_dev);
}
void serial_setbrg(void)
{
- struct dm_serial_ops *ops = serial_get_ops(cur_dev);
+ struct dm_serial_ops *ops = serial_get_ops(gd->cur_serial_dev);
if (ops->setbrg)
- ops->setbrg(cur_dev, gd->baudrate);
+ ops->setbrg(gd->cur_serial_dev, gd->baudrate);
}
void serial_stdio_init(void)
{
}
+#ifdef CONFIG_DM_STDIO
static void serial_stub_putc(struct stdio_dev *sdev, const char ch)
{
_serial_putc(sdev->priv, ch);
}
+#endif
void serial_stub_puts(struct stdio_dev *sdev, const char *str)
{
@@ -177,11 +188,74 @@
return _serial_tstc(sdev->priv);
}
+/**
+ * on_baudrate() - Update the actual baudrate when the env var changes
+ *
+ * This will check for a valid baudrate and only apply it if valid.
+ */
+static int on_baudrate(const char *name, const char *value, enum env_op op,
+ int flags)
+{
+ int i;
+ int baudrate;
+
+ switch (op) {
+ case env_op_create:
+ case env_op_overwrite:
+ /*
+ * Switch to new baudrate if new baudrate is supported
+ */
+ baudrate = simple_strtoul(value, NULL, 10);
+
+ /* Not actually changing */
+ if (gd->baudrate == baudrate)
+ return 0;
+
+ for (i = 0; i < ARRAY_SIZE(baudrate_table); ++i) {
+ if (baudrate == baudrate_table[i])
+ break;
+ }
+ if (i == ARRAY_SIZE(baudrate_table)) {
+ if ((flags & H_FORCE) == 0)
+ printf("## Baudrate %d bps not supported\n",
+ baudrate);
+ return 1;
+ }
+ if ((flags & H_INTERACTIVE) != 0) {
+ printf("## Switch baudrate to %d bps and press ENTER ...\n",
+ baudrate);
+ udelay(50000);
+ }
+
+ gd->baudrate = baudrate;
+
+ serial_setbrg();
+
+ udelay(50000);
+
+ if ((flags & H_INTERACTIVE) != 0)
+ while (1) {
+ if (getc() == '\r')
+ break;
+ }
+
+ return 0;
+ case env_op_delete:
+ printf("## Baudrate may not be deleted\n");
+ return 1;
+ default:
+ return 0;
+ }
+}
+U_BOOT_ENV_CALLBACK(baudrate, on_baudrate);
+
static int serial_post_probe(struct udevice *dev)
{
- struct stdio_dev sdev;
struct dm_serial_ops *ops = serial_get_ops(dev);
+#ifdef CONFIG_DM_STDIO
struct serial_dev_priv *upriv = dev->uclass_priv;
+ struct stdio_dev sdev;
+#endif
int ret;
/* Set the baud rate */
@@ -191,9 +265,9 @@
return ret;
}
+#ifdef CONFIG_DM_STDIO
if (!(gd->flags & GD_FLG_RELOC))
return 0;
-
memset(&sdev, '\0', sizeof(sdev));
strncpy(sdev.name, dev->name, sizeof(sdev.name));
@@ -204,7 +278,7 @@
sdev.getc = serial_stub_getc;
sdev.tstc = serial_stub_tstc;
stdio_register_dev(&sdev, &upriv->sdev);
-
+#endif
return 0;
}
diff --git a/drivers/serial/serial_tegra.c b/drivers/serial/serial_tegra.c
index 7eb70e1..b9227f0 100644
--- a/drivers/serial/serial_tegra.c
+++ b/drivers/serial/serial_tegra.c
@@ -9,6 +9,7 @@
#include <ns16550.h>
#include <serial.h>
+#ifdef CONFIG_OF_CONTROL
static const struct udevice_id tegra_serial_ids[] = {
{ .compatible = "nvidia,tegra20-uart" },
{ }
@@ -26,13 +27,28 @@
return 0;
}
+#else
+struct ns16550_platdata tegra_serial = {
+ .base = CONFIG_SYS_NS16550_COM1,
+ .reg_shift = 2,
+ .clock = V_NS16550_CLK,
+};
+
+U_BOOT_DEVICE(ns16550_serial) = {
+ "serial_tegra20", &tegra_serial
+};
+#endif
+
U_BOOT_DRIVER(serial_ns16550) = {
.name = "serial_tegra20",
.id = UCLASS_SERIAL,
+#ifdef CONFIG_OF_CONTROL
.of_match = tegra_serial_ids,
.ofdata_to_platdata = tegra_serial_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+#endif
.priv_auto_alloc_size = sizeof(struct NS16550),
.probe = ns16550_serial_probe,
.ops = &ns16550_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
};
diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c
index 7fb0b92..75f0ec3 100644
--- a/drivers/serial/usbtty.c
+++ b/drivers/serial/usbtty.c
@@ -882,7 +882,7 @@
space_avail =
current_urb->buffer_length -
current_urb->actual_length;
- popnum = min(space_avail, buf->size);
+ popnum = min(space_avail, (int)buf->size);
if (popnum == 0)
break;
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index ae0fe58..375dc07 100644
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -273,7 +273,7 @@
spi_cs_deactivate(slave);
return 0;
}
- buf_len = 2 * cmd_len + min(data_len, max_tran_len);
+ buf_len = 2 * cmd_len + min(data_len, (size_t)max_tran_len);
len = cmd_len + data_len;
rx_offset = cmd_len;
buffer = (unsigned char *)malloc(buf_len);
@@ -306,7 +306,7 @@
if (data_in)
din = buffer + rx_offset;
dout = buffer;
- tran_len = min(data_len , max_tran_len);
+ tran_len = min(data_len, (size_t)max_tran_len);
num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4);
num_bytes = (tran_len + cmd_len) % 4;
fsl->data_len = tran_len + cmd_len;
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 23f2ba6..0881599 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -315,7 +315,7 @@
tmp = reg_read(®s->rxdata);
data = cpu_to_be32(tmp);
debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
- cnt = min(nbytes, sizeof(data));
+ cnt = min_t(u32, nbytes, sizeof(data));
if (din) {
memcpy(din, &data, cnt);
din += cnt;
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 13c6b77..7a57bce 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -57,7 +57,7 @@
speed = slave->max_hz;
if (spi->max_hz) {
if (speed)
- speed = min(speed, spi->max_hz);
+ speed = min(speed, (int)spi->max_hz);
else
speed = spi->max_hz;
}
@@ -115,16 +115,7 @@
return slave ? slave->cs : -ENOENT;
}
-/**
- * spi_find_chip_select() - Find the slave attached to chip select
- *
- * @bus: SPI bus to search
- * @cs: Chip select to look for
- * @devp: Returns the slave device if found
- * @return 0 if found, -ENODEV on error
- */
-static int spi_find_chip_select(struct udevice *bus, int cs,
- struct udevice **devp)
+int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp)
{
struct udevice *dev;
@@ -197,27 +188,6 @@
return -ENODEV;
}
-int spi_bind_device(struct udevice *bus, int cs, const char *drv_name,
- const char *dev_name, struct udevice **devp)
-{
- struct driver *drv;
- int ret;
-
- drv = lists_driver_lookup_name(drv_name);
- if (!drv) {
- printf("Cannot find driver '%s'\n", drv_name);
- return -ENOENT;
- }
- ret = device_bind(bus, drv, dev_name, NULL, -1, devp);
- if (ret) {
- printf("Cannot create device named '%s' (err=%d)\n",
- dev_name, ret);
- return ret;
- }
-
- return 0;
-}
-
int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp,
struct udevice **devp)
{
@@ -264,7 +234,7 @@
if (ret == -ENODEV && drv_name) {
debug("%s: Binding new device '%s', busnum=%d, cs=%d, driver=%s\n",
__func__, dev_name, busnum, cs, drv_name);
- ret = spi_bind_device(bus, cs, drv_name, dev_name, &dev);
+ ret = device_bind_driver(bus, drv_name, dev_name, &dev);
if (ret)
return ret;
created = true;
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
new file mode 100644
index 0000000..6d4cacd
--- /dev/null
+++ b/drivers/thermal/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2014 Freescale Semiconductor, Inc.
+# Author: Nitin Garg <nitin.garg@freescale.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_DM_THERMAL) += thermal-uclass.o
+obj-$(CONFIG_IMX6_THERMAL) += imx_thermal.o
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
new file mode 100644
index 0000000..1161585
--- /dev/null
+++ b/drivers/thermal/imx_thermal.c
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2014 Freescale Semiconductor, Inc.
+ * Author: Nitin Garg <nitin.garg@freescale.com>
+ * Ye Li <Ye.Li@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <div64.h>
+#include <fuse.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <dm.h>
+#include <errno.h>
+#include <malloc.h>
+#include <thermal.h>
+#include <imx_thermal.h>
+
+#define TEMPERATURE_MIN -40
+#define TEMPERATURE_HOT 80
+#define TEMPERATURE_MAX 125
+#define FACTOR0 10000000
+#define FACTOR1 15976
+#define FACTOR2 4297157
+#define MEASURE_FREQ 327
+
+#define TEMPSENSE0_TEMP_CNT_SHIFT 8
+#define TEMPSENSE0_TEMP_CNT_MASK (0xfff << TEMPSENSE0_TEMP_CNT_SHIFT)
+#define TEMPSENSE0_FINISHED (1 << 2)
+#define TEMPSENSE0_MEASURE_TEMP (1 << 1)
+#define TEMPSENSE0_POWER_DOWN (1 << 0)
+#define MISC0_REFTOP_SELBIASOFF (1 << 3)
+#define TEMPSENSE1_MEASURE_FREQ 0xffff
+
+static int read_cpu_temperature(struct udevice *dev)
+{
+ int temperature;
+ unsigned int reg, n_meas;
+ const struct imx_thermal_plat *pdata = dev_get_platdata(dev);
+ struct anatop_regs *anatop = (struct anatop_regs *)pdata->regs;
+ unsigned int *priv = dev_get_priv(dev);
+ u32 fuse = *priv;
+ int t1, n1;
+ u32 c1, c2;
+ u64 temp64;
+
+ /*
+ * Sensor data layout:
+ * [31:20] - sensor value @ 25C
+ * We use universal formula now and only need sensor value @ 25C
+ * slope = 0.4297157 - (0.0015976 * 25C fuse)
+ */
+ n1 = fuse >> 20;
+ t1 = 25; /* t1 always 25C */
+
+ /*
+ * Derived from linear interpolation:
+ * slope = 0.4297157 - (0.0015976 * 25C fuse)
+ * slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0
+ * (Nmeas - n1) / (Tmeas - t1) = slope
+ * We want to reduce this down to the minimum computation necessary
+ * for each temperature read. Also, we want Tmeas in millicelsius
+ * and we don't want to lose precision from integer division. So...
+ * Tmeas = (Nmeas - n1) / slope + t1
+ * milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1
+ * milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1
+ * Let constant c1 = (-1000 / slope)
+ * milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1
+ * Let constant c2 = n1 *c1 + 1000 * t1
+ * milli_Tmeas = c2 - Nmeas * c1
+ */
+ temp64 = FACTOR0;
+ temp64 *= 1000;
+ do_div(temp64, FACTOR1 * n1 - FACTOR2);
+ c1 = temp64;
+ c2 = n1 * c1 + 1000 * t1;
+
+ /*
+ * now we only use single measure, every time we read
+ * the temperature, we will power on/down anadig thermal
+ * module
+ */
+ writel(TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr);
+ writel(MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
+
+ /* setup measure freq */
+ reg = readl(&anatop->tempsense1);
+ reg &= ~TEMPSENSE1_MEASURE_FREQ;
+ reg |= MEASURE_FREQ;
+ writel(reg, &anatop->tempsense1);
+
+ /* start the measurement process */
+ writel(TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr);
+ writel(TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
+ writel(TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set);
+
+ /* make sure that the latest temp is valid */
+ while ((readl(&anatop->tempsense0) &
+ TEMPSENSE0_FINISHED) == 0)
+ udelay(10000);
+
+ /* read temperature count */
+ reg = readl(&anatop->tempsense0);
+ n_meas = (reg & TEMPSENSE0_TEMP_CNT_MASK)
+ >> TEMPSENSE0_TEMP_CNT_SHIFT;
+ writel(TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
+
+ /* milli_Tmeas = c2 - Nmeas * c1 */
+ temperature = (c2 - n_meas * c1)/1000;
+
+ /* power down anatop thermal sensor */
+ writel(TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set);
+ writel(MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr);
+
+ return temperature;
+}
+
+int imx_thermal_get_temp(struct udevice *dev, int *temp)
+{
+ int cpu_tmp = 0;
+
+ cpu_tmp = read_cpu_temperature(dev);
+ while (cpu_tmp > TEMPERATURE_MIN && cpu_tmp < TEMPERATURE_MAX) {
+ if (cpu_tmp >= TEMPERATURE_HOT) {
+ printf("CPU Temperature is %d C, too hot to boot, waiting...\n",
+ cpu_tmp);
+ udelay(5000000);
+ cpu_tmp = read_cpu_temperature(dev);
+ } else {
+ break;
+ }
+ }
+
+ *temp = cpu_tmp;
+
+ return 0;
+}
+
+static const struct dm_thermal_ops imx_thermal_ops = {
+ .get_temp = imx_thermal_get_temp,
+};
+
+static int imx_thermal_probe(struct udevice *dev)
+{
+ unsigned int fuse = ~0;
+
+ const struct imx_thermal_plat *pdata = dev_get_platdata(dev);
+ unsigned int *priv = dev_get_priv(dev);
+
+ /* Read Temperature calibration data fuse */
+ fuse_read(pdata->fuse_bank, pdata->fuse_word, &fuse);
+
+ /* Check for valid fuse */
+ if (fuse == 0 || fuse == ~0) {
+ printf("CPU: Thermal invalid data, fuse: 0x%x\n", fuse);
+ return -EPERM;
+ } else {
+ printf("CPU: Thermal calibration data: 0x%x\n", fuse);
+ }
+
+ *priv = fuse;
+
+ enable_thermal_clk();
+
+ return 0;
+}
+
+U_BOOT_DRIVER(imx_thermal) = {
+ .name = "imx_thermal",
+ .id = UCLASS_THERMAL,
+ .ops = &imx_thermal_ops,
+ .probe = imx_thermal_probe,
+ .priv_auto_alloc_size = sizeof(unsigned int),
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/thermal/thermal-uclass.c b/drivers/thermal/thermal-uclass.c
new file mode 100644
index 0000000..3bee1a7
--- /dev/null
+++ b/drivers/thermal/thermal-uclass.c
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2014 Freescale Semiconductor, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <thermal.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <linux/list.h>
+
+
+int thermal_get_temp(struct udevice *dev, int *temp)
+{
+ const struct dm_thermal_ops *ops = device_get_ops(dev);
+
+ if (!ops->get_temp)
+ return -ENOSYS;
+
+ return ops->get_temp(dev, temp);
+}
+
+UCLASS_DRIVER(thermal) = {
+ .id = UCLASS_THERMAL,
+ .name = "thermal",
+};
diff --git a/drivers/tpm/tpm_tis_lpc.c b/drivers/tpm/tpm_tis_lpc.c
index eecf18c..d09f8ce 100644
--- a/drivers/tpm/tpm_tis_lpc.c
+++ b/drivers/tpm/tpm_tis_lpc.c
@@ -274,7 +274,7 @@
* changes to zero exactly after the last byte is fed into the
* FIFO.
*/
- count = min(burst, len - offset - 1);
+ count = min((u32)burst, len - offset - 1);
while (count--)
tpm_write_byte(data[offset++],
&lpc_tpm_dev[locality].data);
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index 7bd2562..a4c5606 100644
--- a/drivers/usb/gadget/composite.c
+++ b/drivers/usb/gadget/composite.c
@@ -743,8 +743,8 @@
if (!gadget_is_dualspeed(gadget))
break;
device_qual(cdev);
- value = min(w_length,
- sizeof(struct usb_qualifier_descriptor));
+ value = min_t(int, w_length,
+ sizeof(struct usb_qualifier_descriptor));
break;
case USB_DT_OTHER_SPEED_CONFIG:
if (!gadget_is_dualspeed(gadget))
diff --git a/drivers/usb/gadget/designware_udc.c b/drivers/usb/gadget/designware_udc.c
index 3559400..0db7a3b 100644
--- a/drivers/usb/gadget/designware_udc.c
+++ b/drivers/usb/gadget/designware_udc.c
@@ -269,8 +269,8 @@
UDCDBGA("urb->buffer %p, buffer_length %d, actual_length %d",
urb->buffer, urb->buffer_length, urb->actual_length);
- last = min(urb->actual_length - endpoint->sent,
- endpoint->tx_packetSize);
+ last = min_t(u32, urb->actual_length - endpoint->sent,
+ endpoint->tx_packetSize);
if (last) {
u8 *cp = urb->buffer + endpoint->sent;
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
index efd5c7f..9423555 100644
--- a/drivers/usb/gadget/pxa27x_udc.c
+++ b/drivers/usb/gadget/pxa27x_udc.c
@@ -65,7 +65,8 @@
if (!urb || !urb->actual_length)
return -1;
- n = min(urb->actual_length - endpoint->sent, endpoint->tx_packetSize);
+ n = min_t(unsigned int, urb->actual_length - endpoint->sent,
+ endpoint->tx_packetSize);
if (n <= 0)
return -1;
diff --git a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
index 9c54b46..7e7a2c2 100644
--- a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
+++ b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
@@ -97,8 +97,8 @@
u32 ep_num = ep_index(ep);
buf = req->req.buf + req->req.actual;
- length = min(req->req.length - req->req.actual,
- ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket);
+ length = min_t(u32, req->req.length - req->req.actual,
+ ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket);
ep->len = length;
ep->dma_buf = buf;
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 2a5bbf5..e8142ac 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -503,23 +503,23 @@
case 0:
switch (wValue & 0xff00) {
case 0x0100: /* device descriptor */
- len = min3(txlen, sizeof(root_hub_dev_des), wLength);
+ len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
memcpy(buffer, root_hub_dev_des, len);
break;
case 0x0200: /* configuration descriptor */
- len = min3(txlen, sizeof(root_hub_config_des), wLength);
+ len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
memcpy(buffer, root_hub_config_des, len);
break;
case 0x0300: /* string descriptors */
switch (wValue & 0xff) {
case 0x00:
- len = min3(txlen, sizeof(root_hub_str_index0),
- wLength);
+ len = min3(txlen, (int)sizeof(root_hub_str_index0),
+ (int)wLength);
memcpy(buffer, root_hub_str_index0, len);
break;
case 0x01:
- len = min3(txlen, sizeof(root_hub_str_index1),
- wLength);
+ len = min3(txlen, (int)sizeof(root_hub_str_index1),
+ (int)wLength);
memcpy(buffer, root_hub_str_index1, len);
break;
}
@@ -556,7 +556,7 @@
data[10] = data[9];
}
- len = min3(txlen, data[0], wLength);
+ len = min3(txlen, (int)data[0], (int)wLength);
memcpy(buffer, data, len);
break;
default:
diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
index edd91a8..6fdbf57 100644
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
@@ -85,15 +85,10 @@
}
#endif
-/* Setup the EHCI host controller. */
-static void setup_usb_phy(struct exynos_usb_phy *usb)
+static void exynos5_setup_usb_phy(struct exynos_usb_phy *usb)
{
u32 hsic_ctrl;
- set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
-
- set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
-
clrbits_le32(&usb->usbphyctrl0,
HOST_CTRL0_FSEL_MASK |
HOST_CTRL0_COMMONON_N |
@@ -150,8 +145,34 @@
EHCICTRL_ENAINCR16);
}
-/* Reset the EHCI host controller. */
-static void reset_usb_phy(struct exynos_usb_phy *usb)
+static void exynos4412_setup_usb_phy(struct exynos4412_usb_phy *usb)
+{
+ writel(CLK_24MHZ, &usb->usbphyclk);
+
+ clrbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
+ PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
+ PHYPWR_NORMAL_MASK_PHY0));
+
+ setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
+ udelay(10);
+ clrbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
+}
+
+static void setup_usb_phy(struct exynos_usb_phy *usb)
+{
+ set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
+
+ set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
+
+ if (cpu_is_exynos5())
+ exynos5_setup_usb_phy(usb);
+ else if (cpu_is_exynos4())
+ if (proid_is_exynos4412())
+ exynos4412_setup_usb_phy((struct exynos4412_usb_phy *)
+ usb);
+}
+
+static void exynos5_reset_usb_phy(struct exynos_usb_phy *usb)
{
u32 hsic_ctrl;
@@ -171,6 +192,24 @@
setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
+}
+
+static void exynos4412_reset_usb_phy(struct exynos4412_usb_phy *usb)
+{
+ setbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
+ PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
+ PHYPWR_NORMAL_MASK_PHY0));
+}
+
+/* Reset the EHCI host controller. */
+static void reset_usb_phy(struct exynos_usb_phy *usb)
+{
+ if (cpu_is_exynos5())
+ exynos5_reset_usb_phy(usb);
+ else if (cpu_is_exynos4())
+ if (proid_is_exynos4412())
+ exynos4412_reset_usb_phy((struct exynos4412_usb_phy *)
+ usb);
set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
}
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index c671c72..5520805 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -910,7 +910,7 @@
}
mdelay(1);
- len = min3(srclen, le16_to_cpu(req->length), length);
+ len = min3(srclen, (int)le16_to_cpu(req->length), length);
if (srcptr != NULL && len > 0)
memcpy(buffer, srcptr, len);
else
diff --git a/drivers/usb/host/isp116x-hcd.c b/drivers/usb/host/isp116x-hcd.c
index 46e4cee..0556f32 100644
--- a/drivers/usb/host/isp116x-hcd.c
+++ b/drivers/usb/host/isp116x-hcd.c
@@ -103,12 +103,6 @@
/* ------------------------------------------------------------------------- */
-#define ALIGN(x,a) (((x)+(a)-1UL)&~((a)-1UL))
-#define min_t(type,x,y) \
- ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
-
-/* ------------------------------------------------------------------------- */
-
static int isp116x_reset(struct isp116x *isp116x);
/* --- Debugging functions ------------------------------------------------- */
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index dc0a4e3..97a7ede 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -47,7 +47,7 @@
#include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */
#endif
-#if defined(CONFIG_ARM920T) || \
+#if defined(CONFIG_CPU_ARM920T) || \
defined(CONFIG_S3C24X0) || \
defined(CONFIG_440EP) || \
defined(CONFIG_PCI_OHCI) || \
@@ -65,9 +65,6 @@
#define OHCI_CONTROL_INIT \
(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
-#define min_t(type, x, y) \
- ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
-
#ifdef CONFIG_PCI_OHCI
static struct pci_device_id ohci_pci_ids[] = {
{0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */
diff --git a/drivers/usb/host/ohci-s3c24xx.c b/drivers/usb/host/ohci-s3c24xx.c
index 3c659c6..8bb2275 100644
--- a/drivers/usb/host/ohci-s3c24xx.c
+++ b/drivers/usb/host/ohci-s3c24xx.c
@@ -35,9 +35,6 @@
#define OHCI_CONTROL_INIT \
(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
-#define min_t(type, x, y) \
- ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
-
#undef DEBUG
#ifdef DEBUG
#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c
index 5114544..6f33456 100644
--- a/drivers/usb/host/r8a66597-hcd.c
+++ b/drivers/usb/host/r8a66597-hcd.c
@@ -550,9 +550,6 @@
return -1; /* fail */
}
-/* based on usb_ohci.c */
-#define min_t(type, x, y) \
- ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
/*-------------------------------------------------------------------------*
* Virtual Root Hub
*-------------------------------------------------------------------------*/
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 19c3ec6..b5aade9 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -511,7 +511,7 @@
union xhci_trb *event, int length)
{
udev->act_len = min(length, length -
- EVENT_TRB_LEN(le32_to_cpu(event->trans_event.transfer_len)));
+ (int)EVENT_TRB_LEN(le32_to_cpu(event->trans_event.transfer_len)));
switch (GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len))) {
case COMP_SUCCESS:
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 59dc096..87f2972 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -829,7 +829,7 @@
debug("scrlen = %d\n req->length = %d\n",
srclen, le16_to_cpu(req->length));
- len = min(srclen, le16_to_cpu(req->length));
+ len = min(srclen, (int)le16_to_cpu(req->length));
if (srcptr != NULL && len > 0)
memcpy(buffer, srcptr, len);
diff --git a/drivers/usb/musb/musb_hcd.h b/drivers/usb/musb/musb_hcd.h
index 02b9adc..0c8e75d 100644
--- a/drivers/usb/musb/musb_hcd.h
+++ b/drivers/usb/musb/musb_hcd.h
@@ -37,9 +37,6 @@
((readb(&musbr->power) & MUSB_POWER_HSMODE) \
>> MUSB_POWER_HSMODE_SHIFT)
-#define min_t(type, x, y) \
- ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
-
/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
/* destination of request */
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 14a6781..7301be3 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -39,6 +39,7 @@
obj-$(CONFIG_VIDEO_SED13806) += sed13806.o
obj-$(CONFIG_VIDEO_SM501) += sm501.o
obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
+obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o
obj-$(CONFIG_VIDEO_TEGRA) += tegra.o
obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
obj-$(CONFIG_FORMIKE) += formike.o
diff --git a/drivers/video/ati_radeon_fb.c b/drivers/video/ati_radeon_fb.c
index 38d2eb1..618f5d9 100644
--- a/drivers/video/ati_radeon_fb.c
+++ b/drivers/video/ati_radeon_fb.c
@@ -39,11 +39,6 @@
#define DPRINT(x...) do{}while(0)
#endif
-#ifndef min_t
-#define min_t(type,x,y) \
- ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
-#endif
-
#define MAX_MAPPED_VRAM (2048*2048*4)
#define MIN_MAPPED_VRAM (1024*768*1)
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index a347e13..a653bb4 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -1541,14 +1541,14 @@
#ifdef CONFIG_SPLASH_SCREEN_ALIGN
if (x == BMP_ALIGN_CENTER)
- x = max(0, (VIDEO_VISIBLE_COLS - width) / 2);
+ x = max(0, (int)(VIDEO_VISIBLE_COLS - width) / 2);
else if (x < 0)
- x = max(0, VIDEO_VISIBLE_COLS - width + x + 1);
+ x = max(0, (int)(VIDEO_VISIBLE_COLS - width + x + 1));
if (y == BMP_ALIGN_CENTER)
- y = max(0, (VIDEO_VISIBLE_ROWS - height) / 2);
+ y = max(0, (int)(VIDEO_VISIBLE_ROWS - height) / 2);
else if (y < 0)
- y = max(0, VIDEO_VISIBLE_ROWS - height + y + 1);
+ y = max(0, (int)(VIDEO_VISIBLE_ROWS - height + y + 1));
#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
/*
@@ -1874,14 +1874,14 @@
#ifdef CONFIG_SPLASH_SCREEN_ALIGN
if (x == BMP_ALIGN_CENTER)
- x = max(0, (VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH) / 2);
+ x = max(0, (int)(VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH) / 2);
else if (x < 0)
- x = max(0, VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH + x + 1);
+ x = max(0, (int)(VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH + x + 1));
if (y == BMP_ALIGN_CENTER)
- y = max(0, (VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT) / 2);
+ y = max(0, (int)(VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT) / 2);
else if (y < 0)
- y = max(0, VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT + y + 1);
+ y = max(0, (int)(VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT + y + 1));
#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
dest = (unsigned char *)screen + (y * width + x) * VIDEO_PIXEL_SIZE;
@@ -2028,7 +2028,7 @@
* we need to adjust the logo height
*/
if (video_logo_ypos == BMP_ALIGN_CENTER)
- video_logo_height += max(0, (VIDEO_VISIBLE_ROWS - \
+ video_logo_height += max(0, (int)(VIDEO_VISIBLE_ROWS -
VIDEO_LOGO_HEIGHT) / 2);
else if (video_logo_ypos > 0)
video_logo_height += video_logo_ypos;
diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c
new file mode 100644
index 0000000..d241397
--- /dev/null
+++ b/drivers/video/sunxi_display.c
@@ -0,0 +1,451 @@
+/*
+ * Display driver for Allwinner SoCs.
+ *
+ * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/display.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <fdtdec.h>
+#include <fdt_support.h>
+#include <linux/fb.h>
+#include <video_fb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sunxi_display {
+ GraphicDevice graphic_device;
+ bool enabled;
+} sunxi_display;
+
+static int sunxi_hdmi_hpd_detect(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_hdmi_reg * const hdmi =
+ (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
+
+ /* Set pll3 to 300MHz */
+ clock_set_pll3(300000000);
+
+ /* Set hdmi parent to pll3 */
+ clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
+ CCM_HDMI_CTRL_PLL3);
+
+ /* Set ahb gating to pass */
+#ifdef CONFIG_MACH_SUN6I
+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
+#endif
+ setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
+
+ /* Clock on */
+ setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
+
+ writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
+ writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
+
+ udelay(1000);
+
+ if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
+ return 1;
+
+ /* No need to keep these running */
+ clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
+ clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
+ clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
+#ifdef CONFIG_MACH_SUN6I
+ clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
+#endif
+ clock_set_pll3(0);
+
+ return 0;
+}
+
+/*
+ * This is the entity that mixes and matches the different layers and inputs.
+ * Allwinner calls it the back-end, but i like composer better.
+ */
+static void sunxi_composer_init(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_de_be_reg * const de_be =
+ (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
+ int i;
+
+#ifdef CONFIG_MACH_SUN6I
+ /* Reset off */
+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
+#endif
+
+ /* Clocks on */
+ setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
+ setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
+ clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
+
+ /* Engine bug, clear registers after reset */
+ for (i = 0x0800; i < 0x1000; i += 4)
+ writel(0, SUNXI_DE_BE0_BASE + i);
+
+ setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
+}
+
+static void sunxi_composer_mode_set(struct fb_videomode *mode,
+ unsigned int address)
+{
+ struct sunxi_de_be_reg * const de_be =
+ (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
+
+ writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
+ &de_be->disp_size);
+ writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
+ &de_be->layer0_size);
+ writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
+ writel(address << 3, &de_be->layer0_addr_low32b);
+ writel(address >> 29, &de_be->layer0_addr_high4b);
+ writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
+
+ setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
+}
+
+/*
+ * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
+ */
+static void sunxi_lcdc_pll_set(int dotclock, int *clk_div, int *clk_double)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ int value, n, m, diff;
+ int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
+ int best_double = 0;
+
+ /*
+ * Find the lowest divider resulting in a matching clock, if there
+ * is no match, pick the closest lower clock, as monitors tend to
+ * not sync to higher frequencies.
+ */
+ for (m = 15; m > 0; m--) {
+ n = (m * dotclock) / 3000;
+
+ if ((n >= 9) && (n <= 127)) {
+ value = (3000 * n) / m;
+ diff = dotclock - value;
+ if (diff < best_diff) {
+ best_diff = diff;
+ best_m = m;
+ best_n = n;
+ best_double = 0;
+ }
+ }
+
+ /* These are just duplicates */
+ if (!(m & 1))
+ continue;
+
+ n = (m * dotclock) / 6000;
+ if ((n >= 9) && (n <= 127)) {
+ value = (6000 * n) / m;
+ diff = dotclock - value;
+ if (diff < best_diff) {
+ best_diff = diff;
+ best_m = m;
+ best_n = n;
+ best_double = 1;
+ }
+ }
+ }
+
+ debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
+ dotclock, (best_double + 1) * 3000 * best_n / best_m,
+ best_double + 1, best_n, best_m);
+
+ clock_set_pll3(best_n * 3000000);
+
+ writel(CCM_LCD_CH1_CTRL_GATE |
+ (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X : CCM_LCD_CH1_CTRL_PLL3) |
+ CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
+
+ *clk_div = best_m;
+ *clk_double = best_double;
+}
+
+static void sunxi_lcdc_init(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_lcdc_reg * const lcdc =
+ (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
+
+ /* Reset off */
+#ifdef CONFIG_MACH_SUN6I
+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
+#else
+ setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
+#endif
+
+ /* Clock on */
+ setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
+
+ /* Init lcdc */
+ writel(0, &lcdc->ctrl); /* Disable tcon */
+ writel(0, &lcdc->int0); /* Disable all interrupts */
+
+ /* Disable tcon0 dot clock */
+ clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
+
+ /* Set all io lines to tristate */
+ writel(0xffffffff, &lcdc->tcon0_io_tristate);
+ writel(0xffffffff, &lcdc->tcon1_io_tristate);
+}
+
+static void sunxi_lcdc_mode_set(struct fb_videomode *mode,
+ int *clk_div, int *clk_double)
+{
+ struct sunxi_lcdc_reg * const lcdc =
+ (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
+ int bp, total;
+
+ /* Use tcon1 */
+ clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
+ SUNXI_LCDC_CTRL_IO_MAP_TCON1);
+
+ /* Enabled, 0x1e start delay */
+ writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
+ SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(0x1e), &lcdc->tcon1_ctrl);
+
+ writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
+ &lcdc->tcon1_timing_source);
+ writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
+ &lcdc->tcon1_timing_scale);
+ writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
+ &lcdc->tcon1_timing_out);
+
+ bp = mode->hsync_len + mode->left_margin;
+ total = mode->xres + mode->right_margin + bp;
+ writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
+ SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
+
+ bp = mode->vsync_len + mode->upper_margin;
+ total = mode->yres + mode->lower_margin + bp;
+ writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
+ SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
+
+ writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
+ &lcdc->tcon1_timing_sync);
+
+ sunxi_lcdc_pll_set(mode->pixclock, clk_div, clk_double);
+}
+
+#ifdef CONFIG_MACH_SUN6I
+static void sunxi_drc_init(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* On sun6i the drc must be clocked even when in pass-through mode */
+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
+ clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
+}
+#endif
+
+static void sunxi_hdmi_mode_set(struct fb_videomode *mode,
+ int clk_div, int clk_double)
+{
+ struct sunxi_hdmi_reg * const hdmi =
+ (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
+ int x, y;
+
+ /* Write clear interrupt status bits */
+ writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
+
+ /* Init various registers, select pll3 as clock source */
+ writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
+ writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
+ writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
+ writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
+ writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
+
+ /* Setup clk div and doubler */
+ clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
+ SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
+ if (!clk_double)
+ setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
+
+ /* Setup timing registers */
+ writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
+ &hdmi->video_size);
+
+ x = mode->hsync_len + mode->left_margin;
+ y = mode->vsync_len + mode->upper_margin;
+ writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
+
+ x = mode->right_margin;
+ y = mode->lower_margin;
+ writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
+
+ x = mode->hsync_len;
+ y = mode->vsync_len;
+ writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
+
+ if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
+ setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
+
+ if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
+ setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
+}
+
+static void sunxi_engines_init(void)
+{
+ sunxi_composer_init();
+ sunxi_lcdc_init();
+#ifdef CONFIG_MACH_SUN6I
+ sunxi_drc_init();
+#endif
+}
+
+static void sunxi_mode_set(struct fb_videomode *mode, unsigned int address)
+{
+ struct sunxi_de_be_reg * const de_be =
+ (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
+ struct sunxi_lcdc_reg * const lcdc =
+ (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
+ struct sunxi_hdmi_reg * const hdmi =
+ (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
+ int clk_div, clk_double;
+ int retries = 3;
+
+retry:
+ clrbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
+ clrbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
+ clrbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
+
+ sunxi_composer_mode_set(mode, address);
+ sunxi_lcdc_mode_set(mode, &clk_div, &clk_double);
+ sunxi_hdmi_mode_set(mode, clk_div, clk_double);
+
+ setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
+ setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
+
+ udelay(1000000 / mode->refresh + 500);
+
+ setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
+
+ udelay(1000000 / mode->refresh + 500);
+
+ setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
+
+ udelay(1000000 / mode->refresh + 500);
+
+ /*
+ * Sometimes the display pipeline does not sync up properly, if
+ * this happens the hdmi fifo underrun or overrun bits are set.
+ */
+ if (readl(&hdmi->irq) &
+ (SUNXI_HDMI_IRQ_STATUS_FIFO_UF | SUNXI_HDMI_IRQ_STATUS_FIFO_OF)) {
+ if (retries--)
+ goto retry;
+ printf("HDMI fifo under or overrun\n");
+ }
+}
+
+void *video_hw_init(void)
+{
+ static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
+ /*
+ * Vesa standard 1024x768@60
+ * 65.0 1024 1048 1184 1344 768 771 777 806 -hsync -vsync
+ */
+ struct fb_videomode mode = {
+ .name = "1024x768",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 65000,
+ .left_margin = 160,
+ .right_margin = 24,
+ .upper_margin = 29,
+ .lower_margin = 3,
+ .hsync_len = 136,
+ .vsync_len = 6,
+ .sync = 0,
+ .vmode = 0,
+ .flag = 0,
+ };
+ int ret;
+
+ memset(&sunxi_display, 0, sizeof(struct sunxi_display));
+
+ printf("Reserved %dkB of RAM for Framebuffer.\n",
+ CONFIG_SUNXI_FB_SIZE >> 10);
+ gd->fb_base = gd->ram_top;
+
+ ret = sunxi_hdmi_hpd_detect();
+ if (!ret)
+ return NULL;
+
+ printf("HDMI connected.\n");
+ sunxi_display.enabled = true;
+
+ printf("Setting up a %s console.\n", mode.name);
+ sunxi_engines_init();
+ sunxi_mode_set(&mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
+
+ /*
+ * These are the only members of this structure that are used. All the
+ * others are driver specific. There is nothing to decribe pitch or
+ * stride, but we are lucky with our hw.
+ */
+ graphic_device->frameAdrs = gd->fb_base;
+ graphic_device->gdfIndex = GDF_32BIT_X888RGB;
+ graphic_device->gdfBytesPP = 4;
+ graphic_device->winSizeX = mode.xres;
+ graphic_device->winSizeY = mode.yres;
+
+ return graphic_device;
+}
+
+/*
+ * Simplefb support.
+ */
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
+int sunxi_simplefb_setup(void *blob)
+{
+ static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
+ int offset, ret;
+
+ if (!sunxi_display.enabled)
+ return 0;
+
+ /* Find a framebuffer node, with pipeline == "de_be0-lcd0-hdmi" */
+ offset = fdt_node_offset_by_compatible(blob, -1,
+ "allwinner,simple-framebuffer");
+ while (offset >= 0) {
+ ret = fdt_find_string(blob, offset, "allwinner,pipeline",
+ "de_be0-lcd0-hdmi");
+ if (ret == 0)
+ break;
+ offset = fdt_node_offset_by_compatible(blob, offset,
+ "allwinner,simple-framebuffer");
+ }
+ if (offset < 0) {
+ eprintf("Cannot setup simplefb: node not found\n");
+ return 0; /* Keep older kernels working */
+ }
+
+ ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base,
+ graphic_device->winSizeX, graphic_device->winSizeY,
+ graphic_device->winSizeX * graphic_device->gdfBytesPP,
+ "x8r8g8b8");
+ if (ret)
+ eprintf("Cannot setup simplefb: Error setting properties\n");
+
+ return ret;
+}
+#endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */
diff --git a/fs/ext4/dev.c b/fs/ext4/dev.c
index e0b513a..c77c02c 100644
--- a/fs/ext4/dev.c
+++ b/fs/ext4/dev.c
@@ -73,6 +73,7 @@
debug(" <" LBAFU ", %d, %d>\n", sector, byte_offset, byte_len);
if (byte_offset != 0) {
+ int readlen;
/* read first part which isn't aligned with start of sector */
if (ext4fs_block_dev_desc->
block_read(ext4fs_block_dev_desc->dev,
@@ -81,13 +82,11 @@
printf(" ** ext2fs_devread() read error **\n");
return 0;
}
- memcpy(buf, sec_buf + byte_offset,
- min(ext4fs_block_dev_desc->blksz
- - byte_offset, byte_len));
- buf += min(ext4fs_block_dev_desc->blksz
- - byte_offset, byte_len);
- byte_len -= min(ext4fs_block_dev_desc->blksz
- - byte_offset, byte_len);
+ readlen = min((int)ext4fs_block_dev_desc->blksz - byte_offset,
+ byte_len);
+ memcpy(buf, sec_buf + byte_offset, readlen);
+ buf += readlen;
+ byte_len -= readlen;
sector++;
}
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index cccc06a..cab5465 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -1892,6 +1892,7 @@
{
unsigned int fpos = 0;
int status;
+ loff_t actread;
struct ext2fs_node *diro = (struct ext2fs_node *) dir;
#ifdef DEBUG
@@ -1909,8 +1910,8 @@
status = ext4fs_read_file(diro, fpos,
sizeof(struct ext2_dirent),
- (char *) &dirent);
- if (status < 1)
+ (char *)&dirent, &actread);
+ if (status < 0)
return 0;
if (dirent.namelen != 0) {
@@ -1921,8 +1922,9 @@
status = ext4fs_read_file(diro,
fpos +
sizeof(struct ext2_dirent),
- dirent.namelen, filename);
- if (status < 1)
+ dirent.namelen, filename,
+ &actread);
+ if (status < 0)
return 0;
fdiro = zalloc(sizeof(struct ext2fs_node));
@@ -2004,8 +2006,8 @@
printf("< ? > ");
break;
}
- printf("%10d %s\n",
- __le32_to_cpu(fdiro->inode.size),
+ printf("%10u %s\n",
+ __le32_to_cpu(fdiro->inode.size),
filename);
}
free(fdiro);
@@ -2020,6 +2022,7 @@
char *symlink;
struct ext2fs_node *diro = node;
int status;
+ loff_t actread;
if (!diro->inode_read) {
status = ext4fs_read_inode(diro->data, diro->ino, &diro->inode);
@@ -2036,7 +2039,7 @@
} else {
status = ext4fs_read_file(diro, 0,
__le32_to_cpu(diro->inode.size),
- symlink);
+ symlink, &actread);
if (status == 0) {
free(symlink);
return 0;
@@ -2170,11 +2173,10 @@
return 1;
}
-int ext4fs_open(const char *filename)
+int ext4fs_open(const char *filename, loff_t *len)
{
struct ext2fs_node *fdiro = NULL;
int status;
- int len;
if (ext4fs_root == NULL)
return -1;
@@ -2191,10 +2193,10 @@
if (status == 0)
goto fail;
}
- len = __le32_to_cpu(fdiro->inode.size);
+ *len = __le32_to_cpu(fdiro->inode.size);
ext4fs_file = fdiro;
- return len;
+ return 0;
fail:
ext4fs_free_node(fdiro, &ext4fs_root->diropen);
diff --git a/fs/ext4/ext4_common.h b/fs/ext4/ext4_common.h
index 5fa1719..48fd2ac 100644
--- a/fs/ext4/ext4_common.h
+++ b/fs/ext4/ext4_common.h
@@ -50,8 +50,8 @@
int ext4fs_read_inode(struct ext2_data *data, int ino,
struct ext2_inode *inode);
-int ext4fs_read_file(struct ext2fs_node *node, int pos,
- unsigned int len, char *buf);
+int ext4fs_read_file(struct ext2fs_node *node, loff_t pos, loff_t len,
+ char *buf, loff_t *actread);
int ext4fs_find_file(const char *path, struct ext2fs_node *rootnode,
struct ext2fs_node **foundnode, int expecttype);
int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name,
diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c
index 648a596..f7c52cc 100644
--- a/fs/ext4/ext4_write.c
+++ b/fs/ext4/ext4_write.c
@@ -975,3 +975,35 @@
return -1;
}
+
+int ext4_write_file(const char *filename, void *buf, loff_t offset,
+ loff_t len, loff_t *actwrite)
+{
+ int ret;
+
+ if (offset != 0) {
+ printf("** Cannot support non-zero offset **\n");
+ return -1;
+ }
+
+ /* mount the filesystem */
+ if (!ext4fs_mount(0)) {
+ printf("** Error Bad ext4 partition **\n");
+ goto fail;
+ }
+
+ ret = ext4fs_write(filename, buf, len);
+
+ if (ret) {
+ printf("** Error ext4fs_write() **\n");
+ goto fail;
+ }
+ ext4fs_close();
+
+ return 0;
+
+fail:
+ ext4fs_close();
+
+ return -1;
+}
diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
index cbdc220..943b5bc 100644
--- a/fs/ext4/ext4fs.c
+++ b/fs/ext4/ext4fs.c
@@ -45,8 +45,8 @@
* Optimized read file API : collects and defers contiguous sector
* reads into one potentially more efficient larger sequential read action
*/
-int ext4fs_read_file(struct ext2fs_node *node, int pos,
- unsigned int len, char *buf)
+int ext4fs_read_file(struct ext2fs_node *node, loff_t pos,
+ loff_t len, char *buf, loff_t *actread)
{
struct ext_filesystem *fs = get_fs();
int i;
@@ -150,7 +150,8 @@
previous_block_number = -1;
}
- return len;
+ *actread = len;
+ return 0;
}
int ext4fs_ls(const char *dirname)
@@ -176,23 +177,24 @@
int ext4fs_exists(const char *filename)
{
- int file_len;
+ loff_t file_len;
+ int ret;
- file_len = ext4fs_open(filename);
- return file_len >= 0;
+ ret = ext4fs_open(filename, &file_len);
+ return ret == 0;
}
-int ext4fs_size(const char *filename)
+int ext4fs_size(const char *filename, loff_t *size)
{
- return ext4fs_open(filename);
+ return ext4fs_open(filename, size);
}
-int ext4fs_read(char *buf, unsigned len)
+int ext4fs_read(char *buf, loff_t len, loff_t *actread)
{
if (ext4fs_root == NULL || ext4fs_file == NULL)
return 0;
- return ext4fs_read_file(ext4fs_file, 0, len, buf);
+ return ext4fs_read_file(ext4fs_file, 0, len, buf, actread);
}
int ext4fs_probe(block_dev_desc_t *fs_dev_desc,
@@ -208,18 +210,19 @@
return 0;
}
-int ext4_read_file(const char *filename, void *buf, int offset, int len)
+int ext4_read_file(const char *filename, void *buf, loff_t offset, loff_t len,
+ loff_t *len_read)
{
- int file_len;
- int len_read;
+ loff_t file_len;
+ int ret;
if (offset != 0) {
printf("** Cannot support non-zero offset **\n");
return -1;
}
- file_len = ext4fs_open(filename);
- if (file_len < 0) {
+ ret = ext4fs_open(filename, &file_len);
+ if (ret < 0) {
printf("** File not found %s **\n", filename);
return -1;
}
@@ -227,7 +230,20 @@
if (len == 0)
len = file_len;
- len_read = ext4fs_read(buf, len);
+ return ext4fs_read(buf, len, len_read);
+}
- return len_read;
+int ext4fs_uuid(char *uuid_str)
+{
+ if (ext4fs_root == NULL)
+ return -1;
+
+#ifdef CONFIG_LIB_UUID
+ uuid_bin_to_str((unsigned char *)ext4fs_root->sblock.unique_id,
+ uuid_str, UUID_STR_FORMAT_STD);
+
+ return 0;
+#else
+ return -ENOSYS;
+#endif
}
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 561921f..04a51db 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -317,32 +317,32 @@
/*
* Read at most 'maxsize' bytes from 'pos' in the file associated with 'dentptr'
* into 'buffer'.
- * Return the number of bytes read or -1 on fatal errors.
+ * Update the number of bytes read in *gotsize or return -1 on fatal errors.
*/
__u8 get_contents_vfatname_block[MAX_CLUSTSIZE]
__aligned(ARCH_DMA_MINALIGN);
-static long
-get_contents(fsdata *mydata, dir_entry *dentptr, unsigned long pos,
- __u8 *buffer, unsigned long maxsize)
+static int get_contents(fsdata *mydata, dir_entry *dentptr, loff_t pos,
+ __u8 *buffer, loff_t maxsize, loff_t *gotsize)
{
- unsigned long filesize = FAT2CPU32(dentptr->size), gotsize = 0;
+ loff_t filesize = FAT2CPU32(dentptr->size);
unsigned int bytesperclust = mydata->clust_size * mydata->sect_size;
__u32 curclust = START(dentptr);
__u32 endclust, newclust;
- unsigned long actsize;
+ loff_t actsize;
- debug("Filesize: %ld bytes\n", filesize);
+ *gotsize = 0;
+ debug("Filesize: %llu bytes\n", filesize);
if (pos >= filesize) {
- debug("Read position past EOF: %lu\n", pos);
- return gotsize;
+ debug("Read position past EOF: %llu\n", pos);
+ return 0;
}
if (maxsize > 0 && filesize > pos + maxsize)
filesize = pos + maxsize;
- debug("%ld bytes\n", filesize);
+ debug("%llu bytes\n", filesize);
actsize = bytesperclust;
@@ -352,7 +352,7 @@
if (CHECK_CLUST(curclust, mydata->fatsize)) {
debug("curclust: 0x%x\n", curclust);
debug("Invalid FAT entry\n");
- return gotsize;
+ return 0;
}
actsize += bytesperclust;
}
@@ -364,7 +364,7 @@
/* align to beginning of next cluster if any */
if (pos) {
- actsize = min(filesize, bytesperclust);
+ actsize = min(filesize, (loff_t)bytesperclust);
if (get_cluster(mydata, curclust, get_contents_vfatname_block,
(int)actsize) != 0) {
printf("Error reading cluster\n");
@@ -373,16 +373,16 @@
filesize -= actsize;
actsize -= pos;
memcpy(buffer, get_contents_vfatname_block + pos, actsize);
- gotsize += actsize;
+ *gotsize += actsize;
if (!filesize)
- return gotsize;
+ return 0;
buffer += actsize;
curclust = get_fatent(mydata, curclust);
if (CHECK_CLUST(curclust, mydata->fatsize)) {
debug("curclust: 0x%x\n", curclust);
debug("Invalid FAT entry\n");
- return gotsize;
+ return 0;
}
}
@@ -398,7 +398,7 @@
if (CHECK_CLUST(newclust, mydata->fatsize)) {
debug("curclust: 0x%x\n", newclust);
debug("Invalid FAT entry\n");
- return gotsize;
+ return 0;
}
endclust = newclust;
actsize += bytesperclust;
@@ -410,14 +410,14 @@
printf("Error reading cluster\n");
return -1;
}
- gotsize += actsize;
- return gotsize;
+ *gotsize += actsize;
+ return 0;
getit:
if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) {
printf("Error reading cluster\n");
return -1;
}
- gotsize += (int)actsize;
+ *gotsize += (int)actsize;
filesize -= actsize;
buffer += actsize;
@@ -425,7 +425,7 @@
if (CHECK_CLUST(curclust, mydata->fatsize)) {
debug("curclust: 0x%x\n", curclust);
printf("Invalid FAT entry\n");
- return gotsize;
+ return 0;
}
actsize = bytesperclust;
endclust = curclust;
@@ -633,8 +633,8 @@
}
if (doit) {
if (dirc == ' ') {
- printf(" %8ld %s%c\n",
- (long)FAT2CPU32(dentptr->size),
+ printf(" %8u %s%c\n",
+ FAT2CPU32(dentptr->size),
l_name,
dirc);
} else {
@@ -690,8 +690,8 @@
if (doit) {
if (dirc == ' ') {
- printf(" %8ld %s%c\n",
- (long)FAT2CPU32(dentptr->size),
+ printf(" %8u %s%c\n",
+ FAT2CPU32(dentptr->size),
s_name, dirc);
} else {
printf(" %s%c\n",
@@ -806,9 +806,8 @@
__u8 do_fat_read_at_block[MAX_CLUSTSIZE]
__aligned(ARCH_DMA_MINALIGN);
-long
-do_fat_read_at(const char *filename, unsigned long pos, void *buffer,
- unsigned long maxsize, int dols, int dogetsize)
+int do_fat_read_at(const char *filename, loff_t pos, void *buffer,
+ loff_t maxsize, int dols, int dogetsize, loff_t *size)
{
char fnamecopy[2048];
boot_sector bs;
@@ -821,7 +820,7 @@
__u32 cursect;
int idx, isdir = 0;
int files = 0, dirs = 0;
- long ret = -1;
+ int ret = -1;
int firsttime;
__u32 root_cluster = 0;
int rootdir_size = 0;
@@ -974,8 +973,8 @@
}
if (doit) {
if (dirc == ' ') {
- printf(" %8ld %s%c\n",
- (long)FAT2CPU32(dentptr->size),
+ printf(" %8u %s%c\n",
+ FAT2CPU32(dentptr->size),
l_name,
dirc);
} else {
@@ -1032,8 +1031,8 @@
}
if (doit) {
if (dirc == ' ') {
- printf(" %8ld %s%c\n",
- (long)FAT2CPU32(dentptr->size),
+ printf(" %8u %s%c\n",
+ FAT2CPU32(dentptr->size),
s_name, dirc);
} else {
printf(" %s%c\n",
@@ -1102,7 +1101,7 @@
if (dols == LS_ROOT) {
printf("\n%d file(s), %d dir(s)\n\n",
files, dirs);
- ret = 0;
+ *size = 0;
}
goto exit;
}
@@ -1141,7 +1140,7 @@
if (get_dentfromdir(mydata, startsect, subname, dentptr,
isdir ? 0 : dols) == NULL) {
if (dols && !isdir)
- ret = 0;
+ *size = 0;
goto exit;
}
@@ -1152,21 +1151,23 @@
subname = nextname;
}
- if (dogetsize)
- ret = FAT2CPU32(dentptr->size);
- else
- ret = get_contents(mydata, dentptr, pos, buffer, maxsize);
- debug("Size: %d, got: %ld\n", FAT2CPU32(dentptr->size), ret);
+ if (dogetsize) {
+ *size = FAT2CPU32(dentptr->size);
+ ret = 0;
+ } else {
+ ret = get_contents(mydata, dentptr, pos, buffer, maxsize, size);
+ }
+ debug("Size: %u, got: %llu\n", FAT2CPU32(dentptr->size), *size);
exit:
free(mydata->fatbuf);
return ret;
}
-long
-do_fat_read(const char *filename, void *buffer, unsigned long maxsize, int dols)
+int do_fat_read(const char *filename, void *buffer, loff_t maxsize, int dols,
+ loff_t *actread)
{
- return do_fat_read_at(filename, 0, buffer, maxsize, dols, 0);
+ return do_fat_read_at(filename, 0, buffer, maxsize, dols, 0, actread);
}
int file_fat_detectfs(void)
@@ -1233,44 +1234,55 @@
int file_fat_ls(const char *dir)
{
- return do_fat_read(dir, NULL, 0, LS_YES);
+ loff_t size;
+
+ return do_fat_read(dir, NULL, 0, LS_YES, &size);
}
int fat_exists(const char *filename)
{
- int sz;
- sz = do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1);
- return sz >= 0;
+ int ret;
+ loff_t size;
+
+ ret = do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1, &size);
+ return ret == 0;
}
-int fat_size(const char *filename)
+int fat_size(const char *filename, loff_t *size)
{
- return do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1);
+ return do_fat_read_at(filename, 0, NULL, 0, LS_NO, 1, size);
}
-long file_fat_read_at(const char *filename, unsigned long pos, void *buffer,
- unsigned long maxsize)
+int file_fat_read_at(const char *filename, loff_t pos, void *buffer,
+ loff_t maxsize, loff_t *actread)
{
printf("reading %s\n", filename);
- return do_fat_read_at(filename, pos, buffer, maxsize, LS_NO, 0);
+ return do_fat_read_at(filename, pos, buffer, maxsize, LS_NO, 0,
+ actread);
}
-long file_fat_read(const char *filename, void *buffer, unsigned long maxsize)
+int file_fat_read(const char *filename, void *buffer, int maxsize)
{
- return file_fat_read_at(filename, 0, buffer, maxsize);
+ loff_t actread;
+ int ret;
+
+ ret = file_fat_read_at(filename, 0, buffer, maxsize, &actread);
+ if (ret)
+ return ret;
+ else
+ return actread;
}
-int fat_read_file(const char *filename, void *buf, int offset, int len)
+int fat_read_file(const char *filename, void *buf, loff_t offset, loff_t len,
+ loff_t *actread)
{
- int len_read;
+ int ret;
- len_read = file_fat_read_at(filename, offset, buf, len);
- if (len_read == -1) {
+ ret = file_fat_read_at(filename, offset, buf, len, actread);
+ if (ret)
printf("** Unable to read file %s **\n", filename);
- return -1;
- }
- return len_read;
+ return ret;
}
void fat_close(void)
diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
index 24ed5d3..88dd495 100644
--- a/fs/fat/fat_write.c
+++ b/fs/fat/fat_write.c
@@ -660,24 +660,26 @@
/*
* Write at most 'maxsize' bytes from 'buffer' into
* the file associated with 'dentptr'
- * Return the number of bytes read or -1 on fatal errors.
+ * Update the number of bytes written in *gotsize and return 0
+ * or return -1 on fatal errors.
*/
static int
set_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer,
- unsigned long maxsize)
+ loff_t maxsize, loff_t *gotsize)
{
- unsigned long filesize = FAT2CPU32(dentptr->size), gotsize = 0;
+ loff_t filesize = FAT2CPU32(dentptr->size);
unsigned int bytesperclust = mydata->clust_size * mydata->sect_size;
__u32 curclust = START(dentptr);
__u32 endclust = 0, newclust = 0;
- unsigned long actsize;
+ loff_t actsize;
- debug("Filesize: %ld bytes\n", filesize);
+ *gotsize = 0;
+ debug("Filesize: %llu bytes\n", filesize);
if (maxsize > 0 && filesize > maxsize)
filesize = maxsize;
- debug("%ld bytes\n", filesize);
+ debug("%llu bytes\n", filesize);
actsize = bytesperclust;
endclust = curclust;
@@ -692,7 +694,7 @@
if (CHECK_CLUST(newclust, mydata->fatsize)) {
debug("curclust: 0x%x\n", newclust);
debug("Invalid FAT entry\n");
- return gotsize;
+ return 0;
}
endclust = newclust;
actsize += bytesperclust;
@@ -706,7 +708,7 @@
}
/* set remaining bytes */
- gotsize += (int)actsize;
+ *gotsize += actsize;
filesize -= actsize;
buffer += actsize;
actsize = filesize;
@@ -715,7 +717,7 @@
debug("error: writing cluster\n");
return -1;
}
- gotsize += actsize;
+ *gotsize += actsize;
/* Mark end of file in FAT */
if (mydata->fatsize == 16)
@@ -724,20 +726,20 @@
newclust = 0xfffffff;
set_fatent_value(mydata, endclust, newclust);
- return gotsize;
+ return 0;
getit:
if (set_cluster(mydata, curclust, buffer, (int)actsize) != 0) {
debug("error: writing cluster\n");
return -1;
}
- gotsize += (int)actsize;
+ *gotsize += actsize;
filesize -= actsize;
buffer += actsize;
if (CHECK_CLUST(curclust, mydata->fatsize)) {
debug("curclust: 0x%x\n", curclust);
debug("Invalid FAT entry\n");
- return gotsize;
+ return 0;
}
actsize = bytesperclust;
curclust = endclust = newclust;
@@ -766,7 +768,7 @@
* exceed the size of the block device
* Return -1 when overflow occurs, otherwise return 0
*/
-static int check_overflow(fsdata *mydata, __u32 clustnum, unsigned long size)
+static int check_overflow(fsdata *mydata, __u32 clustnum, loff_t size)
{
__u32 startsect, sect_num;
@@ -923,8 +925,8 @@
return NULL;
}
-static int do_fat_write(const char *filename, void *buffer,
- unsigned long size)
+static int do_fat_write(const char *filename, void *buffer, loff_t size,
+ loff_t *actwrite)
{
dir_entry *dentptr, *retdent;
__u32 startsect;
@@ -936,8 +938,8 @@
int cursect;
int ret = -1, name_len;
char l_filename[VFAT_MAXLEN_BYTES];
- int write_size = size;
+ *actwrite = size;
dir_curclust = 0;
if (read_bootsectandvi(&bs, &volinfo, &mydata->fatsize)) {
@@ -1015,7 +1017,7 @@
ret = check_overflow(mydata, start_cluster, size);
if (ret) {
- printf("Error: %ld overflow\n", size);
+ printf("Error: %llu overflow\n", size);
goto exit;
}
@@ -1025,13 +1027,12 @@
goto exit;
}
- ret = set_contents(mydata, retdent, buffer, size);
+ ret = set_contents(mydata, retdent, buffer, size, actwrite);
if (ret < 0) {
printf("Error: writing contents\n");
goto exit;
}
- write_size = ret;
- debug("attempt to write 0x%x bytes\n", write_size);
+ debug("attempt to write 0x%llx bytes\n", *actwrite);
/* Flush fat buffer */
ret = flush_fat_buffer(mydata);
@@ -1061,7 +1062,7 @@
ret = check_overflow(mydata, start_cluster, size);
if (ret) {
- printf("Error: %ld overflow\n", size);
+ printf("Error: %llu overflow\n", size);
goto exit;
}
@@ -1069,13 +1070,13 @@
fill_dentry(mydata, empty_dentptr, filename,
start_cluster, size, 0x20);
- ret = set_contents(mydata, empty_dentptr, buffer, size);
+ ret = set_contents(mydata, empty_dentptr, buffer, size,
+ actwrite);
if (ret < 0) {
printf("Error: writing contents\n");
goto exit;
}
- write_size = ret;
- debug("attempt to write 0x%x bytes\n", write_size);
+ debug("attempt to write 0x%llx bytes\n", *actwrite);
/* Flush fat buffer */
ret = flush_fat_buffer(mydata);
@@ -1096,11 +1097,17 @@
exit:
free(mydata->fatbuf);
- return ret < 0 ? ret : write_size;
+ return ret;
}
-int file_fat_write(const char *filename, void *buffer, unsigned long maxsize)
+int file_fat_write(const char *filename, void *buffer, loff_t offset,
+ loff_t maxsize, loff_t *actwrite)
{
+ if (offset != 0) {
+ printf("Error: non zero offset is currently not suported.\n");
+ return -1;
+ }
+
printf("writing %s\n", filename);
- return do_fat_write(filename, buffer, maxsize);
+ return do_fat_write(filename, buffer, maxsize, actwrite);
}
diff --git a/fs/fat/file.c b/fs/fat/file.c
index d910c46..8970611 100644
--- a/fs/fat/file.c
+++ b/fs/fat/file.c
@@ -162,8 +162,7 @@
return filesystems[current_filesystem].ls(arg);
}
-long
-file_read(const char *filename, void *buffer, unsigned long maxsize)
+int file_read(const char *filename, void *buffer, int maxsize)
{
char fullpath[1024];
const char *arg;
diff --git a/fs/fs.c b/fs/fs.c
index dd680f3..3da7860 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -15,6 +15,7 @@
*/
#include <config.h>
+#include <errno.h>
#include <common.h>
#include <part.h>
#include <ext4fs.h>
@@ -46,19 +47,21 @@
return 0;
}
-static inline int fs_size_unsupported(const char *filename)
+static inline int fs_size_unsupported(const char *filename, loff_t *size)
{
return -1;
}
static inline int fs_read_unsupported(const char *filename, void *buf,
- int offset, int len)
+ loff_t offset, loff_t len,
+ loff_t *actread)
{
return -1;
}
static inline int fs_write_unsupported(const char *filename, void *buf,
- int offset, int len)
+ loff_t offset, loff_t len,
+ loff_t *actwrite)
{
return -1;
}
@@ -67,6 +70,11 @@
{
}
+static inline int fs_uuid_unsupported(char *uuid_str)
+{
+ return -1;
+}
+
struct fstype_info {
int fstype;
/*
@@ -82,10 +90,13 @@
disk_partition_t *fs_partition);
int (*ls)(const char *dirname);
int (*exists)(const char *filename);
- int (*size)(const char *filename);
- int (*read)(const char *filename, void *buf, int offset, int len);
- int (*write)(const char *filename, void *buf, int offset, int len);
+ int (*size)(const char *filename, loff_t *size);
+ int (*read)(const char *filename, void *buf, loff_t offset,
+ loff_t len, loff_t *actread);
+ int (*write)(const char *filename, void *buf, loff_t offset,
+ loff_t len, loff_t *actwrite);
void (*close)(void);
+ int (*uuid)(char *uuid_str);
};
static struct fstype_info fstypes[] = {
@@ -99,7 +110,12 @@
.exists = fat_exists,
.size = fat_size,
.read = fat_read_file,
+#ifdef CONFIG_FAT_WRITE
+ .write = file_fat_write,
+#else
.write = fs_write_unsupported,
+#endif
+ .uuid = fs_uuid_unsupported,
},
#endif
#ifdef CONFIG_FS_EXT4
@@ -112,7 +128,12 @@
.exists = ext4fs_exists,
.size = ext4fs_size,
.read = ext4_read_file,
+#ifdef CONFIG_CMD_EXT4_WRITE
+ .write = ext4_write_file,
+#else
.write = fs_write_unsupported,
+#endif
+ .uuid = ext4fs_uuid,
},
#endif
#ifdef CONFIG_SANDBOX
@@ -126,6 +147,7 @@
.size = sandbox_fs_size,
.read = fs_read_sandbox,
.write = fs_write_sandbox,
+ .uuid = fs_uuid_unsupported,
},
#endif
{
@@ -138,6 +160,7 @@
.size = fs_size_unsupported,
.read = fs_read_unsupported,
.write = fs_write_unsupported,
+ .uuid = fs_uuid_unsupported,
},
};
@@ -206,6 +229,13 @@
fs_type = FS_TYPE_ANY;
}
+int fs_uuid(char *uuid_str)
+{
+ struct fstype_info *info = fs_get_info(fs_type);
+
+ return info->uuid(uuid_str);
+}
+
int fs_ls(const char *dirname)
{
int ret;
@@ -233,20 +263,21 @@
return ret;
}
-int fs_size(const char *filename)
+int fs_size(const char *filename, loff_t *size)
{
int ret;
struct fstype_info *info = fs_get_info(fs_type);
- ret = info->size(filename);
+ ret = info->size(filename, size);
fs_close();
return ret;
}
-int fs_read(const char *filename, ulong addr, int offset, int len)
+int fs_read(const char *filename, ulong addr, loff_t offset, loff_t len,
+ loff_t *actread)
{
struct fstype_info *info = fs_get_info(fs_type);
void *buf;
@@ -257,11 +288,11 @@
* means read the whole file.
*/
buf = map_sysmem(addr, len);
- ret = info->read(filename, buf, offset, len);
+ ret = info->read(filename, buf, offset, len, actread);
unmap_sysmem(buf);
/* If we requested a specific number of bytes, check we got it */
- if (ret >= 0 && len && ret != len) {
+ if (ret == 0 && len && *actread != len) {
printf("** Unable to read file %s **\n", filename);
ret = -1;
}
@@ -270,17 +301,18 @@
return ret;
}
-int fs_write(const char *filename, ulong addr, int offset, int len)
+int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len,
+ loff_t *actwrite)
{
struct fstype_info *info = fs_get_info(fs_type);
void *buf;
int ret;
buf = map_sysmem(addr, len);
- ret = info->write(filename, buf, offset, len);
+ ret = info->write(filename, buf, offset, len, actwrite);
unmap_sysmem(buf);
- if (ret >= 0 && ret != len) {
+ if (ret < 0 && len != *actwrite) {
printf("** Unable to write file %s **\n", filename);
ret = -1;
}
@@ -292,7 +324,7 @@
int do_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
int fstype)
{
- int size;
+ loff_t size;
if (argc != 4)
return CMD_RET_USAGE;
@@ -300,8 +332,7 @@
if (fs_set_blk_dev(argv[1], argv[2], fstype))
return 1;
- size = fs_size(argv[3]);
- if (size < 0)
+ if (fs_size(argv[3], &size) < 0)
return CMD_RET_FAILURE;
setenv_hex("filesize", size);
@@ -315,9 +346,10 @@
unsigned long addr;
const char *addr_str;
const char *filename;
- unsigned long bytes;
- unsigned long pos;
- int len_read;
+ loff_t bytes;
+ loff_t pos;
+ loff_t len_read;
+ int ret;
unsigned long time;
char *ep;
@@ -359,12 +391,12 @@
pos = 0;
time = get_timer(0);
- len_read = fs_read(filename, addr, pos, bytes);
+ ret = fs_read(filename, addr, pos, bytes, &len_read);
time = get_timer(time);
- if (len_read <= 0)
+ if (ret < 0)
return 1;
- printf("%d bytes read in %lu ms", len_read, time);
+ printf("%llu bytes read in %lu ms", len_read, time);
if (time > 0) {
puts(" (");
print_size(len_read / time * 1000, "/s");
@@ -408,9 +440,10 @@
{
unsigned long addr;
const char *filename;
- unsigned long bytes;
- unsigned long pos;
- int len;
+ loff_t bytes;
+ loff_t pos;
+ loff_t len;
+ int ret;
unsigned long time;
if (argc < 6 || argc > 7)
@@ -419,8 +452,8 @@
if (fs_set_blk_dev(argv[1], argv[2], fstype))
return 1;
- filename = argv[3];
- addr = simple_strtoul(argv[4], NULL, 16);
+ addr = simple_strtoul(argv[3], NULL, 16);
+ filename = argv[4];
bytes = simple_strtoul(argv[5], NULL, 16);
if (argc >= 7)
pos = simple_strtoul(argv[6], NULL, 16);
@@ -428,12 +461,12 @@
pos = 0;
time = get_timer(0);
- len = fs_write(filename, addr, pos, bytes);
+ ret = fs_write(filename, addr, pos, bytes, &len);
time = get_timer(time);
- if (len <= 0)
+ if (ret < 0)
return 1;
- printf("%d bytes written in %lu ms", len, time);
+ printf("%llu bytes written in %lu ms", len, time);
if (time > 0) {
puts(" (");
print_size(len / time * 1000, "/s");
@@ -443,3 +476,28 @@
return 0;
}
+
+int do_fs_uuid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+ int fstype)
+{
+ int ret;
+ char uuid[37];
+ memset(uuid, 0, sizeof(uuid));
+
+ if (argc < 3 || argc > 4)
+ return CMD_RET_USAGE;
+
+ if (fs_set_blk_dev(argv[1], argv[2], fstype))
+ return 1;
+
+ ret = fs_uuid(uuid);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ if (argc == 4)
+ setenv(argv[3], uuid);
+ else
+ printf("%s\n", uuid);
+
+ return CMD_RET_SUCCESS;
+}
diff --git a/fs/sandbox/sandboxfs.c b/fs/sandbox/sandboxfs.c
index ba6402c..a920bc0 100644
--- a/fs/sandbox/sandboxfs.c
+++ b/fs/sandbox/sandboxfs.c
@@ -13,10 +13,10 @@
return 0;
}
-long sandbox_fs_read_at(const char *filename, unsigned long pos,
- void *buffer, unsigned long maxsize)
+int sandbox_fs_read_at(const char *filename, loff_t pos, void *buffer,
+ loff_t maxsize, loff_t *actread)
{
- ssize_t size;
+ loff_t size;
int fd, ret;
fd = os_open(filename, OS_O_RDONLY);
@@ -27,16 +27,31 @@
os_close(fd);
return ret;
}
+ if (!maxsize) {
+ ret = os_get_filesize(filename, &size);
+ if (ret) {
+ os_close(fd);
+ return ret;
+ }
+
+ maxsize = size;
+ }
- if (!maxsize)
- maxsize = os_get_filesize(filename);
+
size = os_read(fd, buffer, maxsize);
os_close(fd);
- return size;
+ if (size < 0) {
+ ret = -1;
+ } else {
+ ret = 0;
+ *actread = size;
+ }
+
+ return ret;
}
-long sandbox_fs_write_at(const char *filename, unsigned long pos,
- void *buffer, unsigned long towrite)
+int sandbox_fs_write_at(const char *filename, loff_t pos, void *buffer,
+ loff_t towrite, loff_t *actwrite)
{
ssize_t size;
int fd, ret;
@@ -52,7 +67,14 @@
size = os_write(fd, buffer, towrite);
os_close(fd);
- return size;
+ if (size == -1) {
+ ret = -1;
+ } else {
+ ret = 0;
+ *actwrite = size;
+ }
+
+ return ret;
}
int sandbox_fs_ls(const char *dirname)
@@ -74,43 +96,42 @@
int sandbox_fs_exists(const char *filename)
{
- ssize_t sz;
+ loff_t size;
+ int ret;
- sz = os_get_filesize(filename);
- return sz >= 0;
+ ret = os_get_filesize(filename, &size);
+ return ret == 0;
}
-int sandbox_fs_size(const char *filename)
+int sandbox_fs_size(const char *filename, loff_t *size)
{
- return os_get_filesize(filename);
+ return os_get_filesize(filename, size);
}
void sandbox_fs_close(void)
{
}
-int fs_read_sandbox(const char *filename, void *buf, int offset, int len)
+int fs_read_sandbox(const char *filename, void *buf, loff_t offset, loff_t len,
+ loff_t *actread)
{
- int len_read;
+ int ret;
- len_read = sandbox_fs_read_at(filename, offset, buf, len);
- if (len_read == -1) {
+ ret = sandbox_fs_read_at(filename, offset, buf, len, actread);
+ if (ret)
printf("** Unable to read file %s **\n", filename);
- return -1;
- }
- return len_read;
+ return ret;
}
-int fs_write_sandbox(const char *filename, void *buf, int offset, int len)
+int fs_write_sandbox(const char *filename, void *buf, loff_t offset,
+ loff_t len, loff_t *actwrite)
{
- int len_written;
+ int ret;
- len_written = sandbox_fs_write_at(filename, offset, buf, len);
- if (len_written == -1) {
+ ret = sandbox_fs_write_at(filename, offset, buf, len, actwrite);
+ if (ret)
printf("** Unable to write file %s **\n", filename);
- return -1;
- }
- return len_written;
+ return ret;
}
diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h
index 0ce2475..c120261 100644
--- a/fs/ubifs/ubifs.h
+++ b/fs/ubifs/ubifs.h
@@ -476,10 +476,6 @@
#define MAX_LFS_FILESIZE 0x7fffffffffffffffUL
#endif
-#define INT_MAX ((int)(~0U>>1))
-#define INT_MIN (-INT_MAX - 1)
-#define LLONG_MAX ((long long)(~0ULL>>1))
-
/*
* These are the fs-independent mount-flags: up to 32 flags are supported
*/
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 74df210..9c5a1e1 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -91,6 +91,7 @@
unsigned long malloc_limit; /* limit address */
unsigned long malloc_ptr; /* current address */
#endif
+ struct udevice *cur_serial_dev; /* current serial device */
struct arch_global_data arch; /* architecture-specific data */
} gd_t;
#endif
@@ -107,5 +108,6 @@
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#define GD_FLG_ENV_READY 0x00080 /* Env. imported into hash table */
#define GD_FLG_SERIAL_READY 0x00100 /* Pre-reloc serial console ready */
+#define GD_FLG_FULL_MALLOC_INIT 0x00200 /* Full malloc() is ready */
#endif /* __ASM_GENERIC_GBL_DATA_H */
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index f81b51a..36a36c6 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -257,6 +257,15 @@
int gpio_lookup_name(const char *name, struct udevice **devp,
unsigned int *offsetp, unsigned int *gpiop);
-int name_to_gpio(const char *name);
+/**
+ * get_gpios() - Turn the values of a list of GPIOs into an integer
+ *
+ * This puts the value of the first GPIO into bit 0, the second into bit 1,
+ * etc. then returns the resulting integer.
+ *
+ * @gpio_list: List of GPIOs to collect
+ * @return resulting integer value
+ */
+unsigned gpio_get_values_as_int(const int *gpio_list);
#endif /* _ASM_GENERIC_GPIO_H_ */
diff --git a/include/common.h b/include/common.h
index ecf7fca..f1ab2cf 100644
--- a/include/common.h
+++ b/include/common.h
@@ -23,6 +23,7 @@
#include <linux/stringify.h>
#include <asm/ptrace.h>
#include <stdarg.h>
+#include <linux/kernel.h>
#if defined(CONFIG_PCI) && defined(CONFIG_4xx)
#include <pci.h>
#endif
@@ -96,15 +97,19 @@
#define _DEBUG 0
#endif
+#ifndef pr_fmt
+#define pr_fmt(fmt) fmt
+#endif
+
/*
* Output a debug text when condition "cond" is met. The "cond" should be
* computed by a preprocessor in the best case, allowing for the best
* optimization.
*/
-#define debug_cond(cond, fmt, args...) \
- do { \
- if (cond) \
- printf(fmt, ##args); \
+#define debug_cond(cond, fmt, args...) \
+ do { \
+ if (cond) \
+ printf(pr_fmt(fmt), ##args); \
} while (0)
#define debug(fmt, args...) \
@@ -126,7 +131,7 @@
__assert_fail(#x, __FILE__, __LINE__, __func__); })
#define error(fmt, args...) do { \
- printf("ERROR: " fmt "\nat %s:%d/%s()\n", \
+ printf("ERROR: " pr_fmt(fmt) "\nat %s:%d/%s()\n", \
##args, __FILE__, __LINE__, __func__); \
} while (0)
@@ -168,58 +173,6 @@
# endif
#endif
-/*
- * General Purpose Utilities
- */
-#define min(X, Y) \
- ({ typeof(X) __x = (X); \
- typeof(Y) __y = (Y); \
- (__x < __y) ? __x : __y; })
-
-#define max(X, Y) \
- ({ typeof(X) __x = (X); \
- typeof(Y) __y = (Y); \
- (__x > __y) ? __x : __y; })
-
-#define min3(X, Y, Z) \
- ({ typeof(X) __x = (X); \
- typeof(Y) __y = (Y); \
- typeof(Z) __z = (Z); \
- __x < __y ? (__x < __z ? __x : __z) : \
- (__y < __z ? __y : __z); })
-
-#define max3(X, Y, Z) \
- ({ typeof(X) __x = (X); \
- typeof(Y) __y = (Y); \
- typeof(Z) __z = (Z); \
- __x > __y ? (__x > __z ? __x : __z) : \
- (__y > __z ? __y : __z); })
-
-/*
- * Return the absolute value of a number.
- *
- * This handles unsigned and signed longs, ints, shorts and chars. For all
- * input types abs() returns a signed long.
- *
- * For 64-bit types, use abs64()
- */
-#define abs(x) ({ \
- long ret; \
- if (sizeof(x) == sizeof(long)) { \
- long __x = (x); \
- ret = (__x < 0) ? -__x : __x; \
- } else { \
- int __x = (x); \
- ret = (__x < 0) ? -__x : __x; \
- } \
- ret; \
- })
-
-#define abs64(x) ({ \
- s64 __x = (x); \
- (__x < 0) ? -__x : __x; \
- })
-
#if defined(CONFIG_ENV_IS_EMBEDDED)
#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
#elif ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \
@@ -230,17 +183,6 @@
#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
#endif
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @ptr: the pointer to the member.
- * @type: the type of the container struct this is embedded in.
- * @member: the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({ \
- const typeof( ((type *)0)->member ) *__mptr = (ptr); \
- (type *)( (char *)__mptr - offsetof(type,member) );})
-
/*
* Function Prototypes
*/
@@ -947,31 +889,7 @@
#error Read section CONFIG_SKIP_LOWLEVEL_INIT in README.
#endif
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
#define ROUND(a,b) (((a) + (b) - 1) & ~((b) - 1))
-#define DIV_ROUND(n,d) (((n) + ((d)/2)) / (d))
-#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
-#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
-
-/*
- * Divide positive or negative dividend by positive divisor and round
- * to closest integer. Result is undefined for negative divisors and
- * for negative dividends if the divisor variable type is unsigned.
- */
-#define DIV_ROUND_CLOSEST(x, divisor)( \
-{ \
- typeof(x) __x = x; \
- typeof(divisor) __d = divisor; \
- (((typeof(x))-1) > 0 || \
- ((typeof(divisor))-1) > 0 || (__x) > 0) ? \
- (((__x) + ((__d) / 2)) / (__d)) : \
- (((__x) - ((__d) / 2)) / (__d)); \
-} \
-)
-
-#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
-#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
/*
* ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture. It
@@ -1053,7 +971,7 @@
* Usage of this macro shall be avoided or used with extreme care!
*/
#define DEFINE_ALIGN_BUFFER(type, name, size, align) \
- static char __##name[roundup(size * sizeof(type), align)] \
+ static char __##name[ALIGN(size * sizeof(type), align)] \
__aligned(align); \
\
static type *name = (type *)__##name
diff --git a/include/config_defaults.h b/include/config_defaults.h
index ad08c1d..4d49315 100644
--- a/include/config_defaults.h
+++ b/include/config_defaults.h
@@ -20,4 +20,10 @@
#define CONFIG_ZLIB 1
#define CONFIG_PARTITIONS 1
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_DM_WARN
+#define CONFIG_DM_DEVICE_REMOVE
+#define CONFIG_DM_STDIO
+#endif
+
#endif
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 695e47b..832c10f 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -387,6 +387,11 @@
#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_PCI_PNP /* do pci plug-and-play */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 1d1f4c0..8ed0f7c 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -685,6 +685,11 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_NETDEV "eth1"
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index ba3da06..6b29add7 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -374,6 +374,49 @@
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "loadaddr=1000000\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off $ubootaddr +$filesize; " \
+ "erase $ubootaddr +$filesize; " \
+ "cp.b $loadaddr $ubootaddr $filesize; " \
+ "protect on $ubootaddr +$filesize; " \
+ "cmp.b $loadaddr $ubootaddr $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=rootfs.ext2.gz.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=p1023rdb.dtb\0" \
+ "othbootargs=ramdisk_size=600000\0" \
+ "bdev=sda1\0" \
"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
+#define CONFIG_HDBOOT \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
#endif /* __CONFIG_H */
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 1d0664d..2178f9d 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -730,7 +730,6 @@
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 2bb86e4..216f34f 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -745,7 +745,6 @@
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 2733358..2f381e7 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -791,7 +791,6 @@
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 400d979..47b3bd5 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -750,7 +750,6 @@
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index e639e1d..48b8dc7 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -533,7 +533,7 @@
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x0) | \
+ FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS3_FTIM3 0x0
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index a97f5fa..94078f5 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -20,8 +20,7 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM920T /* This is an ARM920T Core */
-#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */
#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */
#define CONFIG_VCMA9 /* on a MPL VCMA9 Board */
#define CONFIG_MACH_TYPE MACH_TYPE_MPL_VCMA9 /* Machine type */
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
index a4050f3..120fdc6 100644
--- a/include/configs/a3m071.h
+++ b/include/configs/a3m071.h
@@ -14,6 +14,8 @@
#define CONFIG_MPC5200
#define CONFIG_A3M071 /* A3M071 board */
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h
index cc88ac1..3c67655 100644
--- a/include/configs/a4m072.h
+++ b/include/configs/a4m072.h
@@ -19,6 +19,8 @@
#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
#define CONFIG_A4M072 1 /* ... on A4M072 board */
#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_TEXT_BASE 0xFE000000
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
index 4424c30..403692d 100644
--- a/include/configs/apf27.h
+++ b/include/configs/apf27.h
@@ -18,8 +18,7 @@
/*
* SoC configurations
*/
-#define CONFIG_ARM926EJS /* this is an ARM926EJS CPU */
-#define CONFIG_MX27 /* in a Freescale i.MX27 Chip */
+#define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */
#define CONFIG_MACH_TYPE 1698 /* APF27 */
#define CONFIG_SYS_GENERIC_BOARD
diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h
index b073b97..72469f3 100644
--- a/include/configs/armadillo-800eva.h
+++ b/include/configs/armadillo-800eva.h
@@ -10,7 +10,6 @@
#define __ARMADILLO_800EVA_H
#undef DEBUG
-#define CONFIG_ARMV7
#define CONFIG_R8A7740
#define CONFIG_RMOBILE_BOARD_STRING "Armadillo-800EVA Board\n"
#define CONFIG_SH_GPIO_PFC
diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index f9ee40f..81e8a7c 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -9,6 +9,9 @@
#ifndef __CONFIG_ARNDALE_H
#define __CONFIG_ARNDALE_H
+#define EXYNOS_FDTFILE_SETTING \
+ "fdtfile=exynos5250-arndale.dtb\0"
+
#include "exynos5250-common.h"
/* SD/MMC configuration */
@@ -17,8 +20,6 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CMD_EXT2
-
/* USB */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_EXYNOS
@@ -60,6 +61,4 @@
/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
#define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000
-#define CONFIG_ARMV7_VIRT
-
#endif /* __CONFIG_H */
diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h
index bf09939..1045779 100644
--- a/include/configs/bcm28155_ap.h
+++ b/include/configs/bcm28155_ap.h
@@ -10,8 +10,7 @@
#include <linux/sizes.h>
#include <asm/arch/sysmap.h>
-/* Architecture, CPU, chip, mach, etc */
-#define CONFIG_ARMV7
+/* CPU, chip, mach, etc */
#define CONFIG_KONA
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_GENERIC_BOARD
diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h
index 827844e..fb85c72 100644
--- a/include/configs/bcm_ep_board.h
+++ b/include/configs/bcm_ep_board.h
@@ -9,8 +9,6 @@
#include <asm/arch/configs.h>
-/* Architecture, CPU, chip, etc */
-#define CONFIG_ARMV7
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_GENERIC_BOARD
diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h
index d0828d5..39982ef 100644
--- a/include/configs/bct-brettl2.h
+++ b/include/configs/bct-brettl2.h
@@ -122,8 +122,8 @@
/*
* I2C Settings
*/
-#define CONFIG_BFIN_TWI_I2C 1
-#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
/*
diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h
index 20f6ed1..50e85ca 100644
--- a/include/configs/bf518f-ezbrd.h
+++ b/include/configs/bf518f-ezbrd.h
@@ -134,8 +134,8 @@
/*
* I2C Settings
*/
-#define CONFIG_BFIN_TWI_I2C 1
-#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
/*
diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h
index c33d035..7fc882a 100644
--- a/include/configs/bf526-ezbrd.h
+++ b/include/configs/bf526-ezbrd.h
@@ -131,8 +131,8 @@
/*
* I2C Settings
*/
-#define CONFIG_BFIN_TWI_I2C 1
-#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
/*
diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h
index b497f26..c2958e8 100644
--- a/include/configs/bf527-ad7160-eval.h
+++ b/include/configs/bf527-ad7160-eval.h
@@ -119,8 +119,8 @@
/*
* I2C Settings
*/
-#define CONFIG_BFIN_TWI_I2C 1
-#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
/*
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
index 0bca53f..79e440a 100644
--- a/include/configs/bf527-ezkit.h
+++ b/include/configs/bf527-ezkit.h
@@ -134,8 +134,8 @@
/*
* I2C Settings
*/
-#define CONFIG_BFIN_TWI_I2C 1
-#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
/*
diff --git a/include/configs/bf527-sdp.h b/include/configs/bf527-sdp.h
index 9d43b81..b374ab5 100644
--- a/include/configs/bf527-sdp.h
+++ b/include/configs/bf527-sdp.h
@@ -103,8 +103,8 @@
/*
* I2C Settings
*/
-#define CONFIG_BFIN_TWI_I2C 1
-#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
/*
diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h
index 3bc364c..6df89af 100644
--- a/include/configs/bf537-minotaur.h
+++ b/include/configs/bf537-minotaur.h
@@ -121,8 +121,8 @@
/*
* I2C settings
*/
-#define CONFIG_BFIN_TWI_I2C 1
-#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_SYS_I2C_SLAVE 0
diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h
index ba74a69..4f2b2cb 100644
--- a/include/configs/bf537-pnav.h
+++ b/include/configs/bf537-pnav.h
@@ -142,8 +142,8 @@
/*
* I2C settings
*/
-#define CONFIG_BFIN_TWI_I2C 1
-#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
/*
diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h
index 0b723cf..d01d88f 100644
--- a/include/configs/bf537-srv1.h
+++ b/include/configs/bf537-srv1.h
@@ -120,8 +120,8 @@
/*
* I2C settings
*/
-#define CONFIG_BFIN_TWI_I2C 1
-#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_SYS_I2C_SLAVE 0
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 29f9316..7b5a5a7 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -128,8 +128,8 @@
/*
* I2C Settings
*/
-#define CONFIG_BFIN_TWI_I2C 1
-#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
/*
diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h
index a655282..e60558e 100644
--- a/include/configs/bf538f-ezkit.h
+++ b/include/configs/bf538f-ezkit.h
@@ -126,8 +126,8 @@
/*
* I2C Settings
*/
-#define CONFIG_BFIN_TWI_I2C 1
-#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
/*
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
index da5f029..e71e6d3 100644
--- a/include/configs/bf548-ezkit.h
+++ b/include/configs/bf548-ezkit.h
@@ -134,8 +134,8 @@
/*
* I2C Settings
*/
-#define CONFIG_BFIN_TWI_I2C 1
-#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
/*
diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h
index 12192ff..878009f 100644
--- a/include/configs/bf609-ezkit.h
+++ b/include/configs/bf609-ezkit.h
@@ -81,8 +81,8 @@
#define CONFIG_PHYLIB
/* i2c Settings */
-#define CONFIG_BFIN_TWI_I2C
-#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
/*
* Flash Settings
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 07ec5f2..143d3dd 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -73,7 +73,7 @@
# ifdef CONFIG_SPI_FLASH
# define CONFIG_CMD_SF
# endif
-# if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
+# if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_SOFT)
# define CONFIG_CMD_I2C
# define CONFIG_SOFT_I2C_READ_REPEATED_START
# endif
@@ -301,7 +301,7 @@
/*
* I2C Settings
*/
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
+#if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_SOFT)
# ifndef CONFIG_SYS_I2C_SPEED
# define CONFIG_SYS_I2C_SPEED 50000
# endif
diff --git a/include/configs/br4.h b/include/configs/br4.h
index 3f24008..48cf184 100644
--- a/include/configs/br4.h
+++ b/include/configs/br4.h
@@ -102,8 +102,8 @@
/*
* I2C Settings
*/
-#define CONFIG_BFIN_TWI_I2C
-#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
/*
diff --git a/include/configs/calimain.h b/include/configs/calimain.h
index b27f973..44c947f 100644
--- a/include/configs/calimain.h
+++ b/include/configs/calimain.h
@@ -24,7 +24,6 @@
* SoC Configuration
*/
#define CONFIG_MACH_DAVINCI_CALIMAIN
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h
index 5f30279..f8785db 100644
--- a/include/configs/cam_enc_4xx.h
+++ b/include/configs/cam_enc_4xx.h
@@ -14,7 +14,6 @@
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* SoC Configuration */
-#define CONFIG_ARM926EJS /* arm926ejs CPU */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
#define CONFIG_SOC_DM365
diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
new file mode 100644
index 0000000..8caeca6
--- /dev/null
+++ b/include/configs/chromebook_link.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_CAR_ADDR 0xff7e0000
+#define CONFIG_SYS_CAR_SIZE (128 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (1 << 20)
+#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000
+#define CONFIG_SYS_X86_START16 0xfffff800
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_X86_RESET_VECTOR
+#define CONFIG_NR_DRAM_BANKS 8
+#define CONFIG_X86_MRC_START 0xfffa0000
+#define CONFIG_CACHE_MRC_SIZE_KB 512
+
+#define CONFIG_COREBOOT_SERIAL
+
+#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
+
+/*
+ * These common x86 features are not yet supported, but are added in
+ * follow-on patches in this series. Add undefs here to avoid every patch
+ * having to put things back into x86-common.h
+ */
+#undef CONFIG_VIDEO
+#undef CONFIG_CFB_CONSOLE
+#undef CONFIG_ICH_SPI
+#undef CONFIG_SPI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_SF
+#undef CONFIG_USB_EHCI
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_SCSI
+
+#define CONFIG_PCI_MEM_BUS 0xe0000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x10000000
+
+#define CONFIG_PCI_PREF_BUS 0xd0000000
+#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS
+#define CONFIG_PCI_PREF_SIZE 0x10000000
+
+#define CONFIG_PCI_IO_BUS 0x1000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0xefff
+
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
+ "stdout=vga,serial\0" \
+ "stderr=vga,serial\0"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h
index f5351ad..643c837 100644
--- a/include/configs/cm-bf527.h
+++ b/include/configs/cm-bf527.h
@@ -113,8 +113,8 @@
/*
* I2C Settings
*/
-#define CONFIG_BFIN_TWI_I2C 1
-#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
/*
diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h
index 1729b44..e059568 100644
--- a/include/configs/cm-bf537e.h
+++ b/include/configs/cm-bf537e.h
@@ -122,8 +122,8 @@
/*
* I2C Settings
*/
-#define CONFIG_BFIN_TWI_I2C 1
-#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
/*
diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h
index 272aa74..1f26457 100644
--- a/include/configs/cm-bf537u.h
+++ b/include/configs/cm-bf537u.h
@@ -120,8 +120,8 @@
/*
* I2C Settings
*/
-#define CONFIG_BFIN_TWI_I2C 1
-#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
/*
diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h
index 7f27eda..72eafc5 100644
--- a/include/configs/cm-bf548.h
+++ b/include/configs/cm-bf548.h
@@ -104,8 +104,8 @@
/*
* I2C Settings
*/
-#define CONFIG_BFIN_TWI_I2C 1
-#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
/*
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index fef267f..2581380 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -6,7 +6,6 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <asm/ibmpc.h>
/*
* board/config.h - configuration options, board specific
*/
@@ -14,27 +13,23 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <configs/x86-common.h>
+
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_SYS_COREBOOT
-#define CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_LAST_STAGE_INIT
-#define CONFIG_SYS_VSNPRINTF
-#define CONFIG_ZBOOT_32
-#define CONFIG_PHYSMEM
#define CONFIG_SYS_EARLY_PCI_INIT
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DM
-#define CONFIG_CMD_DM
-#define CONFIG_DM_GPIO
-#define CONFIG_DM_SERIAL
+#define CONFIG_SYS_CAR_ADDR 0x19200000
+#define CONFIG_SYS_CAR_SIZE (16 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_LMB
-#define CONFIG_OF_LIBFDT
+#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
+#define CONFIG_TRACE_EARLY
+#define CONFIG_TRACE_EARLY_ADDR 0x01400000
#define CONFIG_BOOTSTAGE
#define CONFIG_BOOTSTAGE_REPORT
@@ -45,26 +40,6 @@
#define CONFIG_BOOTSTAGE_STASH_SIZE 0x7fc
#define CONFIG_BOOTSTAGE_USER_COUNT 60
-#define CONFIG_LZO
-#define CONFIG_FIT
-#undef CONFIG_ZLIB
-#undef CONFIG_GZIP
-#define CONFIG_SYS_BOOTM_LEN (16 << 20)
-
-/*-----------------------------------------------------------------------
- * Watchdog Configuration
- */
-#undef CONFIG_WATCHDOG
-#undef CONFIG_HW_WATCHDOG
-
-/* SATA AHCI storage */
-
-#define CONFIG_SCSI_AHCI
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_LIBATA
-#define CONFIG_SYS_64BIT_LBA
-#define CONFIG_SATA_INTEL 1
#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
{PCI_VENDOR_ID_INTEL, \
@@ -74,249 +49,27 @@
{PCI_VENDOR_ID_INTEL, \
PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
-/* Generic TPM interfaced through LPC bus */
-#define CONFIG_TPM
-#define CONFIG_TPM_TIS_LPC
-#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000
-
-/*-----------------------------------------------------------------------
- * Real Time Clock Configuration
- */
-#define CONFIG_RTC_MC146818
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
-#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS
-
-/*-----------------------------------------------------------------------
- * Serial Configuration
- */
#define CONFIG_COREBOOT_SERIAL
-#define CONFIG_SYS_NS16550
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
- 9600, 19200, 38400, 115200}
-#define CONFIG_SYS_NS16550_PORT_MAPPED
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
"stdout=vga,serial,cbmem\0" \
"stderr=vga,serial,cbmem\0"
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_CBMEM_CONSOLE
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_COMMAND_HISTORY
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
-
-#define CONFIG_SUPPORT_VFAT
-/************************************************************
- * ATAPI support (experimental)
- ************************************************************/
-#define CONFIG_ATAPI
-
-/************************************************************
- * DISK Partition support
- ************************************************************/
-#define CONFIG_EFI_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION /* Experimental */
-
-#define CONFIG_CMD_PART
-#define CONFIG_CMD_CBFS
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_PARTITION_UUIDS
-
-/*-----------------------------------------------------------------------
- * Video Configuration
- */
-#define CONFIG_VIDEO
#define CONFIG_VIDEO_COREBOOT
-#define CONFIG_VIDEO_SW_CURSOR
-#define VIDEO_FB_16BPP_WORD_SWAP
-#define CONFIG_I8042_KBD
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-/* x86 GPIOs are accessed through a PCI device */
-#define CONFIG_INTEL_ICH6_GPIO
-
-/*-----------------------------------------------------------------------
- * Command line configuration.
- */
-#include <config_cmd_default.h>
+#define CONFIG_NR_DRAM_BANKS 4
#define CONFIG_TRACE
#define CONFIG_CMD_TRACE
#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
-#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
-#define CONFIG_TRACE_EARLY
-#define CONFIG_TRACE_EARLY_ADDR 0x01400000
-
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_ECHO
-#undef CONFIG_CMD_FLASH
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_GPIO
-#define CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#define CONFIG_CMD_IO
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ITEST
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-#define CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_SETGETDCR
-#define CONFIG_CMD_SOURCE
-#define CONFIG_CMD_TIME
-#define CONFIG_CMD_GETTIME
-#define CONFIG_CMD_XIMG
-#define CONFIG_CMD_SCSI
-
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-
-#define CONFIG_CMD_ZBOOT
-#define CONFIG_CMD_ELF
#define CONFIG_BOOTDELAY 2
-#define CONFIG_BOOTARGS \
- "root=/dev/sdb3 init=/sbin/init rootwait ro"
-#define CONFIG_BOOTCOMMAND \
- "ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
-
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 115200
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_CBSIZE 512
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + \
- 16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000
-#define CONFIG_SYS_MEMTEST_END 0x01000000
-#define CONFIG_SYS_LOAD_ADDR 0x20000000
-
-/*-----------------------------------------------------------------------
- * SDRAM Configuration
- */
-#define CONFIG_NR_DRAM_BANKS 4
-
-/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
-#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
-#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
-#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
-#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
-
-/*-----------------------------------------------------------------------
- * CPU Features
- */
-
-#define CONFIG_SYS_X86_TSC_TIMER
-#define CONFIG_SYS_PCAT_INTERRUPTS
-#define CONFIG_SYS_PCAT_TIMER
-#define CONFIG_SYS_NUM_IRQS 16
-
-/*-----------------------------------------------------------------------
- * Memory organization:
- * 32kB Stack
- * 16kB Cache-As-RAM @ 0x19200000
- * 256kB Monitor
- * (128kB + Environment Sector Size) malloc pool
- */
-#define CONFIG_SYS_STACK_SIZE (32 * 1024)
-#define CONFIG_SYS_CAR_ADDR 0x19200000
-#define CONFIG_SYS_CAR_SIZE (16 * 1024)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (0x20000 + 128 * 1024)
-#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/*-----------------------------------------------------------------------
- * FLASH configuration
- */
-#define CONFIG_ICH_SPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_MACRONIX
-#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_SPI_FLASH_GIGADEVICE
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SF_TEST
-#define CONFIG_CMD_SPI
-#define CONFIG_SPI
-
-/*-----------------------------------------------------------------------
- * Environment configuration
- */
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE 0x01000
-
-/*-----------------------------------------------------------------------
- * PCI configuration
- */
-#define CONFIG_PCI
#define CONFIG_CROS_EC
#define CONFIG_CROS_EC_LPC
#define CONFIG_CMD_CROS_EC
#define CONFIG_ARCH_EARLY_INIT_R
-/*-----------------------------------------------------------------------
- * USB configuration
- */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_PCI
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_KEYBOARD
-#define CONFIG_SYS_USB_EVENT_POLL
-
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
-#define CONFIG_USB_ETHER_SMSC95XX
-#define CONFIG_TFTP_TSIZE
-#define CONFIG_CMD_DHCP
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-#define CONFIG_CMD_USB
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_STD_DEVICES_SETTINGS
-
#endif /* __CONFIG_H */
diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h
index ce52101..8c7d97a 100644
--- a/include/configs/cpuat91.h
+++ b/include/configs/cpuat91.h
@@ -26,7 +26,6 @@
#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
-#define CONFIG_ARM920T
#define CONFIG_AT91RM9200
#define CONFIG_CPUAT91
#define USE_920T_MMU
diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h
index 2717195..0bdcef7 100644
--- a/include/configs/da830evm.h
+++ b/include/configs/da830evm.h
@@ -21,7 +21,6 @@
* SoC Configuration
*/
#define CONFIG_MACH_DAVINCI_DA830_EVM
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA830 /* TI DA830 SoC */
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 5f85755..e5f8afe 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -25,7 +25,6 @@
* SoC Configuration
*/
#define CONFIG_MACH_DAVINCI_DA850_EVM
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h
index c2e187e..16b901b 100644
--- a/include/configs/davinci_dm355evm.h
+++ b/include/configs/davinci_dm355evm.h
@@ -15,7 +15,6 @@
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* SoC Configuration */
-#define CONFIG_ARM926EJS /* arm926ejs CPU */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
#define CONFIG_SOC_DM355
diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h
index 5188fdf..4eed722 100644
--- a/include/configs/davinci_dm355leopard.h
+++ b/include/configs/davinci_dm355leopard.h
@@ -14,7 +14,6 @@
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* SoC Configuration */
-#define CONFIG_ARM926EJS /* arm926ejs CPU */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
#define CONFIG_SOC_DM355 /* DM355 based board */
diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h
index c4fccfd..c50c059 100644
--- a/include/configs/davinci_dm365evm.h
+++ b/include/configs/davinci_dm365evm.h
@@ -15,7 +15,6 @@
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* SoC Configuration */
-#define CONFIG_ARM926EJS /* arm926ejs CPU */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
#define CONFIG_SOC_DM365
diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h
index b1b18ad..2c5a837 100644
--- a/include/configs/davinci_dm6467evm.h
+++ b/include/configs/davinci_dm6467evm.h
@@ -15,7 +15,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
/* SoC Configuration */
-#define CONFIG_ARM926EJS /* arm926ejs CPU */
/* Clock rates detection */
#ifndef __ASSEMBLY__
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index 9b3d0fe..2467f70 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -41,7 +41,6 @@
/*===================*/
/* SoC Configuration */
/*===================*/
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SOC_DM644X
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index 96c8fe2..2505465 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -19,7 +19,6 @@
/*===================*/
/* SoC Configuration */
/*===================*/
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SOC_DM644X
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
index 6e07cce..e773835 100644
--- a/include/configs/davinci_sffsdr.h
+++ b/include/configs/davinci_sffsdr.h
@@ -16,7 +16,6 @@
#define CONFIG_SYS_USE_NAND
#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */
/* SoC Configuration */
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SOC_DM644X
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index cd23aaca..dae37cd 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -43,7 +43,6 @@
/*===================*/
/* SoC Configuration */
/*===================*/
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SOC_DM644X
diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h
index af0d602..a9cfc10 100644
--- a/include/configs/dlvision.h
+++ b/include/configs/dlvision.h
@@ -35,6 +35,7 @@
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
@@ -59,8 +60,14 @@
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DTT
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_DIAG
#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_IRQ
+#undef CONFIG_CMD_NFS
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index 1d50a37..ae89368 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -28,7 +28,6 @@
* SoC Configuration
*/
#define CONFIG_MACH_DAVINCI_DA850_EVM
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
index 47a8420..a82e8bc 100644
--- a/include/configs/edb93xx.h
+++ b/include/configs/edb93xx.h
@@ -85,8 +85,7 @@
#endif
/* High-level configuration options */
-#define CONFIG_ARM920T 1 /* This is an ARM920T core... */
-#define CONFIG_EP93XX 1 /* in a Cirrus Logic 93xx SoC */
+#define CONFIG_EP93XX 1 /* This is a Cirrus Logic 93xx SoC */
#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */
#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index 1df4fc1..70a698a 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -23,7 +23,6 @@
*/
#define CONFIG_MARVELL 1
-#define CONFIG_ARM926EJS 1 /* Basic Architecture */
#define CONFIG_FEROCEON 1 /* CPU Core subversion */
#define CONFIG_88F5182 1 /* SOC Name */
#define CONFIG_MACH_EDMINIV2 1 /* Machine type */
diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h
index 30ca95f..cdea4a8 100644
--- a/include/configs/enbw_cmc.h
+++ b/include/configs/enbw_cmc.h
@@ -25,7 +25,6 @@
/*
* SoC Configuration
*/
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
index b258cb9..1f3ee55 100644
--- a/include/configs/exynos-common.h
+++ b/include/configs/exynos-common.h
@@ -30,9 +30,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
-/* Enable fdt support */
-#define CONFIG_OF_LIBFDT
-
/* Keep L2 Cache Disabled */
#define CONFIG_CMD_CACHE
@@ -42,7 +39,6 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_EDITING
#define CONFIG_ENV_OVERWRITE
/* Size of malloc() pool before and after relocation */
@@ -61,7 +57,6 @@
#define CONFIG_EXYNOS_DWMMC
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK
/* PWM */
@@ -71,22 +66,16 @@
#include <config_cmd_default.h>
#define CONFIG_CMD_MMC
-#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
#define CONFIG_CMD_PART
#define CONFIG_PARTITION_UUIDS
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
@@ -96,4 +85,6 @@
#define CONFIG_SYS_NO_FLASH
#undef CONFIG_CMD_IMLS
+#include <config_distro_defaults.h>
+
#endif /* __CONFIG_H */
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index ba591e7..8f9b780 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -47,17 +47,6 @@
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_CONSOLE_MUX
-#define EXYNOS_DEVICE_SETTINGS \
- "stdin=serial\0" \
- "stdout=serial\0" \
- "stderr=serial\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- EXYNOS_DEVICE_SETTINGS
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_NET
#define CONFIG_CMD_HASH
/* Thermal Management Unit */
@@ -174,12 +163,6 @@
#define CONFIG_ENV_SROM_BANK 1
#endif /*CONFIG_CMD_NET*/
-/* Enable PXE Support */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_PXE
-#define CONFIG_MENU
-#endif
-
/* SHA hashing */
#define CONFIG_CMD_HASH
#define CONFIG_HASH_VERIFY
@@ -189,8 +172,6 @@
/* Enable Time Command */
#define CONFIG_CMD_TIME
-#define CONFIG_CMD_BOOTZ
-
#define CONFIG_CMD_GPIO
/* USB boot mode */
@@ -203,4 +184,41 @@
#define CONFIG_FIT
#define CONFIG_FIT_BEST_MATCH
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#ifndef MEM_LAYOUT_ENV_SETTINGS
+/* 2GB RAM, bootm size of 256M, load scripts after that */
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "bootm_size=0x10000000\0" \
+ "kernel_addr_r=0x42000000\0" \
+ "fdt_addr_r=0x43000000\0" \
+ "ramdisk_addr_r=0x43300000\0" \
+ "scriptaddr=0x50000000\0" \
+ "pxefile_addr_r=0x51000000\0"
+#endif
+
+#ifndef EXYNOS_DEVICE_SETTINGS
+#define EXYNOS_DEVICE_SETTINGS \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+#endif
+
+#ifndef EXYNOS_FDTFILE_SETTING
+#define EXYNOS_FDTFILE_SETTING
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ EXYNOS_DEVICE_SETTINGS \
+ EXYNOS_FDTFILE_SETTING \
+ MEM_LAYOUT_ENV_SETTINGS \
+ BOOTENV
+
#endif /* __CONFIG_EXYNOS5_COMMON_H */
diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h
index 66547fa..9cef0b0 100644
--- a/include/configs/exynos5-dt-common.h
+++ b/include/configs/exynos5-dt-common.h
@@ -9,6 +9,13 @@
#ifndef __CONFIG_EXYNOS5_DT_COMMON_H
#define __CONFIG_EXYNOS5_DT_COMMON_H
+/* Console configuration */
+#undef EXYNOS_DEVICE_SETTINGS
+#define EXYNOS_DEVICE_SETTINGS \
+ "stdin=serial,cros-ec-keyb\0" \
+ "stdout=serial,lcd\0" \
+ "stderr=serial,lcd\0"
+
#include "exynos5-common.h"
/* PMIC */
@@ -22,14 +29,4 @@
#define CONFIG_CMD_CROS_EC
#define CONFIG_KEYBOARD
-/* Console configuration */
-#undef EXYNOS_DEVICE_SETTINGS
-#define EXYNOS_DEVICE_SETTINGS \
- "stdin=serial,cros-ec-keyb\0" \
- "stdout=serial,lcd\0" \
- "stderr=serial,lcd\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- EXYNOS_DEVICE_SETTINGS
-
#endif
diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h
index 713614f..a0107e8 100644
--- a/include/configs/exynos5250-common.h
+++ b/include/configs/exynos5250-common.h
@@ -29,8 +29,6 @@
#define CONFIG_SPL_TEXT_BASE 0x02023400
-#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
-
#define CONFIG_IRAM_STACK 0x02050000
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h
index b0f940c..ef6e155 100644
--- a/include/configs/exynos5420-common.h
+++ b/include/configs/exynos5420-common.h
@@ -10,6 +10,8 @@
#define __CONFIG_EXYNOS5420_H
#define CONFIG_EXYNOS5420
+/* A variant of Exynos5420 (Exynos5 Family) */
+#define CONFIG_EXYNOS5800
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SPI_FLASH
@@ -38,14 +40,13 @@
#define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024)
-#define CONFIG_DEVICE_TREE_LIST "exynos5420-peach-pit exynos5420-smdk5420"
+#define CONFIG_DEVICE_TREE_LIST "exynos5800-peach-pi" \
+ "exynos5420-peach-pit exynos5420-smdk5420"
#define CONFIG_MAX_I2C_NUM 11
#define CONFIG_BOARD_REV_GPIO_COUNT 2
-#define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000"
-
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
/*
@@ -54,10 +55,6 @@
*/
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800)
-/* DRAM Memory Banks */
-#define CONFIG_NR_DRAM_BANKS 7
-#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
-
/* Miscellaneous configurable options */
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index 8417567..bf02829 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -16,7 +16,6 @@
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
#define CONFIG_MX35
#define CONFIG_SYS_DCACHE_OFF
diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h
index 8188c7b..1d78e72 100644
--- a/include/configs/hawkboard.h
+++ b/include/configs/hawkboard.h
@@ -20,7 +20,6 @@
* SoC Configuration
*/
#define CONFIG_MACH_DAVINCI_HAWK
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
new file mode 100644
index 0000000..e7df9ad
--- /dev/null
+++ b/include/configs/hrcon.h
@@ -0,0 +1,614 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 family */
+#define CONFIG_MPC83xx 1 /* MPC83xx family */
+#define CONFIG_MPC830x 1 /* MPC830x family */
+#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
+#define CONFIG_HRCON 1 /* HRCON board specific */
+
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
+#define CONFIG_IDENT_STRING " hrcon 0.01"
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_LAST_STAGE_INIT
+
+/* new uImage format support */
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+
+#define CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_CMD_FPGAD
+#define CONFIG_CMD_IOLOOP
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
+#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66.66MHz, then
+ * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
+ * We choose the A type silicon as default, so the core is 400Mhz.
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+ HRCWL_DDR_TO_SCB_CLK_2X1 |\
+ HRCWL_SVCOD_DIV_2 |\
+ HRCWL_CSB_TO_CLKIN_4X1 |\
+ HRCWL_CORE_TO_CSB_3X1)
+/*
+ * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
+ * in 8308's HRCWH according to the manual, but original Freescale's
+ * code has them and I've expirienced some problems using the board
+ * with BDI3000 attached when I've tried to set these bits to zero
+ * (UART doesn't work after the 'reset run' command).
+ */
+#define CONFIG_SYS_HRCW_HIGH (\
+ HRCWH_PCI_HOST |\
+ HRCWH_PCI1_ARBITER_ENABLE |\
+ HRCWH_CORE_ENABLE |\
+ HRCWH_FROM_0XFFF00100 |\
+ HRCWH_BOOTSEQ_DISABLE |\
+ HRCWH_SW_WATCHDOG_DISABLE |\
+ HRCWH_ROM_LOC_LOCAL_16BIT |\
+ HRCWH_RL_EXT_LEGACY |\
+ HRCWH_TSEC1M_IN_RGMII |\
+ HRCWH_TSEC2M_IN_RGMII |\
+ HRCWH_BIG_ENDIAN)
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRH (\
+ SICRH_ESDHC_A_SD |\
+ SICRH_ESDHC_B_SD |\
+ SICRH_ESDHC_C_SD |\
+ SICRH_GPIO_A_GPIO |\
+ SICRH_GPIO_B_GPIO |\
+ SICRH_IEEE1588_A_GPIO |\
+ SICRH_USB |\
+ SICRH_GTM_GPIO |\
+ SICRH_IEEE1588_B_GPIO |\
+ SICRH_ETSEC2_GPIO |\
+ SICRH_GPIOSEL_1 |\
+ SICRH_TMROBI_V3P3 |\
+ SICRH_TSOBI1_V2P5 |\
+ SICRH_TSOBI2_V2P5) /* 0x0037f103 */
+#define CONFIG_SYS_SICRL (\
+ SICRL_SPI_PF0 |\
+ SICRL_UART_PF0 |\
+ SICRL_IRQ_PF0 |\
+ SICRL_I2C2_PF0 |\
+ SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR 0xE0000000
+
+/*
+ * SERDES
+ */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1 0xe3000
+
+/*
+ * Arbiter Setup
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
+#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
+#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
+ | DDRCDR_PZ_LOZ \
+ | DDRCDR_NZ_LOZ \
+ | DDRCDR_ODT \
+ | DDRCDR_Q_DRN)
+ /* 0x7b880001 */
+/*
+ * Manually set up DDR parameters
+ * consist of one chip NT5TU64M16HG from NANYA
+ */
+
+#define CONFIG_SYS_DDR_SIZE 128 /* MB */
+
+#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
+ | CSCONFIG_ODT_RD_NEVER \
+ | CSCONFIG_ODT_WR_ONLY_CURRENT \
+ | CSCONFIG_BANK_BIT_3 \
+ | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+ /* 0x80010102 */
+#define CONFIG_SYS_DDR_TIMING_3 0
+#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
+ | (0 << TIMING_CFG0_WRT_SHIFT) \
+ | (0 << TIMING_CFG0_RRT_SHIFT) \
+ | (0 << TIMING_CFG0_WWT_SHIFT) \
+ | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+ | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+ /* 0x00260802 */
+#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+ | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+ | (7 << TIMING_CFG1_CASLAT_SHIFT) \
+ | (9 << TIMING_CFG1_REFREC_SHIFT) \
+ | (2 << TIMING_CFG1_WRREC_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+ | (2 << TIMING_CFG1_WRTORD_SHIFT))
+ /* 0x26279222 */
+#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
+ | (4 << TIMING_CFG2_CPO_SHIFT) \
+ | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+ | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+ | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+ | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+ | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
+ /* 0x021848c5 */
+#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
+ | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+ /* 0x08240100 */
+#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_DBW_16)
+ /* 0x43100000 */
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
+ | (0x0242 << SDRAM_MODE_SD_SHIFT))
+ /* ODT 150ohm CL=4, AL=0 on SDRAM */
+#define CONFIG_SYS_DDR_MODE2 0x00000000
+
+/*
+ * Memory test
+ */
+#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END 0x07f00000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
+#define CONFIG_SYS_LBC_LBCR 0x00040000
+
+/*
+ * FLASH on the Local Bus
+ */
+#if 1
+#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_FLASH_LEGACY_512Kx16
+#else
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
+
+/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
+
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | BR_PS_16 /* 16 bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+ | OR_UPM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 135
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+/*
+ * FPGA
+ */
+#define CONFIG_SYS_FPGA0_BASE 0xE0600000
+#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
+
+/* Window base at FPGA base */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
+
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
+ | BR_PS_16 /* 16 bit port */ \
+ | BR_MS_GPCM /* MSEL = GPCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
+ | OR_UPM_XAM \
+ | OR_GPCM_CSNT \
+ | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS \
+ | OR_GPCM_SCY_15 \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET)
+
+#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
+#define CONFIG_SYS_FPGA_DONE(k) 0x0010
+
+#define CONFIG_SYS_FPGA_COUNT 1
+
+#define CONFIG_SYS_MCLINK_MAX 3
+
+#define CONFIG_SYS_FPGA_PTR \
+ { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+
+#define CONFIG_PCA953X /* NXP PCA9554 */
+#define CONFIG_PCA9698 /* NXP PCA9698 */
+
+#define CONFIG_SYS_I2C_IHS
+#define CONFIG_SYS_I2C_IHS_CH0
+#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
+#define CONFIG_SYS_I2C_IHS_CH1
+#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
+#define CONFIG_SYS_I2C_IHS_CH2
+#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
+#define CONFIG_SYS_I2C_IHS_CH3
+#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C_SOFT_SPEED 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
+#define I2C_SOFT_DECLARATIONS2
+#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
+#define I2C_SOFT_DECLARATIONS3
+#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
+#define I2C_SOFT_DECLARATIONS4
+#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
+
+#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
+#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
+#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
+
+#ifndef __ASSEMBLY__
+void fpga_gpio_set(unsigned int bus, int pin);
+void fpga_gpio_clear(unsigned int bus, int pin);
+int fpga_gpio_get(unsigned int bus, int pin);
+#endif
+
+#define I2C_ACTIVE { }
+#define I2C_TRISTATE { }
+#define I2C_READ \
+ (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
+#define I2C_SDA(bit) \
+ do { \
+ if (bit) \
+ fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
+ else \
+ fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
+ } while (0)
+#define I2C_SCL(bit) \
+ do { \
+ if (bit) \
+ fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
+ else \
+ fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
+ } while (0)
+#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
+
+/*
+ * Software (bit-bang) MII driver configuration
+ */
+#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
+#define CONFIG_BITBANGMII_MULTI
+
+/*
+ * OSD Setup
+ */
+#define CONFIG_SYS_OSD_SCREENS 1
+#define CONFIG_SYS_DP501_DIFFERENTIAL
+#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCIE1_BASE 0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
+#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
+#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
+
+/* enable PCIE clock */
+#define CONFIG_SYS_SCCR_PCIEXP1CM 1
+
+#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCIE
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
+#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET /* TSEC ethernet support */
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME "eTSEC0"
+#define TSEC1_PHY_ADDR 1
+#define TSEC1_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+
+/* Options are: eTSEC[0-1] */
+#define CONFIG_ETHPRIME "eTSEC0"
+
+/*
+ * Environment
+ */
+#if 1
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+
+#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE | \
+ HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+#define CONFIG_SYS_HID2 HID2_HBE
+
+/*
+ * MMU Setup
+ */
+
+/* DDR: cache cacheable */
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
+
+/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
+ BATU_VP)
+#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
+ BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
+ BATL_CACHEINHIBIT | \
+ BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
+ BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
+
+#define CONFIG_HOSTNAME hrcon
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+
+#define CONFIG_PREBOOT /* enable preboot variable */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyS1\0" \
+ "u-boot=u-boot.bin\0" \
+ "kernel_addr=1000000\0" \
+ "fdt_addr=C00000\0" \
+ "fdtfile=hrcon.dtb\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
+ " +${filesize};cp.b ${fileaddr} " \
+ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
+ "upd=run load update\0" \
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp ${kernel_addr} $bootfile;" \
+ "tftp ${fdt_addr} $fdtfile;" \
+ "bootm ${kernel_addr} - ${fdt_addr}"
+
+#define CONFIG_MMCBOOTCOMMAND \
+ "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
+ "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
+ "bootm ${kernel_addr} - ${fdt_addr}"
+
+#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
+
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index 3e55247..f084834 100644
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -484,7 +484,6 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ sizeof(CONFIG_SYS_PROMPT)+16)
diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
index 9c25efe..386dbd8 100644
--- a/include/configs/imx27lite-common.h
+++ b/include/configs/imx27lite-common.h
@@ -13,7 +13,6 @@
/*
* SoC Configuration
*/
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_MX27
#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 8428d84..0f22032 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -15,8 +15,7 @@
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
-#define CONFIG_MX31 1 /* in a mx31 */
+#define CONFIG_MX31 1 /* This is a mx31 */
#define CONFIG_MX31_CLK32 32000
#define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index ffb67c2..4195fa3 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -15,8 +15,7 @@
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
-#define CONFIG_MX31 /* in a mx31 */
+#define CONFIG_MX31 /* This is a mx31 */
#define CONFIG_MX31_CLK32 32000
#define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h
index 98e819b..310d5e2 100644
--- a/include/configs/ipam390.h
+++ b/include/configs/ipam390.h
@@ -25,7 +25,6 @@
* SoC Configuration
*/
#define CONFIG_MACH_DAVINCI_DA850_EVM
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h
index 759e112..8175621 100644
--- a/include/configs/jadecpu.h
+++ b/include/configs/jadecpu.h
@@ -14,7 +14,6 @@
#define CONFIG_MB86R0x_IOCLK get_bus_freq(0)
#define CONFIG_SYS_TEXT_BASE 0x10000000
-#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_USE_ARCH_MEMSET
diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h
index dd5050f..42280ca 100644
--- a/include/configs/ks2_evm.h
+++ b/include/configs/ks2_evm.h
@@ -20,7 +20,6 @@
#define CONFIG_SYS_THUMB_BUILD
/* SoC Configuration */
-#define CONFIG_ARMV7
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SYS_TEXT_BASE 0x0c001000
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index bb9fbed..48e10ec 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -369,7 +369,6 @@
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE \
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index a5d2976..3eac7ee 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -261,7 +261,6 @@
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE \
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index 51b1a14..0f4bd91 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -12,8 +12,7 @@
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
-#define CONFIG_MX31 1 /* in a mx31 */
+#define CONFIG_MX31 1 /* This is a mx31 */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index bc4583b..2a3e53c 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -17,8 +17,7 @@
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
-#define CONFIG_MX31 /* in a mx31 */
+#define CONFIG_MX31 /* This is a mx31 */
#define CONFIG_SYS_GENERIC_BOARD
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index ab48144..a145f08 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -16,7 +16,6 @@
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
#define CONFIG_MX35
#define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h
index 3f1c88e..51042ca 100644
--- a/include/configs/mx6qsabreauto.h
+++ b/include/configs/mx6qsabreauto.h
@@ -37,6 +37,16 @@
#include "mx6sabre_common.h"
+#undef CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
+#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
#define CONFIG_SYS_FSL_USDHC_NUM 2
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 0
@@ -64,4 +74,10 @@
#define CONFIG_APBH_DMA_BURST
#define CONFIG_APBH_DMA_BURST8
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
#endif /* __MX6QSABREAUTO_CONFIG_H */
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index 1e10422..9fdd841 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -25,6 +25,11 @@
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
+#define CONFIG_DM
+#define CONFIG_DM_THERMAL
+#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
+#define CONFIG_IMX6_THERMAL
+
#define CONFIG_SYS_GENERIC_BOARD
/* Size of malloc() pool */
@@ -37,7 +42,7 @@
#define CONFIG_MXC_UART
#define CONFIG_CMD_FUSE
-#ifdef CONFIG_CMD_FUSE
+#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
#define CONFIG_MXC_OCOTP
#endif
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 4fcaf51..271548c 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -87,7 +87,7 @@
"fdt_addr=0x88000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
- "mmcdev=0\0" \
+ "mmcdev=1\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index e02ea18..d8ab291 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -59,7 +59,7 @@
"fdt_addr=0x88000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
- "mmcdev=0\0" \
+ "mmcdev=2\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
@@ -214,7 +214,6 @@
#define CONFIG_ENV_OFFSET (6 * SZ_64K)
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
@@ -223,4 +222,9 @@
#define CONFIG_CMD_CACHE
#endif
+#define CONFIG_SYS_FSL_USDHC_NUM 3
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/
+#endif
+
#endif /* __CONFIG_H */
diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h
index 5419f55..52cde41 100644
--- a/include/configs/nhk8815.h
+++ b/include/configs/nhk8815.h
@@ -12,7 +12,6 @@
#include <nomadik.h>
-#define CONFIG_ARM926EJS
#define CONFIG_NOMADIK_8815 /* cpu variant */
#define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index b928af8..807e96b 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -198,6 +198,19 @@
#define CONFIG_CMD_GPIO
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_EXYNOS
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+
/*
* Supported Odroid boards: X3, U3
* TODO: Add Odroid X support
diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h
index f3c21c4..bf1d34d 100644
--- a/include/configs/omap3_mvblx.h
+++ b/include/configs/omap3_mvblx.h
@@ -18,7 +18,6 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */
#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
diff --git a/include/configs/origen.h b/include/configs/origen.h
index da9d6a1..8f1e256 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -56,6 +56,10 @@
#undef CONFIG_CMD_PING
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
@@ -63,7 +67,36 @@
#define COPY_BL2_FNPTR_ADDR 0x02020030
#define CONFIG_SPL_TEXT_BASE 0x02021410
-#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x40007000\0" \
+ "rdaddr=0x48000000\0" \
+ "kerneladdr=0x40007000\0" \
+ "ramdiskaddr=0x48000000\0" \
+ "console=ttySAC2,115200n8\0" \
+ "mmcdev=0\0" \
+ "bootenv=uEnv.txt\0" \
+ "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+ "importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t $loadaddr $filesize\0" \
+ "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+ "source ${loadaddr}\0"
+#define CONFIG_BOOTCOMMAND \
+ "if mmc rescan; then " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "echo Loaded environment from ${bootenv};" \
+ "run importbootenv;" \
+ "fi;" \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "fi; " \
+ "fi;" \
+ "load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} "
#define CONFIG_IDENT_STRING " for ORIGEN"
diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h
new file mode 100644
index 0000000..8a82402
--- /dev/null
+++ b/include/configs/peach-pi.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG/GOOGLE PEACH-PI board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_PEACH_PI_H
+#define __CONFIG_PEACH_PI_H
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SPI_FLASH
+#define CONFIG_ENV_SPI_BASE 0x12D30000
+#define FLASH_SIZE (0x4 << 20)
+#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
+
+#include <configs/exynos5420-common.h>
+#include <configs/exynos5-dt-common.h>
+
+#define CONFIG_BOARD_COMMON
+
+/* select serial console configuration */
+#define CONFIG_SERIAL3 /* use SERIAL 3 */
+
+#define CONFIG_SYS_PROMPT "Peach-Pi # "
+#define CONFIG_IDENT_STRING " for Peach-Pi"
+
+#define CONFIG_VIDEO_PARADE
+
+/* Display */
+#define CONFIG_LCD
+#ifdef CONFIG_LCD
+#define CONFIG_EXYNOS_FB
+#define CONFIG_EXYNOS_DP
+#define LCD_BPP LCD_COLOR16
+#endif
+
+#define CONFIG_POWER_TPS65090_EC
+#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
+#define CONFIG_DM_CROS_EC
+
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_EXYNOS
+
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS 7
+#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
+
+#endif /* __CONFIG_PEACH_PI_H */
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
index 91bd37d..ad5db57 100644
--- a/include/configs/peach-pit.h
+++ b/include/configs/peach-pit.h
@@ -23,8 +23,8 @@
/* select serial console configuration */
#define CONFIG_SERIAL3 /* use SERIAL 3 */
-#define CONFIG_SYS_PROMPT "Peach # "
-#define CONFIG_IDENT_STRING " for Peach"
+#define CONFIG_SYS_PROMPT "Peach-Pit # "
+#define CONFIG_IDENT_STRING " for Peach-Pit"
#define CONFIG_VIDEO_PARADE
@@ -43,4 +43,8 @@
#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_EXYNOS
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS 4
+#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
+
#endif /* __CONFIG_PEACH_PIT_H */
diff --git a/include/configs/pr1.h b/include/configs/pr1.h
index 0f57e86..13fb675 100644
--- a/include/configs/pr1.h
+++ b/include/configs/pr1.h
@@ -102,8 +102,8 @@
/*
* I2C Settings
*/
-#define CONFIG_BFIN_TWI_I2C
-#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
/*
diff --git a/include/configs/qong.h b/include/configs/qong.h
index f9d6642..d383fe8 100644
--- a/include/configs/qong.h
+++ b/include/configs/qong.h
@@ -12,8 +12,7 @@
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
-#define CONFIG_MX31 /* in a mx31 */
+#define CONFIG_MX31 /* This is a mx31 */
#define CONFIG_QONG
#define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h
index ca27f9a..41e975f 100644
--- a/include/configs/rpi_b.h
+++ b/include/configs/rpi_b.h
@@ -21,7 +21,6 @@
/* Architecture, CPU, etc.*/
#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_ARM1176
#define CONFIG_BCM2835
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_DCACHE_OFF
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index ee4b244..2b03841 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -48,6 +48,7 @@
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_FS_FAT
+#define CONFIG_FAT_WRITE
#define CONFIG_FS_EXT4
#define CONFIG_EXT4_WRITE
#define CONFIG_CMD_FAT
@@ -57,6 +58,7 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_HOST_MAX_DEVICES 4
#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_MD5SUM
#define CONFIG_SYS_VSNPRINTF
diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h
index e6d272d..f4a40bb 100644
--- a/include/configs/scb9328.h
+++ b/include/configs/scb9328.h
@@ -10,8 +10,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */
-#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */
+#define CONFIG_IMX 1 /* This is a Motorola MC9328MXL Chip */
#define CONFIG_SCB9328 1 /* on a scb9328tronix board */
#define CONFIG_IMX_SERIAL
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index d4ae19f..71eb81c 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -17,13 +17,14 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM920T /* This is an ARM920T Core */
-#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */
#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */
#define CONFIG_SMDK2410 /* on a SAMSUNG SMDK2410 Board */
#define CONFIG_SYS_TEXT_BASE 0x0
+#define CONFIG_SYS_GENERIC_BOARD
+
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
/* input clock of PLL (the SMDK2410 has 12MHz input clock) */
diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
index fd2d482..5c9a3c0 100644
--- a/include/configs/smdk5420.h
+++ b/include/configs/smdk5420.h
@@ -23,4 +23,8 @@
#define CONFIG_IDENT_STRING " for SMDK5420"
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS 7
+#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
+
#endif /* __CONFIG_SMDK5420_H */
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
index 1ebee71..942af2e 100644
--- a/include/configs/snapper9260.h
+++ b/include/configs/snapper9260.h
@@ -15,11 +15,17 @@
#include <asm/hardware.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_TEXT_BASE 0x20000000
+#define CONFIG_SYS_TEXT_BASE 0x21f00000
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DM
+#define CONFIG_CMD_DM
+#define CONFIG_DM_GPIO
+#define CONFIG_DM_SERIAL
+#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
/* CPU */
#define CONFIG_ARCH_CPU_INIT
@@ -84,8 +90,10 @@
/* UARTs/Serial console */
#define CONFIG_ATMEL_USART
+#ifndef CONFIG_DM_SERIAL
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_SYS
+#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_PROMPT "Snapper> "
@@ -159,7 +167,7 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
-#undef CONFIG_CMD_GPIO
+#define CONFIG_CMD_GPIO
#define CONFIG_CMD_USB
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index c436fda..c4ac94d 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -11,7 +11,6 @@
/* Virtual target or real hardware */
#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_ARMV7
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SOCFPGA
diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
index ea40790..f6b1b3e 100644
--- a/include/configs/sun7i.h
+++ b/include/configs/sun7i.h
@@ -22,10 +22,7 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
-#define CONFIG_ARMV7_VIRT 1
-#define CONFIG_ARMV7_NONSEC 1
#define CONFIG_ARMV7_PSCI 1
-#define CONFIG_ARMV7_PSCI_NR_CPUS 2
#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
#define CONFIG_SYS_CLK_FREQ 24000000
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index ce038ed..3f890b2 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -197,6 +197,36 @@
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_CMD_GPIO
+#ifdef CONFIG_VIDEO
+/*
+ * The amount of RAM that is reserved for the FB. This will not show up as
+ * RAM to the kernel, but will be reclaimed by a KMS driver in future.
+ */
+#define CONFIG_SUNXI_FB_SIZE (8 << 20)
+
+/* Do we want to initialize a simple FB? */
+#define CONFIG_VIDEO_DT_SIMPLEFB
+
+#define CONFIG_VIDEO_SUNXI
+
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VIDEO_LOGO
+
+/* allow both serial and cfb console. */
+#define CONFIG_CONSOLE_MUX
+/* stop x86 thinking in cfbconsole from trying to init a pc keyboard */
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+
+#define CONFIG_SYS_MEM_TOP_HIDE ((CONFIG_SUNXI_FB_SIZE + 0xFFF) & ~0xFFF)
+
+/* To be able to hook simplefb into dt */
+#ifdef CONFIG_VIDEO_DT_SIMPLEFB
+#define CONFIG_OF_BOARD_SETUP
+#endif
+
+#endif /* CONFIG_VIDEO */
+
/* Ethernet support */
#ifdef CONFIG_SUNXI_EMAC
#define CONFIG_MII /* MII PHY management */
@@ -217,6 +247,13 @@
#define CONFIG_USB_STORAGE
#endif
+#ifdef CONFIG_USB_KEYBOARD
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_PREBOOT
+#define CONFIG_SYS_STDIO_DEREGISTER
+#define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
+#endif
+
#if !defined CONFIG_ENV_IS_IN_MMC && \
!defined CONFIG_ENV_IS_IN_NAND && \
!defined CONFIG_ENV_IS_IN_FAT && \
@@ -225,6 +262,7 @@
#endif
#define CONFIG_MISC_INIT_R
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h>
@@ -266,7 +304,31 @@
#include <config_distro_bootcmd.h>
+#ifdef CONFIG_USB_KEYBOARD
+#define CONSOLE_STDIN_SETTINGS \
+ "preboot=usb start\0" \
+ "stdin=serial,usbkbd\0"
+#else
+#define CONSOLE_STDIN_SETTINGS \
+ "stdin=serial\0"
+#endif
+
+#ifdef CONFIG_VIDEO
+#define CONSOLE_STDOUT_SETTINGS \
+ "stdout=serial,vga\0" \
+ "stderr=serial,vga\0"
+#else
+#define CONSOLE_STDOUT_SETTINGS \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+#endif
+
+#define CONSOLE_ENV_SETTINGS \
+ CONSOLE_STDIN_SETTINGS \
+ CONSOLE_STDOUT_SETTINGS
+
#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONSOLE_ENV_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
"fdtfile=" CONFIG_FDTFILE "\0" \
"console=ttyS0,115200\0" \
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index d687717..a160329 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -16,7 +16,6 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP_GPIO
diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h
index 6673026..e96a742 100644
--- a/include/configs/tcm-bf518.h
+++ b/include/configs/tcm-bf518.h
@@ -103,8 +103,8 @@
/*
* I2C Settings
*/
-#define CONFIG_BFIN_TWI_I2C 1
-#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
/*
diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h
index 9998343..42129fb 100644
--- a/include/configs/tcm-bf537.h
+++ b/include/configs/tcm-bf537.h
@@ -122,8 +122,8 @@
/*
* I2C Settings
*/
-#define CONFIG_BFIN_TWI_I2C 1
-#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_ADI
/*
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 5d2b12a..d690045 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -118,7 +118,9 @@
#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_USE_ARCH_MEMCPY
+#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h
index 162826f..00a1a9e 100644
--- a/include/configs/tnetv107x_evm.h
+++ b/include/configs/tnetv107x_evm.h
@@ -16,7 +16,6 @@
#include <asm/arch/clock.h>
/* Architecture, CPU, etc */
-#define CONFIG_ARM1176
#define CONFIG_TNETV107X
#define CONFIG_TNETV107X_EVM
#define CONFIG_TNETV107X_WATCHDOG
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
index c94eee1..a099687 100644
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h
@@ -68,6 +68,8 @@
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
+#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K
+
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
@@ -275,12 +277,10 @@
#elif defined(CONFIG_TQMA6X_SPI_BOOT)
-#define CONFIG_FLASH_SECTOR_SIZE 0x10000
-
#define TQMA6_UBOOT_OFFSET 0x400
#define TQMA6_UBOOT_SECTOR_START 0x0
/* max u-boot size: 512k */
-#define TQMA6_UBOOT_SECTOR_SIZE CONFIG_FLASH_SECTOR_SIZE
+#define TQMA6_UBOOT_SECTOR_SIZE TQMA6_SPI_FLASH_SECTOR_SIZE
#define TQMA6_UBOOT_SECTOR_COUNT 0x8
#define TQMA6_UBOOT_SIZE (TQMA6_UBOOT_SECTOR_SIZE * \
TQMA6_UBOOT_SECTOR_COUNT)
@@ -288,7 +288,7 @@
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_OFFSET (TQMA6_UBOOT_SIZE)
-#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
+#define CONFIG_ENV_SECT_SIZE TQMA6_SPI_FLASH_SECTOR_SIZE
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
CONFIG_ENV_SECT_SIZE)
@@ -299,7 +299,7 @@
#define TQMA6_FDT_OFFSET (CONFIG_ENV_OFFSET_REDUND + \
CONFIG_ENV_SECT_SIZE)
-#define TQMA6_FDT_SECT_SIZE (CONFIG_FLASH_SECTOR_SIZE)
+#define TQMA6_FDT_SECT_SIZE (TQMA6_SPI_FLASH_SECTOR_SIZE)
#define TQMA6_FDT_SECTOR_START 0x0a /* 8 Sector u-boot, 2 Sector env */
#define TQMA6_FDT_SECTOR_COUNT 0x01
@@ -320,7 +320,7 @@
"setexpr blkc ${filesize} + " \
__stringify(TQMA6_UBOOT_OFFSET) "; " \
"setexpr size ${uboot_sectors} * " \
- __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
+ __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
"if itest ${blkc} <= ${size}; then " \
"sf probe; " \
"sf erase 0 ${size}; " \
@@ -332,9 +332,9 @@
"update_kernel=run kernel_name; if tftp ${kernel}; then " \
"if itest ${filesize} > 0; then " \
"setexpr size ${kernel_sectors} * " \
- __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
+ __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
"setexpr offset ${kernel_start} * " \
- __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
+ __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
"if itest ${filesize} <= ${size}; then " \
"sf probe; " \
"sf erase ${offset} ${size}; " \
@@ -346,9 +346,9 @@
"update_fdt=if tftp ${fdt_file}; then " \
"if itest ${filesize} > 0; then " \
"setexpr size ${fdt_sectors} * " \
- __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
+ __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
"setexpr offset ${fdt_start} * " \
- __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
+ __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
"if itest ${filesize} <= ${size}; then " \
"sf probe; " \
"sf erase ${offset} ${size}; " \
@@ -359,16 +359,16 @@
"setenv filesize 0; setenv size ; setenv offset\0" \
"loadimage=sf probe; " \
"setexpr size ${kernel_sectors} * " \
- __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
+ __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
"setexpr offset ${kernel_start} * " \
- __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
+ __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
"sf read ${loadaddr} ${offset} ${size}; " \
"setenv size ; setenv offset\0" \
"loadfdt=sf probe; " \
"setexpr size ${fdt_sectors} * " \
- __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
+ __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
"setexpr offset ${fdt_start} * " \
- __stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
+ __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
"sf read ${${fdt_addr}} ${offset} ${size}; " \
"setenv size ; setenv offset\0" \
diff --git a/include/configs/tt01.h b/include/configs/tt01.h
index 0937653..cf169a4 100644
--- a/include/configs/tt01.h
+++ b/include/configs/tt01.h
@@ -13,7 +13,6 @@
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_ARM1136
#define CONFIG_MX31
#define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/udoo.h b/include/configs/udoo.h
index 700e9c1..b4a6245 100644
--- a/include/configs/udoo.h
+++ b/include/configs/udoo.h
@@ -191,7 +191,6 @@
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256
diff --git a/include/configs/versatile.h b/include/configs/versatile.h
index 29c32fe..900b89c 100644
--- a/include/configs/versatile.h
+++ b/include/configs/versatile.h
@@ -19,8 +19,7 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
-#define CONFIG_VERSATILE 1 /* in Versatile Platform Board */
+#define CONFIG_VERSATILE 1 /* This is Versatile Platform Board */
#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */
#define CONFIG_SYS_MEMTEST_START 0x100000
diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h
index 982f4a7..b43afa2 100644
--- a/include/configs/vexpress_ca15_tc2.h
+++ b/include/configs/vexpress_ca15_tc2.h
@@ -18,6 +18,4 @@
#define CONFIG_SYSFLAGS_ADDR 0x1c010030
#define CONFIG_SMP_PEN_ADDR CONFIG_SYSFLAGS_ADDR
-#define CONFIG_ARMV7_VIRT
-
#endif
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
index d3d3e69..c7a17f7 100644
--- a/include/configs/woodburn_common.h
+++ b/include/configs/woodburn_common.h
@@ -14,7 +14,6 @@
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
-#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
#define CONFIG_MX35
#define CONFIG_MX35_HCLK_FREQ 24000000
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
new file mode 100644
index 0000000..f16ae32
--- /dev/null
+++ b/include/configs/x86-common.h
@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/ibmpc.h>
+
+#ifndef __CONFIG_X86_COMMON_H
+#define __CONFIG_X86_COMMON_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_SYS_VSNPRINTF
+#define CONFIG_ZBOOT_32
+#define CONFIG_PHYSMEM
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_DM
+#define CONFIG_CMD_DM
+#define CONFIG_DM_GPIO
+#define CONFIG_DM_SERIAL
+
+#define CONFIG_LMB
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_LZO
+#define CONFIG_FIT
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+#define CONFIG_SYS_BOOTM_LEN (16 << 20)
+
+/* SATA AHCI storage */
+
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SATA_INTEL
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_LIBATA
+#define CONFIG_SYS_64BIT_LBA
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#endif
+
+/* Generic TPM interfaced through LPC bus */
+#define CONFIG_TPM
+#define CONFIG_TPM_TIS_LPC
+#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000
+
+/*-----------------------------------------------------------------------
+ * Real Time Clock Configuration
+ */
+#define CONFIG_RTC_MC146818
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
+#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS
+
+/*-----------------------------------------------------------------------
+ * Serial Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
+ 9600, 19200, 38400, 115200}
+#define CONFIG_SYS_NS16550_PORT_MAPPED
+
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_STDIO_DEREGISTER
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_COMMAND_HISTORY
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+#define CONFIG_SUPPORT_VFAT
+/************************************************************
+ * ATAPI support (experimental)
+ ************************************************************/
+#define CONFIG_ATAPI
+
+/************************************************************
+ * DISK Partition support
+ ************************************************************/
+#define CONFIG_EFI_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION /* Experimental */
+
+#define CONFIG_CMD_PART
+#define CONFIG_CMD_CBFS
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_PARTITION_UUIDS
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* x86 GPIOs are accessed through a PCI device */
+#define CONFIG_INTEL_ICH6_GPIO
+
+/*-----------------------------------------------------------------------
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ECHO
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FPGA_LOADMK
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_IO
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ITEST
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_TIME
+#define CONFIG_CMD_GETTIME
+#define CONFIG_CMD_XIMG
+#define CONFIG_CMD_SCSI
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_CMD_ZBOOT
+#define CONFIG_CMD_ELF
+
+#define CONFIG_BOOTARGS \
+ "root=/dev/sdb3 init=/sbin/init rootwait ro"
+#define CONFIG_BOOTCOMMAND \
+ "ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + \
+ 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x01000000
+#define CONFIG_SYS_LOAD_ADDR 0x20000000
+
+/*-----------------------------------------------------------------------
+ * Video Configuration
+ */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_SW_CURSOR
+#define VIDEO_FB_16BPP_WORD_SWAP
+#define CONFIG_I8042_KBD
+#define CONFIG_CFB_CONSOLE
+
+/*-----------------------------------------------------------------------
+ * CPU Features
+ */
+
+#define CONFIG_SYS_X86_TSC_TIMER
+#define CONFIG_SYS_PCAT_INTERRUPTS
+#define CONFIG_SYS_PCAT_TIMER
+#define CONFIG_SYS_NUM_IRQS 16
+
+#define CONFIG_SYS_STACK_SIZE (32 * 1024)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MALLOC_LEN 0x200000
+#define CONFIG_SYS_MALLOC_F_LEN (2 << 10)
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/*-----------------------------------------------------------------------
+ * FLASH configuration
+ */
+#define CONFIG_ICH_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SPI_FLASH_GIGADEVICE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SF_TEST
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI
+
+/*-----------------------------------------------------------------------
+ * Environment configuration
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x01000
+
+/*-----------------------------------------------------------------------
+ * PCI configuration
+ */
+#define CONFIG_PCI
+
+/*-----------------------------------------------------------------------
+ * USB configuration
+ */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_PCI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_TFTP_TSIZE
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+#define CONFIG_CMD_USB
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_STD_DEVICES_SETTINGS
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h
index 8ffe6f1..356ac88 100644
--- a/include/configs/zmx25.h
+++ b/include/configs/zmx25.h
@@ -12,7 +12,6 @@
#include <asm/arch/imx-regs.h>
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_MX25
#define CONFIG_SYS_TEXT_BASE 0xA0000000
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 2bc1562..c39c568 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -10,9 +10,6 @@
#ifndef __CONFIG_ZYNQ_COMMON_H
#define __CONFIG_ZYNQ_COMMON_H
-/* High Level configuration Options */
-#define CONFIG_ARMV7
-
/* CPU clock */
#ifndef CONFIG_CPU_FREQ_HZ
# define CONFIG_CPU_FREQ_HZ 800000000
diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h
index 44cb7ef..f0cc794 100644
--- a/include/dm/device-internal.h
+++ b/include/dm/device-internal.h
@@ -87,7 +87,11 @@
* @dev: Pointer to device to remove
* @return 0 if OK, -ve on error (an error here is normally a very bad thing)
*/
+#ifdef CONFIG_DM_DEVICE_REMOVE
int device_remove(struct udevice *dev);
+#else
+static inline int device_remove(struct udevice *dev) { return 0; }
+#endif
/**
* device_unbind() - Unbind a device, destroying it
@@ -99,6 +103,12 @@
*/
int device_unbind(struct udevice *dev);
+#ifdef CONFIG_DM_DEVICE_REMOVE
+void device_free(struct udevice *dev);
+#else
+static inline void device_free(struct udevice *dev) {}
+#endif
+
/* Cast away any volatile pointer */
#define DM_ROOT_NON_CONST (((gd_t *)gd)->dm_root)
#define DM_UCLASS_ROOT_NON_CONST (((gd_t *)gd)->uclass_root)
diff --git a/include/dm/device.h b/include/dm/device.h
index 9ce95a8..13598a1 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -47,6 +47,7 @@
* @name: Name of device, typically the FDT node name
* @platdata: Configuration data for this device
* @of_offset: Device tree node offset for this device (- for none)
+ * @of_id: Pointer to the udevice_id structure which created the device
* @parent: Parent of this device, or NULL for the top level device
* @priv: Private data for this device
* @uclass: Pointer to uclass for this device
@@ -65,6 +66,7 @@
const char *name;
void *platdata;
int of_offset;
+ const struct udevice_id *of_id;
struct udevice *parent;
void *priv;
struct uclass *uclass;
@@ -206,6 +208,23 @@
void *dev_get_priv(struct udevice *dev);
/**
+ * struct dev_get_parent() - Get the parent of a device
+ *
+ * @child: Child to check
+ * @return parent of child, or NULL if this is the root device
+ */
+struct udevice *dev_get_parent(struct udevice *child);
+
+/**
+ * dev_get_of_data() - get the device tree data used to bind a device
+ *
+ * When a device is bound using a device tree node, it matches a
+ * particular compatible string as in struct udevice_id. This function
+ * returns the associated data value for that compatible string
+ */
+ulong dev_get_of_data(struct udevice *dev);
+
+/**
* device_get_child() - Get the child of a device by index
*
* Returns the numbered child, 0 being the first. This does not use
diff --git a/include/dm/lists.h b/include/dm/lists.h
index 704e33e..1b50af9 100644
--- a/include/dm/lists.h
+++ b/include/dm/lists.h
@@ -60,4 +60,17 @@
int lists_bind_fdt(struct udevice *parent, const void *blob, int offset,
struct udevice **devp);
+/**
+ * device_bind_driver() - bind a device to a driver
+ *
+ * This binds a new device to a driver.
+ *
+ * @parent: Parent device
+ * @drv_name: Name of driver to attach to this parent
+ * @dev_name: Name of the new device thus created
+ * @devp: Returns the newly bound device
+ */
+int device_bind_driver(struct udevice *parent, const char *drv_name,
+ const char *dev_name, struct udevice **devp);
+
#endif
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index a8944c9..202f59b 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -28,6 +28,7 @@
UCLASS_SPI_GENERIC, /* Generic SPI flash target */
UCLASS_SPI_FLASH, /* SPI flash */
UCLASS_CROS_EC, /* Chrome OS EC */
+ UCLASS_THERMAL, /* Thermal sensor */
UCLASS_COUNT,
UCLASS_INVALID = -1,
diff --git a/include/dm/util.h b/include/dm/util.h
index 6ac3a38..0cec17b 100644
--- a/include/dm/util.h
+++ b/include/dm/util.h
@@ -7,7 +7,13 @@
#ifndef __DM_UTIL_H
#define __DM_UTIL_H
+#ifdef CONFIG_DM_WARN
void dm_warn(const char *fmt, ...);
+#else
+static inline void dm_warn(const char *fmt, ...)
+{
+}
+#endif
#ifdef DEBUG
void dm_dbg(const char *fmt, ...);
diff --git a/include/ext4fs.h b/include/ext4fs.h
index 6c419f3..6888adc 100644
--- a/include/ext4fs.h
+++ b/include/ext4fs.h
@@ -125,24 +125,28 @@
void ext4fs_deinit(void);
int ext4fs_filename_check(char *filename);
int ext4fs_write(const char *fname, unsigned char *buffer,
- unsigned long sizebytes);
+ unsigned long sizebytes);
+int ext4_write_file(const char *filename, void *buf, loff_t offset, loff_t len,
+ loff_t *actwrite);
#endif
struct ext_filesystem *get_fs(void);
-int ext4fs_open(const char *filename);
-int ext4fs_read(char *buf, unsigned len);
+int ext4fs_open(const char *filename, loff_t *len);
+int ext4fs_read(char *buf, loff_t len, loff_t *actread);
int ext4fs_mount(unsigned part_length);
void ext4fs_close(void);
void ext4fs_reinit_global(void);
int ext4fs_ls(const char *dirname);
int ext4fs_exists(const char *filename);
-int ext4fs_size(const char *filename);
+int ext4fs_size(const char *filename, loff_t *size);
void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot);
int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf);
void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
long int read_allocated_block(struct ext2_inode *inode, int fileblock);
int ext4fs_probe(block_dev_desc_t *fs_dev_desc,
disk_partition_t *fs_partition);
-int ext4_read_file(const char *filename, void *buf, int offset, int len);
+int ext4_read_file(const char *filename, void *buf, loff_t offset, loff_t len,
+ loff_t *actread);
int ext4_read_superblock(char *buffer);
+int ext4fs_uuid(char *uuid_str);
#endif
diff --git a/include/fat.h b/include/fat.h
index 20ca3f3..3038bd7 100644
--- a/include/fat.h
+++ b/include/fat.h
@@ -178,8 +178,8 @@
typedef int (file_detectfs_func)(void);
typedef int (file_ls_func)(const char *dir);
-typedef long (file_read_func)(const char *filename, void *buffer,
- unsigned long maxsize);
+typedef int (file_read_func)(const char *filename, void *buffer,
+ int maxsize);
struct filesystem {
file_detectfs_func *detect;
@@ -198,15 +198,17 @@
int file_fat_detectfs(void);
int file_fat_ls(const char *dir);
int fat_exists(const char *filename);
-int fat_size(const char *filename);
-long file_fat_read_at(const char *filename, unsigned long pos, void *buffer,
- unsigned long maxsize);
-long file_fat_read(const char *filename, void *buffer, unsigned long maxsize);
+int fat_size(const char *filename, loff_t *size);
+int file_fat_read_at(const char *filename, loff_t pos, void *buffer,
+ loff_t maxsize, loff_t *actread);
+int file_fat_read(const char *filename, void *buffer, int maxsize);
const char *file_getfsname(int idx);
int fat_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
int fat_register_device(block_dev_desc_t *dev_desc, int part_no);
-int file_fat_write(const char *filename, void *buffer, unsigned long maxsize);
-int fat_read_file(const char *filename, void *buf, int offset, int len);
+int file_fat_write(const char *filename, void *buf, loff_t offset, loff_t len,
+ loff_t *actwrite);
+int fat_read_file(const char *filename, void *buf, loff_t offset, loff_t len,
+ loff_t *actread);
void fat_close(void);
#endif /* _FAT_H_ */
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 55cef94..1f19fe4 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -64,7 +64,20 @@
int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose);
#endif
-void ft_board_setup(void *blob, bd_t *bd);
+int fdt_find_or_add_subnode(void *fdt, int parentoffset, const char *name);
+
+/**
+ * Add board-specific data to the FDT before booting the OS.
+ *
+ * Use CONFIG_SYS_FDT_PAD to ensure there is sufficient space.
+ * This function is called if CONFIG_OF_BOARD_SETUP is defined
+ *
+ * @param blob FDT blob to update
+ * @param bd_t Pointer to board data
+ * @return 0 if ok, or -FDT_ERR_... on error
+ */
+int ft_board_setup(void *blob, bd_t *bd);
+
/*
* The keystone2 SOC requires all 32 bit aliased addresses to be converted
* to their 36 physical format. This has to happen after all fdt nodes
@@ -75,6 +88,18 @@
void ft_cpu_setup(void *blob, bd_t *bd);
void ft_pci_setup(void *blob, bd_t *bd);
+/**
+ * Add system-specific data to the FDT before booting the OS.
+ *
+ * Use CONFIG_SYS_FDT_PAD to ensure there is sufficient space.
+ * This function is called if CONFIG_OF_SYSTEM_SETUP is defined
+ *
+ * @param blob FDT blob to update
+ * @param bd_t Pointer to board data
+ * @return 0 if ok, or -FDT_ERR_... on error
+ */
+int ft_system_setup(void *blob, bd_t *bd);
+
void set_working_fdt_addr(void *addr);
int fdt_shrink_to_minimum(void *blob);
int fdt_increase_size(void *fdt, int add_len);
@@ -147,6 +172,9 @@
int ft_verify_fdt(void *fdt);
int arch_fixup_memory_node(void *blob);
+int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width,
+ u32 height, u32 stride, const char *format);
+
#endif /* ifdef CONFIG_OF_LIBFDT */
#ifdef USE_HOSTCC
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 4ae77be..3da9fab 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -118,6 +118,8 @@
COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */
COMPAT_PARADE_PS8625, /* Parade PS8622 EDP->LVDS bridge */
COMPAT_INTEL_LPC, /* Intel Low Pin Count I/F */
+ COMPAT_INTEL_MICROCODE, /* Intel microcode update */
+ COMPAT_MEMORY_SPD, /* Memory SPD information */
COMPAT_COUNT,
};
@@ -445,6 +447,22 @@
u32 *array, int count);
/**
+ * Look up a property in a node and return its contents in an integer
+ * array of given length. The property must exist but may have less data that
+ * expected (4*count bytes). It may have more, but this will be ignored.
+ *
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param prop_name name of property to find
+ * @param array array to fill with data
+ * @param count number of array elements
+ * @return number of array elements if ok, or -FDT_ERR_NOTFOUND if the
+ * property is not found
+ */
+int fdtdec_get_int_array_count(const void *blob, int node,
+ const char *prop_name, u32 *array, int count);
+
+/**
* Look up a property in a node and return a pointer to its contents as a
* unsigned int array of given length. The property must have at least enough
* data for the array ('count' cells). It may have more, but this will be
@@ -595,17 +613,33 @@
* @param blob FDT blob
* @param node node to examine
* @param prop_name name of property to find
- * @param ptrp returns pointer to region, or NULL if no address
- * @param size returns size of region
- * @return 0 if ok, -1 on error (propery not found)
+ * @param basep Returns base address of region
+ * @param size Returns size of region
+ * @return 0 if ok, -1 on error (property not found)
*/
-int fdtdec_decode_region(const void *blob, int node,
- const char *prop_name, void **ptrp, size_t *size);
+int fdtdec_decode_region(const void *blob, int node, const char *prop_name,
+ fdt_addr_t *basep, fdt_size_t *sizep);
+
+enum fmap_compress_t {
+ FMAP_COMPRESS_NONE,
+ FMAP_COMPRESS_LZO,
+};
+
+enum fmap_hash_t {
+ FMAP_HASH_NONE,
+ FMAP_HASH_SHA1,
+ FMAP_HASH_SHA256,
+};
/* A flash map entry, containing an offset and length */
struct fmap_entry {
uint32_t offset;
uint32_t length;
+ uint32_t used; /* Number of bytes used in region */
+ enum fmap_compress_t compress_algo; /* Compression type */
+ enum fmap_hash_t hash_algo; /* Hash algorithm */
+ const uint8_t *hash; /* Hash value */
+ int hash_size; /* Hash size */
};
/**
@@ -661,4 +695,31 @@
*/
int fdtdec_pci_get_bdf(const void *fdt, int node, int *bdf);
+/**
+ * Decode a named region within a memory bank of a given type.
+ *
+ * This function handles selection of a memory region. The region is
+ * specified as an offset/size within a particular type of memory.
+ *
+ * The properties used are:
+ *
+ * <mem_type>-memory<suffix> for the name of the memory bank
+ * <mem_type>-offset<suffix> for the offset in that bank
+ *
+ * The property value must have an offset and a size. The function checks
+ * that the region is entirely within the memory bank.5
+ *
+ * @param blob FDT blob
+ * @param node Node containing the properties (-1 for /config)
+ * @param mem_type Type of memory to use, which is a name, such as
+ * "u-boot" or "kernel".
+ * @param suffix String to append to the memory/offset
+ * property names
+ * @param basep Returns base of region
+ * @param sizep Returns size of region
+ * @return 0 if OK, -ive on error
+ */
+int fdtdec_decode_memory_region(const void *blob, int node,
+ const char *mem_type, const char *suffix,
+ fdt_addr_t *basep, fdt_size_t *sizep);
#endif
diff --git a/include/flash.h b/include/flash.h
index 5454c9e..30aa080 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -158,6 +158,7 @@
#define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */
#define AMIC_MANUFACT 0x00370037 /* AMIC manuf. ID in D23..D16, D7..D0 */
#define WINB_MANUFACT 0x00DA00DA /* Winbond manuf. ID in D23..D16, D7..D0 */
+#define EON_ALT_MANU 0x001C001C /* EON manuf. ID in D23..D16, D7..D0 */
/* Manufacturers inside bank 1 have ids like 0x01xx01xx */
#define EON_MANUFACT 0x011C011C /* EON manuf. ID in D23..D16, D7..D0 */
diff --git a/include/fs.h b/include/fs.h
index 06a45f2..ffb6ce7 100644
--- a/include/fs.h
+++ b/include/fs.h
@@ -51,32 +51,41 @@
int fs_exists(const char *filename);
/*
- * Determine a file's size
+ * fs_size - Determine a file's size
*
- * Returns the file's size in bytes, or a negative value if it doesn't exist.
+ * @filename: Name of the file
+ * @size: Size of file
+ * @return 0 if ok with valid *size, negative on error
*/
-int fs_size(const char *filename);
+int fs_size(const char *filename, loff_t *size);
/*
- * Read file "filename" from the partition previously set by fs_set_blk_dev(),
- * to address "addr", starting at byte offset "offset", and reading "len"
- * bytes. "offset" may be 0 to read from the start of the file. "len" may be
- * 0 to read the entire file. Note that not all filesystem types support
- * either/both offset!=0 or len!=0.
+ * fs_read - Read file from the partition previously set by fs_set_blk_dev()
+ * Note that not all filesystem types support either/both offset!=0 or len!=0.
*
- * Returns number of bytes read on success. Returns <= 0 on error.
+ * @filename: Name of file to read from
+ * @addr: The address to read into
+ * @offset: The offset in file to read from
+ * @len: The number of bytes to read. Maybe 0 to read entire file
+ * @actread: Returns the actual number of bytes read
+ * @return 0 if ok with valid *actread, -1 on error conditions
*/
-int fs_read(const char *filename, ulong addr, int offset, int len);
+int fs_read(const char *filename, ulong addr, loff_t offset, loff_t len,
+ loff_t *actread);
/*
- * Write file "filename" to the partition previously set by fs_set_blk_dev(),
- * from address "addr", starting at byte offset "offset", and writing "len"
- * bytes. "offset" may be 0 to write to the start of the file. Note that not
- * all filesystem types support offset!=0.
+ * fs_write - Write file to the partition previously set by fs_set_blk_dev()
+ * Note that not all filesystem types support offset!=0.
*
- * Returns number of bytes read on success. Returns <= 0 on error.
+ * @filename: Name of file to read from
+ * @addr: The address to read into
+ * @offset: The offset in file to read from. Maybe 0 to write to start of file
+ * @len: The number of bytes to write
+ * @actwrite: Returns the actual number of bytes written
+ * @return 0 if ok with valid *actwrite, -1 on error conditions
*/
-int fs_write(const char *filename, ulong addr, int offset, int len);
+int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len,
+ loff_t *actwrite);
/*
* Common implementation for various filesystem commands, optionally limited
@@ -93,4 +102,11 @@
int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
int fstype);
+/*
+ * Determine the UUID of the specified filesystem and print it. Optionally it is
+ * possible to store the UUID directly in env.
+ */
+int do_fs_uuid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+ int fstype);
+
#endif /* _FS_H */
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index 276a01e..8a5efe7 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -61,6 +61,22 @@
u16 y_pos;
};
+struct ihs_mdio {
+ u16 control;
+ u16 address_data;
+ u16 rx_data;
+};
+
+struct ihs_io_ep {
+ u16 transmit_data;
+ u16 rx_tx_control;
+ u16 receive_data;
+ u16 rx_tx_status;
+ u16 reserved;
+ u16 device_address;
+ u16 target_address;
+};
+
#ifdef CONFIG_NEO
struct ihs_fpga {
u16 reflection_low; /* 0x0000 */
@@ -119,12 +135,50 @@
u16 versions; /* 0x0002 */
u16 fpga_version; /* 0x0004 */
u16 fpga_features; /* 0x0006 */
+ u16 reserved_0[1]; /* 0x0008 */
+ u16 top_interrupt; /* 0x000a */
+ u16 reserved_1[4]; /* 0x000c */
+ struct ihs_gpio gpio; /* 0x0014 */
+ u16 mpc3w_control; /* 0x001a */
+ u16 reserved_2[2]; /* 0x001c */
+ struct ihs_io_ep ep; /* 0x0020 */
+ u16 reserved_3[9]; /* 0x002e */
+ struct ihs_i2c i2c; /* 0x0040 */
+ u16 reserved_4[10]; /* 0x004c */
+ u16 mc_int; /* 0x0060 */
+ u16 mc_int_en; /* 0x0062 */
+ u16 mc_status; /* 0x0064 */
+ u16 mc_control; /* 0x0066 */
+ u16 mc_tx_data; /* 0x0068 */
+ u16 mc_tx_address; /* 0x006a */
+ u16 mc_tx_cmd; /* 0x006c */
+ u16 mc_res; /* 0x006e */
+ u16 mc_rx_cmd_status; /* 0x0070 */
+ u16 mc_rx_data; /* 0x0072 */
+ u16 reserved_5[69]; /* 0x0074 */
+ u16 reflection_high; /* 0x00fe */
+ struct ihs_osd osd; /* 0x0100 */
+ u16 reserved_6[889]; /* 0x010e */
+ u16 videomem[31736]; /* 0x0800 */
+};
+#endif
+
+#ifdef CONFIG_HRCON
+struct ihs_fpga {
+ u16 reflection_low; /* 0x0000 */
+ u16 versions; /* 0x0002 */
+ u16 fpga_version; /* 0x0004 */
+ u16 fpga_features; /* 0x0006 */
- u16 reserved_0[6]; /* 0x0008 */
+ u16 reserved_0[1]; /* 0x0008 */
+ u16 top_interrupt; /* 0x000a */
+ u16 reserved_1[4]; /* 0x000c */
struct ihs_gpio gpio; /* 0x0014 */
u16 mpc3w_control; /* 0x001a */
- u16 reserved_1[18]; /* 0x001c */
+ u16 reserved_2[2]; /* 0x001c */
+ struct ihs_io_ep ep; /* 0x0020 */
+ u16 reserved_3[9]; /* 0x002e */
struct ihs_i2c i2c; /* 0x0040 */
- u16 reserved_2[10]; /* 0x004c */
+ u16 reserved_4[10]; /* 0x004c */
u16 mc_int; /* 0x0060 */
u16 mc_int_en; /* 0x0062 */
u16 mc_status; /* 0x0064 */
@@ -135,10 +189,10 @@
u16 mc_res; /* 0x006e */
u16 mc_rx_cmd_status; /* 0x0070 */
u16 mc_rx_data; /* 0x0072 */
- u16 reserved_3[69]; /* 0x0074 */
+ u16 reserved_5[69]; /* 0x0074 */
u16 reflection_high; /* 0x00fe */
struct ihs_osd osd; /* 0x0100 */
- u16 reserved_4[889]; /* 0x010e */
+ u16 reserved_6[889]; /* 0x010e */
u16 videomem[31736]; /* 0x0800 */
};
#endif
diff --git a/include/image.h b/include/image.h
index 07e9aed..af30d60 100644
--- a/include/image.h
+++ b/include/image.h
@@ -119,6 +119,12 @@
# define IMAGE_OF_BOARD_SETUP 0
#endif
+#ifdef CONFIG_OF_SYSTEM_SETUP
+# define IMAGE_OF_SYSTEM_SETUP 1
+#else
+# define IMAGE_OF_SYSTEM_SETUP 0
+#endif
+
/*
* Operating System Codes
*/
diff --git a/include/imx_thermal.h b/include/imx_thermal.h
new file mode 100644
index 0000000..be13652
--- /dev/null
+++ b/include/imx_thermal.h
@@ -0,0 +1,17 @@
+/*
+ *
+ * (C) Copyright 2014 Freescale Semiconductor, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _IMX_THERMAL_H_
+#define _IMX_THERMAL_H_
+
+struct imx_thermal_plat {
+ void *regs;
+ int fuse_bank;
+ int fuse_word;
+};
+
+#endif /* _IMX_THERMAL_H_ */
diff --git a/include/linux/compat.h b/include/linux/compat.h
index 7ff6064..47b0889 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -57,17 +57,6 @@
#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
-/*
- * ..and if you can't take the strict
- * types, you can specify one yourself.
- *
- * Or not use min/max at all, of course.
- */
-#define min_t(type,x,y) \
- ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
-#define max_t(type,x,y) \
- ({ type __x = (x); type __y = (y); __x > __y ? __x: __y; })
-
#ifndef BUG
#define BUG() do { \
printf("U-Boot BUG at %s:%d!\n", __FILE__, __LINE__); \
@@ -81,24 +70,6 @@
#define PAGE_SIZE 4096
-/**
- * upper_32_bits - return MSB bits 32-63 of a number if little endian, or
- * return MSB bits 0-31 of a number if big endian.
- * @n: the number we're accessing
- *
- * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
- * the "right shift count >= width of type" warning when that quantity is
- * 32-bits.
- */
-#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
-
-/**
- * lower_32_bits - return LSB bits 0-31 of a number if little endian, or
- * return LSB bits 32-63 of a number if big endian.
- * @n: the number we're accessing
- */
-#define lower_32_bits(n) ((u32)(n))
-
/* drivers/char/random.c */
#define get_random_bytes(...)
@@ -152,17 +123,6 @@
#define ENOTSUPP 524 /* Operation is not supported */
-/* from include/linux/kernel.h */
-/*
- * This looks more complex than it should be. But we need to
- * get the type for the ~ right in round_down (it needs to be
- * as wide as the result!), and we want to evaluate the macro
- * arguments just once each.
- */
-#define __round_mask(x, y) ((__typeof__(x))((y)-1))
-#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1)
-#define round_down(x, y) ((x) & ~__round_mask(x, y))
-
/* module */
#define THIS_MODULE 0
#define try_module_get(...) 1
@@ -198,18 +158,6 @@
#define blocking_notifier_call_chain(...) 0
-/*
- * Multiplies an integer by a fraction, while avoiding unnecessary
- * overflow or loss of precision.
- */
-#define mult_frac(x, numer, denom)( \
-{ \
- typeof(x) quot = (x) / (denom); \
- typeof(x) rem = (x) % (denom); \
- (quot * (numer)) + ((rem * (numer)) / (denom)); \
-} \
-)
-
#define __initdata
#define late_initcall(...)
@@ -267,8 +215,6 @@
#define cond_resched() do { } while (0)
#define yield() do { } while (0)
-#define INT_MAX ((int)(~0U>>1))
-
#define __user
#define __init
#define __exit
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
new file mode 100644
index 0000000..89fcae0
--- /dev/null
+++ b/include/linux/kernel.h
@@ -0,0 +1,245 @@
+#ifndef _LINUX_KERNEL_H
+#define _LINUX_KERNEL_H
+
+
+#include <linux/types.h>
+
+#define USHRT_MAX ((u16)(~0U))
+#define SHRT_MAX ((s16)(USHRT_MAX>>1))
+#define SHRT_MIN ((s16)(-SHRT_MAX - 1))
+#define INT_MAX ((int)(~0U>>1))
+#define INT_MIN (-INT_MAX - 1)
+#define UINT_MAX (~0U)
+#define LONG_MAX ((long)(~0UL>>1))
+#define LONG_MIN (-LONG_MAX - 1)
+#define ULONG_MAX (~0UL)
+#define LLONG_MAX ((long long)(~0ULL>>1))
+#define LLONG_MIN (-LLONG_MAX - 1)
+#define ULLONG_MAX (~0ULL)
+#define SIZE_MAX (~(size_t)0)
+
+#define U8_MAX ((u8)~0U)
+#define S8_MAX ((s8)(U8_MAX>>1))
+#define S8_MIN ((s8)(-S8_MAX - 1))
+#define U16_MAX ((u16)~0U)
+#define S16_MAX ((s16)(U16_MAX>>1))
+#define S16_MIN ((s16)(-S16_MAX - 1))
+#define U32_MAX ((u32)~0U)
+#define S32_MAX ((s32)(U32_MAX>>1))
+#define S32_MIN ((s32)(-S32_MAX - 1))
+#define U64_MAX ((u64)~0ULL)
+#define S64_MAX ((s64)(U64_MAX>>1))
+#define S64_MIN ((s64)(-S64_MAX - 1))
+
+#define STACK_MAGIC 0xdeadbeef
+
+#define REPEAT_BYTE(x) ((~0ul / 0xff) * (x))
+
+#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
+#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
+#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a)))
+#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0)
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/*
+ * This looks more complex than it should be. But we need to
+ * get the type for the ~ right in round_down (it needs to be
+ * as wide as the result!), and we want to evaluate the macro
+ * arguments just once each.
+ */
+#define __round_mask(x, y) ((__typeof__(x))((y)-1))
+#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1)
+#define round_down(x, y) ((x) & ~__round_mask(x, y))
+
+#define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f))
+#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
+
+#if BITS_PER_LONG == 32
+# define DIV_ROUND_UP_SECTOR_T(ll,d) DIV_ROUND_UP_ULL(ll, d)
+#else
+# define DIV_ROUND_UP_SECTOR_T(ll,d) DIV_ROUND_UP(ll,d)
+#endif
+
+/* The `const' in roundup() prevents gcc-3.3 from calling __divdi3 */
+#define roundup(x, y) ( \
+{ \
+ const typeof(y) __y = y; \
+ (((x) + (__y - 1)) / __y) * __y; \
+} \
+)
+#define rounddown(x, y) ( \
+{ \
+ typeof(x) __x = (x); \
+ __x - (__x % (y)); \
+} \
+)
+
+/*
+ * Divide positive or negative dividend by positive divisor and round
+ * to closest integer. Result is undefined for negative divisors and
+ * for negative dividends if the divisor variable type is unsigned.
+ */
+#define DIV_ROUND_CLOSEST(x, divisor)( \
+{ \
+ typeof(x) __x = x; \
+ typeof(divisor) __d = divisor; \
+ (((typeof(x))-1) > 0 || \
+ ((typeof(divisor))-1) > 0 || (__x) > 0) ? \
+ (((__x) + ((__d) / 2)) / (__d)) : \
+ (((__x) - ((__d) / 2)) / (__d)); \
+} \
+)
+
+/*
+ * Multiplies an integer by a fraction, while avoiding unnecessary
+ * overflow or loss of precision.
+ */
+#define mult_frac(x, numer, denom)( \
+{ \
+ typeof(x) quot = (x) / (denom); \
+ typeof(x) rem = (x) % (denom); \
+ (quot * (numer)) + ((rem * (numer)) / (denom)); \
+} \
+)
+
+/**
+ * upper_32_bits - return bits 32-63 of a number
+ * @n: the number we're accessing
+ *
+ * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
+ * the "right shift count >= width of type" warning when that quantity is
+ * 32-bits.
+ */
+#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
+
+/**
+ * lower_32_bits - return bits 0-31 of a number
+ * @n: the number we're accessing
+ */
+#define lower_32_bits(n) ((u32)(n))
+
+/*
+ * abs() handles unsigned and signed longs, ints, shorts and chars. For all
+ * input types abs() returns a signed long.
+ * abs() should not be used for 64-bit types (s64, u64, long long) - use abs64()
+ * for those.
+ */
+#define abs(x) ({ \
+ long ret; \
+ if (sizeof(x) == sizeof(long)) { \
+ long __x = (x); \
+ ret = (__x < 0) ? -__x : __x; \
+ } else { \
+ int __x = (x); \
+ ret = (__x < 0) ? -__x : __x; \
+ } \
+ ret; \
+ })
+
+#define abs64(x) ({ \
+ s64 __x = (x); \
+ (__x < 0) ? -__x : __x; \
+ })
+
+/*
+ * min()/max()/clamp() macros that also do
+ * strict type-checking.. See the
+ * "unnecessary" pointer comparison.
+ */
+#define min(x, y) ({ \
+ typeof(x) _min1 = (x); \
+ typeof(y) _min2 = (y); \
+ (void) (&_min1 == &_min2); \
+ _min1 < _min2 ? _min1 : _min2; })
+
+#define max(x, y) ({ \
+ typeof(x) _max1 = (x); \
+ typeof(y) _max2 = (y); \
+ (void) (&_max1 == &_max2); \
+ _max1 > _max2 ? _max1 : _max2; })
+
+#define min3(x, y, z) min((typeof(x))min(x, y), z)
+#define max3(x, y, z) max((typeof(x))max(x, y), z)
+
+/**
+ * min_not_zero - return the minimum that is _not_ zero, unless both are zero
+ * @x: value1
+ * @y: value2
+ */
+#define min_not_zero(x, y) ({ \
+ typeof(x) __x = (x); \
+ typeof(y) __y = (y); \
+ __x == 0 ? __y : ((__y == 0) ? __x : min(__x, __y)); })
+
+/**
+ * clamp - return a value clamped to a given range with strict typechecking
+ * @val: current value
+ * @lo: lowest allowable value
+ * @hi: highest allowable value
+ *
+ * This macro does strict typechecking of lo/hi to make sure they are of the
+ * same type as val. See the unnecessary pointer comparisons.
+ */
+#define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
+
+/*
+ * ..and if you can't take the strict
+ * types, you can specify one yourself.
+ *
+ * Or not use min/max/clamp at all, of course.
+ */
+#define min_t(type, x, y) ({ \
+ type __min1 = (x); \
+ type __min2 = (y); \
+ __min1 < __min2 ? __min1: __min2; })
+
+#define max_t(type, x, y) ({ \
+ type __max1 = (x); \
+ type __max2 = (y); \
+ __max1 > __max2 ? __max1: __max2; })
+
+/**
+ * clamp_t - return a value clamped to a given range using a given type
+ * @type: the type of variable to use
+ * @val: current value
+ * @lo: minimum allowable value
+ * @hi: maximum allowable value
+ *
+ * This macro does no typechecking and uses temporary variables of type
+ * 'type' to make all the comparisons.
+ */
+#define clamp_t(type, val, lo, hi) min_t(type, max_t(type, val, lo), hi)
+
+/**
+ * clamp_val - return a value clamped to a given range using val's type
+ * @val: current value
+ * @lo: minimum allowable value
+ * @hi: maximum allowable value
+ *
+ * This macro does no typechecking and uses temporary variables of whatever
+ * type the input argument 'val' is. This is useful when val is an unsigned
+ * type and min and max are literals that will otherwise be assigned a signed
+ * integer type.
+ */
+#define clamp_val(val, lo, hi) clamp_t(typeof(val), val, lo, hi)
+
+
+/*
+ * swap - swap value of @a and @b
+ */
+#define swap(a, b) \
+ do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @ptr: the pointer to the member.
+ * @type: the type of the container struct this is embedded in.
+ * @member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({ \
+ const typeof( ((type *)0)->member ) *__mptr = (ptr); \
+ (type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif
diff --git a/include/malloc.h b/include/malloc.h
index c33f3b4..5df6348 100644
--- a/include/malloc.h
+++ b/include/malloc.h
@@ -872,33 +872,46 @@
#else
-#ifdef USE_DL_PREFIX
-#define cALLOc dlcalloc
-#define fREe dlfree
-#define mALLOc dlmalloc
-#define mEMALIGn dlmemalign
-#define rEALLOc dlrealloc
-#define vALLOc dlvalloc
-#define pvALLOc dlpvalloc
-#define mALLINFo dlmallinfo
-#define mALLOPt dlmallopt
-#else /* USE_DL_PREFIX */
-#define cALLOc calloc
-#define fREe free
-#define mALLOc malloc
-#define mEMALIGn memalign
-#define rEALLOc realloc
-#define vALLOc valloc
-#define pvALLOc pvalloc
-#define mALLINFo mallinfo
-#define mALLOPt mallopt
-#endif /* USE_DL_PREFIX */
+#ifdef CONFIG_SYS_MALLOC_SIMPLE
+#define malloc malloc_simple
+#define realloc realloc_simple
+#define memalign memalign_simple
+static inline void free(void *ptr) {}
+void *calloc(size_t nmemb, size_t size);
+void *memalign_simple(size_t alignment, size_t bytes);
+void *realloc_simple(void *ptr, size_t size);
+#else
+
+# ifdef USE_DL_PREFIX
+# define cALLOc dlcalloc
+# define fREe dlfree
+# define mALLOc dlmalloc
+# define mEMALIGn dlmemalign
+# define rEALLOc dlrealloc
+# define vALLOc dlvalloc
+# define pvALLOc dlpvalloc
+# define mALLINFo dlmallinfo
+# define mALLOPt dlmallopt
+# else /* USE_DL_PREFIX */
+# define cALLOc calloc
+# define fREe free
+# define mALLOc malloc
+# define mEMALIGn memalign
+# define rEALLOc realloc
+# define vALLOc valloc
+# define pvALLOc pvalloc
+# define mALLINFo mallinfo
+# define mALLOPt mallopt
+# endif /* USE_DL_PREFIX */
#endif
/* Public routines */
-#if __STD_C
+/* Simple versions which can be used when space is tight */
+void *malloc_simple(size_t size);
+
+# if __STD_C
Void_t* mALLOc(size_t);
void fREe(Void_t*);
@@ -913,7 +926,7 @@
void malloc_stats(void);
int mALLOPt(int, int);
struct mallinfo mALLINFo(void);
-#else
+# else
Void_t* mALLOc();
void fREe();
Void_t* rEALLOc();
@@ -927,6 +940,7 @@
void malloc_stats();
int mALLOPt();
struct mallinfo mALLINFo();
+# endif
#endif
/*
diff --git a/include/os.h b/include/os.h
index 0230a7f..e3645e0 100644
--- a/include/os.h
+++ b/include/os.h
@@ -217,9 +217,10 @@
* Get the size of a file
*
* @param fname Filename to check
- * @return size of file, or -1 if an error ocurred
+ * @param size size of file is returned if no error
+ * @return 0 on success or -1 if an error ocurred
*/
-ssize_t os_get_filesize(const char *fname);
+int os_get_filesize(const char *fname, loff_t *size);
/**
* Write a character to the controlling OS terminal
diff --git a/include/pci.h b/include/pci.h
index 2ff7365..d211351 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -623,6 +623,7 @@
extern struct pci_controller* pci_bus_to_hose(int bus);
extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
+extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
extern int pci_hose_scan(struct pci_controller *hose);
extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
diff --git a/include/phy.h b/include/phy.h
index b495077..d430ed0 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -41,6 +41,7 @@
PHY_INTERFACE_MODE_MII,
PHY_INTERFACE_MODE_GMII,
PHY_INTERFACE_MODE_SGMII,
+ PHY_INTERFACE_MODE_SGMII_2500,
PHY_INTERFACE_MODE_QSGMII,
PHY_INTERFACE_MODE_TBI,
PHY_INTERFACE_MODE_RMII,
@@ -57,6 +58,7 @@
[PHY_INTERFACE_MODE_MII] = "mii",
[PHY_INTERFACE_MODE_GMII] = "gmii",
[PHY_INTERFACE_MODE_SGMII] = "sgmii",
+ [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
[PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
[PHY_INTERFACE_MODE_TBI] = "tbi",
[PHY_INTERFACE_MODE_RMII] = "rmii",
diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h
index c2a772a..b0e4255 100644
--- a/include/power/max77686_pmic.h
+++ b/include/power/max77686_pmic.h
@@ -150,6 +150,7 @@
int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV);
int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode);
+int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV);
int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
#define MAX77686_LDO_VOLT_MAX_HEX 0x3f
@@ -159,6 +160,8 @@
#define MAX77686_LDO_MODE_STANDBY (0x01 << 0x06)
#define MAX77686_LDO_MODE_LPM (0x02 << 0x06)
#define MAX77686_LDO_MODE_ON (0x03 << 0x06)
+#define MAX77686_BUCK_VOLT_MAX_HEX 0x3f
+#define MAX77686_BUCK_VOLT_MASK 0x3f
#define MAX77686_BUCK_MODE_MASK 0x03
#define MAX77686_BUCK_MODE_SHIFT_1 0x00
#define MAX77686_BUCK_MODE_SHIFT_2 0x04
diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h
index 0002f1e..1118489 100644
--- a/include/power/pfuze100_pmic.h
+++ b/include/power/pfuze100_pmic.h
@@ -38,6 +38,86 @@
};
/*
+ * Buck Regulators
+ */
+
+/* SW1A/B/C Output Voltage Configuration */
+#define SW1x_0_300V 0
+#define SW1x_0_325V 1
+#define SW1x_0_350V 2
+#define SW1x_0_375V 3
+#define SW1x_0_400V 4
+#define SW1x_0_425V 5
+#define SW1x_0_450V 6
+#define SW1x_0_475V 7
+#define SW1x_0_500V 8
+#define SW1x_0_525V 9
+#define SW1x_0_550V 10
+#define SW1x_0_575V 11
+#define SW1x_0_600V 12
+#define SW1x_0_625V 13
+#define SW1x_0_650V 14
+#define SW1x_0_675V 15
+#define SW1x_0_700V 16
+#define SW1x_0_725V 17
+#define SW1x_0_750V 18
+#define SW1x_0_775V 19
+#define SW1x_0_800V 20
+#define SW1x_0_825V 21
+#define SW1x_0_850V 22
+#define SW1x_0_875V 23
+#define SW1x_0_900V 24
+#define SW1x_0_925V 25
+#define SW1x_0_950V 26
+#define SW1x_0_975V 27
+#define SW1x_1_000V 28
+#define SW1x_1_025V 29
+#define SW1x_1_050V 30
+#define SW1x_1_075V 31
+#define SW1x_1_100V 32
+#define SW1x_1_125V 33
+#define SW1x_1_150V 34
+#define SW1x_1_175V 35
+#define SW1x_1_200V 36
+#define SW1x_1_225V 37
+#define SW1x_1_250V 38
+#define SW1x_1_275V 39
+#define SW1x_1_300V 40
+#define SW1x_1_325V 41
+#define SW1x_1_350V 42
+#define SW1x_1_375V 43
+#define SW1x_1_400V 44
+#define SW1x_1_425V 45
+#define SW1x_1_450V 46
+#define SW1x_1_475V 47
+#define SW1x_1_500V 48
+#define SW1x_1_525V 49
+#define SW1x_1_550V 50
+#define SW1x_1_575V 51
+#define SW1x_1_600V 52
+#define SW1x_1_625V 53
+#define SW1x_1_650V 54
+#define SW1x_1_675V 55
+#define SW1x_1_700V 56
+#define SW1x_1_725V 57
+#define SW1x_1_750V 58
+#define SW1x_1_775V 59
+#define SW1x_1_800V 60
+#define SW1x_1_825V 61
+#define SW1x_1_850V 62
+#define SW1x_1_875V 63
+
+#define SW1x_NORMAL_MASK 0x3f
+#define SW1x_STBY_MASK 0x3f
+#define SW1x_OFF_MASK 0x3f
+
+#define SW1xCONF_DVSSPEED_MASK 0xc0
+#define SW1xCONF_DVSSPEED_2US 0x00
+#define SW1xCONF_DVSSPEED_4US 0x40
+#define SW1xCONF_DVSSPEED_8US 0x80
+#define SW1xCONF_DVSSPEED_16US 0xc0
+
+/*
* LDO Configuration
*/
diff --git a/include/sandboxfs.h b/include/sandboxfs.h
index e7c3262..4c7745d 100644
--- a/include/sandboxfs.h
+++ b/include/sandboxfs.h
@@ -20,14 +20,18 @@
int sandbox_fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
-long sandbox_fs_read_at(const char *filename, unsigned long pos,
- void *buffer, unsigned long maxsize);
+int sandbox_fs_read_at(const char *filename, loff_t pos, void *buffer,
+ loff_t maxsize, loff_t *actread);
+int sandbox_fs_write_at(const char *filename, loff_t pos, void *buffer,
+ loff_t maxsize, loff_t *actwrite);
void sandbox_fs_close(void);
int sandbox_fs_ls(const char *dirname);
int sandbox_fs_exists(const char *filename);
-int sandbox_fs_size(const char *filename);
-int fs_read_sandbox(const char *filename, void *buf, int offset, int len);
-int fs_write_sandbox(const char *filename, void *buf, int offset, int len);
+int sandbox_fs_size(const char *filename, loff_t *size);
+int fs_read_sandbox(const char *filename, void *buf, loff_t offset, loff_t len,
+ loff_t *actread);
+int fs_write_sandbox(const char *filename, void *buf, loff_t offset,
+ loff_t len, loff_t *actwrite);
#endif
diff --git a/include/sata.h b/include/sata.h
index 38f4b4a..fa61da8 100644
--- a/include/sata.h
+++ b/include/sata.h
@@ -3,12 +3,15 @@
#include <part.h>
int init_sata(int dev);
+int reset_sata(int dev);
int scan_sata(int dev);
ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer);
ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer);
int sata_initialize(void);
int __sata_initialize(void);
+int sata_stop(void);
+int __sata_stop(void);
int sata_port_status(int dev, int port);
extern block_dev_desc_t sata_dev_desc[];
diff --git a/include/spi.h b/include/spi.h
index aa0a48e..5b78271 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -534,18 +534,14 @@
int spi_chip_select(struct udevice *slave);
/**
- * spi_bind_device() - bind a device to a bus's chip select
- *
- * This binds a new device to an given chip select (which must be unused).
+ * spi_find_chip_select() - Find the slave attached to chip select
*
* @bus: SPI bus to search
- * @cs: Chip select to attach to
- * @drv_name: Name of driver to attach to this chip select
- * @dev_name: Name of the new device thus created
- * @devp: Returns the newly bound device
+ * @cs: Chip select to look for
+ * @devp: Returns the slave device if found
+ * @return 0 if found, -ENODEV on error
*/
-int spi_bind_device(struct udevice *bus, int cs, const char *drv_name,
- const char *dev_name, struct udevice **devp);
+int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp);
/**
* spi_ofdata_to_platdata() - decode standard SPI platform data
diff --git a/include/thermal.h b/include/thermal.h
new file mode 100644
index 0000000..5d6101b
--- /dev/null
+++ b/include/thermal.h
@@ -0,0 +1,42 @@
+/*
+ *
+ * (C) Copyright 2014 Freescale Semiconductor, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _THERMAL_H_
+#define _THERMAL_H_
+
+#include <dm.h>
+
+int thermal_get_temp(struct udevice *dev, int *temp);
+
+/**
+ * struct struct dm_thermal_ops - Driver model Thermal operations
+ *
+ * The uclass interface is implemented by all Thermal devices which use
+ * driver model.
+ */
+struct dm_thermal_ops {
+ /**
+ * Get the current temperature
+ *
+ * The device provided is the slave device. It's parent controller
+ * will be used to provide the communication.
+ *
+ * This must be called before doing any transfers with a Thermal slave.
+ * It will enable and initialize any Thermal hardware as necessary,
+ * and make sure that the SCK line is in the correct idle state. It is
+ * not allowed to claim the same bus for several slaves without
+ * releasing the bus in between.
+ *
+ * @dev: The Thermal device
+ *
+ * Returns: 0 if the bus was claimed successfully, or a negative value
+ * if it wasn't.
+ */
+ int (*get_temp)(struct udevice *dev, int *temp);
+};
+
+#endif /* _THERMAL_H_ */
diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h
index 1fd15f4..324fe72 100644
--- a/include/ubi_uboot.h
+++ b/include/ubi_uboot.h
@@ -51,6 +51,14 @@
#undef CONFIG_MTD_UBI_BLOCK
+/* ubi_init() disables returning error codes when built into the Linux
+ * kernel so that it doesn't hang the Linux kernel boot process. Since
+ * the U-Boot driver code depends on getting valid error codes from this
+ * function we just tell the UBI layer that we are building as a module
+ * (which only enables the additional error reporting).
+ */
+#define CONFIG_MTD_UBI_MODULE
+
#if !defined(CONFIG_MTD_UBI_BEB_LIMIT)
#define CONFIG_MTD_UBI_BEB_LIMIT 20
#endif
diff --git a/lib/asm-offsets.c b/lib/asm-offsets.c
index 129bc3e..580f763 100644
--- a/lib/asm-offsets.c
+++ b/lib/asm-offsets.c
@@ -31,6 +31,9 @@
#ifdef CONFIG_SYS_MALLOC_F_LEN
DEFINE(GD_MALLOC_BASE, offsetof(struct global_data, malloc_base));
#endif
+#ifdef CONFIG_X86
+ DEFINE(GD_BIST, offsetof(struct global_data, arch.bist));
+#endif
#if defined(CONFIG_ARM)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 9714620..7c7e673 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -73,6 +73,8 @@
COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
COMPAT(PARADE_PS8625, "parade,ps8625"),
COMPAT(COMPAT_INTEL_LPC, "intel,lpc"),
+ COMPAT(INTEL_MICROCODE, "intel,microcode"),
+ COMPAT(MEMORY_SPD, "memory-spd"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
@@ -355,9 +357,9 @@
slash = strrchr(prop, '/');
if (strcmp(slash + 1, find_name))
continue;
- for (p = name; *p; p++) {
- if (isdigit(*p)) {
- *seqp = simple_strtoul(p, NULL, 10);
+ for (p = name + strlen(name) - 1; p > name; p--) {
+ if (!isdigit(*p)) {
+ *seqp = simple_strtoul(p + 1, NULL, 10);
debug("Found seq %d\n", *seqp);
return 0;
}
@@ -485,6 +487,26 @@
return err;
}
+int fdtdec_get_int_array_count(const void *blob, int node,
+ const char *prop_name, u32 *array, int count)
+{
+ const u32 *cell;
+ int len, elems;
+ int i;
+
+ debug("%s: %s\n", __func__, prop_name);
+ cell = fdt_getprop(blob, node, prop_name, &len);
+ if (!cell)
+ return -FDT_ERR_NOTFOUND;
+ elems = len / sizeof(u32);
+ if (count > elems)
+ count = elems;
+ for (i = 0; i < count; i++)
+ array[i] = fdt32_to_cpu(cell[i]);
+
+ return count;
+}
+
const u32 *fdtdec_locate_array(const void *blob, int node,
const char *prop_name, int count)
{
@@ -669,20 +691,25 @@
return (char *)nodep;
}
-int fdtdec_decode_region(const void *blob, int node,
- const char *prop_name, void **ptrp, size_t *size)
+int fdtdec_decode_region(const void *blob, int node, const char *prop_name,
+ fdt_addr_t *basep, fdt_size_t *sizep)
{
const fdt_addr_t *cell;
int len;
- debug("%s: %s\n", __func__, prop_name);
+ debug("%s: %s: %s\n", __func__, fdt_get_name(blob, node, NULL),
+ prop_name);
cell = fdt_getprop(blob, node, prop_name, &len);
- if (!cell || (len != sizeof(fdt_addr_t) * 2))
+ if (!cell || (len < sizeof(fdt_addr_t) * 2)) {
+ debug("cell=%p, len=%d\n", cell, len);
return -1;
+ }
+
+ *basep = fdt_addr_to_cpu(*cell);
+ *sizep = fdt_size_to_cpu(cell[1]);
+ debug("%s: base=%08lx, size=%lx\n", __func__, (ulong)*basep,
+ (ulong)*sizep);
- *ptrp = map_sysmem(fdt_addr_to_cpu(*cell), *size);
- *size = fdt_size_to_cpu(cell[1]);
- debug("%s: size=%zx\n", __func__, *size);
return 0;
}
@@ -698,6 +725,7 @@
int fdtdec_read_fmap_entry(const void *blob, int node, const char *name,
struct fmap_entry *entry)
{
+ const char *prop;
u32 reg[2];
if (fdtdec_get_int_array(blob, node, "reg", reg, 2)) {
@@ -706,6 +734,13 @@
}
entry->offset = reg[0];
entry->length = reg[1];
+ entry->used = fdtdec_get_int(blob, node, "used", entry->length);
+ prop = fdt_getprop(blob, node, "compress", NULL);
+ entry->compress_algo = prop && !strcmp(prop, "lzo") ?
+ FMAP_COMPRESS_LZO : FMAP_COMPRESS_NONE;
+ prop = fdt_getprop(blob, node, "hash", &entry->hash_size);
+ entry->hash_algo = prop ? FMAP_HASH_SHA256 : FMAP_HASH_NONE;
+ entry->hash = (uint8_t *)prop;
return 0;
}
@@ -780,4 +815,65 @@
return 0;
}
+
+int fdtdec_decode_memory_region(const void *blob, int config_node,
+ const char *mem_type, const char *suffix,
+ fdt_addr_t *basep, fdt_size_t *sizep)
+{
+ char prop_name[50];
+ const char *mem;
+ fdt_size_t size, offset_size;
+ fdt_addr_t base, offset;
+ int node;
+
+ if (config_node == -1) {
+ config_node = fdt_path_offset(blob, "/config");
+ if (config_node < 0) {
+ debug("%s: Cannot find /config node\n", __func__);
+ return -ENOENT;
+ }
+ }
+ if (!suffix)
+ suffix = "";
+
+ snprintf(prop_name, sizeof(prop_name), "%s-memory%s", mem_type,
+ suffix);
+ mem = fdt_getprop(blob, config_node, prop_name, NULL);
+ if (!mem) {
+ debug("%s: No memory type for '%s', using /memory\n", __func__,
+ prop_name);
+ mem = "/memory";
+ }
+
+ node = fdt_path_offset(blob, mem);
+ if (node < 0) {
+ debug("%s: Failed to find node '%s': %s\n", __func__, mem,
+ fdt_strerror(node));
+ return -ENOENT;
+ }
+
+ /*
+ * Not strictly correct - the memory may have multiple banks. We just
+ * use the first
+ */
+ if (fdtdec_decode_region(blob, node, "reg", &base, &size)) {
+ debug("%s: Failed to decode memory region %s\n", __func__,
+ mem);
+ return -EINVAL;
+ }
+
+ snprintf(prop_name, sizeof(prop_name), "%s-offset%s", mem_type,
+ suffix);
+ if (fdtdec_decode_region(blob, config_node, prop_name, &offset,
+ &offset_size)) {
+ debug("%s: Failed to decode memory region '%s'\n", __func__,
+ prop_name);
+ return -EINVAL;
+ }
+
+ *basep = base + offset;
+ *sizep = offset_size;
+
+ return 0;
+}
#endif
diff --git a/lib/strmhz.c b/lib/strmhz.c
index f9a1772..5c16cc4 100644
--- a/lib/strmhz.c
+++ b/lib/strmhz.c
@@ -11,11 +11,11 @@
long l, n;
long m;
- n = DIV_ROUND(hz, 1000) / 1000L;
+ n = DIV_ROUND_CLOSEST(hz, 1000) / 1000L;
l = sprintf (buf, "%ld", n);
hz -= n * 1000000L;
- m = DIV_ROUND(hz, 1000L);
+ m = DIV_ROUND_CLOSEST(hz, 1000L);
if (m != 0)
sprintf (buf + l, ".%03ld", m);
return (buf);
diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index b585713..e0f2648 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -25,9 +25,6 @@
#include <div64.h>
#define noinline __attribute__((noinline))
-/* some reluctance to put this into a new limits.h, so it is here */
-#define INT_MAX ((int)(~0U>>1))
-
unsigned long simple_strtoul(const char *cp, char **endp,
unsigned int base)
{
@@ -518,6 +515,8 @@
static char *pointer(const char *fmt, char *buf, char *end, void *ptr,
int field_width, int precision, int flags)
{
+ u64 num = (uintptr_t)ptr;
+
/*
* Being a boot loader, we explicitly allow pointers to
* (physical) address null.
@@ -530,6 +529,17 @@
#ifdef CONFIG_CMD_NET
switch (*fmt) {
+ case 'a':
+ flags |= SPECIAL | ZEROPAD;
+
+ switch (fmt[1]) {
+ case 'p':
+ default:
+ field_width = sizeof(phys_addr_t) * 2 + 2;
+ num = *(phys_addr_t *)ptr;
+ break;
+ }
+ break;
case 'm':
flags |= SPECIAL;
/* Fallthrough */
@@ -555,8 +565,7 @@
field_width = 2*sizeof(void *);
flags |= ZEROPAD;
}
- return number(buf, end, (unsigned long)ptr, 16, field_width,
- precision, flags);
+ return number(buf, end, num, 16, field_width, precision, flags);
}
static int vsnprintf_internal(char *buf, size_t size, const char *fmt,
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 07db0bf..1905446 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -60,15 +60,13 @@
libs-y += $(CPUDIR)/
-ifdef SOC
-libs-y += $(CPUDIR)/$(SOC)/
-endif
libs-y += $(if $(BOARDDIR),board/$(BOARDDIR)/)
libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
libs-$(CONFIG_SPL_FRAMEWORK) += common/spl/
libs-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/
libs-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/
+libs-$(CONFIG_SPL_DM) += drivers/core/
libs-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/
libs-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/
libs-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/
@@ -80,7 +78,7 @@
libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
libs-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ drivers/power/pmic/
libs-$(CONFIG_SPL_MTD_SUPPORT) += drivers/mtd/
-libs-$(if $(CONFIG_CMD_NAND),$(CONFIG_SPL_NAND_SUPPORT)) += drivers/mtd/nand/
+libs-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/
libs-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += drivers/misc/
libs-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/
libs-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/
diff --git a/test/fs/fs-test.sh b/test/fs/fs-test.sh
new file mode 100755
index 0000000..a4fb055
--- /dev/null
+++ b/test/fs/fs-test.sh
@@ -0,0 +1,561 @@
+#!/bin/bash
+#
+# (C) Copyright 2014 Suriyan Ramasami
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Invoke this test script from U-Boot base directory as ./test/fs/fs-test.sh
+# It currently tests the fs/sb and native commands for ext4 and fat partitions
+# Expected results are as follows:
+# EXT4 tests:
+# fs-test.sb.ext4.out: Summary: PASS: 17 FAIL: 2
+# fs-test.ext4.out: Summary: PASS: 11 FAIL: 8
+# fs-test.fs.ext4.out: Summary: PASS: 11 FAIL: 8
+# FAT tests:
+# fs-test.sb.fat.out: Summary: PASS: 17 FAIL: 2
+# fs-test.fat.out: Summary: PASS: 19 FAIL: 0
+# fs-test.fs.fat.out: Summary: PASS: 19 FAIL: 0
+# Total Summary: TOTAL PASS: 94 TOTAL FAIL: 20
+
+# pre-requisite binaries list.
+PREREQ_BINS="md5sum mkfs mount umount dd fallocate mkdir"
+
+# All generated output files from this test will be in $OUT_DIR
+# Hence everything is sandboxed.
+OUT_DIR="sandbox/test/fs"
+
+# Location of generated sandbox u-boot
+UBOOT="./sandbox/u-boot"
+
+# Our mount directory will be in the sandbox
+MOUNT_DIR="${OUT_DIR}/mnt"
+
+# The file system image we create will have the $IMG prefix.
+IMG="${OUT_DIR}/3GB"
+
+# $SMALL_FILE is the name of the 1MB file in the file system image
+SMALL_FILE="1MB.file"
+
+# $BIG_FILE is the name of the 2.5GB file in the file system image
+BIG_FILE="2.5GB.file"
+
+# $MD5_FILE will have the expected md5s when we do the test
+# They shall have a suffix which represents their file system (ext4/fat)
+MD5_FILE="${OUT_DIR}/md5s.list"
+
+# $OUT shall be the prefix of the test output. Their suffix will be .out
+OUT="${OUT_DIR}/fs-test"
+
+# Full Path of the 1 MB file that shall be created in the fs image.
+MB1="${MOUNT_DIR}/${SMALL_FILE}"
+GB2p5="${MOUNT_DIR}/${BIG_FILE}"
+
+# ************************
+# * Functions start here *
+# ************************
+
+# Check if the prereq binaries exist, or exit
+function check_prereq() {
+ for prereq in $PREREQ_BINS; do
+ if [ ! -x `which $prereq` ]; then
+ echo "Missing $prereq binary. Exiting!"
+ exit
+ fi
+ done
+
+ # We use /dev/urandom to create files. Check if it exists.
+ if [ ! -c /dev/urandom ]; then
+ echo "Missing character special /dev/urandom. Exiting!"
+ exit
+ fi
+}
+
+# If 1st param is "clean", then clean out the generated files and exit
+function check_clean() {
+ if [ "$1" = "clean" ]; then
+ rm -rf "$OUT_DIR"
+ echo "Cleaned up generated files. Exiting"
+ exit
+ fi
+}
+
+# Generate sandbox U-Boot - gleaned from /test/dm/test-dm.sh
+function compile_sandbox() {
+ unset CROSS_COMPILE
+ NUM_CPUS=$(cat /proc/cpuinfo |grep -c processor)
+ make O=sandbox sandbox_config
+ make O=sandbox -s -j${NUM_CPUS}
+
+ # Check if U-Boot exists
+ if [ ! -x "$UBOOT" ]; then
+ echo "$UBOOT does not exist or is not executable"
+ echo "Build error?"
+ echo "Please run this script as ./test/fs/`basename $0`"
+ exit
+ fi
+}
+
+# Clean out all generated files other than the file system images
+# We save time by not deleting and recreating the file system images
+function prepare_env() {
+ rm -f ${MD5_FILE}.* ${OUT}.*
+ mkdir ${OUT_DIR}
+}
+
+# 1st parameter is the name of the image file to be created
+# 2nd parameter is the filesystem - fat ext4 etc
+# -F cant be used with fat as it means something else.
+function create_image() {
+ # Create image if not already present - saves time, while debugging
+ if [ "$2" = "ext4" ]; then
+ MKFS_OPTION="-F"
+ else
+ MKFS_OPTION=""
+ fi
+ if [ ! -f "$1" ]; then
+ fallocate -l 3G "$1" &> /dev/null
+ mkfs -t "$2" $MKFS_OPTION "$1" &> /dev/null
+ if [ $? -ne 0 -a "$2" = "fat" ]; then
+ # If we fail and we did fat, try vfat.
+ mkfs -t vfat $MKFS_OPTION "$1" &> /dev/null
+ fi
+ fi
+}
+
+# 1st parameter is the FS type: fat/ext4
+# 2nd parameter is the name of small file
+# Returns filename which can be used for fat or ext4 for writing
+function fname_for_write() {
+ case $1 in
+ ext4)
+ # ext4 needs absolute path name of file
+ echo /${2}.w
+ ;;
+
+ *)
+ echo ${2}.w
+ ;;
+ esac
+}
+
+# 1st parameter is image file
+# 2nd parameter is file system type - fat/ext4
+# 3rd parameter is name of small file
+# 4th parameter is name of big file
+# 5th parameter is fs/nonfs/sb - to dictate generic fs commands or
+# otherwise or sb hostfs
+# 6th parameter is the directory path for the files. Its "" for generic
+# fs and ext4/fat and full patch for sb hostfs
+# UBOOT is set in env
+function test_image() {
+ addr="0x01000008"
+ length="0x00100000"
+
+ case "$2" in
+ fat)
+ PREFIX="fat"
+ WRITE="write"
+ ;;
+
+ ext4)
+ PREFIX="ext4"
+ WRITE="write"
+ ;;
+
+ *)
+ echo "Unhandled filesystem $2. Exiting!"
+ exit
+ ;;
+ esac
+
+ case "$5" in
+ fs)
+ PREFIX=""
+ WRITE="save"
+ SUFFIX=" 0:0"
+ ;;
+
+ nonfs)
+ SUFFIX=" 0:0"
+ ;;
+
+ sb)
+ PREFIX="sb "
+ WRITE="save"
+ SUFFIX="fs -"
+ ;;
+
+ *)
+ echo "Unhandled mode $5. Exiting!"
+ exit
+ ;;
+
+ esac
+
+ if [ -z "$6" ]; then
+ FILE_WRITE=`fname_for_write $2 $3`
+ FILE_SMALL=$3
+ FILE_BIG=$4
+ else
+ FILE_WRITE=$6/`fname_for_write $2 $3`
+ FILE_SMALL=$6/$3
+ FILE_BIG=$6/$4
+ fi
+
+ # In u-boot commands, <interface> stands for host or hostfs
+ # hostfs maps to the host fs.
+ # host maps to the "sb bind" that we do
+
+ $UBOOT << EOF
+sb=$5
+setenv bind 'if test "\$sb" != sb; then sb bind 0 "$1"; fi'
+run bind
+# Test Case 1 - ls
+${PREFIX}ls host${SUFFIX} $6
+#
+# We want ${PREFIX}size host 0:0 $3 for host commands and
+# sb size hostfs - $3 for hostfs commands.
+# 1MB is 0x0010 0000
+# Test Case 2 - size of small file
+${PREFIX}size host${SUFFIX} $FILE_SMALL
+printenv filesize
+setenv filesize
+
+# 2.5GB (1024*1024*2500) is 0x9C40 0000
+# Test Case 3 - size of big file
+${PREFIX}size host${SUFFIX} $FILE_BIG
+printenv filesize
+setenv filesize
+
+# Notes about load operation
+# If I use 0x01000000 I get DMA misaligned error message
+# Last two parameters are size and offset.
+
+# Test Case 4a - Read full 1MB of small file
+${PREFIX}load host${SUFFIX} $addr $FILE_SMALL
+printenv filesize
+# Test Case 4b - Read full 1MB of small file
+md5sum $addr \$filesize
+setenv filesize
+
+# Test Case 5a - First 1MB of big file
+${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x0
+printenv filesize
+# Test Case 5b - First 1MB of big file
+md5sum $addr \$filesize
+setenv filesize
+
+# fails for ext as no offset support
+# Test Case 6a - Last 1MB of big file
+${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x9C300000
+printenv filesize
+# Test Case 6b - Last 1MB of big file
+md5sum $addr \$filesize
+setenv filesize
+
+# fails for ext as no offset support
+# Test Case 7a - One from the last 1MB chunk of 2GB
+${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x7FF00000
+printenv filesize
+# Test Case 7b - One from the last 1MB chunk of 2GB
+md5sum $addr \$filesize
+setenv filesize
+
+# fails for ext as no offset support
+# Test Case 8a - One from the start 1MB chunk from 2GB
+${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x80000000
+printenv filesize
+# Test Case 8b - One from the start 1MB chunk from 2GB
+md5sum $addr \$filesize
+setenv filesize
+
+# fails for ext as no offset support
+# Test Case 9a - One 1MB chunk crossing the 2GB boundary
+${PREFIX}load host${SUFFIX} $addr $FILE_BIG $length 0x7FF80000
+printenv filesize
+# Test Case 9b - One 1MB chunk crossing the 2GB boundary
+md5sum $addr \$filesize
+setenv filesize
+
+# Generic failure case
+# Test Case 10 - 2MB chunk from the last 1MB of big file
+${PREFIX}load host${SUFFIX} $addr $FILE_BIG 0x00200000 0x9C300000
+printenv filesize
+#
+
+# Read 1MB from small file
+${PREFIX}load host${SUFFIX} $addr $FILE_SMALL
+# Write it back to test the writes
+# Test Case 11a - Check that the write succeeded
+${PREFIX}${WRITE} host${SUFFIX} $addr $FILE_WRITE \$filesize
+mw.b $addr 00 100
+${PREFIX}load host${SUFFIX} $addr $FILE_WRITE
+# Test Case 11b - Check md5 of written to is same as the one read from
+md5sum $addr \$filesize
+setenv filesize
+#
+reset
+
+EOF
+}
+
+# 1st argument is the name of the image file.
+# 2nd argument is the file where we generate the md5s of the files
+# generated with the appropriate start and length that we use to test.
+# It creates the necessary files in the image to test.
+# $GB2p5 is the path of the big file (2.5 GB)
+# $MB1 is the path of the small file (1 MB)
+# $MOUNT_DIR is the path we can use to mount the image file.
+function create_files() {
+ # Mount the image so we can populate it.
+ mkdir -p "$MOUNT_DIR"
+ sudo mount -o loop,rw "$1" "$MOUNT_DIR"
+
+ # Create big file in this image.
+ # Note that we work only on the start 1MB, couple MBs in the 2GB range
+ # and the last 1 MB of the huge 2.5GB file.
+ # So, just put random values only in those areas.
+ if [ ! -f "${GB2p5}" ]; then
+ sudo dd if=/dev/urandom of="${GB2p5}" bs=1M count=1 \
+ &> /dev/null
+ sudo dd if=/dev/urandom of="${GB2p5}" bs=1M count=2 seek=2047 \
+ &> /dev/null
+ sudo dd if=/dev/urandom of="${GB2p5}" bs=1M count=1 seek=2499 \
+ &> /dev/null
+ fi
+
+ # Create a small file in this image.
+ if [ ! -f "${MB1}" ]; then
+ sudo dd if=/dev/urandom of="${MB1}" bs=1M count=1 \
+ &> /dev/null
+ fi
+
+ # Delete the small file which possibly is written as part of a
+ # previous test.
+ sudo rm -f "${MB1}.w"
+
+ # Generate the md5sums of reads that we will test against small file
+ dd if="${MB1}" bs=1M skip=0 count=1 2> /dev/null | md5sum > "$2"
+
+ # Generate the md5sums of reads that we will test against big file
+ # One from beginning of file.
+ dd if="${GB2p5}" bs=1M skip=0 count=1 \
+ 2> /dev/null | md5sum >> "$2"
+
+ # One from end of file.
+ dd if="${GB2p5}" bs=1M skip=2499 count=1 \
+ 2> /dev/null | md5sum >> "$2"
+
+ # One from the last 1MB chunk of 2GB
+ dd if="${GB2p5}" bs=1M skip=2047 count=1 \
+ 2> /dev/null | md5sum >> "$2"
+
+ # One from the start 1MB chunk from 2GB
+ dd if="${GB2p5}" bs=1M skip=2048 count=1 \
+ 2> /dev/null | md5sum >> "$2"
+
+ # One 1MB chunk crossing the 2GB boundary
+ dd if="${GB2p5}" bs=512K skip=4095 count=2 \
+ 2> /dev/null | md5sum >> "$2"
+
+ sync
+ sudo umount "$MOUNT_DIR"
+ rmdir "$MOUNT_DIR"
+}
+
+# 1st parameter is the text to print
+# if $? is 0 its a pass, else a fail
+# As a side effect it shall update env variable PASS and FAIL
+function pass_fail() {
+ if [ $? -eq 0 ]; then
+ echo pass - "$1"
+ PASS=$((PASS + 1))
+ else
+ echo FAIL - "$1"
+ FAIL=$((FAIL + 1))
+ fi
+}
+
+# 1st parameter is the string which leads to an md5 generation
+# 2nd parameter is the file we grep, for that string
+# 3rd parameter is the name of the file which has md5s in it
+# 4th parameter is the line # in the md5 file that we match it against
+# This function checks if the md5 of the file in the sandbox matches
+# that calculated while generating the file
+# 5th parameter is the string to print with the result
+check_md5() {
+ # md5sum in u-boot has output of form:
+ # md5 for 01000008 ... 01100007 ==> <md5>
+ # the 7th field is the actual md5
+ md5_src=`grep -A3 "$1" "$2" | grep "md5 for"`
+ md5_src=($md5_src)
+ md5_src=${md5_src[6]}
+
+ # The md5 list, each line is of the form:
+ # - <md5>
+ # the 2nd field is the actual md5
+ md5_dst=`sed -n $4p $3`
+ md5_dst=($md5_dst)
+ md5_dst=${md5_dst[0]}
+
+ # For a pass they should match.
+ [ "$md5_src" = "$md5_dst" ]
+ pass_fail "$5"
+}
+
+# 1st parameter is the name of the output file to check
+# 2nd parameter is the name of the file containing the md5 expected
+# 3rd parameter is the name of the small file
+# 4th parameter is the name of the big file
+# 5th paramter is the name of the written file
+# This function checks the output file for correct results.
+function check_results() {
+ echo "** Start $1"
+
+ PASS=0
+ FAIL=0
+
+ # Check if the ls is showing correct results for 2.5 gb file
+ grep -A6 "Test Case 1 " "$1" | egrep -iq "2621440000 *$4"
+ pass_fail "TC1: ls of $4"
+
+ # Check if the ls is showing correct results for 1 mb file
+ grep -A6 "Test Case 1 " "$1" | egrep -iq "1048576 *$3"
+ pass_fail "TC1: ls of $3"
+
+ # Check size command on 1MB.file
+ egrep -A3 "Test Case 2 " "$1" | grep -q "filesize=100000"
+ pass_fail "TC2: size of $3"
+
+ # Check size command on 2.5GB.file
+ egrep -A3 "Test Case 3 " "$1" | grep -q "filesize=9c400000"
+ pass_fail "TC3: size of $4"
+
+ # Check read full mb of 1MB.file
+ grep -A6 "Test Case 4a " "$1" | grep -q "filesize=100000"
+ pass_fail "TC4: load of $3 size"
+ check_md5 "Test Case 4b " "$1" "$2" 1 "TC4: load from $3"
+
+ # Check first mb of 2.5GB.file
+ grep -A6 "Test Case 5a " "$1" | grep -q "filesize=100000"
+ pass_fail "TC5: load of 1st MB from $4 size"
+ check_md5 "Test Case 5b " "$1" "$2" 2 "TC5: load of 1st MB from $4"
+
+ # Check last mb of 2.5GB.file
+ grep -A6 "Test Case 6a " "$1" | grep -q "filesize=100000"
+ pass_fail "TC6: load of last MB from $4 size"
+ check_md5 "Test Case 6b " "$1" "$2" 3 "TC6: load of last MB from $4"
+
+ # Check last 1mb chunk of 2gb from 2.5GB file
+ grep -A6 "Test Case 7a " "$1" | grep -q "filesize=100000"
+ pass_fail "TC7: load of last 1mb chunk of 2GB from $4 size"
+ check_md5 "Test Case 7b " "$1" "$2" 4 \
+ "TC7: load of last 1mb chunk of 2GB from $4"
+
+ # Check first 1mb chunk after 2gb from 2.5GB file
+ grep -A6 "Test Case 8a " "$1" | grep -q "filesize=100000"
+ pass_fail "TC8: load 1st MB chunk after 2GB from $4 size"
+ check_md5 "Test Case 8b " "$1" "$2" 5 \
+ "TC8: load 1st MB chunk after 2GB from $4"
+
+ # Check 1mb chunk crossing the 2gb boundary from 2.5GB file
+ grep -A6 "Test Case 9a " "$1" | grep -q "filesize=100000"
+ pass_fail "TC9: load 1MB chunk crossing 2GB boundary from $4 size"
+ check_md5 "Test Case 9b " "$1" "$2" 6 \
+ "TC9: load 1MB chunk crossing 2GB boundary from $4"
+
+ # Check 2mb chunk from the last 1MB of 2.5GB file - generic failure case
+ grep -A6 "Test Case 10 " "$1" | grep -q 'Error: "filesize" not defined'
+ pass_fail "TC10: load 2MB from the last 1MB of $4 - generic fail case"
+
+ # Check 1mb chunk write
+ grep -A3 "Test Case 11a " "$1" | \
+ egrep -q '1048576 bytes written|update journal'
+ pass_fail "TC11: 1MB write to $5 - write succeeded"
+ check_md5 "Test Case 11b " "$1" "$2" 1 \
+ "TC11: 1MB write to $5 - content verified"
+ echo "** End $1"
+}
+
+# Takes in one parameter which is "fs" or "nonfs", which then dictates
+# if a fs test (size/load/save) or a nonfs test (fatread/extread) needs to
+# be performed.
+function test_fs_nonfs() {
+ echo "Creating files in $fs image if not already present."
+ create_files $IMAGE $MD5_FILE_FS
+
+ OUT_FILE="${OUT}.fs.${fs}.out"
+ test_image $IMAGE $fs $SMALL_FILE $BIG_FILE $1 "" \
+ > ${OUT_FILE}
+ check_results $OUT_FILE $MD5_FILE_FS $SMALL_FILE $BIG_FILE \
+ $WRITE_FILE
+ TOTAL_FAIL=$((TOTAL_FAIL + FAIL))
+ TOTAL_PASS=$((TOTAL_PASS + PASS))
+ echo "Summary: PASS: $PASS FAIL: $FAIL"
+ echo "--------------------------------------------"
+}
+
+# ********************
+# * End of functions *
+# ********************
+
+check_clean "$1"
+check_prereq
+compile_sandbox
+prepare_env
+
+# Track TOTAL_FAIL and TOTAL_PASS
+TOTAL_FAIL=0
+TOTAL_PASS=0
+
+# In each loop, for a given file system image, we test both the
+# fs command, like load/size/write, the file system specific command
+# like: ext4load/ext4size/ext4write and the sb load/ls/save commands.
+for fs in ext4 fat; do
+
+ echo "Creating $fs image if not already present."
+ IMAGE=${IMG}.${fs}.img
+ MD5_FILE_FS="${MD5_FILE}.${fs}"
+ create_image $IMAGE $fs
+
+ # sb commands test
+ echo "Creating files in $fs image if not already present."
+ create_files $IMAGE $MD5_FILE_FS
+
+ # Lets mount the image and test sb hostfs commands
+ mkdir -p "$MOUNT_DIR"
+ if [ "$fs" = "fat" ]; then
+ uid="uid=`id -u`"
+ else
+ uid=""
+ fi
+ sudo mount -o loop,rw,$uid "$IMAGE" "$MOUNT_DIR"
+ sudo chmod 777 "$MOUNT_DIR"
+
+ OUT_FILE="${OUT}.sb.${fs}.out"
+ test_image $IMAGE $fs $SMALL_FILE $BIG_FILE sb `pwd`/$MOUNT_DIR \
+ > ${OUT_FILE}
+ sudo umount "$MOUNT_DIR"
+ rmdir "$MOUNT_DIR"
+
+ check_results $OUT_FILE $MD5_FILE_FS $SMALL_FILE $BIG_FILE \
+ $WRITE_FILE
+ TOTAL_FAIL=$((TOTAL_FAIL + FAIL))
+ TOTAL_PASS=$((TOTAL_PASS + PASS))
+ echo "Summary: PASS: $PASS FAIL: $FAIL"
+ echo "--------------------------------------------"
+
+ test_fs_nonfs nonfs
+ test_fs_nonfs fs
+done
+
+echo "Total Summary: TOTAL PASS: $TOTAL_PASS TOTAL FAIL: $TOTAL_FAIL"
+echo "--------------------------------------------"
+if [ $TOTAL_FAIL -eq 0 ]; then
+ echo "PASSED"
+ exit 0
+else
+ echo "FAILED"
+ exit 1
+fi
diff --git a/tools/Makefile b/tools/Makefile
index c422b76..a4216a1 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -126,6 +126,8 @@
hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl
HOSTCFLAGS_mkexynosspl.o := -pedantic
+hostprogs-$(CONFIG_X86) += ifdtool
+
hostprogs-$(CONFIG_MX23) += mxsboot
hostprogs-$(CONFIG_MX28) += mxsboot
HOSTCFLAGS_mxsboot.o := -pedantic
diff --git a/tools/ifdtool.c b/tools/ifdtool.c
new file mode 100644
index 0000000..a4b481f
--- /dev/null
+++ b/tools/ifdtool.c
@@ -0,0 +1,1039 @@
+/*
+ * ifdtool - Manage Intel Firmware Descriptor information
+ *
+ * Copyright 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * From Coreboot project, but it got a serious code clean-up
+ * and a few new features
+ */
+
+#include <assert.h>
+#include <fcntl.h>
+#include <getopt.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include "ifdtool.h"
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define debug(fmt, args...) printf(fmt, ##args)
+#else
+#define debug(fmt, args...)
+#endif
+
+#define FD_SIGNATURE 0x0FF0A55A
+#define FLREG_BASE(reg) ((reg & 0x00000fff) << 12);
+#define FLREG_LIMIT(reg) (((reg & 0x0fff0000) >> 4) | 0xfff);
+
+/**
+ * find_fd() - Find the flash description in the ROM image
+ *
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ * @return pointer to structure, or NULL if not found
+ */
+static struct fdbar_t *find_fd(char *image, int size)
+{
+ uint32_t *ptr, *end;
+
+ /* Scan for FD signature */
+ for (ptr = (uint32_t *)image, end = ptr + size / 4; ptr < end; ptr++) {
+ if (*ptr == FD_SIGNATURE)
+ break;
+ }
+
+ if (ptr == end) {
+ printf("No Flash Descriptor found in this image\n");
+ return NULL;
+ }
+
+ debug("Found Flash Descriptor signature at 0x%08x\n", i);
+
+ return (struct fdbar_t *)ptr;
+}
+
+/**
+ * get_region() - Get information about the selected region
+ *
+ * @frba: Flash region list
+ * @region_type: Type of region (0..MAX_REGIONS-1)
+ * @region: Region information is written here
+ * @return 0 if OK, else -ve
+ */
+static int get_region(struct frba_t *frba, int region_type,
+ struct region_t *region)
+{
+ if (region_type >= MAX_REGIONS) {
+ fprintf(stderr, "Invalid region type.\n");
+ return -1;
+ }
+
+ region->base = FLREG_BASE(frba->flreg[region_type]);
+ region->limit = FLREG_LIMIT(frba->flreg[region_type]);
+ region->size = region->limit - region->base + 1;
+
+ return 0;
+}
+
+static const char *region_name(int region_type)
+{
+ static const char *const regions[] = {
+ "Flash Descriptor",
+ "BIOS",
+ "Intel ME",
+ "GbE",
+ "Platform Data"
+ };
+
+ assert(region_type < MAX_REGIONS);
+
+ return regions[region_type];
+}
+
+static const char *region_filename(int region_type)
+{
+ static const char *const region_filenames[] = {
+ "flashregion_0_flashdescriptor.bin",
+ "flashregion_1_bios.bin",
+ "flashregion_2_intel_me.bin",
+ "flashregion_3_gbe.bin",
+ "flashregion_4_platform_data.bin"
+ };
+
+ assert(region_type < MAX_REGIONS);
+
+ return region_filenames[region_type];
+}
+
+static int dump_region(int num, struct frba_t *frba)
+{
+ struct region_t region;
+ int ret;
+
+ ret = get_region(frba, num, ®ion);
+ if (ret)
+ return ret;
+
+ printf(" Flash Region %d (%s): %08x - %08x %s\n",
+ num, region_name(num), region.base, region.limit,
+ region.size < 1 ? "(unused)" : "");
+
+ return ret;
+}
+
+static void dump_frba(struct frba_t *frba)
+{
+ int i;
+
+ printf("Found Region Section\n");
+ for (i = 0; i < MAX_REGIONS; i++) {
+ printf("FLREG%d: 0x%08x\n", i, frba->flreg[i]);
+ dump_region(i, frba);
+ }
+}
+
+static void decode_spi_frequency(unsigned int freq)
+{
+ switch (freq) {
+ case SPI_FREQUENCY_20MHZ:
+ printf("20MHz");
+ break;
+ case SPI_FREQUENCY_33MHZ:
+ printf("33MHz");
+ break;
+ case SPI_FREQUENCY_50MHZ:
+ printf("50MHz");
+ break;
+ default:
+ printf("unknown<%x>MHz", freq);
+ }
+}
+
+static void decode_component_density(unsigned int density)
+{
+ switch (density) {
+ case COMPONENT_DENSITY_512KB:
+ printf("512KiB");
+ break;
+ case COMPONENT_DENSITY_1MB:
+ printf("1MiB");
+ break;
+ case COMPONENT_DENSITY_2MB:
+ printf("2MiB");
+ break;
+ case COMPONENT_DENSITY_4MB:
+ printf("4MiB");
+ break;
+ case COMPONENT_DENSITY_8MB:
+ printf("8MiB");
+ break;
+ case COMPONENT_DENSITY_16MB:
+ printf("16MiB");
+ break;
+ default:
+ printf("unknown<%x>MiB", density);
+ }
+}
+
+static void dump_fcba(struct fcba_t *fcba)
+{
+ printf("\nFound Component Section\n");
+ printf("FLCOMP 0x%08x\n", fcba->flcomp);
+ printf(" Dual Output Fast Read Support: %ssupported\n",
+ (fcba->flcomp & (1 << 30)) ? "" : "not ");
+ printf(" Read ID/Read Status Clock Frequency: ");
+ decode_spi_frequency((fcba->flcomp >> 27) & 7);
+ printf("\n Write/Erase Clock Frequency: ");
+ decode_spi_frequency((fcba->flcomp >> 24) & 7);
+ printf("\n Fast Read Clock Frequency: ");
+ decode_spi_frequency((fcba->flcomp >> 21) & 7);
+ printf("\n Fast Read Support: %ssupported",
+ (fcba->flcomp & (1 << 20)) ? "" : "not ");
+ printf("\n Read Clock Frequency: ");
+ decode_spi_frequency((fcba->flcomp >> 17) & 7);
+ printf("\n Component 2 Density: ");
+ decode_component_density((fcba->flcomp >> 3) & 7);
+ printf("\n Component 1 Density: ");
+ decode_component_density(fcba->flcomp & 7);
+ printf("\n");
+ printf("FLILL 0x%08x\n", fcba->flill);
+ printf(" Invalid Instruction 3: 0x%02x\n",
+ (fcba->flill >> 24) & 0xff);
+ printf(" Invalid Instruction 2: 0x%02x\n",
+ (fcba->flill >> 16) & 0xff);
+ printf(" Invalid Instruction 1: 0x%02x\n",
+ (fcba->flill >> 8) & 0xff);
+ printf(" Invalid Instruction 0: 0x%02x\n",
+ fcba->flill & 0xff);
+ printf("FLPB 0x%08x\n", fcba->flpb);
+ printf(" Flash Partition Boundary Address: 0x%06x\n\n",
+ (fcba->flpb & 0xfff) << 12);
+}
+
+static void dump_fpsba(struct fpsba_t *fpsba)
+{
+ int i;
+
+ printf("Found PCH Strap Section\n");
+ for (i = 0; i < MAX_STRAPS; i++)
+ printf("PCHSTRP%-2d: 0x%08x\n", i, fpsba->pchstrp[i]);
+}
+
+static const char *get_enabled(int flag)
+{
+ return flag ? "enabled" : "disabled";
+}
+
+static void decode_flmstr(uint32_t flmstr)
+{
+ printf(" Platform Data Region Write Access: %s\n",
+ get_enabled(flmstr & (1 << 28)));
+ printf(" GbE Region Write Access: %s\n",
+ get_enabled(flmstr & (1 << 27)));
+ printf(" Intel ME Region Write Access: %s\n",
+ get_enabled(flmstr & (1 << 26)));
+ printf(" Host CPU/BIOS Region Write Access: %s\n",
+ get_enabled(flmstr & (1 << 25)));
+ printf(" Flash Descriptor Write Access: %s\n",
+ get_enabled(flmstr & (1 << 24)));
+
+ printf(" Platform Data Region Read Access: %s\n",
+ get_enabled(flmstr & (1 << 20)));
+ printf(" GbE Region Read Access: %s\n",
+ get_enabled(flmstr & (1 << 19)));
+ printf(" Intel ME Region Read Access: %s\n",
+ get_enabled(flmstr & (1 << 18)));
+ printf(" Host CPU/BIOS Region Read Access: %s\n",
+ get_enabled(flmstr & (1 << 17)));
+ printf(" Flash Descriptor Read Access: %s\n",
+ get_enabled(flmstr & (1 << 16)));
+
+ printf(" Requester ID: 0x%04x\n\n",
+ flmstr & 0xffff);
+}
+
+static void dump_fmba(struct fmba_t *fmba)
+{
+ printf("Found Master Section\n");
+ printf("FLMSTR1: 0x%08x (Host CPU/BIOS)\n", fmba->flmstr1);
+ decode_flmstr(fmba->flmstr1);
+ printf("FLMSTR2: 0x%08x (Intel ME)\n", fmba->flmstr2);
+ decode_flmstr(fmba->flmstr2);
+ printf("FLMSTR3: 0x%08x (GbE)\n", fmba->flmstr3);
+ decode_flmstr(fmba->flmstr3);
+}
+
+static void dump_fmsba(struct fmsba_t *fmsba)
+{
+ int i;
+
+ printf("Found Processor Strap Section\n");
+ for (i = 0; i < 4; i++)
+ printf("????: 0x%08x\n", fmsba->data[0]);
+}
+
+static void dump_jid(uint32_t jid)
+{
+ printf(" SPI Component Device ID 1: 0x%02x\n",
+ (jid >> 16) & 0xff);
+ printf(" SPI Component Device ID 0: 0x%02x\n",
+ (jid >> 8) & 0xff);
+ printf(" SPI Component Vendor ID: 0x%02x\n",
+ jid & 0xff);
+}
+
+static void dump_vscc(uint32_t vscc)
+{
+ printf(" Lower Erase Opcode: 0x%02x\n",
+ vscc >> 24);
+ printf(" Lower Write Enable on Write Status: 0x%02x\n",
+ vscc & (1 << 20) ? 0x06 : 0x50);
+ printf(" Lower Write Status Required: %s\n",
+ vscc & (1 << 19) ? "Yes" : "No");
+ printf(" Lower Write Granularity: %d bytes\n",
+ vscc & (1 << 18) ? 64 : 1);
+ printf(" Lower Block / Sector Erase Size: ");
+ switch ((vscc >> 16) & 0x3) {
+ case 0:
+ printf("256 Byte\n");
+ break;
+ case 1:
+ printf("4KB\n");
+ break;
+ case 2:
+ printf("8KB\n");
+ break;
+ case 3:
+ printf("64KB\n");
+ break;
+ }
+
+ printf(" Upper Erase Opcode: 0x%02x\n",
+ (vscc >> 8) & 0xff);
+ printf(" Upper Write Enable on Write Status: 0x%02x\n",
+ vscc & (1 << 4) ? 0x06 : 0x50);
+ printf(" Upper Write Status Required: %s\n",
+ vscc & (1 << 3) ? "Yes" : "No");
+ printf(" Upper Write Granularity: %d bytes\n",
+ vscc & (1 << 2) ? 64 : 1);
+ printf(" Upper Block / Sector Erase Size: ");
+ switch (vscc & 0x3) {
+ case 0:
+ printf("256 Byte\n");
+ break;
+ case 1:
+ printf("4KB\n");
+ break;
+ case 2:
+ printf("8KB\n");
+ break;
+ case 3:
+ printf("64KB\n");
+ break;
+ }
+}
+
+static void dump_vtba(struct vtba_t *vtba, int vtl)
+{
+ int i;
+ int num = (vtl >> 1) < 8 ? (vtl >> 1) : 8;
+
+ printf("ME VSCC table:\n");
+ for (i = 0; i < num; i++) {
+ printf(" JID%d: 0x%08x\n", i, vtba->entry[i].jid);
+ dump_jid(vtba->entry[i].jid);
+ printf(" VSCC%d: 0x%08x\n", i, vtba->entry[i].vscc);
+ dump_vscc(vtba->entry[i].vscc);
+ }
+ printf("\n");
+}
+
+static void dump_oem(uint8_t *oem)
+{
+ int i, j;
+ printf("OEM Section:\n");
+ for (i = 0; i < 4; i++) {
+ printf("%02x:", i << 4);
+ for (j = 0; j < 16; j++)
+ printf(" %02x", oem[(i<<4)+j]);
+ printf("\n");
+ }
+ printf("\n");
+}
+
+/**
+ * dump_fd() - Display a dump of the full flash description
+ *
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ * @return 0 if OK, -1 on error
+ */
+static int dump_fd(char *image, int size)
+{
+ struct fdbar_t *fdb = find_fd(image, size);
+
+ if (!fdb)
+ return -1;
+
+ printf("FLMAP0: 0x%08x\n", fdb->flmap0);
+ printf(" NR: %d\n", (fdb->flmap0 >> 24) & 7);
+ printf(" FRBA: 0x%x\n", ((fdb->flmap0 >> 16) & 0xff) << 4);
+ printf(" NC: %d\n", ((fdb->flmap0 >> 8) & 3) + 1);
+ printf(" FCBA: 0x%x\n", ((fdb->flmap0) & 0xff) << 4);
+
+ printf("FLMAP1: 0x%08x\n", fdb->flmap1);
+ printf(" ISL: 0x%02x\n", (fdb->flmap1 >> 24) & 0xff);
+ printf(" FPSBA: 0x%x\n", ((fdb->flmap1 >> 16) & 0xff) << 4);
+ printf(" NM: %d\n", (fdb->flmap1 >> 8) & 3);
+ printf(" FMBA: 0x%x\n", ((fdb->flmap1) & 0xff) << 4);
+
+ printf("FLMAP2: 0x%08x\n", fdb->flmap2);
+ printf(" PSL: 0x%04x\n", (fdb->flmap2 >> 8) & 0xffff);
+ printf(" FMSBA: 0x%x\n", ((fdb->flmap2) & 0xff) << 4);
+
+ printf("FLUMAP1: 0x%08x\n", fdb->flumap1);
+ printf(" Intel ME VSCC Table Length (VTL): %d\n",
+ (fdb->flumap1 >> 8) & 0xff);
+ printf(" Intel ME VSCC Table Base Address (VTBA): 0x%06x\n\n",
+ (fdb->flumap1 & 0xff) << 4);
+ dump_vtba((struct vtba_t *)
+ (image + ((fdb->flumap1 & 0xff) << 4)),
+ (fdb->flumap1 >> 8) & 0xff);
+ dump_oem((uint8_t *)image + 0xf00);
+ dump_frba((struct frba_t *)(image + (((fdb->flmap0 >> 16) & 0xff)
+ << 4)));
+ dump_fcba((struct fcba_t *)(image + (((fdb->flmap0) & 0xff) << 4)));
+ dump_fpsba((struct fpsba_t *)
+ (image + (((fdb->flmap1 >> 16) & 0xff) << 4)));
+ dump_fmba((struct fmba_t *)(image + (((fdb->flmap1) & 0xff) << 4)));
+ dump_fmsba((struct fmsba_t *)(image + (((fdb->flmap2) & 0xff) << 4)));
+
+ return 0;
+}
+
+/**
+ * write_regions() - Write each region from an image to its own file
+ *
+ * The filename to use in each case is fixed - see region_filename()
+ *
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ * @return 0 if OK, -ve on error
+ */
+static int write_regions(char *image, int size)
+{
+ struct fdbar_t *fdb;
+ struct frba_t *frba;
+ int ret = 0;
+ int i;
+
+ fdb = find_fd(image, size);
+ if (!fdb)
+ return -1;
+
+ frba = (struct frba_t *)(image + (((fdb->flmap0 >> 16) & 0xff) << 4));
+
+ for (i = 0; i < MAX_REGIONS; i++) {
+ struct region_t region;
+ int region_fd;
+
+ ret = get_region(frba, i, ®ion);
+ if (ret)
+ return ret;
+ dump_region(i, frba);
+ if (region.size == 0)
+ continue;
+ region_fd = open(region_filename(i),
+ O_WRONLY | O_CREAT | O_TRUNC, S_IRUSR |
+ S_IWUSR | S_IRGRP | S_IROTH);
+ if (write(region_fd, image + region.base, region.size) !=
+ region.size) {
+ perror("Error while writing");
+ ret = -1;
+ }
+ close(region_fd);
+ }
+
+ return ret;
+}
+
+/**
+ * write_image() - Write the image to a file
+ *
+ * @filename: Filename to use for the image
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ * @return 0 if OK, -ve on error
+ */
+static int write_image(char *filename, char *image, int size)
+{
+ int new_fd;
+
+ debug("Writing new image to %s\n", filename);
+
+ new_fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC, S_IRUSR |
+ S_IWUSR | S_IRGRP | S_IROTH);
+ if (write(new_fd, image, size) != size) {
+ perror("Error while writing");
+ return -1;
+ }
+ close(new_fd);
+
+ return 0;
+}
+
+/**
+ * set_spi_frequency() - Set the SPI frequency to use when booting
+ *
+ * Several frequencies are supported, some of which work with fast devices.
+ * For SPI emulators, the slowest (SPI_FREQUENCY_20MHZ) is often used. The
+ * Intel boot system uses this information somehow on boot.
+ *
+ * The image is updated with the supplied value
+ *
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ * @freq: SPI frequency to use
+ */
+static void set_spi_frequency(char *image, int size, enum spi_frequency freq)
+{
+ struct fdbar_t *fdb = find_fd(image, size);
+ struct fcba_t *fcba;
+
+ fcba = (struct fcba_t *)(image + (((fdb->flmap0) & 0xff) << 4));
+
+ /* clear bits 21-29 */
+ fcba->flcomp &= ~0x3fe00000;
+ /* Read ID and Read Status Clock Frequency */
+ fcba->flcomp |= freq << 27;
+ /* Write and Erase Clock Frequency */
+ fcba->flcomp |= freq << 24;
+ /* Fast Read Clock Frequency */
+ fcba->flcomp |= freq << 21;
+}
+
+/**
+ * set_em100_mode() - Set a SPI frequency that will work with Dediprog EM100
+ *
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ */
+static void set_em100_mode(char *image, int size)
+{
+ struct fdbar_t *fdb = find_fd(image, size);
+ struct fcba_t *fcba;
+
+ fcba = (struct fcba_t *)(image + (((fdb->flmap0) & 0xff) << 4));
+ fcba->flcomp &= ~(1 << 30);
+ set_spi_frequency(image, size, SPI_FREQUENCY_20MHZ);
+}
+
+/**
+ * lock_descriptor() - Lock the NE descriptor so it cannot be updated
+ *
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ */
+static void lock_descriptor(char *image, int size)
+{
+ struct fdbar_t *fdb = find_fd(image, size);
+ struct fmba_t *fmba;
+
+ /*
+ * TODO: Dynamically take Platform Data Region and GbE Region into
+ * account.
+ */
+ fmba = (struct fmba_t *)(image + (((fdb->flmap1) & 0xff) << 4));
+ fmba->flmstr1 = 0x0a0b0000;
+ fmba->flmstr2 = 0x0c0d0000;
+ fmba->flmstr3 = 0x08080118;
+}
+
+/**
+ * unlock_descriptor() - Lock the NE descriptor so it can be updated
+ *
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ */
+static void unlock_descriptor(char *image, int size)
+{
+ struct fdbar_t *fdb = find_fd(image, size);
+ struct fmba_t *fmba;
+
+ fmba = (struct fmba_t *)(image + (((fdb->flmap1) & 0xff) << 4));
+ fmba->flmstr1 = 0xffff0000;
+ fmba->flmstr2 = 0xffff0000;
+ fmba->flmstr3 = 0x08080118;
+}
+
+/**
+ * open_for_read() - Open a file for reading
+ *
+ * @fname: Filename to open
+ * @sizep: Returns file size in bytes
+ * @return 0 if OK, -1 on error
+ */
+int open_for_read(const char *fname, int *sizep)
+{
+ int fd = open(fname, O_RDONLY);
+ struct stat buf;
+
+ if (fd == -1) {
+ perror("Could not open file");
+ return -1;
+ }
+ if (fstat(fd, &buf) == -1) {
+ perror("Could not stat file");
+ return -1;
+ }
+ *sizep = buf.st_size;
+ debug("File %s is %d bytes\n", fname, *sizep);
+
+ return fd;
+}
+
+/**
+ * inject_region() - Add a file to an image region
+ *
+ * This puts a file into a particular region of the flash. Several pre-defined
+ * regions are used.
+ *
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ * @region_type: Region where the file should be added
+ * @region_fname: Filename to add to the image
+ * @return 0 if OK, -ve on error
+ */
+int inject_region(char *image, int size, int region_type, char *region_fname)
+{
+ struct fdbar_t *fdb = find_fd(image, size);
+ struct region_t region;
+ struct frba_t *frba;
+ int region_size;
+ int offset = 0;
+ int region_fd;
+ int ret;
+
+ if (!fdb)
+ exit(EXIT_FAILURE);
+ frba = (struct frba_t *)(image + (((fdb->flmap0 >> 16) & 0xff) << 4));
+
+ ret = get_region(frba, region_type, ®ion);
+ if (ret)
+ return -1;
+ if (region.size <= 0xfff) {
+ fprintf(stderr, "Region %s is disabled in target. Not injecting.\n",
+ region_name(region_type));
+ return -1;
+ }
+
+ region_fd = open_for_read(region_fname, ®ion_size);
+ if (region_fd < 0)
+ return region_fd;
+
+ if ((region_size > region.size) ||
+ ((region_type != 1) && (region_size > region.size))) {
+ fprintf(stderr, "Region %s is %d(0x%x) bytes. File is %d(0x%x) bytes. Not injecting.\n",
+ region_name(region_type), region.size,
+ region.size, region_size, region_size);
+ return -1;
+ }
+
+ if ((region_type == 1) && (region_size < region.size)) {
+ fprintf(stderr, "Region %s is %d(0x%x) bytes. File is %d(0x%x) bytes. Padding before injecting.\n",
+ region_name(region_type), region.size,
+ region.size, region_size, region_size);
+ offset = region.size - region_size;
+ memset(image + region.base, 0xff, offset);
+ }
+
+ if (size < region.base + offset + region_size) {
+ fprintf(stderr, "Output file is too small. (%d < %d)\n",
+ size, region.base + offset + region_size);
+ return -1;
+ }
+
+ if (read(region_fd, image + region.base + offset, region_size)
+ != region_size) {
+ perror("Could not read file");
+ return -1;
+ }
+
+ close(region_fd);
+
+ debug("Adding %s as the %s section\n", region_fname,
+ region_name(region_type));
+
+ return 0;
+}
+
+/**
+ * write_data() - Write some raw data into a region
+ *
+ * This puts a file into a particular place in the flash, ignoring the
+ * regions. Be careful not to overwrite something important.
+ *
+ * @image: Pointer to image
+ * @size: Size of image in bytes
+ * @addr: x86 ROM address to put file. The ROM ends at
+ * 0xffffffff so use an address relative to that. For an
+ * 8MB ROM the start address is 0xfff80000.
+ * @write_fname: Filename to add to the image
+ * @return 0 if OK, -ve on error
+ */
+static int write_data(char *image, int size, unsigned int addr,
+ const char *write_fname)
+{
+ int write_fd, write_size;
+ int offset;
+
+ write_fd = open_for_read(write_fname, &write_size);
+ if (write_fd < 0)
+ return write_fd;
+
+ offset = addr + size;
+ debug("Writing %s to offset %#x\n", write_fname, offset);
+
+ if (offset < 0 || offset + write_size > size) {
+ fprintf(stderr, "Output file is too small. (%d < %d)\n",
+ size, offset + write_size);
+ return -1;
+ }
+
+ if (read(write_fd, image + offset, write_size) != write_size) {
+ perror("Could not read file");
+ return -1;
+ }
+
+ close(write_fd);
+
+ return 0;
+}
+
+static void print_version(void)
+{
+ printf("ifdtool v%s -- ", IFDTOOL_VERSION);
+ printf("Copyright (C) 2014 Google Inc.\n\n");
+ printf("SPDX-License-Identifier: GPL-2.0+\n");
+}
+
+static void print_usage(const char *name)
+{
+ printf("usage: %s [-vhdix?] <filename> [<outfile>]\n", name);
+ printf("\n"
+ " -d | --dump: dump intel firmware descriptor\n"
+ " -x | --extract: extract intel fd modules\n"
+ " -i | --inject <region>:<module> inject file <module> into region <region>\n"
+ " -w | --write <addr>:<file> write file to appear at memory address <addr>\n"
+ " -s | --spifreq <20|33|50> set the SPI frequency\n"
+ " -e | --em100 set SPI frequency to 20MHz and disable\n"
+ " Dual Output Fast Read Support\n"
+ " -l | --lock Lock firmware descriptor and ME region\n"
+ " -u | --unlock Unlock firmware descriptor and ME region\n"
+ " -r | --romsize Specify ROM size\n"
+ " -D | --write-descriptor <file> Write descriptor at base\n"
+ " -c | --create Create a new empty image\n"
+ " -v | --version: print the version\n"
+ " -h | --help: print this help\n\n"
+ "<region> is one of Descriptor, BIOS, ME, GbE, Platform\n"
+ "\n");
+}
+
+/**
+ * get_two_words() - Convert a string into two words separated by :
+ *
+ * The supplied string is split at ':', two substrings are allocated and
+ * returned.
+ *
+ * @str: String to split
+ * @firstp: Returns first string
+ * @secondp: Returns second string
+ * @return 0 if OK, -ve if @str does not have a :
+ */
+static int get_two_words(const char *str, char **firstp, char **secondp)
+{
+ const char *p;
+
+ p = strchr(str, ':');
+ if (!p)
+ return -1;
+ *firstp = strdup(str);
+ (*firstp)[p - str] = '\0';
+ *secondp = strdup(p + 1);
+
+ return 0;
+}
+
+int main(int argc, char *argv[])
+{
+ int opt, option_index = 0;
+ int mode_dump = 0, mode_extract = 0, mode_inject = 0;
+ int mode_spifreq = 0, mode_em100 = 0, mode_locked = 0;
+ int mode_unlocked = 0, mode_write = 0, mode_write_descriptor = 0;
+ int create = 0;
+ char *region_type_string = NULL, *src_fname = NULL;
+ char *addr_str = NULL;
+ int region_type = -1, inputfreq = 0;
+ enum spi_frequency spifreq = SPI_FREQUENCY_20MHZ;
+ unsigned int addr = 0;
+ int rom_size = -1;
+ bool write_it;
+ char *filename;
+ char *outfile = NULL;
+ struct stat buf;
+ int size = 0;
+ int bios_fd;
+ char *image;
+ int ret;
+ static struct option long_options[] = {
+ {"create", 0, NULL, 'c'},
+ {"dump", 0, NULL, 'd'},
+ {"descriptor", 1, NULL, 'D'},
+ {"em100", 0, NULL, 'e'},
+ {"extract", 0, NULL, 'x'},
+ {"inject", 1, NULL, 'i'},
+ {"lock", 0, NULL, 'l'},
+ {"romsize", 1, NULL, 'r'},
+ {"spifreq", 1, NULL, 's'},
+ {"unlock", 0, NULL, 'u'},
+ {"write", 1, NULL, 'w'},
+ {"version", 0, NULL, 'v'},
+ {"help", 0, NULL, 'h'},
+ {0, 0, 0, 0}
+ };
+
+ while ((opt = getopt_long(argc, argv, "cdD:ehi:lr:s:uvw:x?",
+ long_options, &option_index)) != EOF) {
+ switch (opt) {
+ case 'c':
+ create = 1;
+ break;
+ case 'd':
+ mode_dump = 1;
+ break;
+ case 'D':
+ mode_write_descriptor = 1;
+ src_fname = optarg;
+ break;
+ case 'e':
+ mode_em100 = 1;
+ break;
+ case 'i':
+ if (get_two_words(optarg, ®ion_type_string,
+ &src_fname)) {
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+ if (!strcasecmp("Descriptor", region_type_string))
+ region_type = 0;
+ else if (!strcasecmp("BIOS", region_type_string))
+ region_type = 1;
+ else if (!strcasecmp("ME", region_type_string))
+ region_type = 2;
+ else if (!strcasecmp("GbE", region_type_string))
+ region_type = 3;
+ else if (!strcasecmp("Platform", region_type_string))
+ region_type = 4;
+ if (region_type == -1) {
+ fprintf(stderr, "No such region type: '%s'\n\n",
+ region_type_string);
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+ mode_inject = 1;
+ break;
+ case 'l':
+ mode_locked = 1;
+ break;
+ case 'r':
+ rom_size = strtol(optarg, NULL, 0);
+ debug("ROM size %d\n", rom_size);
+ break;
+ case 's':
+ /* Parse the requested SPI frequency */
+ inputfreq = strtol(optarg, NULL, 0);
+ switch (inputfreq) {
+ case 20:
+ spifreq = SPI_FREQUENCY_20MHZ;
+ break;
+ case 33:
+ spifreq = SPI_FREQUENCY_33MHZ;
+ break;
+ case 50:
+ spifreq = SPI_FREQUENCY_50MHZ;
+ break;
+ default:
+ fprintf(stderr, "Invalid SPI Frequency: %d\n",
+ inputfreq);
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+ mode_spifreq = 1;
+ break;
+ case 'u':
+ mode_unlocked = 1;
+ break;
+ case 'v':
+ print_version();
+ exit(EXIT_SUCCESS);
+ break;
+ case 'w':
+ mode_write = 1;
+ if (get_two_words(optarg, &addr_str, &src_fname)) {
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+ addr = strtol(optarg, NULL, 0);
+ break;
+ case 'x':
+ mode_extract = 1;
+ break;
+ case 'h':
+ case '?':
+ default:
+ print_usage(argv[0]);
+ exit(EXIT_SUCCESS);
+ break;
+ }
+ }
+
+ if (mode_locked == 1 && mode_unlocked == 1) {
+ fprintf(stderr, "Locking/Unlocking FD and ME are mutually exclusive\n");
+ exit(EXIT_FAILURE);
+ }
+
+ if (mode_inject == 1 && mode_write == 1) {
+ fprintf(stderr, "Inject/Write are mutually exclusive\n");
+ exit(EXIT_FAILURE);
+ }
+
+ if ((mode_dump + mode_extract + mode_inject +
+ (mode_spifreq | mode_em100 | mode_unlocked |
+ mode_locked)) > 1) {
+ fprintf(stderr, "You may not specify more than one mode.\n\n");
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+
+ if ((mode_dump + mode_extract + mode_inject + mode_spifreq +
+ mode_em100 + mode_locked + mode_unlocked + mode_write +
+ mode_write_descriptor) == 0 && !create) {
+ fprintf(stderr, "You need to specify a mode.\n\n");
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+
+ if (create && rom_size == -1) {
+ fprintf(stderr, "You need to specify a rom size when creating.\n\n");
+ exit(EXIT_FAILURE);
+ }
+
+ if (optind + 1 != argc) {
+ fprintf(stderr, "You need to specify a file.\n\n");
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+
+ filename = argv[optind];
+ if (optind + 2 != argc)
+ outfile = argv[optind + 1];
+
+ if (create)
+ bios_fd = open(filename, O_WRONLY | O_CREAT, 0666);
+ else
+ bios_fd = open(filename, outfile ? O_RDONLY : O_RDWR);
+
+ if (bios_fd == -1) {
+ perror("Could not open file");
+ exit(EXIT_FAILURE);
+ }
+
+ if (!create) {
+ if (fstat(bios_fd, &buf) == -1) {
+ perror("Could not stat file");
+ exit(EXIT_FAILURE);
+ }
+ size = buf.st_size;
+ }
+
+ debug("File %s is %d bytes\n", filename, size);
+
+ if (rom_size == -1)
+ rom_size = size;
+
+ image = malloc(rom_size);
+ if (!image) {
+ printf("Out of memory.\n");
+ exit(EXIT_FAILURE);
+ }
+
+ memset(image, '\xff', rom_size);
+ if (!create && read(bios_fd, image, size) != size) {
+ perror("Could not read file");
+ exit(EXIT_FAILURE);
+ }
+ if (size != rom_size) {
+ debug("ROM size changed to %d bytes\n", rom_size);
+ size = rom_size;
+ }
+
+ write_it = true;
+ ret = 0;
+ if (mode_dump) {
+ ret = dump_fd(image, size);
+ write_it = false;
+ }
+
+ if (mode_extract) {
+ ret = write_regions(image, size);
+ write_it = false;
+ }
+
+ if (mode_write_descriptor)
+ ret = write_data(image, size, -size, src_fname);
+
+ if (mode_inject)
+ ret = inject_region(image, size, region_type, src_fname);
+
+ if (mode_write)
+ ret = write_data(image, size, addr, src_fname);
+
+ if (mode_spifreq)
+ set_spi_frequency(image, size, spifreq);
+
+ if (mode_em100)
+ set_em100_mode(image, size);
+
+ if (mode_locked)
+ lock_descriptor(image, size);
+
+ if (mode_unlocked)
+ unlock_descriptor(image, size);
+
+ if (write_it) {
+ if (outfile) {
+ ret = write_image(outfile, image, size);
+ } else {
+ if (lseek(bios_fd, 0, SEEK_SET)) {
+ perror("Error while seeking");
+ ret = -1;
+ }
+ if (write(bios_fd, image, size) != size) {
+ perror("Error while writing");
+ ret = -1;
+ }
+ }
+ }
+
+ free(image);
+ close(bios_fd);
+
+ return ret ? 1 : 0;
+}
diff --git a/tools/ifdtool.h b/tools/ifdtool.h
new file mode 100644
index 0000000..fbec421
--- /dev/null
+++ b/tools/ifdtool.h
@@ -0,0 +1,88 @@
+/*
+ * ifdtool - Manage Intel Firmware Descriptor information
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * From Coreboot project
+ */
+
+#include <stdint.h>
+
+#define __packed __attribute__((packed))
+
+#define IFDTOOL_VERSION "1.1-U-Boot"
+
+enum spi_frequency {
+ SPI_FREQUENCY_20MHZ = 0,
+ SPI_FREQUENCY_33MHZ = 1,
+ SPI_FREQUENCY_50MHZ = 4,
+};
+
+enum component_density {
+ COMPONENT_DENSITY_512KB = 0,
+ COMPONENT_DENSITY_1MB = 1,
+ COMPONENT_DENSITY_2MB = 2,
+ COMPONENT_DENSITY_4MB = 3,
+ COMPONENT_DENSITY_8MB = 4,
+ COMPONENT_DENSITY_16MB = 5,
+};
+
+/* flash descriptor */
+struct __packed fdbar_t {
+ uint32_t flvalsig;
+ uint32_t flmap0;
+ uint32_t flmap1;
+ uint32_t flmap2;
+ uint8_t reserved[0xefc - 0x20];
+ uint32_t flumap1;
+};
+
+#define MAX_REGIONS 5
+
+/* regions */
+struct __packed frba_t {
+ uint32_t flreg[MAX_REGIONS];
+};
+
+/* component section */
+struct __packed fcba_t {
+ uint32_t flcomp;
+ uint32_t flill;
+ uint32_t flpb;
+};
+
+#define MAX_STRAPS 18
+
+/* pch strap */
+struct __packed fpsba_t {
+ uint32_t pchstrp[MAX_STRAPS];
+};
+
+/* master */
+struct __packed fmba_t {
+ uint32_t flmstr1;
+ uint32_t flmstr2;
+ uint32_t flmstr3;
+};
+
+/* processor strap */
+struct __packed fmsba_t {
+ uint32_t data[8];
+};
+
+/* ME VSCC */
+struct vscc_t {
+ uint32_t jid;
+ uint32_t vscc;
+};
+
+struct vtba_t {
+ /* Actual number of entries specified in vtl */
+ struct vscc_t entry[8];
+};
+
+struct region_t {
+ int base, limit, size;
+};
diff --git a/tools/mxsimage.c b/tools/mxsimage.c
index 81c7f2d..04beefe 100644
--- a/tools/mxsimage.c
+++ b/tools/mxsimage.c
@@ -125,7 +125,7 @@
unsigned int in_section:1;
unsigned int in_dcd:1;
/* Image configuration */
- unsigned int verbose_boot:1;
+ unsigned int display_progress:1;
unsigned int silent_dump:1;
char *input_filename;
char *output_filename;
@@ -1308,8 +1308,8 @@
sizeof(struct sb_sections_header) / SB_BLOCK_SIZE;
hdr->timestamp_us = sb_get_timestamp() * 1000000;
- /* FIXME -- add proper config option */
- hdr->flags = ictx->verbose_boot ? SB_IMAGE_FLAG_VERBOSE : 0,
+ hdr->flags = ictx->display_progress ?
+ SB_IMAGE_FLAG_DISPLAY_PROGRESS : 0;
/* FIXME -- We support only default key */
hdr->key_count = 1;
@@ -1416,7 +1416,7 @@
{
char *tok;
char *line = cmd->cmd;
- char *rptr;
+ char *rptr = NULL;
int ret;
/* Analyze the identifier on this line first. */
@@ -1428,6 +1428,12 @@
cmd->cmd = rptr;
+ /* set DISPLAY_PROGRESS flag */
+ if (!strcmp(tok, "DISPLAYPROGRESS")) {
+ ictx->display_progress = 1;
+ return 0;
+ }
+
/* DCD */
if (!strcmp(tok, "DCD")) {
ictx->in_section = 0;
@@ -1681,10 +1687,11 @@
ntohs(hdr->component_version.minor),
ntohs(hdr->component_version.revision));
- if (hdr->flags & ~SB_IMAGE_FLAG_VERBOSE)
+ if (hdr->flags & ~SB_IMAGE_FLAGS_MASK)
ret = -EINVAL;
soprintf(ictx, "%s Image flags: %s\n", stat[!!ret],
- hdr->flags & SB_IMAGE_FLAG_VERBOSE ? "Verbose_boot" : "");
+ hdr->flags & SB_IMAGE_FLAG_DISPLAY_PROGRESS ?
+ "Display_progress" : "");
if (ret)
return ret;
@@ -2287,7 +2294,6 @@
ctx.cfg_filename = params->imagename;
ctx.output_filename = params->imagefile;
- ctx.verbose_boot = 1;
ret = sb_build_tree_from_cfg(&ctx);
if (ret)
diff --git a/tools/mxsimage.h b/tools/mxsimage.h
index 6cd59d2..88f72eb 100644
--- a/tools/mxsimage.h
+++ b/tools/mxsimage.h
@@ -81,8 +81,9 @@
#define SB_VERSION_MAJOR 1
#define SB_VERSION_MINOR 1
-/* Enable to HTLLC verbose boot report. */
-#define SB_IMAGE_FLAG_VERBOSE (1 << 0)
+/* Enable to HTLLC boot report. */
+#define SB_IMAGE_FLAG_DISPLAY_PROGRESS (1 << 0)
+#define SB_IMAGE_FLAGS_MASK SB_IMAGE_FLAG_DISPLAY_PROGRESS
struct sb_key_dictionary_key {
/* The CBC-MAC of image and sections header. */