| commit | fac0b5d20af72f9c435a247b3a8f41ddcb986a69 | [log] [tgz] |
|---|---|---|
| author | Haiying Wang <Haiying.Wang@freescale.com> | Tue Jan 13 16:29:28 2009 -0500 |
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | Tue Jan 13 16:58:46 2009 -0600 |
| tree | 86bc278f77095fe7d3279605e972eb45007e976c | |
| parent | 8a353d55490385b3abfa9566288115db00055c1a [diff] |
Some changes of TLB entry setting for MPC8572DS - Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode, all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0 can not access PIXIS_BASE anymore (any access will cause DataTLBError exception) - Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>