commit fa3cb1939b1f15d93abe21c89aeda252c1ae1956
author Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Thu Jul 15 20:53:57 2021 +0200
committer Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Sun Jul 18 20:37:39 2021 +0200
tree 63db09302930124a65a960f1f153fe294bdbcde9
parent f59925e845d463706305d13e5271cb4135918f03

pci: gt64120: convert to driver model

This driver is currently only used on MIPS Malta boards.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

Reviewed-by: Simon Glass <sjg@chromium.org>

drivers/pci/pci_gt64120.c

diff --git a/drivers/pci/pci_gt64120.c b/drivers/pci/pci_gt64120.c
index 80f11fe..e57fedf 100644
--- a/drivers/pci/pci_gt64120.c
+++ b/drivers/pci/pci_gt64120.c
@@ -8,7 +8,7 @@
  *            Maciej W. Rozycki <macro@mips.com>
  */
 
-#include <common.h>
+#include <dm.h>
 #include <gt64120.h>
 #include <init.h>
 #include <log.h>
@@ -114,6 +114,7 @@
 	return 0;
 }
 
+#if !IS_ENABLED(CONFIG_DM_PCI)
 static int gt_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
 				int where, u32 *value)
 {
@@ -175,3 +176,74 @@
 	pci_register_hose(hose);
 	hose->last_busno = pci_hose_scan(hose);
 }
+#else
+static int gt64120_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
+				   uint where, ulong *val,
+				   enum pci_size_t size)
+{
+	struct gt64120_pci_controller *gt = dev_get_priv(dev);
+	u32 data = 0;
+
+	if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, &data)) {
+		*val = pci_get_ff(size);
+		return 0;
+	}
+
+	*val = pci_conv_32_to_size(data, where, size);
+
+	return 0;
+}
+
+static int gt64120_pci_write_config(struct udevice *dev, pci_dev_t bdf,
+				    uint where, ulong val,
+				    enum pci_size_t size)
+{
+	struct gt64120_pci_controller *gt = dev_get_priv(dev);
+	u32 data = 0;
+
+	if (size == PCI_SIZE_32) {
+		data = val;
+	} else {
+		u32 old;
+
+		if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, &old))
+			return 0;
+
+		data = pci_conv_size_to_32(old, val, where, size);
+	}
+
+	gt_config_access(gt, PCI_ACCESS_WRITE, bdf, where, &data);
+
+	return 0;
+}
+
+static int gt64120_pci_probe(struct udevice *dev)
+{
+	struct gt64120_pci_controller *gt = dev_get_priv(dev);
+
+	gt->regs = dev_remap_addr(dev);
+	if (!gt->regs)
+		return -EINVAL;
+
+	return 0;
+}
+
+static const struct dm_pci_ops gt64120_pci_ops = {
+	.read_config	= gt64120_pci_read_config,
+	.write_config	= gt64120_pci_write_config,
+};
+
+static const struct udevice_id gt64120_pci_ids[] = {
+	{ .compatible = "marvell,pci-gt64120" },
+	{ }
+};
+
+U_BOOT_DRIVER(gt64120_pci) = {
+	.name		= "gt64120_pci",
+	.id		= UCLASS_PCI,
+	.of_match	= gt64120_pci_ids,
+	.ops		= &gt64120_pci_ops,
+	.probe		= gt64120_pci_probe,
+	.priv_auto	= sizeof(struct gt64120_pci_controller),
+};
+#endif