Merge git://git.denx.de/u-boot-mpc83xx
- Update MPC83xx platform support to current best practices, etc.
diff --git a/Kconfig b/Kconfig
index da208d6..5f5c5cc 100644
--- a/Kconfig
+++ b/Kconfig
@@ -512,7 +512,7 @@
config SYS_CLK_FREQ
- depends on ARC || ARCH_SUNXI
+ depends on ARC || ARCH_SUNXI || MPC83xx
int "CPU clock frequency"
help
TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 0b1629b..c2c577f 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -39,6 +39,12 @@
endchoice
+config HIGH_BATS
+ bool "Enable high BAT registers"
+ help
+ Enable BATs (block address translation registers) 4-7 on machines
+ that support them.
+
source "arch/powerpc/cpu/mpc83xx/Kconfig"
source "arch/powerpc/cpu/mpc85xx/Kconfig"
source "arch/powerpc/cpu/mpc86xx/Kconfig"
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 571cf8f..b99288a 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -10,38 +10,66 @@
config TARGET_MPC8308_P1M
bool "Support mpc8308_p1m"
+ select ARCH_MPC8308
config TARGET_SBC8349
bool "Support sbc8349"
+ select ARCH_MPC8349
config TARGET_VE8313
bool "Support ve8313"
+ select ARCH_MPC8313
config TARGET_VME8349
bool "Support vme8349"
+ select ARCH_MPC8349
+
+config TARGET_CADDY2
+ bool "Support caddy2"
+ select ARCH_MPC8349
config TARGET_MPC8308RDB
bool "Support MPC8308RDB"
+ select ARCH_MPC8308
select SYS_FSL_ERRATUM_ESDHC111
-config TARGET_MPC8313ERDB
- bool "Support MPC8313ERDB"
+config TARGET_MPC8313ERDB_NOR
+ bool "Support MPC8313ERDB_NOR"
+ select ARCH_MPC8313
select BOARD_EARLY_INIT_F
select SUPPORT_SPL
+config TARGET_MPC8313ERDB_NAND
+ bool "Support MPC8313ERDB_NAND"
+ select ARCH_MPC8313
+ select BOARD_EARLY_INIT_F
+ select SUPPORT_SPL
+
config TARGET_MPC8315ERDB
bool "Support MPC8315ERDB"
+ select ARCH_MPC8315
select BOARD_EARLY_INIT_F
config TARGET_MPC8323ERDB
bool "Support MPC8323ERDB"
+ select ARCH_MPC832X
config TARGET_MPC832XEMDS
bool "Support MPC832XEMDS"
+ select ARCH_MPC832X
select BOARD_EARLY_INIT_F
config TARGET_MPC8349EMDS
bool "Support MPC8349EMDS"
+ select ARCH_MPC8349
+ select BOARD_EARLY_INIT_F
+ select SYS_FSL_DDR
+ select SYS_FSL_DDR_BE
+ select SYS_FSL_HAS_DDR2
+
+config TARGET_MPC8349EMDS_SDRAM
+ bool "Support MPC8349EMDS_SDRAM"
+ select ARCH_MPC8349
select BOARD_EARLY_INIT_F
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
@@ -49,53 +77,272 @@
config TARGET_MPC8349ITX
bool "Support MPC8349ITX"
+ select ARCH_MPC8349
imply CMD_IRQ
config TARGET_MPC837XEMDS
bool "Support MPC837XEMDS"
+ select ARCH_MPC837X
select BOARD_EARLY_INIT_F
imply CMD_SATA
imply FSL_SATA
config TARGET_MPC837XERDB
bool "Support MPC837XERDB"
+ select ARCH_MPC837X
select BOARD_EARLY_INIT_F
config TARGET_IDS8313
bool "Support ids8313"
+ select ARCH_MPC8313
select DM
imply CMD_DM
-config TARGET_KM8360
- bool "Support km8360"
+config TARGET_KMETER1
+ bool "Support kmeter1"
+ select ARCH_MPC8360
imply CMD_CRAMFS
imply CMD_DIAG
imply FS_CRAMFS
+config TARGET_KMCOGE5NE
+ bool "Support kmcoge5ne"
+ select ARCH_MPC8360
+ imply CMD_CRAMFS
+ imply CMD_DIAG
+ imply FS_CRAMFS
+
config TARGET_SUVD3
bool "Support suvd3"
+ select ARCH_MPC832X
+ imply CMD_CRAMFS
+ imply FS_CRAMFS
+
+config TARGET_KMVECT1
+ bool "Support kmvect1"
+ select ARCH_MPC8309
+ imply CMD_CRAMFS
+ imply FS_CRAMFS
+
+config TARGET_KMTEGR1
+ bool "Support kmtegr1"
+ select ARCH_MPC8309
imply CMD_CRAMFS
imply FS_CRAMFS
config TARGET_TUXX1
bool "Support tuxx1"
+ select ARCH_MPC832X
+ imply CMD_CRAMFS
+ imply FS_CRAMFS
+
+config TARGET_KMSUPX5
+ bool "Support kmsupx5"
+ select ARCH_MPC832X
imply CMD_CRAMFS
imply FS_CRAMFS
+config TARGET_TUGE1
+ bool "Support tuge1"
+ select ARCH_MPC832X
+ imply CMD_CRAMFS
+ imply FS_CRAMFS
+
+config TARGET_KMOPTI2
+ bool "Support kmopti2"
+ select ARCH_MPC832X
+ imply CMD_CRAMFS
+ imply FS_CRAMFS
+
+config TARGET_KMTEPR2
+ bool "Support kmtepr2"
+ select ARCH_MPC832X
+ imply CMD_CRAMFS
+ imply FS_CRAMFS
+
config TARGET_TQM834X
bool "Support TQM834x"
+ select ARCH_MPC8349
config TARGET_HRCON
bool "Support hrcon"
+ select ARCH_MPC8308
select SYS_FSL_ERRATUM_ESDHC111
config TARGET_STRIDER
bool "Support strider"
+ select ARCH_MPC8308
select SYS_FSL_ERRATUM_ESDHC111
imply CMD_PCA953X
+config TARGET_GAZERBEAM
+ bool "Support gazerbeam"
+ select ARCH_MPC8308
+ select SYS_FSL_ERRATUM_ESDHC111
+ imply ENV_IS_IN_FLASH
+ help
+ The "Gazerbeam" is a modular system by Guntermann & Drunck GmbH
+ Systementwicklung based on the NXP MPC8308 SoC for usage in KVM
+ appliances.
+
+ Features include:
+ * Two gigabit ethernet ports
+ * Multiple USB ports (depending on variant)
+ * Several gigabit ethernet or optical fiber ports (depending on
+ variant)
+ * Several display port inputs and outputs, and supporting redrivers
+ (depending on variant)
+ * Several FPGAs with custom logic (depending on variant)
+
endchoice
+config MPC83XX_QUICC_ENGINE
+ bool
+
+# TODO: Imply MPC83xx PCI driver
+config MPC83XX_PCI_SUPPORT
+ bool
+
+# TODO: Imply TSEC driver
+config MPC83XX_TSEC1_SUPPORT
+ bool
+
+config MPC83XX_TSEC2_SUPPORT
+ bool
+
+config MPC83XX_PCIE1_SUPPORT
+ bool
+
+config MPC83XX_PCIE2_SUPPORT
+ bool
+
+config MPC83XX_SDHC_SUPPORT
+ bool
+
+config MPC83XX_SATA_SUPPORT
+ bool
+
+config MPC83XX_SECOND_I2C_SUPPORT
+ bool
+
+config MPC83XX_LDP_PIN
+ bool
+
+config ARCH_MPC830X
+ bool
+ select MPC83XX_SDHC_SUPPORT
+
+config ARCH_MPC8308
+ bool
+ select ARCH_MPC830X
+ select MPC83XX_TSEC1_SUPPORT
+ select MPC83XX_TSEC2_SUPPORT
+ select MPC83XX_PCIE1_SUPPORT
+ select MPC83XX_SECOND_I2C_SUPPORT
+
+config ARCH_MPC8309
+ bool
+ select ARCH_MPC830X
+ select MPC83XX_QUICC_ENGINE
+ select MPC83XX_PCI_SUPPORT
+ select MPC83XX_SECOND_I2C_SUPPORT
+
+config ARCH_MPC831X
+ bool
+ select MPC83XX_PCI_SUPPORT
+ select MPC83XX_TSEC1_SUPPORT
+ select MPC83XX_TSEC2_SUPPORT
+
+config ARCH_MPC8313
+ bool
+ select ARCH_MPC831X
+ select MPC83XX_SECOND_I2C_SUPPORT
+
+config ARCH_MPC8315
+ bool
+ select ARCH_MPC831X
+ select MPC83XX_PCIE1_SUPPORT
+ select MPC83XX_PCIE2_SUPPORT
+ select MPC83XX_SATA_SUPPORT
+
+config ARCH_MPC832X
+ bool
+ select MPC83XX_QUICC_ENGINE
+ select MPC83XX_PCI_SUPPORT
+
+config ARCH_MPC834X
+ bool
+
+config ARCH_MPC8349
+ bool
+ select ARCH_MPC834X
+ select MPC83XX_PCI_SUPPORT
+ select MPC83XX_TSEC1_SUPPORT
+ select MPC83XX_TSEC2_SUPPORT
+ select MPC83XX_LDP_PIN
+ select MPC83XX_SECOND_I2C_SUPPORT
+
+config ARCH_MPC8360
+ bool
+ select MPC83XX_QUICC_ENGINE
+ select MPC83XX_PCI_SUPPORT
+ select MPC83XX_LDP_PIN
+ select MPC83XX_SECOND_I2C_SUPPORT
+
+config ARCH_MPC837X
+ bool
+ select MPC83XX_PCI_SUPPORT
+ select MPC83XX_TSEC1_SUPPORT
+ select MPC83XX_TSEC2_SUPPORT
+ select MPC83XX_PCIE1_SUPPORT
+ select MPC83XX_PCIE2_SUPPORT
+ select MPC83XX_SDHC_SUPPORT
+ select MPC83XX_SATA_SUPPORT
+ select MPC83XX_LDP_PIN
+ select MPC83XX_SECOND_I2C_SUPPORT
+
+config SYS_IMMR
+ hex "Value for IMMR"
+ default 0xE0000000
+ help
+ Address for the Internal Memory-Mapped Registers (IMMR) window used
+ to configure the features of the SoC.
+
+source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/bats/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/hid/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig"
+
+menu "Legacy options"
+
+if ARCH_MPC8349
+
+#TODO(mario.six@gdsys.cc): Remove when mpc83xx PCI has been converted to DM/DT
+choice
+ prompt "PMC slot configuration"
+
+config PCI_ALL_PCI1
+ bool "All PMC slots on PCI1"
+
+config PCI_ONE_PCI1
+ bool "First PMC1 on PCI1"
+
+config PCI_TWO_PCI1
+ bool "First two PMC1 on PCI1"
+
+endchoice
+
+config PCI_64BIT
+ bool "PMC2 is 64bit"
+
+endif
+
+endmenu
+
source "board/esd/vme8349/Kconfig"
source "board/freescale/mpc8308rdb/Kconfig"
source "board/freescale/mpc8313erdb/Kconfig"
diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile
index aa4affa..3040299 100644
--- a/arch/powerpc/cpu/mpc83xx/Makefile
+++ b/arch/powerpc/cpu/mpc83xx/Makefile
@@ -29,7 +29,9 @@
obj-y += ecc.o
obj-$(CONFIG_QE) += qe_io.o
obj-$(CONFIG_FSL_SERDES) += serdes.o
+ifndef CONFIG_ARCH_MPC8308
obj-$(CONFIG_PCI) += pci.o
+endif
obj-$(CONFIG_PCIE) += pcie.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/powerpc/cpu/mpc83xx/arbiter/Kconfig b/arch/powerpc/cpu/mpc83xx/arbiter/Kconfig
new file mode 100644
index 0000000..f562476
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/arbiter/Kconfig
@@ -0,0 +1,139 @@
+menu "Arbiter"
+
+choice
+ prompt "Pipeline depth"
+
+config ACR_PIPE_DEP_UNSET
+ bool "Don't set value"
+
+config ACR_PIPE_DEP_1
+ bool "1"
+
+config ACR_PIPE_DEP_2
+ bool "2"
+
+config ACR_PIPE_DEP_3
+ bool "3"
+
+config ACR_PIPE_DEP_4
+ bool "4"
+
+endchoice
+
+choice
+ prompt "Repeat count"
+
+config ACR_RPTCNT_UNSET
+ bool "Don't set value"
+
+config ACR_RPTCNT_1
+ bool "1"
+
+config ACR_RPTCNT_2
+ bool "2"
+
+config ACR_RPTCNT_3
+ bool "3"
+
+config ACR_RPTCNT_4
+ bool "4"
+
+config ACR_RPTCNT_5
+ bool "5"
+
+config ACR_RPTCNT_6
+ bool "6"
+
+config ACR_RPTCNT_7
+ bool "7"
+
+config ACR_RPTCNT_8
+ bool "8"
+
+endchoice
+
+choice
+ prompt "Address parking"
+
+config ACR_APARK_UNSET
+ bool "Don't set value"
+
+config ACR_APARK_MASTER
+ bool "Park to master"
+
+config ACR_APARK_LAST
+ bool "Park to last owner"
+
+config ACR_APARK_DISABLE
+ bool "Disabled"
+
+endchoice
+
+choice
+ prompt "Parking master"
+
+config ACR_PARKM_UNSET
+ bool "Don't set value"
+
+config ACR_PARKM_E300
+ bool "e300 core"
+
+config ACR_PARKM_TSEC_1_2
+ bool "TSEC1, TSEC2"
+
+config ACR_PARKM_USB_I2C1_BOOT
+ bool "USB/I2C1_BOOT"
+
+config ACR_PARKM_DMA_ESDHC_USB
+ bool "DMA, ESDHC, USB"
+
+config ACR_PARKM_PEX
+ bool "PCI Express"
+
+if MPC83XX_QUICC_ENGINE
+
+config ACR_PARKM_ENC_CORE
+ bool "Encryption core"
+
+endif
+
+endchoice
+
+config ACR_PIPE_DEP
+ hex
+ default 0x0 if ACR_PIPE_DEP_UNSET
+ default 0x0 if ACR_PIPE_DEP_1
+ default 0x10000 if ACR_PIPE_DEP_2
+ default 0x20000 if ACR_PIPE_DEP_3
+ default 0x30000 if ACR_PIPE_DEP_4
+
+config ACR_RPTCNT
+ hex
+ default 0x0 if ACR_RPTCNT_UNSET
+ default 0x0 if ACR_RPTCNT_1
+ default 0x100 if ACR_RPTCNT_2
+ default 0x200 if ACR_RPTCNT_3
+ default 0x300 if ACR_RPTCNT_4
+ default 0x400 if ACR_RPTCNT_5
+ default 0x500 if ACR_RPTCNT_6
+ default 0x600 if ACR_RPTCNT_7
+ default 0x700 if ACR_RPTCNT_8
+
+config ACR_APARK
+ hex
+ default 0x0 if ACR_APARK_UNSET
+ default 0x0 if ACR_APARK_MASTER
+ default 0x10 if ACR_APARK_LAST
+ default 0x20 if ACR_APARK_DISABLE
+
+config ACR_PARKM
+ hex
+ default 0x0 if ACR_PARKM_UNSET
+ default 0x0 if ACR_PARKM_E300
+ default 0x2 if ACR_PARKM_TSEC_1_2
+ default 0x3 if ACR_PARKM_USB_I2C1_BOOT
+ default 0x4 if ACR_PARKM_DMA_ESDHC_USB
+ default 0x5 if ACR_PARKM_PEX
+ default 0x5 if ACR_PARKM_ENC_CORE
+
+endmenu
diff --git a/arch/powerpc/cpu/mpc83xx/arbiter/arbiter.h b/arch/powerpc/cpu/mpc83xx/arbiter/arbiter.h
new file mode 100644
index 0000000..10a47e4
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/arbiter/arbiter.h
@@ -0,0 +1,28 @@
+ const __be32 acr_mask =
+#ifndef CONFIG_ACR_PIPE_DEP_UNSET
+ ACR_PIPE_DEP |
+#endif
+#ifndef CONFIG_ACR_RPTCNT_UNSET
+ ACR_RPTCNT |
+#endif
+#ifndef CONFIG_ACR_APARK_UNSET
+ ACR_APARK |
+#endif
+#ifndef CONFIG_ACR_PARKM_UNSET
+ ACR_PARKM |
+#endif
+ 0;
+ const __be32 acr_val =
+#ifndef CONFIG_ACR_PIPE_DEP_UNSET
+ CONFIG_ACR_PIPE_DEP |
+#endif
+#ifndef CONFIG_ACR_RPTCNT_UNSET
+ CONFIG_ACR_RPTCNT |
+#endif
+#ifndef CONFIG_ACR_APARK_UNSET
+ CONFIG_ACR_APARK |
+#endif
+#ifndef CONFIG_ACR_PARKM_UNSET
+ CONFIG_ACR_PARKM |
+#endif
+ 0;
diff --git a/arch/powerpc/cpu/mpc83xx/bats/Kconfig b/arch/powerpc/cpu/mpc83xx/bats/Kconfig
new file mode 100644
index 0000000..218920c
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/bats/Kconfig
@@ -0,0 +1,1311 @@
+menu "BATS setup"
+
+menuconfig BAT0
+ bool "BAT0"
+
+if BAT0
+
+config BAT0_NAME
+ string "Identifier"
+
+config BAT0_BASE
+ hex "Base"
+
+choice
+ prompt "Block length"
+
+config BAT0_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config BAT0_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config BAT0_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config BAT0_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config BAT0_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config BAT0_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config BAT0_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config BAT0_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config BAT0_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config BAT0_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config BAT0_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config BAT0_LENGTH_256_MBYTES
+ bool "256 mb"
+endchoice
+
+choice
+ prompt "Protection mode"
+
+config BAT0_ACCESS_NONE
+ bool "No access"
+
+config BAT0_ACCESS_RO
+ bool "Read-only"
+
+config BAT0_ACCESS_RW
+ bool "Read-write"
+
+endchoice
+
+config BAT0_ICACHE_WRITETHROUGH
+ bool "I-cache Write-through"
+
+config BAT0_ICACHE_INHIBITED
+ bool "I-cache Inhibited"
+
+config BAT0_ICACHE_MEMORYCOHERENCE
+ bool "I-cache Memory coherence"
+
+config BAT0_ICACHE_GUARDED
+ bool "I-cache Guarded"
+
+config BAT0_DCACHE_WRITETHROUGH
+ bool "D-cache Write-through"
+
+config BAT0_DCACHE_INHIBITED
+ bool "D-cache Inhibited"
+
+config BAT0_DCACHE_MEMORYCOHERENCE
+ bool "D-cache Memory coherence"
+
+config BAT0_DCACHE_GUARDED
+ bool "D-cache Guarded"
+
+config BAT0_USER_MODE_VALID
+ bool "User mode valid"
+
+config BAT0_SUPERVISOR_MODE_VALID
+ bool "Supervisor mode valid"
+
+endif
+
+config BAT0_LENGTH
+ hex
+ default 0x00000000 if BAT0_LENGTH_128_KBYTES
+ default 0x00000004 if BAT0_LENGTH_256_KBYTES
+ default 0x0000000c if BAT0_LENGTH_512_KBYTES
+ default 0x0000001c if BAT0_LENGTH_1_MBYTES
+ default 0x0000003c if BAT0_LENGTH_2_MBYTES
+ default 0x0000007c if BAT0_LENGTH_4_MBYTES
+ default 0x000000fc if BAT0_LENGTH_8_MBYTES
+ default 0x000001fc if BAT0_LENGTH_16_MBYTES
+ default 0x000003fc if BAT0_LENGTH_32_MBYTES
+ default 0x000007fc if BAT0_LENGTH_64_MBYTES
+ default 0x00000ffc if BAT0_LENGTH_128_MBYTES
+ default 0x00001ffc if BAT0_LENGTH_256_MBYTES
+
+config BAT0_PAGE_PROTECTION
+ hex
+ default 0x0 if BAT0_ACCESS_NONE
+ default 0x1 if BAT0_ACCESS_RO
+ default 0x2 if BAT0_ACCESS_RW
+
+config BAT0_WIMG_ICACHE
+ hex
+ default 0x0 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+ default 0x8 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+ default 0x10 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+ default 0x18 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+ default 0x20 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+ default 0x28 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+ default 0x30 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+ default 0x38 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+ default 0x40 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+ default 0x48 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+ default 0x50 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+ default 0x58 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+ default 0x60 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+ default 0x68 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+ default 0x70 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+ default 0x78 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+
+config BAT0_WIMG_DCACHE
+ hex
+ default 0x0 if !BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+ default 0x8 if !BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+ default 0x10 if !BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+ default 0x18 if !BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+ default 0x20 if !BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+ default 0x28 if !BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+ default 0x30 if !BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+ default 0x38 if !BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+ default 0x40 if BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+ default 0x48 if BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+ default 0x50 if BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+ default 0x58 if BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+ default 0x60 if BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+ default 0x68 if BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+ default 0x70 if BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+ default 0x78 if BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+
+config BAT0_VALID_BITS
+ hex
+ default 0x0 if !BAT0_SUPERVISOR_MODE_VALID && !BAT0_USER_MODE_VALID
+ default 0x1 if !BAT0_SUPERVISOR_MODE_VALID && BAT0_USER_MODE_VALID
+ default 0x2 if BAT0_SUPERVISOR_MODE_VALID && !BAT0_USER_MODE_VALID
+ default 0x3 if BAT0_SUPERVISOR_MODE_VALID && BAT0_USER_MODE_VALID
+
+menuconfig BAT1
+ bool "BAT1"
+
+if BAT1
+
+config BAT1_NAME
+ string "Identifier"
+
+config BAT1_BASE
+ hex "Base"
+
+choice
+ prompt "Block length"
+
+config BAT1_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config BAT1_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config BAT1_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config BAT1_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config BAT1_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config BAT1_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config BAT1_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config BAT1_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config BAT1_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config BAT1_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config BAT1_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config BAT1_LENGTH_256_MBYTES
+ bool "256 mb"
+endchoice
+
+choice
+ prompt "Protection mode"
+
+config BAT1_ACCESS_NONE
+ bool "No access"
+
+config BAT1_ACCESS_RO
+ bool "Read-only"
+
+config BAT1_ACCESS_RW
+ bool "Read-write"
+
+endchoice
+
+config BAT1_ICACHE_WRITETHROUGH
+ bool "I-cache Write-through"
+
+config BAT1_ICACHE_INHIBITED
+ bool "I-cache Inhibited"
+
+config BAT1_ICACHE_MEMORYCOHERENCE
+ bool "I-cache Memory coherence"
+
+config BAT1_ICACHE_GUARDED
+ bool "I-cache Guarded"
+
+config BAT1_DCACHE_WRITETHROUGH
+ bool "D-cache Write-through"
+
+config BAT1_DCACHE_INHIBITED
+ bool "D-cache Inhibited"
+
+config BAT1_DCACHE_MEMORYCOHERENCE
+ bool "D-cache Memory coherence"
+
+config BAT1_DCACHE_GUARDED
+ bool "D-cache Guarded"
+
+config BAT1_USER_MODE_VALID
+ bool "User mode valid"
+
+config BAT1_SUPERVISOR_MODE_VALID
+ bool "Supervisor mode valid"
+
+endif
+
+config BAT1_LENGTH
+ hex
+ default 0x00000000 if BAT1_LENGTH_128_KBYTES
+ default 0x00000004 if BAT1_LENGTH_256_KBYTES
+ default 0x0000000c if BAT1_LENGTH_512_KBYTES
+ default 0x0000001c if BAT1_LENGTH_1_MBYTES
+ default 0x0000003c if BAT1_LENGTH_2_MBYTES
+ default 0x0000007c if BAT1_LENGTH_4_MBYTES
+ default 0x000000fc if BAT1_LENGTH_8_MBYTES
+ default 0x000001fc if BAT1_LENGTH_16_MBYTES
+ default 0x000003fc if BAT1_LENGTH_32_MBYTES
+ default 0x000007fc if BAT1_LENGTH_64_MBYTES
+ default 0x00000ffc if BAT1_LENGTH_128_MBYTES
+ default 0x00001ffc if BAT1_LENGTH_256_MBYTES
+
+config BAT1_PAGE_PROTECTION
+ hex
+ default 0x0 if BAT1_ACCESS_NONE
+ default 0x1 if BAT1_ACCESS_RO
+ default 0x2 if BAT1_ACCESS_RW
+
+config BAT1_WIMG_ICACHE
+ hex
+ default 0x0 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+ default 0x8 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+ default 0x10 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+ default 0x18 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+ default 0x20 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+ default 0x28 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+ default 0x30 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+ default 0x38 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+ default 0x40 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+ default 0x48 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+ default 0x50 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+ default 0x58 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+ default 0x60 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+ default 0x68 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+ default 0x70 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+ default 0x78 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+
+config BAT1_WIMG_DCACHE
+ hex
+ default 0x0 if !BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+ default 0x8 if !BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+ default 0x10 if !BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+ default 0x18 if !BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+ default 0x20 if !BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+ default 0x28 if !BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+ default 0x30 if !BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+ default 0x38 if !BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+ default 0x40 if BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+ default 0x48 if BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+ default 0x50 if BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+ default 0x58 if BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+ default 0x60 if BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+ default 0x68 if BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+ default 0x70 if BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+ default 0x78 if BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+
+config BAT1_VALID_BITS
+ hex
+ default 0x0 if !BAT1_SUPERVISOR_MODE_VALID && !BAT1_USER_MODE_VALID
+ default 0x1 if !BAT1_SUPERVISOR_MODE_VALID && BAT1_USER_MODE_VALID
+ default 0x2 if BAT1_SUPERVISOR_MODE_VALID && !BAT1_USER_MODE_VALID
+ default 0x3 if BAT1_SUPERVISOR_MODE_VALID && BAT1_USER_MODE_VALID
+
+menuconfig BAT2
+ bool "BAT2"
+
+if BAT2
+
+config BAT2_NAME
+ string "Identifier"
+
+config BAT2_BASE
+ hex "Base"
+
+choice
+ prompt "Block length"
+
+config BAT2_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config BAT2_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config BAT2_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config BAT2_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config BAT2_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config BAT2_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config BAT2_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config BAT2_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config BAT2_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config BAT2_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config BAT2_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config BAT2_LENGTH_256_MBYTES
+ bool "256 mb"
+endchoice
+
+choice
+ prompt "Protection mode"
+
+config BAT2_ACCESS_NONE
+ bool "No access"
+
+config BAT2_ACCESS_RO
+ bool "Read-only"
+
+config BAT2_ACCESS_RW
+ bool "Read-write"
+
+endchoice
+
+config BAT2_ICACHE_WRITETHROUGH
+ bool "I-cache Write-through"
+
+config BAT2_ICACHE_INHIBITED
+ bool "I-cache Inhibited"
+
+config BAT2_ICACHE_MEMORYCOHERENCE
+ bool "I-cache Memory coherence"
+
+config BAT2_ICACHE_GUARDED
+ bool "I-cache Guarded"
+
+config BAT2_DCACHE_WRITETHROUGH
+ bool "D-cache Write-through"
+
+config BAT2_DCACHE_INHIBITED
+ bool "D-cache Inhibited"
+
+config BAT2_DCACHE_MEMORYCOHERENCE
+ bool "D-cache Memory coherence"
+
+config BAT2_DCACHE_GUARDED
+ bool "D-cache Guarded"
+
+config BAT2_USER_MODE_VALID
+ bool "User mode valid"
+
+config BAT2_SUPERVISOR_MODE_VALID
+ bool "Supervisor mode valid"
+
+endif
+
+config BAT2_LENGTH
+ hex
+ default 0x00000000 if BAT2_LENGTH_128_KBYTES
+ default 0x00000004 if BAT2_LENGTH_256_KBYTES
+ default 0x0000000c if BAT2_LENGTH_512_KBYTES
+ default 0x0000001c if BAT2_LENGTH_1_MBYTES
+ default 0x0000003c if BAT2_LENGTH_2_MBYTES
+ default 0x0000007c if BAT2_LENGTH_4_MBYTES
+ default 0x000000fc if BAT2_LENGTH_8_MBYTES
+ default 0x000001fc if BAT2_LENGTH_16_MBYTES
+ default 0x000003fc if BAT2_LENGTH_32_MBYTES
+ default 0x000007fc if BAT2_LENGTH_64_MBYTES
+ default 0x00000ffc if BAT2_LENGTH_128_MBYTES
+ default 0x00001ffc if BAT2_LENGTH_256_MBYTES
+
+config BAT2_PAGE_PROTECTION
+ hex
+ default 0x0 if BAT2_ACCESS_NONE
+ default 0x1 if BAT2_ACCESS_RO
+ default 0x2 if BAT2_ACCESS_RW
+
+config BAT2_WIMG_ICACHE
+ hex
+ default 0x0 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+ default 0x8 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+ default 0x10 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+ default 0x18 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+ default 0x20 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+ default 0x28 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+ default 0x30 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+ default 0x38 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+ default 0x40 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+ default 0x48 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+ default 0x50 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+ default 0x58 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+ default 0x60 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+ default 0x68 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+ default 0x70 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+ default 0x78 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+
+config BAT2_WIMG_DCACHE
+ hex
+ default 0x0 if !BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+ default 0x8 if !BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+ default 0x10 if !BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+ default 0x18 if !BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+ default 0x20 if !BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+ default 0x28 if !BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+ default 0x30 if !BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+ default 0x38 if !BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+ default 0x40 if BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+ default 0x48 if BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+ default 0x50 if BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+ default 0x58 if BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+ default 0x60 if BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+ default 0x68 if BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+ default 0x70 if BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+ default 0x78 if BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+
+config BAT2_VALID_BITS
+ hex
+ default 0x0 if !BAT2_SUPERVISOR_MODE_VALID && !BAT2_USER_MODE_VALID
+ default 0x1 if !BAT2_SUPERVISOR_MODE_VALID && BAT2_USER_MODE_VALID
+ default 0x2 if BAT2_SUPERVISOR_MODE_VALID && !BAT2_USER_MODE_VALID
+ default 0x3 if BAT2_SUPERVISOR_MODE_VALID && BAT2_USER_MODE_VALID
+
+menuconfig BAT3
+ bool "BAT3"
+
+if BAT3
+
+config BAT3_NAME
+ string "Identifier"
+
+config BAT3_BASE
+ hex "Base"
+
+choice
+ prompt "Block length"
+
+config BAT3_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config BAT3_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config BAT3_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config BAT3_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config BAT3_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config BAT3_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config BAT3_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config BAT3_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config BAT3_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config BAT3_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config BAT3_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config BAT3_LENGTH_256_MBYTES
+ bool "256 mb"
+endchoice
+
+choice
+ prompt "Protection mode"
+
+config BAT3_ACCESS_NONE
+ bool "No access"
+
+config BAT3_ACCESS_RO
+ bool "Read-only"
+
+config BAT3_ACCESS_RW
+ bool "Read-write"
+
+endchoice
+
+config BAT3_ICACHE_WRITETHROUGH
+ bool "I-cache Write-through"
+
+config BAT3_ICACHE_INHIBITED
+ bool "I-cache Inhibited"
+
+config BAT3_ICACHE_MEMORYCOHERENCE
+ bool "I-cache Memory coherence"
+
+config BAT3_ICACHE_GUARDED
+ bool "I-cache Guarded"
+
+config BAT3_DCACHE_WRITETHROUGH
+ bool "D-cache Write-through"
+
+config BAT3_DCACHE_INHIBITED
+ bool "D-cache Inhibited"
+
+config BAT3_DCACHE_MEMORYCOHERENCE
+ bool "D-cache Memory coherence"
+
+config BAT3_DCACHE_GUARDED
+ bool "D-cache Guarded"
+
+config BAT3_USER_MODE_VALID
+ bool "User mode valid"
+
+config BAT3_SUPERVISOR_MODE_VALID
+ bool "Supervisor mode valid"
+
+endif
+
+config BAT3_LENGTH
+ hex
+ default 0x00000000 if BAT3_LENGTH_128_KBYTES
+ default 0x00000004 if BAT3_LENGTH_256_KBYTES
+ default 0x0000000c if BAT3_LENGTH_512_KBYTES
+ default 0x0000001c if BAT3_LENGTH_1_MBYTES
+ default 0x0000003c if BAT3_LENGTH_2_MBYTES
+ default 0x0000007c if BAT3_LENGTH_4_MBYTES
+ default 0x000000fc if BAT3_LENGTH_8_MBYTES
+ default 0x000001fc if BAT3_LENGTH_16_MBYTES
+ default 0x000003fc if BAT3_LENGTH_32_MBYTES
+ default 0x000007fc if BAT3_LENGTH_64_MBYTES
+ default 0x00000ffc if BAT3_LENGTH_128_MBYTES
+ default 0x00001ffc if BAT3_LENGTH_256_MBYTES
+
+config BAT3_PAGE_PROTECTION
+ hex
+ default 0x0 if BAT3_ACCESS_NONE
+ default 0x1 if BAT3_ACCESS_RO
+ default 0x2 if BAT3_ACCESS_RW
+
+config BAT3_WIMG_ICACHE
+ hex
+ default 0x0 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+ default 0x8 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+ default 0x10 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+ default 0x18 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+ default 0x20 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+ default 0x28 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+ default 0x30 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+ default 0x38 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+ default 0x40 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+ default 0x48 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+ default 0x50 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+ default 0x58 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+ default 0x60 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+ default 0x68 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+ default 0x70 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+ default 0x78 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+
+config BAT3_WIMG_DCACHE
+ hex
+ default 0x0 if !BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+ default 0x8 if !BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+ default 0x10 if !BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+ default 0x18 if !BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+ default 0x20 if !BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+ default 0x28 if !BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+ default 0x30 if !BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+ default 0x38 if !BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+ default 0x40 if BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+ default 0x48 if BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+ default 0x50 if BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+ default 0x58 if BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+ default 0x60 if BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+ default 0x68 if BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+ default 0x70 if BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+ default 0x78 if BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+
+config BAT3_VALID_BITS
+ hex
+ default 0x0 if !BAT3_SUPERVISOR_MODE_VALID && !BAT3_USER_MODE_VALID
+ default 0x1 if !BAT3_SUPERVISOR_MODE_VALID && BAT3_USER_MODE_VALID
+ default 0x2 if BAT3_SUPERVISOR_MODE_VALID && !BAT3_USER_MODE_VALID
+ default 0x3 if BAT3_SUPERVISOR_MODE_VALID && BAT3_USER_MODE_VALID
+
+if HIGH_BATS
+
+menuconfig BAT4
+ bool "BAT4"
+
+if BAT4
+
+config BAT4_NAME
+ string "Identifier"
+
+config BAT4_BASE
+ hex "Base"
+
+choice
+ prompt "Block length"
+
+config BAT4_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config BAT4_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config BAT4_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config BAT4_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config BAT4_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config BAT4_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config BAT4_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config BAT4_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config BAT4_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config BAT4_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config BAT4_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config BAT4_LENGTH_256_MBYTES
+ bool "256 mb"
+endchoice
+
+choice
+ prompt "Protection mode"
+
+config BAT4_ACCESS_NONE
+ bool "No access"
+
+config BAT4_ACCESS_RO
+ bool "Read-only"
+
+config BAT4_ACCESS_RW
+ bool "Read-write"
+
+endchoice
+
+config BAT4_ICACHE_WRITETHROUGH
+ bool "I-cache Write-through"
+
+config BAT4_ICACHE_INHIBITED
+ bool "I-cache Inhibited"
+
+config BAT4_ICACHE_MEMORYCOHERENCE
+ bool "I-cache Memory coherence"
+
+config BAT4_ICACHE_GUARDED
+ bool "I-cache Guarded"
+
+config BAT4_DCACHE_WRITETHROUGH
+ bool "D-cache Write-through"
+
+config BAT4_DCACHE_INHIBITED
+ bool "D-cache Inhibited"
+
+config BAT4_DCACHE_MEMORYCOHERENCE
+ bool "D-cache Memory coherence"
+
+config BAT4_DCACHE_GUARDED
+ bool "D-cache Guarded"
+
+config BAT4_USER_MODE_VALID
+ bool "User mode valid"
+
+config BAT4_SUPERVISOR_MODE_VALID
+ bool "Supervisor mode valid"
+
+endif
+
+config BAT4_LENGTH
+ hex
+ default 0x00000000 if BAT4_LENGTH_128_KBYTES
+ default 0x00000004 if BAT4_LENGTH_256_KBYTES
+ default 0x0000000c if BAT4_LENGTH_512_KBYTES
+ default 0x0000001c if BAT4_LENGTH_1_MBYTES
+ default 0x0000003c if BAT4_LENGTH_2_MBYTES
+ default 0x0000007c if BAT4_LENGTH_4_MBYTES
+ default 0x000000fc if BAT4_LENGTH_8_MBYTES
+ default 0x000001fc if BAT4_LENGTH_16_MBYTES
+ default 0x000003fc if BAT4_LENGTH_32_MBYTES
+ default 0x000007fc if BAT4_LENGTH_64_MBYTES
+ default 0x00000ffc if BAT4_LENGTH_128_MBYTES
+ default 0x00001ffc if BAT4_LENGTH_256_MBYTES
+
+config BAT4_PAGE_PROTECTION
+ hex
+ default 0x0 if BAT4_ACCESS_NONE
+ default 0x1 if BAT4_ACCESS_RO
+ default 0x2 if BAT4_ACCESS_RW
+
+config BAT4_WIMG_ICACHE
+ hex
+ default 0x0 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+ default 0x8 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+ default 0x10 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+ default 0x18 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+ default 0x20 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+ default 0x28 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+ default 0x30 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+ default 0x38 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+ default 0x40 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+ default 0x48 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+ default 0x50 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+ default 0x58 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+ default 0x60 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+ default 0x68 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+ default 0x70 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+ default 0x78 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+
+config BAT4_WIMG_DCACHE
+ hex
+ default 0x0 if !BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+ default 0x8 if !BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+ default 0x10 if !BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+ default 0x18 if !BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+ default 0x20 if !BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+ default 0x28 if !BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+ default 0x30 if !BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+ default 0x38 if !BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+ default 0x40 if BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+ default 0x48 if BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+ default 0x50 if BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+ default 0x58 if BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+ default 0x60 if BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+ default 0x68 if BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+ default 0x70 if BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+ default 0x78 if BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+
+config BAT4_VALID_BITS
+ hex
+ default 0x0 if !BAT4_SUPERVISOR_MODE_VALID && !BAT4_USER_MODE_VALID
+ default 0x1 if !BAT4_SUPERVISOR_MODE_VALID && BAT4_USER_MODE_VALID
+ default 0x2 if BAT4_SUPERVISOR_MODE_VALID && !BAT4_USER_MODE_VALID
+ default 0x3 if BAT4_SUPERVISOR_MODE_VALID && BAT4_USER_MODE_VALID
+
+menuconfig BAT5
+ bool "BAT5"
+
+if BAT5
+
+config BAT5_NAME
+ string "Identifier"
+
+config BAT5_BASE
+ hex "Base"
+
+choice
+ prompt "Block length"
+
+config BAT5_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config BAT5_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config BAT5_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config BAT5_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config BAT5_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config BAT5_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config BAT5_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config BAT5_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config BAT5_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config BAT5_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config BAT5_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config BAT5_LENGTH_256_MBYTES
+ bool "256 mb"
+endchoice
+
+choice
+ prompt "Protection mode"
+
+config BAT5_ACCESS_NONE
+ bool "No access"
+
+config BAT5_ACCESS_RO
+ bool "Read-only"
+
+config BAT5_ACCESS_RW
+ bool "Read-write"
+
+endchoice
+
+config BAT5_ICACHE_WRITETHROUGH
+ bool "I-cache Write-through"
+
+config BAT5_ICACHE_INHIBITED
+ bool "I-cache Inhibited"
+
+config BAT5_ICACHE_MEMORYCOHERENCE
+ bool "I-cache Memory coherence"
+
+config BAT5_ICACHE_GUARDED
+ bool "I-cache Guarded"
+
+config BAT5_DCACHE_WRITETHROUGH
+ bool "D-cache Write-through"
+
+config BAT5_DCACHE_INHIBITED
+ bool "D-cache Inhibited"
+
+config BAT5_DCACHE_MEMORYCOHERENCE
+ bool "D-cache Memory coherence"
+
+config BAT5_DCACHE_GUARDED
+ bool "D-cache Guarded"
+
+config BAT5_USER_MODE_VALID
+ bool "User mode valid"
+
+config BAT5_SUPERVISOR_MODE_VALID
+ bool "Supervisor mode valid"
+
+endif
+
+config BAT5_LENGTH
+ hex
+ default 0x00000000 if BAT5_LENGTH_128_KBYTES
+ default 0x00000004 if BAT5_LENGTH_256_KBYTES
+ default 0x0000000c if BAT5_LENGTH_512_KBYTES
+ default 0x0000001c if BAT5_LENGTH_1_MBYTES
+ default 0x0000003c if BAT5_LENGTH_2_MBYTES
+ default 0x0000007c if BAT5_LENGTH_4_MBYTES
+ default 0x000000fc if BAT5_LENGTH_8_MBYTES
+ default 0x000001fc if BAT5_LENGTH_16_MBYTES
+ default 0x000003fc if BAT5_LENGTH_32_MBYTES
+ default 0x000007fc if BAT5_LENGTH_64_MBYTES
+ default 0x00000ffc if BAT5_LENGTH_128_MBYTES
+ default 0x00001ffc if BAT5_LENGTH_256_MBYTES
+
+config BAT5_PAGE_PROTECTION
+ hex
+ default 0x0 if BAT5_ACCESS_NONE
+ default 0x1 if BAT5_ACCESS_RO
+ default 0x2 if BAT5_ACCESS_RW
+
+config BAT5_WIMG_ICACHE
+ hex
+ default 0x0 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+ default 0x8 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+ default 0x10 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+ default 0x18 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+ default 0x20 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+ default 0x28 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+ default 0x30 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+ default 0x38 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+ default 0x40 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+ default 0x48 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+ default 0x50 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+ default 0x58 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+ default 0x60 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+ default 0x68 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+ default 0x70 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+ default 0x78 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+
+config BAT5_WIMG_DCACHE
+ hex
+ default 0x0 if !BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+ default 0x8 if !BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+ default 0x10 if !BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+ default 0x18 if !BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+ default 0x20 if !BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+ default 0x28 if !BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+ default 0x30 if !BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+ default 0x38 if !BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+ default 0x40 if BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+ default 0x48 if BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+ default 0x50 if BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+ default 0x58 if BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+ default 0x60 if BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+ default 0x68 if BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+ default 0x70 if BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+ default 0x78 if BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+
+config BAT5_VALID_BITS
+ hex
+ default 0x0 if !BAT5_SUPERVISOR_MODE_VALID && !BAT5_USER_MODE_VALID
+ default 0x1 if !BAT5_SUPERVISOR_MODE_VALID && BAT5_USER_MODE_VALID
+ default 0x2 if BAT5_SUPERVISOR_MODE_VALID && !BAT5_USER_MODE_VALID
+ default 0x3 if BAT5_SUPERVISOR_MODE_VALID && BAT5_USER_MODE_VALID
+
+menuconfig BAT6
+ bool "BAT6"
+
+if BAT6
+
+config BAT6_NAME
+ string "Identifier"
+
+config BAT6_BASE
+ hex "Base"
+
+choice
+ prompt "Block length"
+
+config BAT6_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config BAT6_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config BAT6_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config BAT6_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config BAT6_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config BAT6_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config BAT6_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config BAT6_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config BAT6_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config BAT6_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config BAT6_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config BAT6_LENGTH_256_MBYTES
+ bool "256 mb"
+endchoice
+
+choice
+ prompt "Protection mode"
+
+config BAT6_ACCESS_NONE
+ bool "No access"
+
+config BAT6_ACCESS_RO
+ bool "Read-only"
+
+config BAT6_ACCESS_RW
+ bool "Read-write"
+
+endchoice
+
+config BAT6_ICACHE_WRITETHROUGH
+ bool "I-cache Write-through"
+
+config BAT6_ICACHE_INHIBITED
+ bool "I-cache Inhibited"
+
+config BAT6_ICACHE_MEMORYCOHERENCE
+ bool "I-cache Memory coherence"
+
+config BAT6_ICACHE_GUARDED
+ bool "I-cache Guarded"
+
+config BAT6_DCACHE_WRITETHROUGH
+ bool "D-cache Write-through"
+
+config BAT6_DCACHE_INHIBITED
+ bool "D-cache Inhibited"
+
+config BAT6_DCACHE_MEMORYCOHERENCE
+ bool "D-cache Memory coherence"
+
+config BAT6_DCACHE_GUARDED
+ bool "D-cache Guarded"
+
+config BAT6_USER_MODE_VALID
+ bool "User mode valid"
+
+config BAT6_SUPERVISOR_MODE_VALID
+ bool "Supervisor mode valid"
+
+endif
+
+config BAT6_LENGTH
+ hex
+ default 0x00000000 if BAT6_LENGTH_128_KBYTES
+ default 0x00000004 if BAT6_LENGTH_256_KBYTES
+ default 0x0000000c if BAT6_LENGTH_512_KBYTES
+ default 0x0000001c if BAT6_LENGTH_1_MBYTES
+ default 0x0000003c if BAT6_LENGTH_2_MBYTES
+ default 0x0000007c if BAT6_LENGTH_4_MBYTES
+ default 0x000000fc if BAT6_LENGTH_8_MBYTES
+ default 0x000001fc if BAT6_LENGTH_16_MBYTES
+ default 0x000003fc if BAT6_LENGTH_32_MBYTES
+ default 0x000007fc if BAT6_LENGTH_64_MBYTES
+ default 0x00000ffc if BAT6_LENGTH_128_MBYTES
+ default 0x00001ffc if BAT6_LENGTH_256_MBYTES
+
+config BAT6_PAGE_PROTECTION
+ hex
+ default 0x0 if BAT6_ACCESS_NONE
+ default 0x1 if BAT6_ACCESS_RO
+ default 0x2 if BAT6_ACCESS_RW
+
+config BAT6_WIMG_ICACHE
+ hex
+ default 0x0 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+ default 0x8 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+ default 0x10 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+ default 0x18 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+ default 0x20 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+ default 0x28 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+ default 0x30 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+ default 0x38 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+ default 0x40 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+ default 0x48 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+ default 0x50 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+ default 0x58 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+ default 0x60 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+ default 0x68 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+ default 0x70 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+ default 0x78 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+
+config BAT6_WIMG_DCACHE
+ hex
+ default 0x0 if !BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+ default 0x8 if !BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+ default 0x10 if !BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+ default 0x18 if !BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+ default 0x20 if !BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+ default 0x28 if !BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+ default 0x30 if !BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+ default 0x38 if !BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+ default 0x40 if BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+ default 0x48 if BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+ default 0x50 if BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+ default 0x58 if BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+ default 0x60 if BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+ default 0x68 if BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+ default 0x70 if BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+ default 0x78 if BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+
+config BAT6_VALID_BITS
+ hex
+ default 0x0 if !BAT6_SUPERVISOR_MODE_VALID && !BAT6_USER_MODE_VALID
+ default 0x1 if !BAT6_SUPERVISOR_MODE_VALID && BAT6_USER_MODE_VALID
+ default 0x2 if BAT6_SUPERVISOR_MODE_VALID && !BAT6_USER_MODE_VALID
+ default 0x3 if BAT6_SUPERVISOR_MODE_VALID && BAT6_USER_MODE_VALID
+
+menuconfig BAT7
+ bool "BAT7"
+
+if BAT7
+
+config BAT7_NAME
+ string "Identifier"
+
+config BAT7_BASE
+ hex "Base"
+
+choice
+ prompt "Block length"
+
+config BAT7_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config BAT7_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config BAT7_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config BAT7_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config BAT7_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config BAT7_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config BAT7_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config BAT7_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config BAT7_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config BAT7_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config BAT7_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config BAT7_LENGTH_256_MBYTES
+ bool "256 mb"
+endchoice
+
+choice
+ prompt "Protection mode"
+
+config BAT7_ACCESS_NONE
+ bool "No access"
+
+config BAT7_ACCESS_RO
+ bool "Read-only"
+
+config BAT7_ACCESS_RW
+ bool "Read-write"
+
+endchoice
+
+config BAT7_ICACHE_WRITETHROUGH
+ bool "I-cache Write-through"
+
+config BAT7_ICACHE_INHIBITED
+ bool "I-cache Inhibited"
+
+config BAT7_ICACHE_MEMORYCOHERENCE
+ bool "I-cache Memory coherence"
+
+config BAT7_ICACHE_GUARDED
+ bool "I-cache Guarded"
+
+config BAT7_DCACHE_WRITETHROUGH
+ bool "D-cache Write-through"
+
+config BAT7_DCACHE_INHIBITED
+ bool "D-cache Inhibited"
+
+config BAT7_DCACHE_MEMORYCOHERENCE
+ bool "D-cache Memory coherence"
+
+config BAT7_DCACHE_GUARDED
+ bool "D-cache Guarded"
+
+config BAT7_USER_MODE_VALID
+ bool "User mode valid"
+
+config BAT7_SUPERVISOR_MODE_VALID
+ bool "Supervisor mode valid"
+
+endif
+
+config BAT7_LENGTH
+ hex
+ default 0x00000000 if BAT7_LENGTH_128_KBYTES
+ default 0x00000004 if BAT7_LENGTH_256_KBYTES
+ default 0x0000000c if BAT7_LENGTH_512_KBYTES
+ default 0x0000001c if BAT7_LENGTH_1_MBYTES
+ default 0x0000003c if BAT7_LENGTH_2_MBYTES
+ default 0x0000007c if BAT7_LENGTH_4_MBYTES
+ default 0x000000fc if BAT7_LENGTH_8_MBYTES
+ default 0x000001fc if BAT7_LENGTH_16_MBYTES
+ default 0x000003fc if BAT7_LENGTH_32_MBYTES
+ default 0x000007fc if BAT7_LENGTH_64_MBYTES
+ default 0x00000ffc if BAT7_LENGTH_128_MBYTES
+ default 0x00001ffc if BAT7_LENGTH_256_MBYTES
+
+config BAT7_PAGE_PROTECTION
+ hex
+ default 0x0 if BAT7_ACCESS_NONE
+ default 0x1 if BAT7_ACCESS_RO
+ default 0x2 if BAT7_ACCESS_RW
+
+config BAT7_WIMG_ICACHE
+ hex
+ default 0x0 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+ default 0x8 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+ default 0x10 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+ default 0x18 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+ default 0x20 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+ default 0x28 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+ default 0x30 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+ default 0x38 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+ default 0x40 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+ default 0x48 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+ default 0x50 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+ default 0x58 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+ default 0x60 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+ default 0x68 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+ default 0x70 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+ default 0x78 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+
+config BAT7_WIMG_DCACHE
+ hex
+ default 0x0 if !BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+ default 0x8 if !BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+ default 0x10 if !BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+ default 0x18 if !BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+ default 0x20 if !BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+ default 0x28 if !BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+ default 0x30 if !BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+ default 0x38 if !BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+ default 0x40 if BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+ default 0x48 if BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+ default 0x50 if BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+ default 0x58 if BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+ default 0x60 if BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+ default 0x68 if BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+ default 0x70 if BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+ default 0x78 if BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+
+config BAT7_VALID_BITS
+ hex
+ default 0x0 if !BAT7_SUPERVISOR_MODE_VALID && !BAT7_USER_MODE_VALID
+ default 0x1 if !BAT7_SUPERVISOR_MODE_VALID && BAT7_USER_MODE_VALID
+ default 0x2 if BAT7_SUPERVISOR_MODE_VALID && !BAT7_USER_MODE_VALID
+ default 0x3 if BAT7_SUPERVISOR_MODE_VALID && BAT7_USER_MODE_VALID
+
+endif
+
+endmenu
diff --git a/arch/powerpc/cpu/mpc83xx/bats/bats.h b/arch/powerpc/cpu/mpc83xx/bats/bats.h
new file mode 100644
index 0000000..f0754c2
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/bats/bats.h
@@ -0,0 +1,223 @@
+#ifdef CONFIG_BAT0
+#define CONFIG_SYS_IBAT0L (\
+ (CONFIG_BAT0_BASE) |\
+ (CONFIG_BAT0_PAGE_PROTECTION) |\
+ (CONFIG_BAT0_WIMG_ICACHE) \
+ )
+#define CONFIG_SYS_IBAT0U (\
+ (CONFIG_BAT0_BASE) |\
+ (CONFIG_BAT0_LENGTH) |\
+ (CONFIG_BAT0_VALID_BITS) \
+ )
+#define CONFIG_SYS_DBAT0L (\
+ (CONFIG_BAT0_BASE) |\
+ (CONFIG_BAT0_PAGE_PROTECTION) |\
+ (CONFIG_BAT0_WIMG_DCACHE) \
+ )
+#define CONFIG_SYS_DBAT0U (\
+ (CONFIG_BAT0_BASE) |\
+ (CONFIG_BAT0_LENGTH) |\
+ (CONFIG_BAT0_VALID_BITS) \
+ )
+#else
+#define CONFIG_SYS_IBAT0L (0)
+#define CONFIG_SYS_IBAT0U (0)
+#define CONFIG_SYS_DBAT0L (0)
+#define CONFIG_SYS_DBAT0U (0)
+#endif /* CONFIG_BAT0 */
+
+#ifdef CONFIG_BAT1
+#define CONFIG_SYS_IBAT1L (\
+ (CONFIG_BAT1_BASE) |\
+ (CONFIG_BAT1_PAGE_PROTECTION) |\
+ (CONFIG_BAT1_WIMG_ICACHE) \
+ )
+#define CONFIG_SYS_IBAT1U (\
+ (CONFIG_BAT1_BASE) |\
+ (CONFIG_BAT1_LENGTH) |\
+ (CONFIG_BAT1_VALID_BITS) \
+ )
+#define CONFIG_SYS_DBAT1L (\
+ (CONFIG_BAT1_BASE) |\
+ (CONFIG_BAT1_PAGE_PROTECTION) |\
+ (CONFIG_BAT1_WIMG_DCACHE) \
+ )
+#define CONFIG_SYS_DBAT1U (\
+ (CONFIG_BAT1_BASE) |\
+ (CONFIG_BAT1_LENGTH) |\
+ (CONFIG_BAT1_VALID_BITS) \
+ )
+#else
+#define CONFIG_SYS_IBAT1L (0)
+#define CONFIG_SYS_IBAT1U (0)
+#define CONFIG_SYS_DBAT1L (0)
+#define CONFIG_SYS_DBAT1U (0)
+#endif /* CONFIG_BAT1 */
+
+#ifdef CONFIG_BAT2
+#define CONFIG_SYS_IBAT2L (\
+ (CONFIG_BAT2_BASE) |\
+ (CONFIG_BAT2_PAGE_PROTECTION) |\
+ (CONFIG_BAT2_WIMG_ICACHE) \
+ )
+#define CONFIG_SYS_IBAT2U (\
+ (CONFIG_BAT2_BASE) |\
+ (CONFIG_BAT2_LENGTH) |\
+ (CONFIG_BAT2_VALID_BITS) \
+ )
+#define CONFIG_SYS_DBAT2L (\
+ (CONFIG_BAT2_BASE) |\
+ (CONFIG_BAT2_PAGE_PROTECTION) |\
+ (CONFIG_BAT2_WIMG_DCACHE) \
+ )
+#define CONFIG_SYS_DBAT2U (\
+ (CONFIG_BAT2_BASE) |\
+ (CONFIG_BAT2_LENGTH) |\
+ (CONFIG_BAT2_VALID_BITS) \
+ )
+#else
+#define CONFIG_SYS_IBAT2L (0)
+#define CONFIG_SYS_IBAT2U (0)
+#define CONFIG_SYS_DBAT2L (0)
+#define CONFIG_SYS_DBAT2U (0)
+#endif /* CONFIG_BAT2 */
+
+#ifdef CONFIG_BAT3
+#define CONFIG_SYS_IBAT3L (\
+ (CONFIG_BAT3_BASE) |\
+ (CONFIG_BAT3_PAGE_PROTECTION) |\
+ (CONFIG_BAT3_WIMG_ICACHE) \
+ )
+#define CONFIG_SYS_IBAT3U (\
+ (CONFIG_BAT3_BASE) |\
+ (CONFIG_BAT3_LENGTH) |\
+ (CONFIG_BAT3_VALID_BITS) \
+ )
+#define CONFIG_SYS_DBAT3L (\
+ (CONFIG_BAT3_BASE) |\
+ (CONFIG_BAT3_PAGE_PROTECTION) |\
+ (CONFIG_BAT3_WIMG_DCACHE) \
+ )
+#define CONFIG_SYS_DBAT3U (\
+ (CONFIG_BAT3_BASE) |\
+ (CONFIG_BAT3_LENGTH) |\
+ (CONFIG_BAT3_VALID_BITS) \
+ )
+#else
+#define CONFIG_SYS_IBAT3L (0)
+#define CONFIG_SYS_IBAT3U (0)
+#define CONFIG_SYS_DBAT3L (0)
+#define CONFIG_SYS_DBAT3U (0)
+#endif /* CONFIG_BAT3 */
+
+#ifdef CONFIG_BAT4
+#define CONFIG_SYS_IBAT4L (\
+ (CONFIG_BAT4_BASE) |\
+ (CONFIG_BAT4_PAGE_PROTECTION) |\
+ (CONFIG_BAT4_WIMG_ICACHE) \
+ )
+#define CONFIG_SYS_IBAT4U (\
+ (CONFIG_BAT4_BASE) |\
+ (CONFIG_BAT4_LENGTH) |\
+ (CONFIG_BAT4_VALID_BITS) \
+ )
+#define CONFIG_SYS_DBAT4L (\
+ (CONFIG_BAT4_BASE) |\
+ (CONFIG_BAT4_PAGE_PROTECTION) |\
+ (CONFIG_BAT4_WIMG_DCACHE) \
+ )
+#define CONFIG_SYS_DBAT4U (\
+ (CONFIG_BAT4_BASE) |\
+ (CONFIG_BAT4_LENGTH) |\
+ (CONFIG_BAT4_VALID_BITS) \
+ )
+#else
+#define CONFIG_SYS_IBAT4L (0)
+#define CONFIG_SYS_IBAT4U (0)
+#define CONFIG_SYS_DBAT4L (0)
+#define CONFIG_SYS_DBAT4U (0)
+#endif /* CONFIG_BAT4 */
+
+#ifdef CONFIG_BAT5
+#define CONFIG_SYS_IBAT5L (\
+ (CONFIG_BAT5_BASE) |\
+ (CONFIG_BAT5_PAGE_PROTECTION) |\
+ (CONFIG_BAT5_WIMG_ICACHE) \
+ )
+#define CONFIG_SYS_IBAT5U (\
+ (CONFIG_BAT5_BASE) |\
+ (CONFIG_BAT5_LENGTH) |\
+ (CONFIG_BAT5_VALID_BITS) \
+ )
+#define CONFIG_SYS_DBAT5L (\
+ (CONFIG_BAT5_BASE) |\
+ (CONFIG_BAT5_PAGE_PROTECTION) |\
+ (CONFIG_BAT5_WIMG_DCACHE) \
+ )
+#define CONFIG_SYS_DBAT5U (\
+ (CONFIG_BAT5_BASE) |\
+ (CONFIG_BAT5_LENGTH) |\
+ (CONFIG_BAT5_VALID_BITS) \
+ )
+#else
+#define CONFIG_SYS_IBAT5L (0)
+#define CONFIG_SYS_IBAT5U (0)
+#define CONFIG_SYS_DBAT5L (0)
+#define CONFIG_SYS_DBAT5U (0)
+#endif /* CONFIG_BAT5 */
+
+#ifdef CONFIG_BAT6
+#define CONFIG_SYS_IBAT6L (\
+ (CONFIG_BAT6_BASE) |\
+ (CONFIG_BAT6_PAGE_PROTECTION) |\
+ (CONFIG_BAT6_WIMG_ICACHE) \
+ )
+#define CONFIG_SYS_IBAT6U (\
+ (CONFIG_BAT6_BASE) |\
+ (CONFIG_BAT6_LENGTH) |\
+ (CONFIG_BAT6_VALID_BITS) \
+ )
+#define CONFIG_SYS_DBAT6L (\
+ (CONFIG_BAT6_BASE) |\
+ (CONFIG_BAT6_PAGE_PROTECTION) |\
+ (CONFIG_BAT6_WIMG_DCACHE) \
+ )
+#define CONFIG_SYS_DBAT6U (\
+ (CONFIG_BAT6_BASE) |\
+ (CONFIG_BAT6_LENGTH) |\
+ (CONFIG_BAT6_VALID_BITS) \
+ )
+#else
+#define CONFIG_SYS_IBAT6L (0)
+#define CONFIG_SYS_IBAT6U (0)
+#define CONFIG_SYS_DBAT6L (0)
+#define CONFIG_SYS_DBAT6U (0)
+#endif /* CONFIG_BAT6 */
+
+#ifdef CONFIG_BAT7
+#define CONFIG_SYS_IBAT7L (\
+ (CONFIG_BAT7_BASE) |\
+ (CONFIG_BAT7_PAGE_PROTECTION) |\
+ (CONFIG_BAT7_WIMG_ICACHE) \
+ )
+#define CONFIG_SYS_IBAT7U (\
+ (CONFIG_BAT7_BASE) |\
+ (CONFIG_BAT7_LENGTH) |\
+ (CONFIG_BAT7_VALID_BITS) \
+ )
+#define CONFIG_SYS_DBAT7L (\
+ (CONFIG_BAT7_BASE) |\
+ (CONFIG_BAT7_PAGE_PROTECTION) |\
+ (CONFIG_BAT7_WIMG_DCACHE) \
+ )
+#define CONFIG_SYS_DBAT7U (\
+ (CONFIG_BAT7_BASE) |\
+ (CONFIG_BAT7_LENGTH) |\
+ (CONFIG_BAT7_VALID_BITS) \
+ )
+#else
+#define CONFIG_SYS_IBAT7L (0)
+#define CONFIG_SYS_IBAT7U (0)
+#define CONFIG_SYS_DBAT7L (0)
+#define CONFIG_SYS_DBAT7U (0)
+#endif /* CONFIG_BAT7 */
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index b29f271..3048ecf 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -18,7 +18,7 @@
#include <tsec.h>
#include <netdev.h>
#include <fsl_esdhc.h>
-#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
+#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_ARCH_MPC831X)
#include <linux/immap_qe.h>
#include <asm/io.h>
#endif
@@ -133,18 +133,18 @@
#ifdef MPC83xx_RESET
/* Interrupts and MMU off */
- __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
-
- msr &= ~( MSR_EE | MSR_IR | MSR_DR);
- __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
+ msr = mfmsr();
+ msr &= ~(MSR_EE | MSR_IR | MSR_DR);
+ mtmsr(msr);
/* enable Reset Control Reg */
immap->reset.rpr = 0x52535445;
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
+ sync();
+ isync();
/* confirm Reset Control Reg is enabled */
- while(!((immap->reset.rcer) & RCER_CRE));
+ while(!((immap->reset.rcer) & RCER_CRE))
+ ;
udelay(200);
@@ -156,10 +156,9 @@
immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
/* Interrupts and MMU off */
- __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
-
+ msr = mfmsr();
msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
- __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
+ mtmsr(msr);
/*
* Trying to execute the next instruction at a non-existing address
@@ -199,6 +198,7 @@
}
#endif
+#ifndef CONFIG_DM_ETH
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
@@ -214,6 +214,7 @@
#endif
return 0;
}
+#endif /* !CONFIG_DM_ETH */
/*
* Initializes on-chip MMC controllers.
@@ -227,3 +228,21 @@
return 0;
#endif
}
+
+void ppcDWstore(unsigned int *addr, unsigned int *value)
+{
+ asm("lfd 1, 0(%1)\n\t"
+ "stfd 1, 0(%0)"
+ :
+ : "r" (addr), "r" (value)
+ : "memory");
+}
+
+void ppcDWload(unsigned int *addr, unsigned int *ret)
+{
+ asm("lfd 1, 0(%0)\n\t"
+ "stfd 1, 0(%1)"
+ :
+ : "r" (addr), "r" (ret)
+ : "memory");
+}
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 1555205..af8faca 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -12,6 +12,12 @@
#include <usb/ehci-ci.h>
#endif
+#include "lblaw/lblaw.h"
+#include "elbc/elbc.h"
+#include "sysio/sysio.h"
+#include "arbiter/arbiter.h"
+#include "initreg/initreg.h"
+
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_QE
@@ -47,62 +53,6 @@
*/
void cpu_init_f (volatile immap_t * im)
{
- __be32 acr_mask =
-#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
- ACR_PIPE_DEP |
-#endif
-#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
- ACR_RPTCNT |
-#endif
-#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
- ACR_APARK |
-#endif
-#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
- ACR_PARKM |
-#endif
- 0;
- __be32 acr_val =
-#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
- (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
- (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
- (CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
- (CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
-#endif
- 0;
- __be32 spcr_mask =
-#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
- SPCR_OPT |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
- SPCR_TSECEP |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
- SPCR_TSEC1EP |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
- SPCR_TSEC2EP |
-#endif
- 0;
- __be32 spcr_val =
-#ifdef CONFIG_SYS_SPCR_OPT
- (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
- (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
- (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
- (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
-#endif
- 0;
__be32 sccr_mask =
#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
SCCR_ENCCM |
@@ -179,28 +129,6 @@
(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
#endif
0;
- __be32 lcrr_mask =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
- LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
- LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
- LCRR_CLKDIV |
-#endif
- 0;
- __be32 lcrr_val =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
- CONFIG_SYS_LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC
- CONFIG_SYS_LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
- CONFIG_SYS_LCRR_CLKDIV |
-#endif
- 0;
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
@@ -240,7 +168,7 @@
/* System General Purpose Register */
#ifdef CONFIG_SYS_SICRH
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
+#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
__raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
&im->sysconf.sicrh);
@@ -312,7 +240,7 @@
im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
#endif
-#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_MPC831x)
+#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
uint32_t temp;
struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c
index 73f0be2..10e9b96 100644
--- a/arch/powerpc/cpu/mpc83xx/ecc.c
+++ b/arch/powerpc/cpu/mpc83xx/ecc.c
@@ -191,8 +191,8 @@
}
ddr->err_disable = val;
- __asm__ __volatile__("sync");
- __asm__ __volatile__("isync");
+ sync();
+ isync();
return 0;
} else if (strcmp(argv[1], "errdetectclr") == 0) {
val = ddr->err_detect;
@@ -249,8 +249,8 @@
printf("Incorrect command\n");
ddr->ecc_err_inject = val;
- __asm__ __volatile__("sync");
- __asm__ __volatile__("isync");
+ sync();
+ isync();
return 0;
} else if (strcmp(argv[1], "mirror") == 0) {
val = ddr->ecc_err_inject;
@@ -282,26 +282,26 @@
/* enable injects */
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
- __asm__ __volatile__("sync");
- __asm__ __volatile__("isync");
+ sync();
+ isync();
/* write memory location injecting errors */
ppcDWstore((u32 *) i, pattern);
- __asm__ __volatile__("sync");
+ sync();
/* disable injects */
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
- __asm__ __volatile__("sync");
- __asm__ __volatile__("isync");
+ sync();
+ isync();
/* read data, this generates ECC error */
ppcDWload((u32 *) i, ret);
- __asm__ __volatile__("sync");
+ sync();
/* re-initialize memory, double word write the location again,
* generates new ECC code this time */
ppcDWstore((u32 *) i, writeback);
- __asm__ __volatile__("sync");
+ sync();
}
enable_interrupts();
return 0;
@@ -321,29 +321,29 @@
/* enable injects */
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
- __asm__ __volatile__("sync");
- __asm__ __volatile__("isync");
+ sync();
+ isync();
/* write memory location injecting errors */
*(u32 *) i = 0xfedcba98UL;
- __asm__ __volatile__("sync");
+ sync();
/* sub double word write,
* bus will read-modify-write,
* generates ECC error */
*((u32 *) i + 1) = 0x76543210UL;
- __asm__ __volatile__("sync");
+ sync();
/* disable injects */
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
- __asm__ __volatile__("sync");
- __asm__ __volatile__("isync");
+ sync();
+ isync();
/* re-initialize memory,
* double word write the location again,
* generates new ECC code this time */
ppcDWstore((u32 *) i, writeback);
- __asm__ __volatile__("sync");
+ sync();
}
enable_interrupts();
return 0;
diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig
new file mode 100644
index 0000000..74c4ff3
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig
@@ -0,0 +1,32 @@
+menu "ELBC register setup"
+
+choice
+ prompt "OR/BR for NAND SPL"
+
+config ELBC_BR_OR_NAND_PRELIM_NONE
+ bool "None"
+
+config ELBC_BR_OR_NAND_PRELIM_0
+ bool "0"
+
+config ELBC_BR_OR_NAND_PRELIM_1
+ bool "1"
+
+config ELBC_BR_OR_NAND_PRELIM_2
+ bool "2"
+
+config ELBC_BR_OR_NAND_PRELIM_3
+ bool "3"
+
+config ELBC_BR_OR_NAND_PRELIM_4
+ bool "4"
+
+endchoice
+
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0"
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1"
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2"
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3"
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4"
+
+endmenu
diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0
new file mode 100644
index 0000000..23e81ab
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0
@@ -0,0 +1,733 @@
+menuconfig ELBC_BR0_OR0
+ bool "ELBC BR0/OR0"
+
+if ELBC_BR0_OR0
+
+config BR0_OR0_NAME
+ string "Identifier"
+
+config BR0_OR0_BASE
+ hex "Port base"
+
+choice
+ prompt "Port size"
+
+config BR0_PORTSIZE_8BIT
+ bool "8-bit"
+
+config BR0_PORTSIZE_16BIT
+ depends on !BR0_MACHINE_FCM
+ bool "16-bit"
+
+
+config BR0_PORTSIZE_32BIT
+ depends on !BR0_MACHINE_FCM
+ depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+ bool "32-bit"
+
+endchoice
+
+if BR0_MACHINE_FCM
+
+choice
+ prompt "Data Error Checking"
+
+config BR0_ERRORCHECKING_DISABLED
+ bool "Disabled"
+
+config BR0_ERRORCHECKING_ECC_CHECKING
+ bool "ECC checking / No ECC generation"
+
+config BR0_ERRORCHECKING_BOTH
+ bool "ECC checking and generation"
+
+endchoice
+
+endif
+
+config BR0_WRITE_PROTECT
+ bool "Write-protect"
+
+config BR0_MACHINE_UPM
+ bool
+
+choice
+ prompt "Machine select"
+
+config BR0_MACHINE_GPCM
+ bool "GPCM"
+
+config BR0_MACHINE_FCM
+ depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ bool "FCM"
+
+config BR0_MACHINE_SDRAM
+ depends on ARCH_MPC8349 || ARCH_MPC8360
+ bool "SDRAM"
+
+config BR0_MACHINE_UPMA
+ select BR0_MACHINE_UPM
+ bool "UPM (A)"
+
+config BR0_MACHINE_UPMB
+ select BR0_MACHINE_UPM
+ bool "UPM (B)"
+
+config BR0_MACHINE_UPMC
+ select BR0_MACHINE_UPM
+ bool "UPM (C)"
+
+endchoice
+
+if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
+
+choice
+ prompt "Atomic operations"
+
+config BR0_ATOMIC_NONE
+ bool "No atomic operations"
+
+config BR0_ATOMIC_RAWA
+ bool "Read-after-write-atomic"
+
+config BR0_ATOMIC_WARA
+ bool "Write-after-read-atomic"
+
+endchoice
+
+endif
+
+if BR0_MACHINE_GPCM || BR0_MACHINE_FCM || BR0_MACHINE_UPM || BR0_MACHINE_SDRAM
+
+choice
+ prompt "Address mask"
+
+config OR0_AM_32_KBYTES
+ depends on !BR0_MACHINE_SDRAM
+ bool "32 kb"
+
+config OR0_AM_64_KBYTES
+ bool "64 kb"
+
+config OR0_AM_128_KBYTES
+ bool "128 kb"
+
+config OR0_AM_256_KBYTES
+ bool "256 kb"
+
+config OR0_AM_512_KBYTES
+ bool "512 kb"
+
+config OR0_AM_1_MBYTES
+ bool "1 mb"
+
+config OR0_AM_2_MBYTES
+ bool "2 mb"
+
+config OR0_AM_4_MBYTES
+ bool "4 mb"
+
+config OR0_AM_8_MBYTES
+ bool "8 mb"
+
+config OR0_AM_16_MBYTES
+ bool "16 mb"
+
+config OR0_AM_32_MBYTES
+ bool "32 mb"
+
+config OR0_AM_64_MBYTES
+ bool "64 mb"
+
+# XXX: Some boards define 128MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR0_AM_128_MBYTES
+ bool "128 mb"
+
+# XXX: Some boards define 256MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR0_AM_256_MBYTES
+ bool "256 mb"
+
+config OR0_AM_512_MBYTES
+ depends on BR0_MACHINE_FCM
+ bool "512 mb"
+
+# XXX: Some boards define 1GB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR0_AM_1_GBYTES
+ bool "1 gb"
+
+config OR0_AM_2_GBYTES
+ depends on BR0_MACHINE_FCM
+ bool "2 gb"
+
+config OR0_AM_4_GBYTES
+ depends on BR0_MACHINE_FCM
+ bool "4 gb"
+
+endchoice
+
+config OR0_XAM_SET
+ bool "Set unused bytes after address mask"
+choice
+ prompt "Buffer control disable"
+
+config OR0_BCTLD_ASSERTED
+ bool "Asserted"
+
+config OR0_BCTLD_NOT_ASSERTED
+ bool "Not asserted"
+
+endchoice
+
+endif
+
+if BR0_MACHINE_GPCM || BR0_MACHINE_FCM
+
+choice
+ prompt "Cycle length in bus clocks"
+
+config OR0_SCY_0
+ bool "No wait states"
+
+config OR0_SCY_1
+ bool "1 wait state"
+
+config OR0_SCY_2
+ bool "2 wait states"
+
+config OR0_SCY_3
+ bool "3 wait states"
+
+config OR0_SCY_4
+ bool "4 wait states"
+
+config OR0_SCY_5
+ bool "5 wait states"
+
+config OR0_SCY_6
+ bool "6 wait states"
+
+config OR0_SCY_7
+ bool "7 wait states"
+
+config OR0_SCY_8
+ depends on BR0_MACHINE_GPCM
+ bool "8 wait states"
+
+config OR0_SCY_9
+ depends on BR0_MACHINE_GPCM
+ bool "9 wait states"
+
+config OR0_SCY_10
+ depends on BR0_MACHINE_GPCM
+ bool "10 wait states"
+
+config OR0_SCY_11
+ depends on BR0_MACHINE_GPCM
+ bool "11 wait states"
+
+config OR0_SCY_12
+ depends on BR0_MACHINE_GPCM
+ bool "12 wait states"
+
+config OR0_SCY_13
+ depends on BR0_MACHINE_GPCM
+ bool "13 wait states"
+
+config OR0_SCY_14
+ depends on BR0_MACHINE_GPCM
+ bool "14 wait states"
+
+config OR0_SCY_15
+ depends on BR0_MACHINE_GPCM
+ bool "15 wait states"
+
+endchoice
+
+endif # BR0_MACHINE_GPCM || BR0_MACHINE_FCM
+
+if BR0_MACHINE_GPCM
+
+choice
+ prompt "Chip select negotiation time"
+
+config OR0_CSNT_NORMAL
+ bool "Normal"
+
+config OR0_CSNT_EARLIER
+ bool "Earlier"
+
+endchoice
+
+choice
+ prompt "Address to chip-select setup"
+
+config OR0_ACS_SAME_TIME
+ bool "At the same time"
+
+config OR0_ACS_HALF_CYCLE_EARLIER
+ bool "Half of a bus clock cycle earlier"
+
+config OR0_ACS_QUARTER_CYCLE_EARLIER
+ bool "Half/Quarter of a bus clock cycle earlier"
+
+endchoice
+
+choice
+ prompt "Extra address to check-select setup"
+
+config OR0_XACS_NORMAL
+ bool "Normal"
+
+config OR0_XACS_EXTENDED
+ bool "Extended"
+
+endchoice
+
+choice
+ prompt "External address termination"
+
+config OR0_SETA_INTERNAL
+ bool "Access is terminated internally"
+
+config OR0_SETA_EXTERNAL
+ bool "Access is terminated externally"
+
+endchoice
+
+endif # BR0_MACHINE_GPCM
+
+if BR0_MACHINE_FCM
+
+choice
+ prompt "NAND Flash EEPROM page size"
+
+config OR0_PGS_SMALL
+ bool "Small page device"
+
+config OR0_PGS_LARGE
+ bool "Large page device"
+
+endchoice
+
+choice
+ prompt "Chip select to command time"
+
+config OR0_CSCT_1_CYCLE
+ depends on OR0_TRLX_NORMAL
+ bool "1 cycle"
+
+config OR0_CSCT_2_CYCLE
+ depends on OR0_TRLX_RELAXED
+ bool "2 cycles"
+
+config OR0_CSCT_4_CYCLE
+ depends on OR0_TRLX_NORMAL
+ bool "4 cycles"
+
+config OR0_CSCT_8_CYCLE
+ depends on OR0_TRLX_RELAXED
+ bool "8 cycles"
+
+endchoice
+
+choice
+ prompt "Command setup time"
+
+config OR0_CST_COINCIDENT
+ depends on OR0_TRLX_NORMAL
+ bool "Coincident with any command"
+
+config OR0_CST_QUARTER_CLOCK
+ depends on OR0_TRLX_NORMAL
+ bool "0.25 clocks after"
+
+config OR0_CST_HALF_CLOCK
+ depends on OR0_TRLX_RELAXED
+ bool "0.5 clocks after"
+
+config OR0_CST_ONE_CLOCK
+ depends on OR0_TRLX_RELAXED
+ bool "1 clock after"
+
+endchoice
+
+choice
+ prompt "Command hold time"
+
+config OR0_CHT_HALF_CLOCK
+ depends on OR0_TRLX_NORMAL
+ bool "0.5 clocks before"
+
+config OR0_CHT_ONE_CLOCK
+ depends on OR0_TRLX_NORMAL
+ bool "1 clock before"
+
+config OR0_CHT_ONE_HALF_CLOCK
+ depends on OR0_TRLX_RELAXED
+ bool "1.5 clocks before"
+
+config OR0_CHT_TWO_CLOCK
+ depends on OR0_TRLX_RELAXED
+ bool "2 clocks before"
+
+endchoice
+
+choice
+ prompt "Reset setup time"
+
+config OR0_RST_THREE_QUARTER_CLOCK
+ depends on OR0_TRLX_NORMAL
+ bool "0.75 clocks prior"
+
+config OR0_RST_ONE_HALF_CLOCK
+ depends on OR0_TRLX_RELAXED
+ bool "0.5 clocks prior"
+
+config OR0_RST_ONE_CLOCK
+ bool "1 clock prior"
+
+endchoice
+
+endif # BR0_MACHINE_FCM
+
+if BR0_MACHINE_UPM
+
+choice
+ prompt "Burst inhibit"
+
+config OR0_BI_BURSTSUPPORT
+ bool "Support burst access"
+
+config OR0_BI_BURSTINHIBIT
+ bool "Inhibit burst access"
+
+endchoice
+
+endif # BR0_MACHINE_UPM
+
+if BR0_MACHINE_SDRAM
+
+choice
+ prompt "Number of column address lines"
+
+config OR0_COLS_7
+ bool "7"
+
+config OR0_COLS_8
+ bool "8"
+
+config OR0_COLS_9
+ bool "9"
+
+config OR0_COLS_10
+ bool "10"
+
+config OR0_COLS_11
+ bool "11"
+
+config OR0_COLS_12
+ bool "12"
+
+config OR0_COLS_13
+ bool "13"
+
+config OR0_COLS_14
+ bool "14"
+
+endchoice
+
+choice
+ prompt "Number of rows address lines"
+
+config OR0_ROWS_9
+ bool "9"
+
+config OR0_ROWS_10
+ bool "10"
+
+config OR0_ROWS_11
+ bool "11"
+
+config OR0_ROWS_12
+ bool "12"
+
+config OR0_ROWS_13
+ bool "13"
+
+config OR0_ROWS_14
+ bool "14"
+
+config OR0_ROWS_15
+ bool "15"
+
+endchoice
+
+choice
+ prompt "Page mode select"
+
+config OR0_PMSEL_BTB
+ bool "Back-to-back"
+
+config OR0_PMSEL_KEPT_OPEN
+ bool "Page kept open until page miss or refresh"
+
+endchoice
+
+endif # BR0_MACHINE_SDRAM
+
+choice
+ prompt "Relaxed timing"
+
+config OR0_TRLX_NORMAL
+ bool "Normal"
+
+config OR0_TRLX_RELAXED
+ bool "Relaxed"
+
+endchoice
+
+choice
+ prompt "Extended hold time"
+
+config OR0_EHTR_NORMAL
+ depends on OR0_TRLX_NORMAL
+ bool "Normal"
+
+config OR0_EHTR_1_CYCLE
+ depends on OR0_TRLX_NORMAL
+ bool "1 idle clock cycle inserted"
+
+config OR0_EHTR_4_CYCLE
+ depends on OR0_TRLX_RELAXED
+ bool "4 idle clock cycles inserted"
+
+config OR0_EHTR_8_CYCLE
+ depends on OR0_TRLX_RELAXED
+ bool "8 idle clock cycles inserted"
+
+endchoice
+
+if !ARCH_MPC8308
+
+choice
+ prompt "External address latch delay"
+
+config OR0_EAD_NONE
+ bool "None"
+
+config OR0_EAD_EXTRA
+ bool "Extra"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+endif # ELBC_BR0_OR0
+
+config BR0_PORTSIZE
+ hex
+ default 0x800 if BR0_PORTSIZE_8BIT
+ default 0x1000 if BR0_PORTSIZE_16BIT
+ default 0x1800 if BR0_PORTSIZE_32BIT
+
+config BR0_ERRORCHECKING
+ hex
+ default 0x0 if !BR0_MACHINE_FCM
+ default 0x0 if BR0_ERRORCHECKING_DISABLED
+ default 0x200 if BR0_ERRORCHECKING_ECC_CHECKING
+ default 0x400 if BR0_ERRORCHECKING_BOTH
+
+config BR0_WRITE_PROTECT_BIT
+ hex
+ default 0x0 if !BR0_WRITE_PROTECT
+ default 0x100 if BR0_WRITE_PROTECT
+
+config BR0_MACHINE
+ hex
+ default 0x0 if BR0_MACHINE_GPCM
+ default 0x20 if BR0_MACHINE_FCM
+ default 0x60 if BR0_MACHINE_SDRAM
+ default 0x80 if BR0_MACHINE_UPMA
+ default 0xa0 if BR0_MACHINE_UPMB
+ default 0xc0 if BR0_MACHINE_UPMC
+
+config BR0_ATOMIC
+ hex
+ default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
+ default 0x0 if BR0_ATOMIC_NONE
+ default 0x4 if BR0_ATOMIC_RAWA
+ default 0x8 if BR0_ATOMIC_WARA
+
+config BR0_VALID_BIT
+ hex
+ default 0x0 if !ELBC_BR0_OR0
+ default 0x1 if ELBC_BR0_OR0
+
+config OR0_AM
+ hex
+ default 0xffff8000 if OR0_AM_32_KBYTES && !BR0_MACHINE_SDRAM
+ default 0xffff0000 if OR0_AM_64_KBYTES
+ default 0xfffe0000 if OR0_AM_128_KBYTES
+ default 0xfffc0000 if OR0_AM_256_KBYTES
+ default 0xfff80000 if OR0_AM_512_KBYTES
+ default 0xfff00000 if OR0_AM_1_MBYTES
+ default 0xffe00000 if OR0_AM_2_MBYTES
+ default 0xffc00000 if OR0_AM_4_MBYTES
+ default 0xff800000 if OR0_AM_8_MBYTES
+ default 0xff000000 if OR0_AM_16_MBYTES
+ default 0xfe000000 if OR0_AM_32_MBYTES
+ default 0xfc000000 if OR0_AM_64_MBYTES
+ default 0xf8000000 if OR0_AM_128_MBYTES
+ default 0xf0000000 if OR0_AM_256_MBYTES
+ default 0xe0000000 if OR0_AM_512_MBYTES
+ default 0xc0000000 if OR0_AM_1_GBYTES
+ default 0x80000000 if OR0_AM_2_GBYTES
+ default 0x00000000 if OR0_AM_4_GBYTES
+
+config OR0_XAM
+ hex
+ default 0x0 if !OR0_XAM_SET
+ default 0x6000 if OR0_XAM_SET
+
+config OR0_BCTLD
+ hex
+ default 0x0 if OR0_BCTLD_ASSERTED
+ default 0x1000 if OR0_BCTLD_NOT_ASSERTED
+
+config OR0_BI
+ hex
+ default 0x0 if !BR0_MACHINE_UPM
+ default 0x0 if OR0_BI_BURSTSUPPORT
+ default 0x100 if OR0_BI_BURSTINHIBIT
+
+config OR0_COLS
+ hex
+ default 0x0 if !BR0_MACHINE_SDRAM
+ default 0x0 if OR0_COLS_7
+ default 0x400 if OR0_COLS_8
+ default 0x800 if OR0_COLS_9
+ default 0xc00 if OR0_COLS_10
+ default 0x1000 if OR0_COLS_11
+ default 0x1400 if OR0_COLS_12
+ default 0x1800 if OR0_COLS_13
+ default 0x1c00 if OR0_COLS_14
+
+config OR0_ROWS
+ hex
+ default 0x0 if !BR0_MACHINE_SDRAM
+ default 0x0 if OR0_ROWS_9
+ default 0x40 if OR0_ROWS_10
+ default 0x80 if OR0_ROWS_11
+ default 0xc0 if OR0_ROWS_12
+ default 0x100 if OR0_ROWS_13
+ default 0x140 if OR0_ROWS_14
+ default 0x180 if OR0_ROWS_15
+
+config OR0_PMSEL
+ hex
+ default 0x0 if !BR0_MACHINE_SDRAM
+ default 0x0 if OR0_PMSEL_BTB
+ default 0x20 if OR0_PMSEL_KEPT_OPEN
+
+config OR0_SCY
+ hex
+ default 0x0 if !BR0_MACHINE_GPCM && !BR0_MACHINE_FCM
+ default 0x0 if OR0_SCY_0
+ default 0x10 if OR0_SCY_1
+ default 0x20 if OR0_SCY_2
+ default 0x30 if OR0_SCY_3
+ default 0x40 if OR0_SCY_4
+ default 0x50 if OR0_SCY_5
+ default 0x60 if OR0_SCY_6
+ default 0x70 if OR0_SCY_7
+ default 0x80 if OR0_SCY_8
+ default 0x90 if OR0_SCY_9
+ default 0xa0 if OR0_SCY_10
+ default 0xb0 if OR0_SCY_11
+ default 0xc0 if OR0_SCY_12
+ default 0xd0 if OR0_SCY_13
+ default 0xe0 if OR0_SCY_14
+ default 0xf0 if OR0_SCY_15
+
+config OR0_PGS
+ hex
+ default 0x0 if !BR0_MACHINE_FCM
+ default 0x0 if OR0_PGS_SMALL
+ default 0x400 if OR0_PGS_LARGE
+
+config OR0_CSCT
+ hex
+ default 0x0 if !BR0_MACHINE_FCM
+ default 0x0 if OR0_CSCT_1_CYCLE
+ default 0x0 if OR0_CSCT_2_CYCLE
+ default 0x200 if OR0_CSCT_4_CYCLE
+ default 0x200 if OR0_CSCT_8_CYCLE
+
+config OR0_CST
+ hex
+ default 0x0 if !BR0_MACHINE_FCM
+ default 0x0 if OR0_CST_COINCIDENT
+ default 0x100 if OR0_CST_QUARTER_CLOCK
+ default 0x0 if OR0_CST_HALF_CLOCK
+ default 0x100 if OR0_CST_ONE_CLOCK
+
+config OR0_CHT
+ hex
+ default 0x0 if !BR0_MACHINE_FCM
+ default 0x0 if OR0_CHT_HALF_CLOCK
+ default 0x80 if OR0_CHT_ONE_CLOCK
+ default 0x0 if OR0_CHT_ONE_HALF_CLOCK
+ default 0x80 if OR0_CHT_TWO_CLOCK
+
+config OR0_RST
+ hex
+ default 0x0 if !BR0_MACHINE_FCM
+ default 0x0 if OR0_RST_THREE_QUARTER_CLOCK
+ default 0x8 if OR0_RST_ONE_CLOCK
+ default 0x0 if OR0_RST_ONE_HALF_CLOCK
+
+config OR0_CSNT
+ hex
+ default 0x0 if !BR0_MACHINE_GPCM
+ default 0x0 if OR0_CSNT_NORMAL
+ default 0x800 if OR0_CSNT_EARLIER
+
+config OR0_ACS
+ hex
+ default 0x0 if !BR0_MACHINE_GPCM
+ default 0x0 if OR0_ACS_SAME_TIME
+ default 0x400 if OR0_ACS_QUARTER_CYCLE_EARLIER
+ default 0x600 if OR0_ACS_HALF_CYCLE_EARLIER
+
+config OR0_XACS
+ hex
+ default 0x0 if !BR0_MACHINE_GPCM
+ default 0x0 if OR0_XACS_NORMAL
+ default 0x100 if OR0_XACS_EXTENDED
+
+config OR0_SETA
+ hex
+ default 0x0 if !BR0_MACHINE_GPCM
+ default 0x0 if OR0_SETA_INTERNAL
+ default 0x8 if OR0_SETA_EXTERNAL
+
+config OR0_TRLX
+ hex
+ default 0x0 if OR0_TRLX_NORMAL
+ default 0x4 if OR0_TRLX_RELAXED
+
+config OR0_EHTR
+ hex
+ default 0x0 if OR0_EHTR_NORMAL
+ default 0x2 if OR0_EHTR_1_CYCLE
+ default 0x0 if OR0_EHTR_4_CYCLE
+ default 0x2 if OR0_EHTR_8_CYCLE
+
+config OR0_EAD
+ hex
+ default 0x0 if ARCH_MPC8308
+ default 0x0 if OR0_EAD_NONE
+ default 0x1 if OR0_EAD_EXTRA
diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1
new file mode 100644
index 0000000..08dcc7d
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1
@@ -0,0 +1,733 @@
+menuconfig ELBC_BR1_OR1
+ bool "ELBC BR1/OR1"
+
+if ELBC_BR1_OR1
+
+config BR1_OR1_NAME
+ string "Identifier"
+
+config BR1_OR1_BASE
+ hex "Port base"
+
+choice
+ prompt "Port size"
+
+config BR1_PORTSIZE_8BIT
+ bool "8-bit"
+
+config BR1_PORTSIZE_16BIT
+ depends on !BR1_MACHINE_FCM
+ bool "16-bit"
+
+
+config BR1_PORTSIZE_32BIT
+ depends on !BR1_MACHINE_FCM
+ depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+ bool "32-bit"
+
+endchoice
+
+if BR1_MACHINE_FCM
+
+choice
+ prompt "Data Error Checking"
+
+config BR1_ERRORCHECKING_DISABLED
+ bool "Disabled"
+
+config BR1_ERRORCHECKING_ECC_CHECKING
+ bool "ECC checking / No ECC generation"
+
+config BR1_ERRORCHECKING_BOTH
+ bool "ECC checking and generation"
+
+endchoice
+
+endif
+
+config BR1_WRITE_PROTECT
+ bool "Write-protect"
+
+config BR1_MACHINE_UPM
+ bool
+
+choice
+ prompt "Machine select"
+
+config BR1_MACHINE_GPCM
+ bool "GPCM"
+
+config BR1_MACHINE_FCM
+ depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ bool "FCM"
+
+config BR1_MACHINE_SDRAM
+ depends on ARCH_MPC8349 || ARCH_MPC8360
+ bool "SDRAM"
+
+config BR1_MACHINE_UPMA
+ select BR1_MACHINE_UPM
+ bool "UPM (A)"
+
+config BR1_MACHINE_UPMB
+ select BR1_MACHINE_UPM
+ bool "UPM (B)"
+
+config BR1_MACHINE_UPMC
+ select BR1_MACHINE_UPM
+ bool "UPM (C)"
+
+endchoice
+
+if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
+
+choice
+ prompt "Atomic operations"
+
+config BR1_ATOMIC_NONE
+ bool "No atomic operations"
+
+config BR1_ATOMIC_RAWA
+ bool "Read-after-write-atomic"
+
+config BR1_ATOMIC_WARA
+ bool "Write-after-read-atomic"
+
+endchoice
+
+endif
+
+if BR1_MACHINE_GPCM || BR1_MACHINE_FCM || BR1_MACHINE_UPM || BR1_MACHINE_SDRAM
+
+choice
+ prompt "Address mask"
+
+config OR1_AM_32_KBYTES
+ depends on !BR1_MACHINE_SDRAM
+ bool "32 kb"
+
+config OR1_AM_64_KBYTES
+ bool "64 kb"
+
+config OR1_AM_128_KBYTES
+ bool "128 kb"
+
+config OR1_AM_256_KBYTES
+ bool "256 kb"
+
+config OR1_AM_512_KBYTES
+ bool "512 kb"
+
+config OR1_AM_1_MBYTES
+ bool "1 mb"
+
+config OR1_AM_2_MBYTES
+ bool "2 mb"
+
+config OR1_AM_4_MBYTES
+ bool "4 mb"
+
+config OR1_AM_8_MBYTES
+ bool "8 mb"
+
+config OR1_AM_16_MBYTES
+ bool "16 mb"
+
+config OR1_AM_32_MBYTES
+ bool "32 mb"
+
+config OR1_AM_64_MBYTES
+ bool "64 mb"
+
+# XXX: Some boards define 128MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR1_AM_128_MBYTES
+ bool "128 mb"
+
+# XXX: Some boards define 256MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR1_AM_256_MBYTES
+ bool "256 mb"
+
+config OR1_AM_512_MBYTES
+ depends on BR1_MACHINE_FCM
+ bool "512 mb"
+
+# XXX: Some boards define 1GB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR1_AM_1_GBYTES
+ bool "1 gb"
+
+config OR1_AM_2_GBYTES
+ depends on BR1_MACHINE_FCM
+ bool "2 gb"
+
+config OR1_AM_4_GBYTES
+ depends on BR1_MACHINE_FCM
+ bool "4 gb"
+
+endchoice
+
+config OR1_XAM_SET
+ bool "Set unused bytes after address mask"
+choice
+ prompt "Buffer control disable"
+
+config OR1_BCTLD_ASSERTED
+ bool "Asserted"
+
+config OR1_BCTLD_NOT_ASSERTED
+ bool "Not asserted"
+
+endchoice
+
+endif
+
+if BR1_MACHINE_GPCM || BR1_MACHINE_FCM
+
+choice
+ prompt "Cycle length in bus clocks"
+
+config OR1_SCY_0
+ bool "No wait states"
+
+config OR1_SCY_1
+ bool "1 wait state"
+
+config OR1_SCY_2
+ bool "2 wait states"
+
+config OR1_SCY_3
+ bool "3 wait states"
+
+config OR1_SCY_4
+ bool "4 wait states"
+
+config OR1_SCY_5
+ bool "5 wait states"
+
+config OR1_SCY_6
+ bool "6 wait states"
+
+config OR1_SCY_7
+ bool "7 wait states"
+
+config OR1_SCY_8
+ depends on BR1_MACHINE_GPCM
+ bool "8 wait states"
+
+config OR1_SCY_9
+ depends on BR1_MACHINE_GPCM
+ bool "9 wait states"
+
+config OR1_SCY_10
+ depends on BR1_MACHINE_GPCM
+ bool "10 wait states"
+
+config OR1_SCY_11
+ depends on BR1_MACHINE_GPCM
+ bool "11 wait states"
+
+config OR1_SCY_12
+ depends on BR1_MACHINE_GPCM
+ bool "12 wait states"
+
+config OR1_SCY_13
+ depends on BR1_MACHINE_GPCM
+ bool "13 wait states"
+
+config OR1_SCY_14
+ depends on BR1_MACHINE_GPCM
+ bool "14 wait states"
+
+config OR1_SCY_15
+ depends on BR1_MACHINE_GPCM
+ bool "15 wait states"
+
+endchoice
+
+endif # BR1_MACHINE_GPCM || BR1_MACHINE_FCM
+
+if BR1_MACHINE_GPCM
+
+choice
+ prompt "Chip select negotiation time"
+
+config OR1_CSNT_NORMAL
+ bool "Normal"
+
+config OR1_CSNT_EARLIER
+ bool "Earlier"
+
+endchoice
+
+choice
+ prompt "Address to chip-select setup"
+
+config OR1_ACS_SAME_TIME
+ bool "At the same time"
+
+config OR1_ACS_HALF_CYCLE_EARLIER
+ bool "Half of a bus clock cycle earlier"
+
+config OR1_ACS_QUARTER_CYCLE_EARLIER
+ bool "Half/Quarter of a bus clock cycle earlier"
+
+endchoice
+
+choice
+ prompt "Extra address to check-select setup"
+
+config OR1_XACS_NORMAL
+ bool "Normal"
+
+config OR1_XACS_EXTENDED
+ bool "Extended"
+
+endchoice
+
+choice
+ prompt "External address termination"
+
+config OR1_SETA_INTERNAL
+ bool "Access is terminated internally"
+
+config OR1_SETA_EXTERNAL
+ bool "Access is terminated externally"
+
+endchoice
+
+endif # BR1_MACHINE_GPCM
+
+if BR1_MACHINE_FCM
+
+choice
+ prompt "NAND Flash EEPROM page size"
+
+config OR1_PGS_SMALL
+ bool "Small page device"
+
+config OR1_PGS_LARGE
+ bool "Large page device"
+
+endchoice
+
+choice
+ prompt "Chip select to command time"
+
+config OR1_CSCT_1_CYCLE
+ depends on OR1_TRLX_NORMAL
+ bool "1 cycle"
+
+config OR1_CSCT_2_CYCLE
+ depends on OR1_TRLX_RELAXED
+ bool "2 cycles"
+
+config OR1_CSCT_4_CYCLE
+ depends on OR1_TRLX_NORMAL
+ bool "4 cycles"
+
+config OR1_CSCT_8_CYCLE
+ depends on OR1_TRLX_RELAXED
+ bool "8 cycles"
+
+endchoice
+
+choice
+ prompt "Command setup time"
+
+config OR1_CST_COINCIDENT
+ depends on OR1_TRLX_NORMAL
+ bool "Coincident with any command"
+
+config OR1_CST_QUARTER_CLOCK
+ depends on OR1_TRLX_NORMAL
+ bool "0.25 clocks after"
+
+config OR1_CST_HALF_CLOCK
+ depends on OR1_TRLX_RELAXED
+ bool "0.5 clocks after"
+
+config OR1_CST_ONE_CLOCK
+ depends on OR1_TRLX_RELAXED
+ bool "1 clock after"
+
+endchoice
+
+choice
+ prompt "Command hold time"
+
+config OR1_CHT_HALF_CLOCK
+ depends on OR1_TRLX_NORMAL
+ bool "0.5 clocks before"
+
+config OR1_CHT_ONE_CLOCK
+ depends on OR1_TRLX_NORMAL
+ bool "1 clock before"
+
+config OR1_CHT_ONE_HALF_CLOCK
+ depends on OR1_TRLX_RELAXED
+ bool "1.5 clocks before"
+
+config OR1_CHT_TWO_CLOCK
+ depends on OR1_TRLX_RELAXED
+ bool "2 clocks before"
+
+endchoice
+
+choice
+ prompt "Reset setup time"
+
+config OR1_RST_THREE_QUARTER_CLOCK
+ depends on OR1_TRLX_NORMAL
+ bool "0.75 clocks prior"
+
+config OR1_RST_ONE_HALF_CLOCK
+ depends on OR1_TRLX_RELAXED
+ bool "0.5 clocks prior"
+
+config OR1_RST_ONE_CLOCK
+ bool "1 clock prior"
+
+endchoice
+
+endif # BR1_MACHINE_FCM
+
+if BR1_MACHINE_UPM
+
+choice
+ prompt "Burst inhibit"
+
+config OR1_BI_BURSTSUPPORT
+ bool "Support burst access"
+
+config OR1_BI_BURSTINHIBIT
+ bool "Inhibit burst access"
+
+endchoice
+
+endif # BR1_MACHINE_UPM
+
+if BR1_MACHINE_SDRAM
+
+choice
+ prompt "Number of column address lines"
+
+config OR1_COLS_7
+ bool "7"
+
+config OR1_COLS_8
+ bool "8"
+
+config OR1_COLS_9
+ bool "9"
+
+config OR1_COLS_10
+ bool "10"
+
+config OR1_COLS_11
+ bool "11"
+
+config OR1_COLS_12
+ bool "12"
+
+config OR1_COLS_13
+ bool "13"
+
+config OR1_COLS_14
+ bool "14"
+
+endchoice
+
+choice
+ prompt "Number of rows address lines"
+
+config OR1_ROWS_9
+ bool "9"
+
+config OR1_ROWS_10
+ bool "10"
+
+config OR1_ROWS_11
+ bool "11"
+
+config OR1_ROWS_12
+ bool "12"
+
+config OR1_ROWS_13
+ bool "13"
+
+config OR1_ROWS_14
+ bool "14"
+
+config OR1_ROWS_15
+ bool "15"
+
+endchoice
+
+choice
+ prompt "Page mode select"
+
+config OR1_PMSEL_BTB
+ bool "Back-to-back"
+
+config OR1_PMSEL_KEPT_OPEN
+ bool "Page kept open until page miss or refresh"
+
+endchoice
+
+endif # BR1_MACHINE_SDRAM
+
+choice
+ prompt "Relaxed timing"
+
+config OR1_TRLX_NORMAL
+ bool "Normal"
+
+config OR1_TRLX_RELAXED
+ bool "Relaxed"
+
+endchoice
+
+choice
+ prompt "Extended hold time"
+
+config OR1_EHTR_NORMAL
+ depends on OR1_TRLX_NORMAL
+ bool "Normal"
+
+config OR1_EHTR_1_CYCLE
+ depends on OR1_TRLX_NORMAL
+ bool "1 idle clock cycle inserted"
+
+config OR1_EHTR_4_CYCLE
+ depends on OR1_TRLX_RELAXED
+ bool "4 idle clock cycles inserted"
+
+config OR1_EHTR_8_CYCLE
+ depends on OR1_TRLX_RELAXED
+ bool "8 idle clock cycles inserted"
+
+endchoice
+
+if !ARCH_MPC8308
+
+choice
+ prompt "External address latch delay"
+
+config OR1_EAD_NONE
+ bool "None"
+
+config OR1_EAD_EXTRA
+ bool "Extra"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+endif # ELBC_BR1_OR1
+
+config BR1_PORTSIZE
+ hex
+ default 0x800 if BR1_PORTSIZE_8BIT
+ default 0x1000 if BR1_PORTSIZE_16BIT
+ default 0x1800 if BR1_PORTSIZE_32BIT
+
+config BR1_ERRORCHECKING
+ hex
+ default 0x0 if !BR1_MACHINE_FCM
+ default 0x0 if BR1_ERRORCHECKING_DISABLED
+ default 0x200 if BR1_ERRORCHECKING_ECC_CHECKING
+ default 0x400 if BR1_ERRORCHECKING_BOTH
+
+config BR1_WRITE_PROTECT_BIT
+ hex
+ default 0x0 if !BR1_WRITE_PROTECT
+ default 0x100 if BR1_WRITE_PROTECT
+
+config BR1_MACHINE
+ hex
+ default 0x0 if BR1_MACHINE_GPCM
+ default 0x20 if BR1_MACHINE_FCM
+ default 0x60 if BR1_MACHINE_SDRAM
+ default 0x80 if BR1_MACHINE_UPMA
+ default 0xa0 if BR1_MACHINE_UPMB
+ default 0xc0 if BR1_MACHINE_UPMC
+
+config BR1_ATOMIC
+ hex
+ default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
+ default 0x0 if BR1_ATOMIC_NONE
+ default 0x4 if BR1_ATOMIC_RAWA
+ default 0x8 if BR1_ATOMIC_WARA
+
+config BR1_VALID_BIT
+ hex
+ default 0x0 if !ELBC_BR1_OR1
+ default 0x1 if ELBC_BR1_OR1
+
+config OR1_AM
+ hex
+ default 0xffff8000 if OR1_AM_32_KBYTES && !BR1_MACHINE_SDRAM
+ default 0xffff0000 if OR1_AM_64_KBYTES
+ default 0xfffe0000 if OR1_AM_128_KBYTES
+ default 0xfffc0000 if OR1_AM_256_KBYTES
+ default 0xfff80000 if OR1_AM_512_KBYTES
+ default 0xfff00000 if OR1_AM_1_MBYTES
+ default 0xffe00000 if OR1_AM_2_MBYTES
+ default 0xffc00000 if OR1_AM_4_MBYTES
+ default 0xff800000 if OR1_AM_8_MBYTES
+ default 0xff000000 if OR1_AM_16_MBYTES
+ default 0xfe000000 if OR1_AM_32_MBYTES
+ default 0xfc000000 if OR1_AM_64_MBYTES
+ default 0xf8000000 if OR1_AM_128_MBYTES
+ default 0xf0000000 if OR1_AM_256_MBYTES
+ default 0xe0000000 if OR1_AM_512_MBYTES
+ default 0xc0000000 if OR1_AM_1_GBYTES
+ default 0x80000000 if OR1_AM_2_GBYTES
+ default 0x00000000 if OR1_AM_4_GBYTES
+
+config OR1_XAM
+ hex
+ default 0x0 if !OR1_XAM_SET
+ default 0x6000 if OR1_XAM_SET
+
+config OR1_BCTLD
+ hex
+ default 0x0 if OR1_BCTLD_ASSERTED
+ default 0x1000 if OR1_BCTLD_NOT_ASSERTED
+
+config OR1_BI
+ hex
+ default 0x0 if !BR1_MACHINE_UPM
+ default 0x0 if OR1_BI_BURSTSUPPORT
+ default 0x100 if OR1_BI_BURSTINHIBIT
+
+config OR1_COLS
+ hex
+ default 0x0 if !BR1_MACHINE_SDRAM
+ default 0x0 if OR1_COLS_7
+ default 0x400 if OR1_COLS_8
+ default 0x800 if OR1_COLS_9
+ default 0xc00 if OR1_COLS_10
+ default 0x1000 if OR1_COLS_11
+ default 0x1400 if OR1_COLS_12
+ default 0x1800 if OR1_COLS_13
+ default 0x1c00 if OR1_COLS_14
+
+config OR1_ROWS
+ hex
+ default 0x0 if !BR1_MACHINE_SDRAM
+ default 0x0 if OR1_ROWS_9
+ default 0x40 if OR1_ROWS_10
+ default 0x80 if OR1_ROWS_11
+ default 0xc0 if OR1_ROWS_12
+ default 0x100 if OR1_ROWS_13
+ default 0x140 if OR1_ROWS_14
+ default 0x180 if OR1_ROWS_15
+
+config OR1_PMSEL
+ hex
+ default 0x0 if !BR1_MACHINE_SDRAM
+ default 0x0 if OR1_PMSEL_BTB
+ default 0x20 if OR1_PMSEL_KEPT_OPEN
+
+config OR1_SCY
+ hex
+ default 0x0 if !BR1_MACHINE_GPCM && !BR1_MACHINE_FCM
+ default 0x0 if OR1_SCY_0
+ default 0x10 if OR1_SCY_1
+ default 0x20 if OR1_SCY_2
+ default 0x30 if OR1_SCY_3
+ default 0x40 if OR1_SCY_4
+ default 0x50 if OR1_SCY_5
+ default 0x60 if OR1_SCY_6
+ default 0x70 if OR1_SCY_7
+ default 0x80 if OR1_SCY_8
+ default 0x90 if OR1_SCY_9
+ default 0xa0 if OR1_SCY_10
+ default 0xb0 if OR1_SCY_11
+ default 0xc0 if OR1_SCY_12
+ default 0xd0 if OR1_SCY_13
+ default 0xe0 if OR1_SCY_14
+ default 0xf0 if OR1_SCY_15
+
+config OR1_PGS
+ hex
+ default 0x0 if !BR1_MACHINE_FCM
+ default 0x0 if OR1_PGS_SMALL
+ default 0x400 if OR1_PGS_LARGE
+
+config OR1_CSCT
+ hex
+ default 0x0 if !BR1_MACHINE_FCM
+ default 0x0 if OR1_CSCT_1_CYCLE
+ default 0x0 if OR1_CSCT_2_CYCLE
+ default 0x200 if OR1_CSCT_4_CYCLE
+ default 0x200 if OR1_CSCT_8_CYCLE
+
+config OR1_CST
+ hex
+ default 0x0 if !BR1_MACHINE_FCM
+ default 0x0 if OR1_CST_COINCIDENT
+ default 0x100 if OR1_CST_QUARTER_CLOCK
+ default 0x0 if OR1_CST_HALF_CLOCK
+ default 0x100 if OR1_CST_ONE_CLOCK
+
+config OR1_CHT
+ hex
+ default 0x0 if !BR1_MACHINE_FCM
+ default 0x0 if OR1_CHT_HALF_CLOCK
+ default 0x80 if OR1_CHT_ONE_CLOCK
+ default 0x0 if OR1_CHT_ONE_HALF_CLOCK
+ default 0x80 if OR1_CHT_TWO_CLOCK
+
+config OR1_RST
+ hex
+ default 0x0 if !BR1_MACHINE_FCM
+ default 0x0 if OR1_RST_THREE_QUARTER_CLOCK
+ default 0x8 if OR1_RST_ONE_CLOCK
+ default 0x0 if OR1_RST_ONE_HALF_CLOCK
+
+config OR1_CSNT
+ hex
+ default 0x0 if !BR1_MACHINE_GPCM
+ default 0x0 if OR1_CSNT_NORMAL
+ default 0x800 if OR1_CSNT_EARLIER
+
+config OR1_ACS
+ hex
+ default 0x0 if !BR1_MACHINE_GPCM
+ default 0x0 if OR1_ACS_SAME_TIME
+ default 0x400 if OR1_ACS_QUARTER_CYCLE_EARLIER
+ default 0x600 if OR1_ACS_HALF_CYCLE_EARLIER
+
+config OR1_XACS
+ hex
+ default 0x0 if !BR1_MACHINE_GPCM
+ default 0x0 if OR1_XACS_NORMAL
+ default 0x100 if OR1_XACS_EXTENDED
+
+config OR1_SETA
+ hex
+ default 0x0 if !BR1_MACHINE_GPCM
+ default 0x0 if OR1_SETA_INTERNAL
+ default 0x8 if OR1_SETA_EXTERNAL
+
+config OR1_TRLX
+ hex
+ default 0x0 if OR1_TRLX_NORMAL
+ default 0x4 if OR1_TRLX_RELAXED
+
+config OR1_EHTR
+ hex
+ default 0x0 if OR1_EHTR_NORMAL
+ default 0x2 if OR1_EHTR_1_CYCLE
+ default 0x0 if OR1_EHTR_4_CYCLE
+ default 0x2 if OR1_EHTR_8_CYCLE
+
+config OR1_EAD
+ hex
+ default 0x0 if ARCH_MPC8308
+ default 0x0 if OR1_EAD_NONE
+ default 0x1 if OR1_EAD_EXTRA
diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2
new file mode 100644
index 0000000..298d87f
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2
@@ -0,0 +1,733 @@
+menuconfig ELBC_BR2_OR2
+ bool "ELBC BR2/OR2"
+
+if ELBC_BR2_OR2
+
+config BR2_OR2_NAME
+ string "Identifier"
+
+config BR2_OR2_BASE
+ hex "Port base"
+
+choice
+ prompt "Port size"
+
+config BR2_PORTSIZE_8BIT
+ bool "8-bit"
+
+config BR2_PORTSIZE_16BIT
+ depends on !BR2_MACHINE_FCM
+ bool "16-bit"
+
+
+config BR2_PORTSIZE_32BIT
+ depends on !BR2_MACHINE_FCM
+ depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+ bool "32-bit"
+
+endchoice
+
+if BR2_MACHINE_FCM
+
+choice
+ prompt "Data Error Checking"
+
+config BR2_ERRORCHECKING_DISABLED
+ bool "Disabled"
+
+config BR2_ERRORCHECKING_ECC_CHECKING
+ bool "ECC checking / No ECC generation"
+
+config BR2_ERRORCHECKING_BOTH
+ bool "ECC checking and generation"
+
+endchoice
+
+endif
+
+config BR2_WRITE_PROTECT
+ bool "Write-protect"
+
+config BR2_MACHINE_UPM
+ bool
+
+choice
+ prompt "Machine select"
+
+config BR2_MACHINE_GPCM
+ bool "GPCM"
+
+config BR2_MACHINE_FCM
+ depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ bool "FCM"
+
+config BR2_MACHINE_SDRAM
+ depends on ARCH_MPC8349 || ARCH_MPC8360
+ bool "SDRAM"
+
+config BR2_MACHINE_UPMA
+ select BR2_MACHINE_UPM
+ bool "UPM (A)"
+
+config BR2_MACHINE_UPMB
+ select BR2_MACHINE_UPM
+ bool "UPM (B)"
+
+config BR2_MACHINE_UPMC
+ select BR2_MACHINE_UPM
+ bool "UPM (C)"
+
+endchoice
+
+if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
+
+choice
+ prompt "Atomic operations"
+
+config BR2_ATOMIC_NONE
+ bool "No atomic operations"
+
+config BR2_ATOMIC_RAWA
+ bool "Read-after-write-atomic"
+
+config BR2_ATOMIC_WARA
+ bool "Write-after-read-atomic"
+
+endchoice
+
+endif
+
+if BR2_MACHINE_GPCM || BR2_MACHINE_FCM || BR2_MACHINE_UPM || BR2_MACHINE_SDRAM
+
+choice
+ prompt "Address mask"
+
+config OR2_AM_32_KBYTES
+ depends on !BR2_MACHINE_SDRAM
+ bool "32 kb"
+
+config OR2_AM_64_KBYTES
+ bool "64 kb"
+
+config OR2_AM_128_KBYTES
+ bool "128 kb"
+
+config OR2_AM_256_KBYTES
+ bool "256 kb"
+
+config OR2_AM_512_KBYTES
+ bool "512 kb"
+
+config OR2_AM_1_MBYTES
+ bool "1 mb"
+
+config OR2_AM_2_MBYTES
+ bool "2 mb"
+
+config OR2_AM_4_MBYTES
+ bool "4 mb"
+
+config OR2_AM_8_MBYTES
+ bool "8 mb"
+
+config OR2_AM_16_MBYTES
+ bool "16 mb"
+
+config OR2_AM_32_MBYTES
+ bool "32 mb"
+
+config OR2_AM_64_MBYTES
+ bool "64 mb"
+
+# XXX: Some boards define 128MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR2_AM_128_MBYTES
+ bool "128 mb"
+
+# XXX: Some boards define 256MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR2_AM_256_MBYTES
+ bool "256 mb"
+
+config OR2_AM_512_MBYTES
+ depends on BR2_MACHINE_FCM
+ bool "512 mb"
+
+# XXX: Some boards define 1GB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR2_AM_1_GBYTES
+ bool "1 gb"
+
+config OR2_AM_2_GBYTES
+ depends on BR2_MACHINE_FCM
+ bool "2 gb"
+
+config OR2_AM_4_GBYTES
+ depends on BR2_MACHINE_FCM
+ bool "4 gb"
+
+endchoice
+
+config OR2_XAM_SET
+ bool "Set unused bytes after address mask"
+choice
+ prompt "Buffer control disable"
+
+config OR2_BCTLD_ASSERTED
+ bool "Asserted"
+
+config OR2_BCTLD_NOT_ASSERTED
+ bool "Not asserted"
+
+endchoice
+
+endif
+
+if BR2_MACHINE_GPCM || BR2_MACHINE_FCM
+
+choice
+ prompt "Cycle length in bus clocks"
+
+config OR2_SCY_0
+ bool "No wait states"
+
+config OR2_SCY_1
+ bool "1 wait state"
+
+config OR2_SCY_2
+ bool "2 wait states"
+
+config OR2_SCY_3
+ bool "3 wait states"
+
+config OR2_SCY_4
+ bool "4 wait states"
+
+config OR2_SCY_5
+ bool "5 wait states"
+
+config OR2_SCY_6
+ bool "6 wait states"
+
+config OR2_SCY_7
+ bool "7 wait states"
+
+config OR2_SCY_8
+ depends on BR2_MACHINE_GPCM
+ bool "8 wait states"
+
+config OR2_SCY_9
+ depends on BR2_MACHINE_GPCM
+ bool "9 wait states"
+
+config OR2_SCY_10
+ depends on BR2_MACHINE_GPCM
+ bool "10 wait states"
+
+config OR2_SCY_11
+ depends on BR2_MACHINE_GPCM
+ bool "11 wait states"
+
+config OR2_SCY_12
+ depends on BR2_MACHINE_GPCM
+ bool "12 wait states"
+
+config OR2_SCY_13
+ depends on BR2_MACHINE_GPCM
+ bool "13 wait states"
+
+config OR2_SCY_14
+ depends on BR2_MACHINE_GPCM
+ bool "14 wait states"
+
+config OR2_SCY_15
+ depends on BR2_MACHINE_GPCM
+ bool "15 wait states"
+
+endchoice
+
+endif # BR2_MACHINE_GPCM || BR2_MACHINE_FCM
+
+if BR2_MACHINE_GPCM
+
+choice
+ prompt "Chip select negotiation time"
+
+config OR2_CSNT_NORMAL
+ bool "Normal"
+
+config OR2_CSNT_EARLIER
+ bool "Earlier"
+
+endchoice
+
+choice
+ prompt "Address to chip-select setup"
+
+config OR2_ACS_SAME_TIME
+ bool "At the same time"
+
+config OR2_ACS_HALF_CYCLE_EARLIER
+ bool "Half of a bus clock cycle earlier"
+
+config OR2_ACS_QUARTER_CYCLE_EARLIER
+ bool "Half/Quarter of a bus clock cycle earlier"
+
+endchoice
+
+choice
+ prompt "Extra address to check-select setup"
+
+config OR2_XACS_NORMAL
+ bool "Normal"
+
+config OR2_XACS_EXTENDED
+ bool "Extended"
+
+endchoice
+
+choice
+ prompt "External address termination"
+
+config OR2_SETA_INTERNAL
+ bool "Access is terminated internally"
+
+config OR2_SETA_EXTERNAL
+ bool "Access is terminated externally"
+
+endchoice
+
+endif # BR2_MACHINE_GPCM
+
+if BR2_MACHINE_FCM
+
+choice
+ prompt "NAND Flash EEPROM page size"
+
+config OR2_PGS_SMALL
+ bool "Small page device"
+
+config OR2_PGS_LARGE
+ bool "Large page device"
+
+endchoice
+
+choice
+ prompt "Chip select to command time"
+
+config OR2_CSCT_1_CYCLE
+ depends on OR2_TRLX_NORMAL
+ bool "1 cycle"
+
+config OR2_CSCT_2_CYCLE
+ depends on OR2_TRLX_RELAXED
+ bool "2 cycles"
+
+config OR2_CSCT_4_CYCLE
+ depends on OR2_TRLX_NORMAL
+ bool "4 cycles"
+
+config OR2_CSCT_8_CYCLE
+ depends on OR2_TRLX_RELAXED
+ bool "8 cycles"
+
+endchoice
+
+choice
+ prompt "Command setup time"
+
+config OR2_CST_COINCIDENT
+ depends on OR2_TRLX_NORMAL
+ bool "Coincident with any command"
+
+config OR2_CST_QUARTER_CLOCK
+ depends on OR2_TRLX_NORMAL
+ bool "0.25 clocks after"
+
+config OR2_CST_HALF_CLOCK
+ depends on OR2_TRLX_RELAXED
+ bool "0.5 clocks after"
+
+config OR2_CST_ONE_CLOCK
+ depends on OR2_TRLX_RELAXED
+ bool "1 clock after"
+
+endchoice
+
+choice
+ prompt "Command hold time"
+
+config OR2_CHT_HALF_CLOCK
+ depends on OR2_TRLX_NORMAL
+ bool "0.5 clocks before"
+
+config OR2_CHT_ONE_CLOCK
+ depends on OR2_TRLX_NORMAL
+ bool "1 clock before"
+
+config OR2_CHT_ONE_HALF_CLOCK
+ depends on OR2_TRLX_RELAXED
+ bool "1.5 clocks before"
+
+config OR2_CHT_TWO_CLOCK
+ depends on OR2_TRLX_RELAXED
+ bool "2 clocks before"
+
+endchoice
+
+choice
+ prompt "Reset setup time"
+
+config OR2_RST_THREE_QUARTER_CLOCK
+ depends on OR2_TRLX_NORMAL
+ bool "0.75 clocks prior"
+
+config OR2_RST_ONE_HALF_CLOCK
+ depends on OR2_TRLX_RELAXED
+ bool "0.5 clocks prior"
+
+config OR2_RST_ONE_CLOCK
+ bool "1 clock prior"
+
+endchoice
+
+endif # BR2_MACHINE_FCM
+
+if BR2_MACHINE_UPM
+
+choice
+ prompt "Burst inhibit"
+
+config OR2_BI_BURSTSUPPORT
+ bool "Support burst access"
+
+config OR2_BI_BURSTINHIBIT
+ bool "Inhibit burst access"
+
+endchoice
+
+endif # BR2_MACHINE_UPM
+
+if BR2_MACHINE_SDRAM
+
+choice
+ prompt "Number of column address lines"
+
+config OR2_COLS_7
+ bool "7"
+
+config OR2_COLS_8
+ bool "8"
+
+config OR2_COLS_9
+ bool "9"
+
+config OR2_COLS_10
+ bool "10"
+
+config OR2_COLS_11
+ bool "11"
+
+config OR2_COLS_12
+ bool "12"
+
+config OR2_COLS_13
+ bool "13"
+
+config OR2_COLS_14
+ bool "14"
+
+endchoice
+
+choice
+ prompt "Number of rows address lines"
+
+config OR2_ROWS_9
+ bool "9"
+
+config OR2_ROWS_10
+ bool "10"
+
+config OR2_ROWS_11
+ bool "11"
+
+config OR2_ROWS_12
+ bool "12"
+
+config OR2_ROWS_13
+ bool "13"
+
+config OR2_ROWS_14
+ bool "14"
+
+config OR2_ROWS_15
+ bool "15"
+
+endchoice
+
+choice
+ prompt "Page mode select"
+
+config OR2_PMSEL_BTB
+ bool "Back-to-back"
+
+config OR2_PMSEL_KEPT_OPEN
+ bool "Page kept open until page miss or refresh"
+
+endchoice
+
+endif # BR2_MACHINE_SDRAM
+
+choice
+ prompt "Relaxed timing"
+
+config OR2_TRLX_NORMAL
+ bool "Normal"
+
+config OR2_TRLX_RELAXED
+ bool "Relaxed"
+
+endchoice
+
+choice
+ prompt "Extended hold time"
+
+config OR2_EHTR_NORMAL
+ depends on OR2_TRLX_NORMAL
+ bool "Normal"
+
+config OR2_EHTR_1_CYCLE
+ depends on OR2_TRLX_NORMAL
+ bool "1 idle clock cycle inserted"
+
+config OR2_EHTR_4_CYCLE
+ depends on OR2_TRLX_RELAXED
+ bool "4 idle clock cycles inserted"
+
+config OR2_EHTR_8_CYCLE
+ depends on OR2_TRLX_RELAXED
+ bool "8 idle clock cycles inserted"
+
+endchoice
+
+if !ARCH_MPC8308
+
+choice
+ prompt "External address latch delay"
+
+config OR2_EAD_NONE
+ bool "None"
+
+config OR2_EAD_EXTRA
+ bool "Extra"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+endif # ELBC_BR2_OR2
+
+config BR2_PORTSIZE
+ hex
+ default 0x800 if BR2_PORTSIZE_8BIT
+ default 0x1000 if BR2_PORTSIZE_16BIT
+ default 0x1800 if BR2_PORTSIZE_32BIT
+
+config BR2_ERRORCHECKING
+ hex
+ default 0x0 if !BR2_MACHINE_FCM
+ default 0x0 if BR2_ERRORCHECKING_DISABLED
+ default 0x200 if BR2_ERRORCHECKING_ECC_CHECKING
+ default 0x400 if BR2_ERRORCHECKING_BOTH
+
+config BR2_WRITE_PROTECT_BIT
+ hex
+ default 0x0 if !BR2_WRITE_PROTECT
+ default 0x100 if BR2_WRITE_PROTECT
+
+config BR2_MACHINE
+ hex
+ default 0x0 if BR2_MACHINE_GPCM
+ default 0x20 if BR2_MACHINE_FCM
+ default 0x60 if BR2_MACHINE_SDRAM
+ default 0x80 if BR2_MACHINE_UPMA
+ default 0xa0 if BR2_MACHINE_UPMB
+ default 0xc0 if BR2_MACHINE_UPMC
+
+config BR2_ATOMIC
+ hex
+ default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
+ default 0x0 if BR2_ATOMIC_NONE
+ default 0x4 if BR2_ATOMIC_RAWA
+ default 0x8 if BR2_ATOMIC_WARA
+
+config BR2_VALID_BIT
+ hex
+ default 0x0 if !ELBC_BR2_OR2
+ default 0x1 if ELBC_BR2_OR2
+
+config OR2_AM
+ hex
+ default 0xffff8000 if OR2_AM_32_KBYTES && !BR2_MACHINE_SDRAM
+ default 0xffff0000 if OR2_AM_64_KBYTES
+ default 0xfffe0000 if OR2_AM_128_KBYTES
+ default 0xfffc0000 if OR2_AM_256_KBYTES
+ default 0xfff80000 if OR2_AM_512_KBYTES
+ default 0xfff00000 if OR2_AM_1_MBYTES
+ default 0xffe00000 if OR2_AM_2_MBYTES
+ default 0xffc00000 if OR2_AM_4_MBYTES
+ default 0xff800000 if OR2_AM_8_MBYTES
+ default 0xff000000 if OR2_AM_16_MBYTES
+ default 0xfe000000 if OR2_AM_32_MBYTES
+ default 0xfc000000 if OR2_AM_64_MBYTES
+ default 0xf8000000 if OR2_AM_128_MBYTES
+ default 0xf0000000 if OR2_AM_256_MBYTES
+ default 0xe0000000 if OR2_AM_512_MBYTES
+ default 0xc0000000 if OR2_AM_1_GBYTES
+ default 0x80000000 if OR2_AM_2_GBYTES
+ default 0x00000000 if OR2_AM_4_GBYTES
+
+config OR2_XAM
+ hex
+ default 0x0 if !OR2_XAM_SET
+ default 0x6000 if OR2_XAM_SET
+
+config OR2_BCTLD
+ hex
+ default 0x0 if OR2_BCTLD_ASSERTED
+ default 0x1000 if OR2_BCTLD_NOT_ASSERTED
+
+config OR2_BI
+ hex
+ default 0x0 if !BR2_MACHINE_UPM
+ default 0x0 if OR2_BI_BURSTSUPPORT
+ default 0x100 if OR2_BI_BURSTINHIBIT
+
+config OR2_COLS
+ hex
+ default 0x0 if !BR2_MACHINE_SDRAM
+ default 0x0 if OR2_COLS_7
+ default 0x400 if OR2_COLS_8
+ default 0x800 if OR2_COLS_9
+ default 0xc00 if OR2_COLS_10
+ default 0x1000 if OR2_COLS_11
+ default 0x1400 if OR2_COLS_12
+ default 0x1800 if OR2_COLS_13
+ default 0x1c00 if OR2_COLS_14
+
+config OR2_ROWS
+ hex
+ default 0x0 if !BR2_MACHINE_SDRAM
+ default 0x0 if OR2_ROWS_9
+ default 0x40 if OR2_ROWS_10
+ default 0x80 if OR2_ROWS_11
+ default 0xc0 if OR2_ROWS_12
+ default 0x100 if OR2_ROWS_13
+ default 0x140 if OR2_ROWS_14
+ default 0x180 if OR2_ROWS_15
+
+config OR2_PMSEL
+ hex
+ default 0x0 if !BR2_MACHINE_SDRAM
+ default 0x0 if OR2_PMSEL_BTB
+ default 0x20 if OR2_PMSEL_KEPT_OPEN
+
+config OR2_SCY
+ hex
+ default 0x0 if !BR2_MACHINE_GPCM && !BR2_MACHINE_FCM
+ default 0x0 if OR2_SCY_0
+ default 0x10 if OR2_SCY_1
+ default 0x20 if OR2_SCY_2
+ default 0x30 if OR2_SCY_3
+ default 0x40 if OR2_SCY_4
+ default 0x50 if OR2_SCY_5
+ default 0x60 if OR2_SCY_6
+ default 0x70 if OR2_SCY_7
+ default 0x80 if OR2_SCY_8
+ default 0x90 if OR2_SCY_9
+ default 0xa0 if OR2_SCY_10
+ default 0xb0 if OR2_SCY_11
+ default 0xc0 if OR2_SCY_12
+ default 0xd0 if OR2_SCY_13
+ default 0xe0 if OR2_SCY_14
+ default 0xf0 if OR2_SCY_15
+
+config OR2_PGS
+ hex
+ default 0x0 if !BR2_MACHINE_FCM
+ default 0x0 if OR2_PGS_SMALL
+ default 0x400 if OR2_PGS_LARGE
+
+config OR2_CSCT
+ hex
+ default 0x0 if !BR2_MACHINE_FCM
+ default 0x0 if OR2_CSCT_1_CYCLE
+ default 0x0 if OR2_CSCT_2_CYCLE
+ default 0x200 if OR2_CSCT_4_CYCLE
+ default 0x200 if OR2_CSCT_8_CYCLE
+
+config OR2_CST
+ hex
+ default 0x0 if !BR2_MACHINE_FCM
+ default 0x0 if OR2_CST_COINCIDENT
+ default 0x100 if OR2_CST_QUARTER_CLOCK
+ default 0x0 if OR2_CST_HALF_CLOCK
+ default 0x100 if OR2_CST_ONE_CLOCK
+
+config OR2_CHT
+ hex
+ default 0x0 if !BR2_MACHINE_FCM
+ default 0x0 if OR2_CHT_HALF_CLOCK
+ default 0x80 if OR2_CHT_ONE_CLOCK
+ default 0x0 if OR2_CHT_ONE_HALF_CLOCK
+ default 0x80 if OR2_CHT_TWO_CLOCK
+
+config OR2_RST
+ hex
+ default 0x0 if !BR2_MACHINE_FCM
+ default 0x0 if OR2_RST_THREE_QUARTER_CLOCK
+ default 0x8 if OR2_RST_ONE_CLOCK
+ default 0x0 if OR2_RST_ONE_HALF_CLOCK
+
+config OR2_CSNT
+ hex
+ default 0x0 if !BR2_MACHINE_GPCM
+ default 0x0 if OR2_CSNT_NORMAL
+ default 0x800 if OR2_CSNT_EARLIER
+
+config OR2_ACS
+ hex
+ default 0x0 if !BR2_MACHINE_GPCM
+ default 0x0 if OR2_ACS_SAME_TIME
+ default 0x400 if OR2_ACS_QUARTER_CYCLE_EARLIER
+ default 0x600 if OR2_ACS_HALF_CYCLE_EARLIER
+
+config OR2_XACS
+ hex
+ default 0x0 if !BR2_MACHINE_GPCM
+ default 0x0 if OR2_XACS_NORMAL
+ default 0x100 if OR2_XACS_EXTENDED
+
+config OR2_SETA
+ hex
+ default 0x0 if !BR2_MACHINE_GPCM
+ default 0x0 if OR2_SETA_INTERNAL
+ default 0x8 if OR2_SETA_EXTERNAL
+
+config OR2_TRLX
+ hex
+ default 0x0 if OR2_TRLX_NORMAL
+ default 0x4 if OR2_TRLX_RELAXED
+
+config OR2_EHTR
+ hex
+ default 0x0 if OR2_EHTR_NORMAL
+ default 0x2 if OR2_EHTR_1_CYCLE
+ default 0x0 if OR2_EHTR_4_CYCLE
+ default 0x2 if OR2_EHTR_8_CYCLE
+
+config OR2_EAD
+ hex
+ default 0x0 if ARCH_MPC8308
+ default 0x0 if OR2_EAD_NONE
+ default 0x1 if OR2_EAD_EXTRA
diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3
new file mode 100644
index 0000000..963831b
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3
@@ -0,0 +1,733 @@
+menuconfig ELBC_BR3_OR3
+ bool "ELBC BR3/OR3"
+
+if ELBC_BR3_OR3
+
+config BR3_OR3_NAME
+ string "Identifier"
+
+config BR3_OR3_BASE
+ hex "Port base"
+
+choice
+ prompt "Port size"
+
+config BR3_PORTSIZE_8BIT
+ bool "8-bit"
+
+config BR3_PORTSIZE_16BIT
+ depends on !BR3_MACHINE_FCM
+ bool "16-bit"
+
+
+config BR3_PORTSIZE_32BIT
+ depends on !BR3_MACHINE_FCM
+ depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+ bool "32-bit"
+
+endchoice
+
+if BR3_MACHINE_FCM
+
+choice
+ prompt "Data Error Checking"
+
+config BR3_ERRORCHECKING_DISABLED
+ bool "Disabled"
+
+config BR3_ERRORCHECKING_ECC_CHECKING
+ bool "ECC checking / No ECC generation"
+
+config BR3_ERRORCHECKING_BOTH
+ bool "ECC checking and generation"
+
+endchoice
+
+endif
+
+config BR3_WRITE_PROTECT
+ bool "Write-protect"
+
+config BR3_MACHINE_UPM
+ bool
+
+choice
+ prompt "Machine select"
+
+config BR3_MACHINE_GPCM
+ bool "GPCM"
+
+config BR3_MACHINE_FCM
+ depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ bool "FCM"
+
+config BR3_MACHINE_SDRAM
+ depends on ARCH_MPC8349 || ARCH_MPC8360
+ bool "SDRAM"
+
+config BR3_MACHINE_UPMA
+ select BR3_MACHINE_UPM
+ bool "UPM (A)"
+
+config BR3_MACHINE_UPMB
+ select BR3_MACHINE_UPM
+ bool "UPM (B)"
+
+config BR3_MACHINE_UPMC
+ select BR3_MACHINE_UPM
+ bool "UPM (C)"
+
+endchoice
+
+if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
+
+choice
+ prompt "Atomic operations"
+
+config BR3_ATOMIC_NONE
+ bool "No atomic operations"
+
+config BR3_ATOMIC_RAWA
+ bool "Read-after-write-atomic"
+
+config BR3_ATOMIC_WARA
+ bool "Write-after-read-atomic"
+
+endchoice
+
+endif
+
+if BR3_MACHINE_GPCM || BR3_MACHINE_FCM || BR3_MACHINE_UPM || BR3_MACHINE_SDRAM
+
+choice
+ prompt "Address mask"
+
+config OR3_AM_32_KBYTES
+ depends on !BR3_MACHINE_SDRAM
+ bool "32 kb"
+
+config OR3_AM_64_KBYTES
+ bool "64 kb"
+
+config OR3_AM_128_KBYTES
+ bool "128 kb"
+
+config OR3_AM_256_KBYTES
+ bool "256 kb"
+
+config OR3_AM_512_KBYTES
+ bool "512 kb"
+
+config OR3_AM_1_MBYTES
+ bool "1 mb"
+
+config OR3_AM_2_MBYTES
+ bool "2 mb"
+
+config OR3_AM_4_MBYTES
+ bool "4 mb"
+
+config OR3_AM_8_MBYTES
+ bool "8 mb"
+
+config OR3_AM_16_MBYTES
+ bool "16 mb"
+
+config OR3_AM_32_MBYTES
+ bool "32 mb"
+
+config OR3_AM_64_MBYTES
+ bool "64 mb"
+
+# XXX: Some boards define 128MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR3_AM_128_MBYTES
+ bool "128 mb"
+
+# XXX: Some boards define 256MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR3_AM_256_MBYTES
+ bool "256 mb"
+
+config OR3_AM_512_MBYTES
+ depends on BR3_MACHINE_FCM
+ bool "512 mb"
+
+# XXX: Some boards define 1GB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR3_AM_1_GBYTES
+ bool "1 gb"
+
+config OR3_AM_2_GBYTES
+ depends on BR3_MACHINE_FCM
+ bool "2 gb"
+
+config OR3_AM_4_GBYTES
+ depends on BR3_MACHINE_FCM
+ bool "4 gb"
+
+endchoice
+
+config OR3_XAM_SET
+ bool "Set unused bytes after address mask"
+choice
+ prompt "Buffer control disable"
+
+config OR3_BCTLD_ASSERTED
+ bool "Asserted"
+
+config OR3_BCTLD_NOT_ASSERTED
+ bool "Not asserted"
+
+endchoice
+
+endif
+
+if BR3_MACHINE_GPCM || BR3_MACHINE_FCM
+
+choice
+ prompt "Cycle length in bus clocks"
+
+config OR3_SCY_0
+ bool "No wait states"
+
+config OR3_SCY_1
+ bool "1 wait state"
+
+config OR3_SCY_2
+ bool "2 wait states"
+
+config OR3_SCY_3
+ bool "3 wait states"
+
+config OR3_SCY_4
+ bool "4 wait states"
+
+config OR3_SCY_5
+ bool "5 wait states"
+
+config OR3_SCY_6
+ bool "6 wait states"
+
+config OR3_SCY_7
+ bool "7 wait states"
+
+config OR3_SCY_8
+ depends on BR3_MACHINE_GPCM
+ bool "8 wait states"
+
+config OR3_SCY_9
+ depends on BR3_MACHINE_GPCM
+ bool "9 wait states"
+
+config OR3_SCY_10
+ depends on BR3_MACHINE_GPCM
+ bool "10 wait states"
+
+config OR3_SCY_11
+ depends on BR3_MACHINE_GPCM
+ bool "11 wait states"
+
+config OR3_SCY_12
+ depends on BR3_MACHINE_GPCM
+ bool "12 wait states"
+
+config OR3_SCY_13
+ depends on BR3_MACHINE_GPCM
+ bool "13 wait states"
+
+config OR3_SCY_14
+ depends on BR3_MACHINE_GPCM
+ bool "14 wait states"
+
+config OR3_SCY_15
+ depends on BR3_MACHINE_GPCM
+ bool "15 wait states"
+
+endchoice
+
+endif # BR3_MACHINE_GPCM || BR3_MACHINE_FCM
+
+if BR3_MACHINE_GPCM
+
+choice
+ prompt "Chip select negotiation time"
+
+config OR3_CSNT_NORMAL
+ bool "Normal"
+
+config OR3_CSNT_EARLIER
+ bool "Earlier"
+
+endchoice
+
+choice
+ prompt "Address to chip-select setup"
+
+config OR3_ACS_SAME_TIME
+ bool "At the same time"
+
+config OR3_ACS_HALF_CYCLE_EARLIER
+ bool "Half of a bus clock cycle earlier"
+
+config OR3_ACS_QUARTER_CYCLE_EARLIER
+ bool "Half/Quarter of a bus clock cycle earlier"
+
+endchoice
+
+choice
+ prompt "Extra address to check-select setup"
+
+config OR3_XACS_NORMAL
+ bool "Normal"
+
+config OR3_XACS_EXTENDED
+ bool "Extended"
+
+endchoice
+
+choice
+ prompt "External address termination"
+
+config OR3_SETA_INTERNAL
+ bool "Access is terminated internally"
+
+config OR3_SETA_EXTERNAL
+ bool "Access is terminated externally"
+
+endchoice
+
+endif # BR3_MACHINE_GPCM
+
+if BR3_MACHINE_FCM
+
+choice
+ prompt "NAND Flash EEPROM page size"
+
+config OR3_PGS_SMALL
+ bool "Small page device"
+
+config OR3_PGS_LARGE
+ bool "Large page device"
+
+endchoice
+
+choice
+ prompt "Chip select to command time"
+
+config OR3_CSCT_1_CYCLE
+ depends on OR3_TRLX_NORMAL
+ bool "1 cycle"
+
+config OR3_CSCT_2_CYCLE
+ depends on OR3_TRLX_RELAXED
+ bool "2 cycles"
+
+config OR3_CSCT_4_CYCLE
+ depends on OR3_TRLX_NORMAL
+ bool "4 cycles"
+
+config OR3_CSCT_8_CYCLE
+ depends on OR3_TRLX_RELAXED
+ bool "8 cycles"
+
+endchoice
+
+choice
+ prompt "Command setup time"
+
+config OR3_CST_COINCIDENT
+ depends on OR3_TRLX_NORMAL
+ bool "Coincident with any command"
+
+config OR3_CST_QUARTER_CLOCK
+ depends on OR3_TRLX_NORMAL
+ bool "0.25 clocks after"
+
+config OR3_CST_HALF_CLOCK
+ depends on OR3_TRLX_RELAXED
+ bool "0.5 clocks after"
+
+config OR3_CST_ONE_CLOCK
+ depends on OR3_TRLX_RELAXED
+ bool "1 clock after"
+
+endchoice
+
+choice
+ prompt "Command hold time"
+
+config OR3_CHT_HALF_CLOCK
+ depends on OR3_TRLX_NORMAL
+ bool "0.5 clocks before"
+
+config OR3_CHT_ONE_CLOCK
+ depends on OR3_TRLX_NORMAL
+ bool "1 clock before"
+
+config OR3_CHT_ONE_HALF_CLOCK
+ depends on OR3_TRLX_RELAXED
+ bool "1.5 clocks before"
+
+config OR3_CHT_TWO_CLOCK
+ depends on OR3_TRLX_RELAXED
+ bool "2 clocks before"
+
+endchoice
+
+choice
+ prompt "Reset setup time"
+
+config OR3_RST_THREE_QUARTER_CLOCK
+ depends on OR3_TRLX_NORMAL
+ bool "0.75 clocks prior"
+
+config OR3_RST_ONE_HALF_CLOCK
+ depends on OR3_TRLX_RELAXED
+ bool "0.5 clocks prior"
+
+config OR3_RST_ONE_CLOCK
+ bool "1 clock prior"
+
+endchoice
+
+endif # BR3_MACHINE_FCM
+
+if BR3_MACHINE_UPM
+
+choice
+ prompt "Burst inhibit"
+
+config OR3_BI_BURSTSUPPORT
+ bool "Support burst access"
+
+config OR3_BI_BURSTINHIBIT
+ bool "Inhibit burst access"
+
+endchoice
+
+endif # BR3_MACHINE_UPM
+
+if BR3_MACHINE_SDRAM
+
+choice
+ prompt "Number of column address lines"
+
+config OR3_COLS_7
+ bool "7"
+
+config OR3_COLS_8
+ bool "8"
+
+config OR3_COLS_9
+ bool "9"
+
+config OR3_COLS_10
+ bool "10"
+
+config OR3_COLS_11
+ bool "11"
+
+config OR3_COLS_12
+ bool "12"
+
+config OR3_COLS_13
+ bool "13"
+
+config OR3_COLS_14
+ bool "14"
+
+endchoice
+
+choice
+ prompt "Number of rows address lines"
+
+config OR3_ROWS_9
+ bool "9"
+
+config OR3_ROWS_10
+ bool "10"
+
+config OR3_ROWS_11
+ bool "11"
+
+config OR3_ROWS_12
+ bool "12"
+
+config OR3_ROWS_13
+ bool "13"
+
+config OR3_ROWS_14
+ bool "14"
+
+config OR3_ROWS_15
+ bool "15"
+
+endchoice
+
+choice
+ prompt "Page mode select"
+
+config OR3_PMSEL_BTB
+ bool "Back-to-back"
+
+config OR3_PMSEL_KEPT_OPEN
+ bool "Page kept open until page miss or refresh"
+
+endchoice
+
+endif # BR3_MACHINE_SDRAM
+
+choice
+ prompt "Relaxed timing"
+
+config OR3_TRLX_NORMAL
+ bool "Normal"
+
+config OR3_TRLX_RELAXED
+ bool "Relaxed"
+
+endchoice
+
+choice
+ prompt "Extended hold time"
+
+config OR3_EHTR_NORMAL
+ depends on OR3_TRLX_NORMAL
+ bool "Normal"
+
+config OR3_EHTR_1_CYCLE
+ depends on OR3_TRLX_NORMAL
+ bool "1 idle clock cycle inserted"
+
+config OR3_EHTR_4_CYCLE
+ depends on OR3_TRLX_RELAXED
+ bool "4 idle clock cycles inserted"
+
+config OR3_EHTR_8_CYCLE
+ depends on OR3_TRLX_RELAXED
+ bool "8 idle clock cycles inserted"
+
+endchoice
+
+if !ARCH_MPC8308
+
+choice
+ prompt "External address latch delay"
+
+config OR3_EAD_NONE
+ bool "None"
+
+config OR3_EAD_EXTRA
+ bool "Extra"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+endif # ELBC_BR3_OR3
+
+config BR3_PORTSIZE
+ hex
+ default 0x800 if BR3_PORTSIZE_8BIT
+ default 0x1000 if BR3_PORTSIZE_16BIT
+ default 0x1800 if BR3_PORTSIZE_32BIT
+
+config BR3_ERRORCHECKING
+ hex
+ default 0x0 if !BR3_MACHINE_FCM
+ default 0x0 if BR3_ERRORCHECKING_DISABLED
+ default 0x200 if BR3_ERRORCHECKING_ECC_CHECKING
+ default 0x400 if BR3_ERRORCHECKING_BOTH
+
+config BR3_WRITE_PROTECT_BIT
+ hex
+ default 0x0 if !BR3_WRITE_PROTECT
+ default 0x100 if BR3_WRITE_PROTECT
+
+config BR3_MACHINE
+ hex
+ default 0x0 if BR3_MACHINE_GPCM
+ default 0x20 if BR3_MACHINE_FCM
+ default 0x60 if BR3_MACHINE_SDRAM
+ default 0x80 if BR3_MACHINE_UPMA
+ default 0xa0 if BR3_MACHINE_UPMB
+ default 0xc0 if BR3_MACHINE_UPMC
+
+config BR3_ATOMIC
+ hex
+ default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
+ default 0x0 if BR3_ATOMIC_NONE
+ default 0x4 if BR3_ATOMIC_RAWA
+ default 0x8 if BR3_ATOMIC_WARA
+
+config BR3_VALID_BIT
+ hex
+ default 0x0 if !ELBC_BR3_OR3
+ default 0x1 if ELBC_BR3_OR3
+
+config OR3_AM
+ hex
+ default 0xffff8000 if OR3_AM_32_KBYTES && !BR3_MACHINE_SDRAM
+ default 0xffff0000 if OR3_AM_64_KBYTES
+ default 0xfffe0000 if OR3_AM_128_KBYTES
+ default 0xfffc0000 if OR3_AM_256_KBYTES
+ default 0xfff80000 if OR3_AM_512_KBYTES
+ default 0xfff00000 if OR3_AM_1_MBYTES
+ default 0xffe00000 if OR3_AM_2_MBYTES
+ default 0xffc00000 if OR3_AM_4_MBYTES
+ default 0xff800000 if OR3_AM_8_MBYTES
+ default 0xff000000 if OR3_AM_16_MBYTES
+ default 0xfe000000 if OR3_AM_32_MBYTES
+ default 0xfc000000 if OR3_AM_64_MBYTES
+ default 0xf8000000 if OR3_AM_128_MBYTES
+ default 0xf0000000 if OR3_AM_256_MBYTES
+ default 0xe0000000 if OR3_AM_512_MBYTES
+ default 0xc0000000 if OR3_AM_1_GBYTES
+ default 0x80000000 if OR3_AM_2_GBYTES
+ default 0x00000000 if OR3_AM_4_GBYTES
+
+config OR3_XAM
+ hex
+ default 0x0 if !OR3_XAM_SET
+ default 0x6000 if OR3_XAM_SET
+
+config OR3_BCTLD
+ hex
+ default 0x0 if OR3_BCTLD_ASSERTED
+ default 0x1000 if OR3_BCTLD_NOT_ASSERTED
+
+config OR3_BI
+ hex
+ default 0x0 if !BR3_MACHINE_UPM
+ default 0x0 if OR3_BI_BURSTSUPPORT
+ default 0x100 if OR3_BI_BURSTINHIBIT
+
+config OR3_COLS
+ hex
+ default 0x0 if !BR3_MACHINE_SDRAM
+ default 0x0 if OR3_COLS_7
+ default 0x400 if OR3_COLS_8
+ default 0x800 if OR3_COLS_9
+ default 0xc00 if OR3_COLS_10
+ default 0x1000 if OR3_COLS_11
+ default 0x1400 if OR3_COLS_12
+ default 0x1800 if OR3_COLS_13
+ default 0x1c00 if OR3_COLS_14
+
+config OR3_ROWS
+ hex
+ default 0x0 if !BR3_MACHINE_SDRAM
+ default 0x0 if OR3_ROWS_9
+ default 0x40 if OR3_ROWS_10
+ default 0x80 if OR3_ROWS_11
+ default 0xc0 if OR3_ROWS_12
+ default 0x100 if OR3_ROWS_13
+ default 0x140 if OR3_ROWS_14
+ default 0x180 if OR3_ROWS_15
+
+config OR3_PMSEL
+ hex
+ default 0x0 if !BR3_MACHINE_SDRAM
+ default 0x0 if OR3_PMSEL_BTB
+ default 0x20 if OR3_PMSEL_KEPT_OPEN
+
+config OR3_SCY
+ hex
+ default 0x0 if !BR3_MACHINE_GPCM && !BR3_MACHINE_FCM
+ default 0x0 if OR3_SCY_0
+ default 0x10 if OR3_SCY_1
+ default 0x20 if OR3_SCY_2
+ default 0x30 if OR3_SCY_3
+ default 0x40 if OR3_SCY_4
+ default 0x50 if OR3_SCY_5
+ default 0x60 if OR3_SCY_6
+ default 0x70 if OR3_SCY_7
+ default 0x80 if OR3_SCY_8
+ default 0x90 if OR3_SCY_9
+ default 0xa0 if OR3_SCY_10
+ default 0xb0 if OR3_SCY_11
+ default 0xc0 if OR3_SCY_12
+ default 0xd0 if OR3_SCY_13
+ default 0xe0 if OR3_SCY_14
+ default 0xf0 if OR3_SCY_15
+
+config OR3_PGS
+ hex
+ default 0x0 if !BR3_MACHINE_FCM
+ default 0x0 if OR3_PGS_SMALL
+ default 0x400 if OR3_PGS_LARGE
+
+config OR3_CSCT
+ hex
+ default 0x0 if !BR3_MACHINE_FCM
+ default 0x0 if OR3_CSCT_1_CYCLE
+ default 0x0 if OR3_CSCT_2_CYCLE
+ default 0x200 if OR3_CSCT_4_CYCLE
+ default 0x200 if OR3_CSCT_8_CYCLE
+
+config OR3_CST
+ hex
+ default 0x0 if !BR3_MACHINE_FCM
+ default 0x0 if OR3_CST_COINCIDENT
+ default 0x100 if OR3_CST_QUARTER_CLOCK
+ default 0x0 if OR3_CST_HALF_CLOCK
+ default 0x100 if OR3_CST_ONE_CLOCK
+
+config OR3_CHT
+ hex
+ default 0x0 if !BR3_MACHINE_FCM
+ default 0x0 if OR3_CHT_HALF_CLOCK
+ default 0x80 if OR3_CHT_ONE_CLOCK
+ default 0x0 if OR3_CHT_ONE_HALF_CLOCK
+ default 0x80 if OR3_CHT_TWO_CLOCK
+
+config OR3_RST
+ hex
+ default 0x0 if !BR3_MACHINE_FCM
+ default 0x0 if OR3_RST_THREE_QUARTER_CLOCK
+ default 0x8 if OR3_RST_ONE_CLOCK
+ default 0x0 if OR3_RST_ONE_HALF_CLOCK
+
+config OR3_CSNT
+ hex
+ default 0x0 if !BR3_MACHINE_GPCM
+ default 0x0 if OR3_CSNT_NORMAL
+ default 0x800 if OR3_CSNT_EARLIER
+
+config OR3_ACS
+ hex
+ default 0x0 if !BR3_MACHINE_GPCM
+ default 0x0 if OR3_ACS_SAME_TIME
+ default 0x400 if OR3_ACS_QUARTER_CYCLE_EARLIER
+ default 0x600 if OR3_ACS_HALF_CYCLE_EARLIER
+
+config OR3_XACS
+ hex
+ default 0x0 if !BR3_MACHINE_GPCM
+ default 0x0 if OR3_XACS_NORMAL
+ default 0x100 if OR3_XACS_EXTENDED
+
+config OR3_SETA
+ hex
+ default 0x0 if !BR3_MACHINE_GPCM
+ default 0x0 if OR3_SETA_INTERNAL
+ default 0x8 if OR3_SETA_EXTERNAL
+
+config OR3_TRLX
+ hex
+ default 0x0 if OR3_TRLX_NORMAL
+ default 0x4 if OR3_TRLX_RELAXED
+
+config OR3_EHTR
+ hex
+ default 0x0 if OR3_EHTR_NORMAL
+ default 0x2 if OR3_EHTR_1_CYCLE
+ default 0x0 if OR3_EHTR_4_CYCLE
+ default 0x2 if OR3_EHTR_8_CYCLE
+
+config OR3_EAD
+ hex
+ default 0x0 if ARCH_MPC8308
+ default 0x0 if OR3_EAD_NONE
+ default 0x1 if OR3_EAD_EXTRA
diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4
new file mode 100644
index 0000000..0063dab
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4
@@ -0,0 +1,733 @@
+menuconfig ELBC_BR4_OR4
+ bool "ELBC BR4/OR4"
+
+if ELBC_BR4_OR4
+
+config BR4_OR4_NAME
+ string "Identifier"
+
+config BR4_OR4_BASE
+ hex "Port base"
+
+choice
+ prompt "Port size"
+
+config BR4_PORTSIZE_8BIT
+ bool "8-bit"
+
+config BR4_PORTSIZE_16BIT
+ depends on !BR4_MACHINE_FCM
+ bool "16-bit"
+
+
+config BR4_PORTSIZE_32BIT
+ depends on !BR4_MACHINE_FCM
+ depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+ bool "32-bit"
+
+endchoice
+
+if BR4_MACHINE_FCM
+
+choice
+ prompt "Data Error Checking"
+
+config BR4_ERRORCHECKING_DISABLED
+ bool "Disabled"
+
+config BR4_ERRORCHECKING_ECC_CHECKING
+ bool "ECC checking / No ECC generation"
+
+config BR4_ERRORCHECKING_BOTH
+ bool "ECC checking and generation"
+
+endchoice
+
+endif
+
+config BR4_WRITE_PROTECT
+ bool "Write-protect"
+
+config BR4_MACHINE_UPM
+ bool
+
+choice
+ prompt "Machine select"
+
+config BR4_MACHINE_GPCM
+ bool "GPCM"
+
+config BR4_MACHINE_FCM
+ depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ bool "FCM"
+
+config BR4_MACHINE_SDRAM
+ depends on ARCH_MPC8349 || ARCH_MPC8360
+ bool "SDRAM"
+
+config BR4_MACHINE_UPMA
+ select BR4_MACHINE_UPM
+ bool "UPM (A)"
+
+config BR4_MACHINE_UPMB
+ select BR4_MACHINE_UPM
+ bool "UPM (B)"
+
+config BR4_MACHINE_UPMC
+ select BR4_MACHINE_UPM
+ bool "UPM (C)"
+
+endchoice
+
+if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
+
+choice
+ prompt "Atomic operations"
+
+config BR4_ATOMIC_NONE
+ bool "No atomic operations"
+
+config BR4_ATOMIC_RAWA
+ bool "Read-after-write-atomic"
+
+config BR4_ATOMIC_WARA
+ bool "Write-after-read-atomic"
+
+endchoice
+
+endif
+
+if BR4_MACHINE_GPCM || BR4_MACHINE_FCM || BR4_MACHINE_UPM || BR4_MACHINE_SDRAM
+
+choice
+ prompt "Address mask"
+
+config OR4_AM_32_KBYTES
+ depends on !BR4_MACHINE_SDRAM
+ bool "32 kb"
+
+config OR4_AM_64_KBYTES
+ bool "64 kb"
+
+config OR4_AM_128_KBYTES
+ bool "128 kb"
+
+config OR4_AM_256_KBYTES
+ bool "256 kb"
+
+config OR4_AM_512_KBYTES
+ bool "512 kb"
+
+config OR4_AM_1_MBYTES
+ bool "1 mb"
+
+config OR4_AM_2_MBYTES
+ bool "2 mb"
+
+config OR4_AM_4_MBYTES
+ bool "4 mb"
+
+config OR4_AM_8_MBYTES
+ bool "8 mb"
+
+config OR4_AM_16_MBYTES
+ bool "16 mb"
+
+config OR4_AM_32_MBYTES
+ bool "32 mb"
+
+config OR4_AM_64_MBYTES
+ bool "64 mb"
+
+# XXX: Some boards define 128MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR4_AM_128_MBYTES
+ bool "128 mb"
+
+# XXX: Some boards define 256MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR4_AM_256_MBYTES
+ bool "256 mb"
+
+config OR4_AM_512_MBYTES
+ depends on BR4_MACHINE_FCM
+ bool "512 mb"
+
+# XXX: Some boards define 1GB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR4_AM_1_GBYTES
+ bool "1 gb"
+
+config OR4_AM_2_GBYTES
+ depends on BR4_MACHINE_FCM
+ bool "2 gb"
+
+config OR4_AM_4_GBYTES
+ depends on BR4_MACHINE_FCM
+ bool "4 gb"
+
+endchoice
+
+config OR4_XAM_SET
+ bool "Set unused bytes after address mask"
+choice
+ prompt "Buffer control disable"
+
+config OR4_BCTLD_ASSERTED
+ bool "Asserted"
+
+config OR4_BCTLD_NOT_ASSERTED
+ bool "Not asserted"
+
+endchoice
+
+endif
+
+if BR4_MACHINE_GPCM || BR4_MACHINE_FCM
+
+choice
+ prompt "Cycle length in bus clocks"
+
+config OR4_SCY_0
+ bool "No wait states"
+
+config OR4_SCY_1
+ bool "1 wait state"
+
+config OR4_SCY_2
+ bool "2 wait states"
+
+config OR4_SCY_3
+ bool "3 wait states"
+
+config OR4_SCY_4
+ bool "4 wait states"
+
+config OR4_SCY_5
+ bool "5 wait states"
+
+config OR4_SCY_6
+ bool "6 wait states"
+
+config OR4_SCY_7
+ bool "7 wait states"
+
+config OR4_SCY_8
+ depends on BR4_MACHINE_GPCM
+ bool "8 wait states"
+
+config OR4_SCY_9
+ depends on BR4_MACHINE_GPCM
+ bool "9 wait states"
+
+config OR4_SCY_10
+ depends on BR4_MACHINE_GPCM
+ bool "10 wait states"
+
+config OR4_SCY_11
+ depends on BR4_MACHINE_GPCM
+ bool "11 wait states"
+
+config OR4_SCY_12
+ depends on BR4_MACHINE_GPCM
+ bool "12 wait states"
+
+config OR4_SCY_13
+ depends on BR4_MACHINE_GPCM
+ bool "13 wait states"
+
+config OR4_SCY_14
+ depends on BR4_MACHINE_GPCM
+ bool "14 wait states"
+
+config OR4_SCY_15
+ depends on BR4_MACHINE_GPCM
+ bool "15 wait states"
+
+endchoice
+
+endif # BR4_MACHINE_GPCM || BR4_MACHINE_FCM
+
+if BR4_MACHINE_GPCM
+
+choice
+ prompt "Chip select negotiation time"
+
+config OR4_CSNT_NORMAL
+ bool "Normal"
+
+config OR4_CSNT_EARLIER
+ bool "Earlier"
+
+endchoice
+
+choice
+ prompt "Address to chip-select setup"
+
+config OR4_ACS_SAME_TIME
+ bool "At the same time"
+
+config OR4_ACS_HALF_CYCLE_EARLIER
+ bool "Half of a bus clock cycle earlier"
+
+config OR4_ACS_QUARTER_CYCLE_EARLIER
+ bool "Half/Quarter of a bus clock cycle earlier"
+
+endchoice
+
+choice
+ prompt "Extra address to check-select setup"
+
+config OR4_XACS_NORMAL
+ bool "Normal"
+
+config OR4_XACS_EXTENDED
+ bool "Extended"
+
+endchoice
+
+choice
+ prompt "External address termination"
+
+config OR4_SETA_INTERNAL
+ bool "Access is terminated internally"
+
+config OR4_SETA_EXTERNAL
+ bool "Access is terminated externally"
+
+endchoice
+
+endif # BR4_MACHINE_GPCM
+
+if BR4_MACHINE_FCM
+
+choice
+ prompt "NAND Flash EEPROM page size"
+
+config OR4_PGS_SMALL
+ bool "Small page device"
+
+config OR4_PGS_LARGE
+ bool "Large page device"
+
+endchoice
+
+choice
+ prompt "Chip select to command time"
+
+config OR4_CSCT_1_CYCLE
+ depends on OR4_TRLX_NORMAL
+ bool "1 cycle"
+
+config OR4_CSCT_2_CYCLE
+ depends on OR4_TRLX_RELAXED
+ bool "2 cycles"
+
+config OR4_CSCT_4_CYCLE
+ depends on OR4_TRLX_NORMAL
+ bool "4 cycles"
+
+config OR4_CSCT_8_CYCLE
+ depends on OR4_TRLX_RELAXED
+ bool "8 cycles"
+
+endchoice
+
+choice
+ prompt "Command setup time"
+
+config OR4_CST_COINCIDENT
+ depends on OR4_TRLX_NORMAL
+ bool "Coincident with any command"
+
+config OR4_CST_QUARTER_CLOCK
+ depends on OR4_TRLX_NORMAL
+ bool "0.25 clocks after"
+
+config OR4_CST_HALF_CLOCK
+ depends on OR4_TRLX_RELAXED
+ bool "0.5 clocks after"
+
+config OR4_CST_ONE_CLOCK
+ depends on OR4_TRLX_RELAXED
+ bool "1 clock after"
+
+endchoice
+
+choice
+ prompt "Command hold time"
+
+config OR4_CHT_HALF_CLOCK
+ depends on OR4_TRLX_NORMAL
+ bool "0.5 clocks before"
+
+config OR4_CHT_ONE_CLOCK
+ depends on OR4_TRLX_NORMAL
+ bool "1 clock before"
+
+config OR4_CHT_ONE_HALF_CLOCK
+ depends on OR4_TRLX_RELAXED
+ bool "1.5 clocks before"
+
+config OR4_CHT_TWO_CLOCK
+ depends on OR4_TRLX_RELAXED
+ bool "2 clocks before"
+
+endchoice
+
+choice
+ prompt "Reset setup time"
+
+config OR4_RST_THREE_QUARTER_CLOCK
+ depends on OR4_TRLX_NORMAL
+ bool "0.75 clocks prior"
+
+config OR4_RST_ONE_HALF_CLOCK
+ depends on OR4_TRLX_RELAXED
+ bool "0.5 clocks prior"
+
+config OR4_RST_ONE_CLOCK
+ bool "1 clock prior"
+
+endchoice
+
+endif # BR4_MACHINE_FCM
+
+if BR4_MACHINE_UPM
+
+choice
+ prompt "Burst inhibit"
+
+config OR4_BI_BURSTSUPPORT
+ bool "Support burst access"
+
+config OR4_BI_BURSTINHIBIT
+ bool "Inhibit burst access"
+
+endchoice
+
+endif # BR4_MACHINE_UPM
+
+if BR4_MACHINE_SDRAM
+
+choice
+ prompt "Number of column address lines"
+
+config OR4_COLS_7
+ bool "7"
+
+config OR4_COLS_8
+ bool "8"
+
+config OR4_COLS_9
+ bool "9"
+
+config OR4_COLS_10
+ bool "10"
+
+config OR4_COLS_11
+ bool "11"
+
+config OR4_COLS_12
+ bool "12"
+
+config OR4_COLS_13
+ bool "13"
+
+config OR4_COLS_14
+ bool "14"
+
+endchoice
+
+choice
+ prompt "Number of rows address lines"
+
+config OR4_ROWS_9
+ bool "9"
+
+config OR4_ROWS_10
+ bool "10"
+
+config OR4_ROWS_11
+ bool "11"
+
+config OR4_ROWS_12
+ bool "12"
+
+config OR4_ROWS_13
+ bool "13"
+
+config OR4_ROWS_14
+ bool "14"
+
+config OR4_ROWS_15
+ bool "15"
+
+endchoice
+
+choice
+ prompt "Page mode select"
+
+config OR4_PMSEL_BTB
+ bool "Back-to-back"
+
+config OR4_PMSEL_KEPT_OPEN
+ bool "Page kept open until page miss or refresh"
+
+endchoice
+
+endif # BR4_MACHINE_SDRAM
+
+choice
+ prompt "Relaxed timing"
+
+config OR4_TRLX_NORMAL
+ bool "Normal"
+
+config OR4_TRLX_RELAXED
+ bool "Relaxed"
+
+endchoice
+
+choice
+ prompt "Extended hold time"
+
+config OR4_EHTR_NORMAL
+ depends on OR4_TRLX_NORMAL
+ bool "Normal"
+
+config OR4_EHTR_1_CYCLE
+ depends on OR4_TRLX_NORMAL
+ bool "1 idle clock cycle inserted"
+
+config OR4_EHTR_4_CYCLE
+ depends on OR4_TRLX_RELAXED
+ bool "4 idle clock cycles inserted"
+
+config OR4_EHTR_8_CYCLE
+ depends on OR4_TRLX_RELAXED
+ bool "8 idle clock cycles inserted"
+
+endchoice
+
+if !ARCH_MPC8308
+
+choice
+ prompt "External address latch delay"
+
+config OR4_EAD_NONE
+ bool "None"
+
+config OR4_EAD_EXTRA
+ bool "Extra"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+endif # ELBC_BR4_OR4
+
+config BR4_PORTSIZE
+ hex
+ default 0x800 if BR4_PORTSIZE_8BIT
+ default 0x1000 if BR4_PORTSIZE_16BIT
+ default 0x1800 if BR4_PORTSIZE_32BIT
+
+config BR4_ERRORCHECKING
+ hex
+ default 0x0 if !BR4_MACHINE_FCM
+ default 0x0 if BR4_ERRORCHECKING_DISABLED
+ default 0x200 if BR4_ERRORCHECKING_ECC_CHECKING
+ default 0x400 if BR4_ERRORCHECKING_BOTH
+
+config BR4_WRITE_PROTECT_BIT
+ hex
+ default 0x0 if !BR4_WRITE_PROTECT
+ default 0x100 if BR4_WRITE_PROTECT
+
+config BR4_MACHINE
+ hex
+ default 0x0 if BR4_MACHINE_GPCM
+ default 0x20 if BR4_MACHINE_FCM
+ default 0x60 if BR4_MACHINE_SDRAM
+ default 0x80 if BR4_MACHINE_UPMA
+ default 0xa0 if BR4_MACHINE_UPMB
+ default 0xc0 if BR4_MACHINE_UPMC
+
+config BR4_ATOMIC
+ hex
+ default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
+ default 0x0 if BR4_ATOMIC_NONE
+ default 0x4 if BR4_ATOMIC_RAWA
+ default 0x8 if BR4_ATOMIC_WARA
+
+config BR4_VALID_BIT
+ hex
+ default 0x0 if !ELBC_BR4_OR4
+ default 0x1 if ELBC_BR4_OR4
+
+config OR4_AM
+ hex
+ default 0xffff8000 if OR4_AM_32_KBYTES && !BR4_MACHINE_SDRAM
+ default 0xffff0000 if OR4_AM_64_KBYTES
+ default 0xfffe0000 if OR4_AM_128_KBYTES
+ default 0xfffc0000 if OR4_AM_256_KBYTES
+ default 0xfff80000 if OR4_AM_512_KBYTES
+ default 0xfff00000 if OR4_AM_1_MBYTES
+ default 0xffe00000 if OR4_AM_2_MBYTES
+ default 0xffc00000 if OR4_AM_4_MBYTES
+ default 0xff800000 if OR4_AM_8_MBYTES
+ default 0xff000000 if OR4_AM_16_MBYTES
+ default 0xfe000000 if OR4_AM_32_MBYTES
+ default 0xfc000000 if OR4_AM_64_MBYTES
+ default 0xf8000000 if OR4_AM_128_MBYTES
+ default 0xf0000000 if OR4_AM_256_MBYTES
+ default 0xe0000000 if OR4_AM_512_MBYTES
+ default 0xc0000000 if OR4_AM_1_GBYTES
+ default 0x80000000 if OR4_AM_2_GBYTES
+ default 0x00000000 if OR4_AM_4_GBYTES
+
+config OR4_XAM
+ hex
+ default 0x0 if !OR4_XAM_SET
+ default 0x6000 if OR4_XAM_SET
+
+config OR4_BCTLD
+ hex
+ default 0x0 if OR4_BCTLD_ASSERTED
+ default 0x1000 if OR4_BCTLD_NOT_ASSERTED
+
+config OR4_BI
+ hex
+ default 0x0 if !BR4_MACHINE_UPM
+ default 0x0 if OR4_BI_BURSTSUPPORT
+ default 0x100 if OR4_BI_BURSTINHIBIT
+
+config OR4_COLS
+ hex
+ default 0x0 if !BR4_MACHINE_SDRAM
+ default 0x0 if OR4_COLS_7
+ default 0x400 if OR4_COLS_8
+ default 0x800 if OR4_COLS_9
+ default 0xc00 if OR4_COLS_10
+ default 0x1000 if OR4_COLS_11
+ default 0x1400 if OR4_COLS_12
+ default 0x1800 if OR4_COLS_13
+ default 0x1c00 if OR4_COLS_14
+
+config OR4_ROWS
+ hex
+ default 0x0 if !BR4_MACHINE_SDRAM
+ default 0x0 if OR4_ROWS_9
+ default 0x40 if OR4_ROWS_10
+ default 0x80 if OR4_ROWS_11
+ default 0xc0 if OR4_ROWS_12
+ default 0x100 if OR4_ROWS_13
+ default 0x140 if OR4_ROWS_14
+ default 0x180 if OR4_ROWS_15
+
+config OR4_PMSEL
+ hex
+ default 0x0 if !BR4_MACHINE_SDRAM
+ default 0x0 if OR4_PMSEL_BTB
+ default 0x20 if OR4_PMSEL_KEPT_OPEN
+
+config OR4_SCY
+ hex
+ default 0x0 if !BR4_MACHINE_GPCM && !BR4_MACHINE_FCM
+ default 0x0 if OR4_SCY_0
+ default 0x10 if OR4_SCY_1
+ default 0x20 if OR4_SCY_2
+ default 0x30 if OR4_SCY_3
+ default 0x40 if OR4_SCY_4
+ default 0x50 if OR4_SCY_5
+ default 0x60 if OR4_SCY_6
+ default 0x70 if OR4_SCY_7
+ default 0x80 if OR4_SCY_8
+ default 0x90 if OR4_SCY_9
+ default 0xa0 if OR4_SCY_10
+ default 0xb0 if OR4_SCY_11
+ default 0xc0 if OR4_SCY_12
+ default 0xd0 if OR4_SCY_13
+ default 0xe0 if OR4_SCY_14
+ default 0xf0 if OR4_SCY_15
+
+config OR4_PGS
+ hex
+ default 0x0 if !BR4_MACHINE_FCM
+ default 0x0 if OR4_PGS_SMALL
+ default 0x400 if OR4_PGS_LARGE
+
+config OR4_CSCT
+ hex
+ default 0x0 if !BR4_MACHINE_FCM
+ default 0x0 if OR4_CSCT_1_CYCLE
+ default 0x0 if OR4_CSCT_2_CYCLE
+ default 0x200 if OR4_CSCT_4_CYCLE
+ default 0x200 if OR4_CSCT_8_CYCLE
+
+config OR4_CST
+ hex
+ default 0x0 if !BR4_MACHINE_FCM
+ default 0x0 if OR4_CST_COINCIDENT
+ default 0x100 if OR4_CST_QUARTER_CLOCK
+ default 0x0 if OR4_CST_HALF_CLOCK
+ default 0x100 if OR4_CST_ONE_CLOCK
+
+config OR4_CHT
+ hex
+ default 0x0 if !BR4_MACHINE_FCM
+ default 0x0 if OR4_CHT_HALF_CLOCK
+ default 0x80 if OR4_CHT_ONE_CLOCK
+ default 0x0 if OR4_CHT_ONE_HALF_CLOCK
+ default 0x80 if OR4_CHT_TWO_CLOCK
+
+config OR4_RST
+ hex
+ default 0x0 if !BR4_MACHINE_FCM
+ default 0x0 if OR4_RST_THREE_QUARTER_CLOCK
+ default 0x8 if OR4_RST_ONE_CLOCK
+ default 0x0 if OR4_RST_ONE_HALF_CLOCK
+
+config OR4_CSNT
+ hex
+ default 0x0 if !BR4_MACHINE_GPCM
+ default 0x0 if OR4_CSNT_NORMAL
+ default 0x800 if OR4_CSNT_EARLIER
+
+config OR4_ACS
+ hex
+ default 0x0 if !BR4_MACHINE_GPCM
+ default 0x0 if OR4_ACS_SAME_TIME
+ default 0x400 if OR4_ACS_QUARTER_CYCLE_EARLIER
+ default 0x600 if OR4_ACS_HALF_CYCLE_EARLIER
+
+config OR4_XACS
+ hex
+ default 0x0 if !BR4_MACHINE_GPCM
+ default 0x0 if OR4_XACS_NORMAL
+ default 0x100 if OR4_XACS_EXTENDED
+
+config OR4_SETA
+ hex
+ default 0x0 if !BR4_MACHINE_GPCM
+ default 0x0 if OR4_SETA_INTERNAL
+ default 0x8 if OR4_SETA_EXTERNAL
+
+config OR4_TRLX
+ hex
+ default 0x0 if OR4_TRLX_NORMAL
+ default 0x4 if OR4_TRLX_RELAXED
+
+config OR4_EHTR
+ hex
+ default 0x0 if OR4_EHTR_NORMAL
+ default 0x2 if OR4_EHTR_1_CYCLE
+ default 0x0 if OR4_EHTR_4_CYCLE
+ default 0x2 if OR4_EHTR_8_CYCLE
+
+config OR4_EAD
+ hex
+ default 0x0 if ARCH_MPC8308
+ default 0x0 if OR4_EAD_NONE
+ default 0x1 if OR4_EAD_EXTRA
diff --git a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
new file mode 100644
index 0000000..245fe7c
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
@@ -0,0 +1,186 @@
+#ifdef CONFIG_ELBC_BR0_OR0
+#define CONFIG_SYS_BR0_PRELIM (\
+ CONFIG_BR0_OR0_BASE |\
+ CONFIG_BR0_PORTSIZE |\
+ CONFIG_BR0_ERRORCHECKING |\
+ CONFIG_BR0_WRITE_PROTECT_BIT |\
+ CONFIG_BR0_MACHINE |\
+ CONFIG_BR0_ATOMIC |\
+ CONFIG_BR0_VALID_BIT \
+)
+#define CONFIG_SYS_OR0_PRELIM (\
+ CONFIG_OR0_AM |\
+ CONFIG_OR0_XAM |\
+ CONFIG_OR0_BCTLD |\
+ CONFIG_OR0_BI |\
+ CONFIG_OR0_COLS |\
+ CONFIG_OR0_ROWS |\
+ CONFIG_OR0_PMSEL |\
+ CONFIG_OR0_SCY |\
+ CONFIG_OR0_PGS |\
+ CONFIG_OR0_CSCT |\
+ CONFIG_OR0_CST |\
+ CONFIG_OR0_CHT |\
+ CONFIG_OR0_RST |\
+ CONFIG_OR0_CSNT |\
+ CONFIG_OR0_ACS |\
+ CONFIG_OR0_XACS |\
+ CONFIG_OR0_SETA |\
+ CONFIG_OR0_TRLX |\
+ CONFIG_OR0_EHTR |\
+ CONFIG_OR0_EAD \
+)
+#endif /* CONFIG_ELBC_BR0_OR0 */
+
+#ifdef CONFIG_ELBC_BR1_OR1
+#define CONFIG_SYS_BR1_PRELIM (\
+ CONFIG_BR1_OR1_BASE |\
+ CONFIG_BR1_PORTSIZE |\
+ CONFIG_BR1_ERRORCHECKING |\
+ CONFIG_BR1_WRITE_PROTECT_BIT |\
+ CONFIG_BR1_MACHINE |\
+ CONFIG_BR1_ATOMIC |\
+ CONFIG_BR1_VALID_BIT \
+)
+#define CONFIG_SYS_OR1_PRELIM (\
+ CONFIG_OR1_AM |\
+ CONFIG_OR1_XAM |\
+ CONFIG_OR1_BCTLD |\
+ CONFIG_OR1_BI |\
+ CONFIG_OR1_COLS |\
+ CONFIG_OR1_ROWS |\
+ CONFIG_OR1_PMSEL |\
+ CONFIG_OR1_SCY |\
+ CONFIG_OR1_PGS |\
+ CONFIG_OR1_CSCT |\
+ CONFIG_OR1_CST |\
+ CONFIG_OR1_CHT |\
+ CONFIG_OR1_RST |\
+ CONFIG_OR1_CSNT |\
+ CONFIG_OR1_ACS |\
+ CONFIG_OR1_XACS |\
+ CONFIG_OR1_SETA |\
+ CONFIG_OR1_TRLX |\
+ CONFIG_OR1_EHTR |\
+ CONFIG_OR1_EAD \
+)
+#endif /* CONFIG_ELBC_BR1_OR1 */
+
+#ifdef CONFIG_ELBC_BR2_OR2
+#define CONFIG_SYS_BR2_PRELIM (\
+ CONFIG_BR2_OR2_BASE |\
+ CONFIG_BR2_PORTSIZE |\
+ CONFIG_BR2_ERRORCHECKING |\
+ CONFIG_BR2_WRITE_PROTECT_BIT |\
+ CONFIG_BR2_MACHINE |\
+ CONFIG_BR2_ATOMIC |\
+ CONFIG_BR2_VALID_BIT \
+)
+#define CONFIG_SYS_OR2_PRELIM (\
+ CONFIG_OR2_AM |\
+ CONFIG_OR2_XAM |\
+ CONFIG_OR2_BCTLD |\
+ CONFIG_OR2_BI |\
+ CONFIG_OR2_COLS |\
+ CONFIG_OR2_ROWS |\
+ CONFIG_OR2_PMSEL |\
+ CONFIG_OR2_SCY |\
+ CONFIG_OR2_PGS |\
+ CONFIG_OR2_CSCT |\
+ CONFIG_OR2_CST |\
+ CONFIG_OR2_CHT |\
+ CONFIG_OR2_RST |\
+ CONFIG_OR2_CSNT |\
+ CONFIG_OR2_ACS |\
+ CONFIG_OR2_XACS |\
+ CONFIG_OR2_SETA |\
+ CONFIG_OR2_TRLX |\
+ CONFIG_OR2_EHTR |\
+ CONFIG_OR2_EAD \
+)
+#endif /* CONFIG_ELBC_BR2_OR2 */
+
+#ifdef CONFIG_ELBC_BR3_OR3
+#define CONFIG_SYS_BR3_PRELIM (\
+ CONFIG_BR3_OR3_BASE |\
+ CONFIG_BR3_PORTSIZE |\
+ CONFIG_BR3_ERRORCHECKING |\
+ CONFIG_BR3_WRITE_PROTECT_BIT |\
+ CONFIG_BR3_MACHINE |\
+ CONFIG_BR3_ATOMIC |\
+ CONFIG_BR3_VALID_BIT \
+)
+#define CONFIG_SYS_OR3_PRELIM (\
+ CONFIG_OR3_AM |\
+ CONFIG_OR3_XAM |\
+ CONFIG_OR3_BCTLD |\
+ CONFIG_OR3_BI |\
+ CONFIG_OR3_COLS |\
+ CONFIG_OR3_ROWS |\
+ CONFIG_OR3_PMSEL |\
+ CONFIG_OR3_SCY |\
+ CONFIG_OR3_PGS |\
+ CONFIG_OR3_CSCT |\
+ CONFIG_OR3_CST |\
+ CONFIG_OR3_CHT |\
+ CONFIG_OR3_RST |\
+ CONFIG_OR3_CSNT |\
+ CONFIG_OR3_ACS |\
+ CONFIG_OR3_XACS |\
+ CONFIG_OR3_SETA |\
+ CONFIG_OR3_TRLX |\
+ CONFIG_OR3_EHTR |\
+ CONFIG_OR3_EAD \
+)
+#endif /* CONFIG_ELBC_BR3_OR3 */
+
+#ifdef CONFIG_ELBC_BR4_OR4
+#define CONFIG_SYS_BR4_PRELIM (\
+ CONFIG_BR4_OR4_BASE |\
+ CONFIG_BR4_PORTSIZE |\
+ CONFIG_BR4_ERRORCHECKING |\
+ CONFIG_BR4_WRITE_PROTECT_BIT |\
+ CONFIG_BR4_MACHINE |\
+ CONFIG_BR4_ATOMIC |\
+ CONFIG_BR4_VALID_BIT \
+)
+#define CONFIG_SYS_OR4_PRELIM (\
+ CONFIG_OR4_AM |\
+ CONFIG_OR4_XAM |\
+ CONFIG_OR4_BCTLD |\
+ CONFIG_OR4_BI |\
+ CONFIG_OR4_COLS |\
+ CONFIG_OR4_ROWS |\
+ CONFIG_OR4_PMSEL |\
+ CONFIG_OR4_SCY |\
+ CONFIG_OR4_PGS |\
+ CONFIG_OR4_CSCT |\
+ CONFIG_OR4_CST |\
+ CONFIG_OR4_CHT |\
+ CONFIG_OR4_RST |\
+ CONFIG_OR4_CSNT |\
+ CONFIG_OR4_ACS |\
+ CONFIG_OR4_XACS |\
+ CONFIG_OR4_SETA |\
+ CONFIG_OR4_TRLX |\
+ CONFIG_OR4_EHTR |\
+ CONFIG_OR4_EAD \
+)
+#endif /* CONFIG_ELBC_BR4_OR4 */
+
+#if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0)
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
+#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_1)
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
+#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_2)
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM
+#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_3)
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM
+#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_4)
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM
+#endif
diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c
index 0ecafd7..b487e31 100644
--- a/arch/powerpc/cpu/mpc83xx/fdt.c
+++ b/arch/powerpc/cpu/mpc83xx/fdt.c
@@ -16,7 +16,7 @@
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
- (defined(CONFIG_QE) && !defined(CONFIG_MPC831x))
+ (defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))
#include <linux/immap_qe.h>
void fdt_fixup_muram (void *blob)
@@ -52,7 +52,7 @@
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\
defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5)
-#ifdef CONFIG_MPC8313
+#ifdef CONFIG_ARCH_MPC8313
/*
* mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1
* h/w (see AN3545). The base device tree in use has rev. 1 ID numbers,
@@ -116,14 +116,14 @@
#endif
#ifdef CONFIG_SYS_NS16550
- do_fixup_by_compat_u32(blob, "ns16550",
- "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
+ do_fixup_by_compat_u32(blob, "ns16550",
+ "clock-frequency", get_serial_clock(), 1);
#endif
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
- (defined(CONFIG_QE) && !defined(CONFIG_MPC831x))
+ (defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))
fdt_fixup_muram (blob);
#endif
}
diff --git a/arch/powerpc/cpu/mpc83xx/hid/Kconfig b/arch/powerpc/cpu/mpc83xx/hid/Kconfig
new file mode 100644
index 0000000..c367ad2
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/hid/Kconfig
@@ -0,0 +1,565 @@
+menu "HID setup"
+
+menu "HID0 initial"
+
+config HID0_INIT_EMCP
+ bool "Enable machine check int on mcp"
+
+config HID0_INIT_ECPE
+ bool "Enable cache parity errors"
+
+config HID0_INIT_EBA
+ bool "Enable address parity checking"
+
+config HID0_INIT_EBD
+ bool "Enable data parity checking"
+
+choice
+ prompt "HID0 clock configuration"
+
+config HID0_INIT_CLKOUT_OFF
+ bool "Clock output off"
+
+config HID0_INIT_CLKOUT_CORE_HALF
+ bool "Core clock / 2"
+
+config HID0_INIT_CLKOUT_CORE
+ bool "Core clock"
+
+config HID0_INIT_CLKOUT_BUS
+ bool "Bus clock"
+
+endchoice
+
+config HID0_INIT_PAR
+ bool "Disable precharge of artry_out"
+
+config HID0_INIT_DOZE
+ bool "Enable doze mode"
+
+config HID0_INIT_NAP
+ bool "Enable nap mode"
+
+config HID0_INIT_SLEEP
+ bool "Enable sleep mode"
+
+config HID0_INIT_DPM
+ bool "Enable dynamic power management"
+
+config HID0_INIT_ICE
+ bool "Enable instruction cache"
+
+config HID0_INIT_DCE
+ bool "Enable data cache"
+
+config HID0_INIT_ILOCK
+ bool "Lock instruction cache"
+
+config HID0_INIT_DLOCK
+ bool "Lock data cache"
+
+config HID0_INIT_ICFI
+ bool "Flash invalidate instruction cache"
+
+config HID0_INIT_DCFI
+ bool "Flash invalidate data cache"
+
+config HID0_INIT_IFEM
+ bool "Enable m bit on bus for instruction fetches"
+
+config HID0_INIT_DECAREN
+ bool "Decrementer auto reload"
+
+config HID0_INIT_FBIOB
+ bool "Force indirect branch on the bus"
+
+config HID0_INIT_ABE
+ bool "Enable address broadcast"
+
+config HID0_INIT_NOOPTI
+ bool "No-op data cache touch intructions"
+
+endmenu
+
+menu "HID0 final"
+
+config HID0_FINAL_EMCP
+ bool "Enable machine check int on mcp"
+
+config HID0_FINAL_ECPE
+ bool "Enable cache parity errors"
+
+config HID0_FINAL_EBA
+ bool "Enable address parity checking"
+
+config HID0_FINAL_EBD
+ bool "Enable data parity checking"
+
+choice
+ prompt "HID0 clock configuration"
+
+config HID0_FINAL_CLKOUT_OFF
+ bool "Clock output off"
+
+config HID0_FINAL_CLKOUT_CORE_HALF
+ bool "Core clock / 2"
+
+config HID0_FINAL_CLKOUT_CORE
+ bool "Core clock"
+
+config HID0_FINAL_CLKOUT_BUS
+ bool "Bus clock"
+
+endchoice
+
+config HID0_FINAL_PAR
+ bool "Disable precharge of artry_out"
+
+config HID0_FINAL_DOZE
+ bool "Enable doze mode"
+
+config HID0_FINAL_NAP
+ bool "Enable nap mode"
+
+config HID0_FINAL_SLEEP
+ bool "Enable sleep mode"
+
+config HID0_FINAL_DPM
+ bool "Enable dynamic power management"
+
+config HID0_FINAL_ICE
+ bool "Enable instruction cache"
+
+config HID0_FINAL_DCE
+ bool "Enable data cache"
+
+config HID0_FINAL_ILOCK
+ bool "Lock instruction cache"
+
+config HID0_FINAL_DLOCK
+ bool "Lock data cache"
+
+config HID0_FINAL_ICFI
+ bool "Flash invalidate instruction cache"
+
+config HID0_FINAL_DCFI
+ bool "Flash invalidate data cache"
+
+config HID0_FINAL_IFEM
+ bool "Enable m bit on bus for instruction fetches"
+
+config HID0_FINAL_DECAREN
+ bool "Decrementer auto reload"
+
+config HID0_FINAL_FBIOB
+ bool "Force indirect branch on the bus"
+
+config HID0_FINAL_ABE
+ bool "Enable address broadcast"
+
+config HID0_FINAL_NOOPTI
+ bool "No-op data cache touch intructions"
+
+endmenu
+
+config HID0_INIT_EMCP_BIT
+ hex
+ default 0x0 if !HID0_INIT_EMCP
+ default 0x80000000 if HID0_INIT_EMCP
+
+config HID0_INIT_ECPE_BIT
+ hex
+ default 0x0 if !HID0_INIT_ECPE
+ default 0x40000000 if HID0_INIT_ECPE
+
+config HID0_INIT_EBA_BIT
+ hex
+ default 0x0 if !HID0_INIT_EBA
+ default 0x20000000 if HID0_INIT_EBA
+
+config HID0_INIT_EBD_BIT
+ hex
+ default 0x0 if !HID0_INIT_EBD
+ default 0x10000000 if HID0_INIT_EBD
+
+config HID0_INIT_CLKOUT
+ hex
+ default 0x0 if HID0_INIT_CLKOUT_OFF
+ default 0x8000000 if HID0_INIT_CLKOUT_CORE_HALF
+ default 0x2000000 if HID0_INIT_CLKOUT_CORE
+ default 0xa000000 if HID0_INIT_CLKOUT_BUS
+
+config HID0_INIT_PAR_BIT
+ hex
+ default 0x0 if !HID0_INIT_PAR
+ default 0x1000000 if HID0_INIT_PAR
+
+config HID0_INIT_DOZE_BIT
+ hex
+ default 0x0 if !HID0_INIT_DOZE
+ default 0x800000 if HID0_INIT_DOZE
+
+config HID0_INIT_NAP_BIT
+ hex
+ default 0x0 if !HID0_INIT_NAP
+ default 0x400000 if HID0_INIT_NAP
+
+config HID0_INIT_SLEEP_BIT
+ hex
+ default 0x0 if !HID0_INIT_SLEEP
+ default 0x200000 if HID0_INIT_SLEEP
+
+config HID0_INIT_DPM_BIT
+ hex
+ default 0x0 if !HID0_INIT_DPM
+ default 0x100000 if HID0_INIT_DPM
+
+config HID0_INIT_ICE_BIT
+ hex
+ default 0x0 if !HID0_INIT_ICE
+ default 0x8000 if HID0_INIT_ICE
+
+config HID0_INIT_DCE_BIT
+ hex
+ default 0x0 if !HID0_INIT_DCE
+ default 0x4000 if HID0_INIT_DCE
+
+config HID0_INIT_ILOCK_BIT
+ hex
+ default 0x0 if !HID0_INIT_ILOCK
+ default 0x2000 if HID0_INIT_ILOCK
+
+config HID0_INIT_DLOCK_BIT
+ hex
+ default 0x0 if !HID0_INIT_DLOCK
+ default 0x1000 if HID0_INIT_DLOCK
+
+config HID0_INIT_ICFI_BIT
+ hex
+ default 0x0 if !HID0_INIT_ICFI
+ default 0x800 if HID0_INIT_ICFI
+
+config HID0_INIT_DCFI_BIT
+ hex
+ default 0x0 if !HID0_INIT_DCFI
+ default 0x400 if HID0_INIT_DCFI
+
+config HID0_INIT_IFEM_BIT
+ hex
+ default 0x0 if !HID0_INIT_IFEM
+ default 0x80 if HID0_INIT_IFEM
+
+config HID0_INIT_DECAREN_BIT
+ hex
+ default 0x0 if !HID0_INIT_DECAREN
+ default 0x40 if HID0_INIT_DECAREN
+
+config HID0_INIT_FBIOB_BIT
+ hex
+ default 0x0 if !HID0_INIT_FBIOB
+ default 0x10 if HID0_INIT_FBIOB
+
+config HID0_INIT_ABE_BIT
+ hex
+ default 0x0 if !HID0_INIT_ABE
+ default 0x8 if HID0_INIT_ABE
+
+config HID0_INIT_NOOPTI_BIT
+ hex
+ default 0x0 if !HID0_INIT_NOOPTI
+ default 0x1 if HID0_INIT_NOOPTI
+
+config HID0_FINAL_EMCP_BIT
+ hex
+ default 0x0 if !HID0_FINAL_EMCP
+ default 0x80000000 if HID0_FINAL_EMCP
+
+config HID0_FINAL_ECPE_BIT
+ hex
+ default 0x0 if !HID0_FINAL_ECPE
+ default 0x40000000 if HID0_FINAL_ECPE
+
+config HID0_FINAL_EBA_BIT
+ hex
+ default 0x0 if !HID0_FINAL_EBA
+ default 0x20000000 if HID0_FINAL_EBA
+
+config HID0_FINAL_EBD_BIT
+ hex
+ default 0x0 if !HID0_FINAL_EBD
+ default 0x10000000 if HID0_FINAL_EBD
+
+config HID0_FINAL_CLKOUT
+ hex
+ default 0x0 if HID0_FINAL_CLKOUT_OFF
+ default 0x8000000 if HID0_FINAL_CLKOUT_CORE_HALF
+ default 0x2000000 if HID0_FINAL_CLKOUT_CORE
+ default 0xa000000 if HID0_FINAL_CLKOUT_BUS
+
+config HID0_FINAL_SBCLK_BIT
+ hex
+ default 0x0 if !HID0_FINAL_SBCLK
+ default 0x8000000 if HID0_FINAL_SBCLK
+
+config HID0_FINAL_ECLK_BIT
+ hex
+ default 0x0 if !HID0_FINAL_ECLK
+ default 0x2000000 if HID0_FINAL_ECLK
+
+config HID0_FINAL_PAR_BIT
+ hex
+ default 0x0 if !HID0_FINAL_PAR
+ default 0x1000000 if HID0_FINAL_PAR
+
+config HID0_FINAL_DOZE_BIT
+ hex
+ default 0x0 if !HID0_FINAL_DOZE
+ default 0x800000 if HID0_FINAL_DOZE
+
+config HID0_FINAL_NAP_BIT
+ hex
+ default 0x0 if !HID0_FINAL_NAP
+ default 0x400000 if HID0_FINAL_NAP
+
+config HID0_FINAL_SLEEP_BIT
+ hex
+ default 0x0 if !HID0_FINAL_SLEEP
+ default 0x200000 if HID0_FINAL_SLEEP
+
+config HID0_FINAL_DPM_BIT
+ hex
+ default 0x0 if !HID0_FINAL_DPM
+ default 0x100000 if HID0_FINAL_DPM
+
+config HID0_FINAL_ICE_BIT
+ hex
+ default 0x0 if !HID0_FINAL_ICE
+ default 0x8000 if HID0_FINAL_ICE
+
+config HID0_FINAL_DCE_BIT
+ hex
+ default 0x0 if !HID0_FINAL_DCE
+ default 0x4000 if HID0_FINAL_DCE
+
+config HID0_FINAL_ILOCK_BIT
+ hex
+ default 0x0 if !HID0_FINAL_ILOCK
+ default 0x2000 if HID0_FINAL_ILOCK
+
+config HID0_FINAL_DLOCK_BIT
+ hex
+ default 0x0 if !HID0_FINAL_DLOCK
+ default 0x1000 if HID0_FINAL_DLOCK
+
+config HID0_FINAL_ICFI_BIT
+ hex
+ default 0x0 if !HID0_FINAL_ICFI
+ default 0x800 if HID0_FINAL_ICFI
+
+config HID0_FINAL_DCFI_BIT
+ hex
+ default 0x0 if !HID0_FINAL_DCFI
+ default 0x400 if HID0_FINAL_DCFI
+
+config HID0_FINAL_IFEM_BIT
+ hex
+ default 0x0 if !HID0_FINAL_IFEM
+ default 0x80 if HID0_FINAL_IFEM
+
+config HID0_FINAL_DECAREN_BIT
+ hex
+ default 0x0 if !HID0_FINAL_DECAREN
+ default 0x40 if HID0_FINAL_DECAREN
+
+config HID0_FINAL_FBIOB_BIT
+ hex
+ default 0x0 if !HID0_FINAL_FBIOB
+ default 0x10 if HID0_FINAL_FBIOB
+
+config HID0_FINAL_ABE_BIT
+ hex
+ default 0x0 if !HID0_FINAL_ABE
+ default 0x8 if HID0_FINAL_ABE
+
+config HID0_FINAL_NOOPTI_BIT
+ hex
+ default 0x0 if !HID0_FINAL_NOOPTI
+ default 0x1 if HID0_FINAL_NOOPTI
+
+menu "HID2"
+
+config HID2_LET
+ bool "True little-endian mode"
+
+config HID2_IFEB
+ bool "Instruction fetch burst extension"
+
+config HID2_MESISTATE
+ bool "MESI state enable"
+
+config HID2_IFEC
+ bool "Instruction fetch cancel extension"
+
+config HID2_EBQS
+ bool "BIU queue sharing"
+
+config HID2_EBPX
+ bool "BIU pipeline extension"
+
+if !ARCH_MPC8360
+
+config HID2_ELRW
+ bool "Weighted LRU"
+
+config HID2_NOKS
+ bool "No kill for snoop"
+
+endif
+
+config HID2_HBE
+ bool "High bat enable"
+
+choice
+ prompt "Instruction cache way-lock"
+
+config HID2_IWLCK_NONE
+ bool "No ways locked"
+
+config HID2_IWLCK_0
+ bool "Way 0 locked"
+
+config HID2_IWLCK_1
+ bool "Way 0 through 1 locked"
+
+config HID2_IWLCK_2
+ bool "Way 0 through 2 locked"
+
+if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+
+config HID2_IWLCK_3
+ bool "Way 0 through 3 locked"
+
+config HID2_IWLCK_4
+ bool "Way 0 through 4 locked"
+
+config HID2_IWLCK_5
+ bool "Way 0 through 5 locked"
+
+config HID2_IWLCK_6
+ bool "Way 0 through 6 locked"
+
+endif
+
+endchoice
+
+config HID2_ICWP
+ bool "Instruction cache way protection"
+
+choice
+ prompt "Data cache way-lock"
+
+config HID2_DWLCK_NONE
+ bool "No ways locked"
+
+config HID2_DWLCK_0
+ bool "Way 0 locked"
+
+config HID2_DWLCK_1
+ bool "Way 0 through 1 locked"
+
+config HID2_DWLCK_2
+ bool "Way 0 through 2 locked"
+
+if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+
+config HID2_DWLCK_3
+ bool "Way 0 through 3 locked"
+
+config HID2_DWLCK_4
+ bool "Way 0 through 4 locked"
+
+config HID2_DWLCK_5
+ bool "Way 0 through 5 locked"
+
+config HID2_DWLCK_6
+ bool "Way 0 through 6 locked"
+
+endif
+
+endchoice
+
+config HID2_LET_BIT
+ hex
+ default 0x0 if !HID2_LET
+ default 0x8000000 if HID2_LET
+
+config HID2_IFEB_BIT
+ hex
+ default 0x0 if !HID2_IFEB
+ default 0x4000000 if HID2_IFEB
+
+config HID2_MESISTATE_BIT
+ hex
+ default 0x0 if !HID2_MESISTATE
+ default 0x1000000 if HID2_MESISTATE
+
+config HID2_IFEC_BIT
+ hex
+ default 0x0 if !HID2_IFEC
+ default 0x800000 if HID2_IFEC
+
+config HID2_EBQS_BIT
+ hex
+ default 0x0 if !HID2_EBQS
+ default 0x400000 if HID2_EBQS
+
+config HID2_EBPX_BIT
+ hex
+ default 0x0 if !HID2_EBPX
+ default 0x200000 if HID2_EBPX
+
+config HID2_ELRW_BIT
+ hex
+ default 0x0 if !HID2_ELRW
+ default 0x100000 if HID2_ELRW
+
+config HID2_NOKS_BIT
+ hex
+ default 0x0 if !HID2_NOKS
+ default 0x80000 if HID2_NOKS
+
+config HID2_HBE_BIT
+ hex
+ default 0x0 if !HID2_HBE
+ default 0x40000 if HID2_HBE
+
+config HID2_IWLCK
+ hex
+ default 0x0 if HID2_IWLCK_NONE
+ default 0x2000 if HID2_IWLCK_0
+ default 0x4000 if HID2_IWLCK_1
+ default 0x6000 if HID2_IWLCK_2
+ default 0x8000 if HID2_IWLCK_3
+ default 0xA000 if HID2_IWLCK_4
+ default 0xC000 if HID2_IWLCK_5
+ default 0xE000 if HID2_IWLCK_6
+
+config HID2_ICWP_BIT
+ hex
+ default 0x0 if !HID2_ICWP
+ default 0x1000 if HID2_ICWP
+
+config HID2_DWLCK
+ hex
+ default 0x0 if HID2_DWLCK_NONE
+ default 0x20 if HID2_DWLCK_0
+ default 0x40 if HID2_DWLCK_1
+ default 0x60 if HID2_DWLCK_2
+ default 0x80 if HID2_DWLCK_3
+ default 0xA0 if HID2_DWLCK_4
+ default 0xC0 if HID2_DWLCK_5
+ default 0xE0 if HID2_DWLCK_6
+
+endmenu
+
+endmenu
diff --git a/arch/powerpc/cpu/mpc83xx/hid/hid.h b/arch/powerpc/cpu/mpc83xx/hid/hid.h
new file mode 100644
index 0000000..9f5260c
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/hid/hid.h
@@ -0,0 +1,72 @@
+#define CONFIG_SYS_HID0_FINAL ( \
+ CONFIG_HID0_FINAL_ABE_BIT |\
+ CONFIG_HID0_FINAL_CLKOUT |\
+ CONFIG_HID0_FINAL_DCE_BIT |\
+ CONFIG_HID0_FINAL_DCFI_BIT |\
+ CONFIG_HID0_FINAL_DECAREN_BIT |\
+ CONFIG_HID0_FINAL_DLOCK_BIT |\
+ CONFIG_HID0_FINAL_DOZE_BIT |\
+ CONFIG_HID0_FINAL_DPM_BIT |\
+ CONFIG_HID0_FINAL_EBA_BIT |\
+ CONFIG_HID0_FINAL_EBD_BIT |\
+ CONFIG_HID0_FINAL_ECLK_BIT |\
+ CONFIG_HID0_FINAL_ECPE_BIT |\
+ CONFIG_HID0_FINAL_EMCP_BIT |\
+ CONFIG_HID0_FINAL_FBIOB_BIT |\
+ CONFIG_HID0_FINAL_ICE_BIT |\
+ CONFIG_HID0_FINAL_ICFI_BIT |\
+ CONFIG_HID0_FINAL_IFEM_BIT |\
+ CONFIG_HID0_FINAL_ILOCK_BIT |\
+ CONFIG_HID0_FINAL_NAP_BIT |\
+ CONFIG_HID0_FINAL_NOOPTI_BIT |\
+ CONFIG_HID0_FINAL_PAR_BIT |\
+ CONFIG_HID0_FINAL_SBCLK_BIT |\
+ CONFIG_HID0_FINAL_SLEEP_BIT \
+)
+
+#define CONFIG_SYS_HID0_INIT ( \
+ CONFIG_HID0_INIT_ABE_BIT |\
+ CONFIG_HID0_INIT_CLKOUT |\
+ CONFIG_HID0_INIT_DCE_BIT |\
+ CONFIG_HID0_INIT_DCFI_BIT |\
+ CONFIG_HID0_INIT_DECAREN_BIT |\
+ CONFIG_HID0_INIT_DLOCK_BIT |\
+ CONFIG_HID0_INIT_DOZE_BIT |\
+ CONFIG_HID0_INIT_DPM_BIT |\
+ CONFIG_HID0_INIT_EBA_BIT |\
+ CONFIG_HID0_INIT_EBD_BIT |\
+ CONFIG_HID0_INIT_ECPE_BIT |\
+ CONFIG_HID0_INIT_EMCP_BIT |\
+ CONFIG_HID0_INIT_FBIOB_BIT |\
+ CONFIG_HID0_INIT_ICE_BIT |\
+ CONFIG_HID0_INIT_ICFI_BIT |\
+ CONFIG_HID0_INIT_IFEM_BIT |\
+ CONFIG_HID0_INIT_ILOCK_BIT |\
+ CONFIG_HID0_INIT_NAP_BIT |\
+ CONFIG_HID0_INIT_NOOPTI_BIT |\
+ CONFIG_HID0_INIT_PAR_BIT |\
+ CONFIG_HID0_INIT_SLEEP_BIT \
+)
+
+#ifdef CONFIG_TARGET_IDS8313
+/* IDS8313 defines a reserved bit; keep to not break compatibility */
+#define CONFIG_HID2_SPECIAL 0x00020000
+#else
+#define CONFIG_HID2_SPECIAL 0x0
+#endif
+
+#define CONFIG_SYS_HID2 ( \
+ CONFIG_HID2_LET_BIT |\
+ CONFIG_HID2_IFEB_BIT |\
+ CONFIG_HID2_MESISTATE_BIT |\
+ CONFIG_HID2_IFEC_BIT |\
+ CONFIG_HID2_EBQS_BIT |\
+ CONFIG_HID2_EBPX_BIT |\
+ CONFIG_HID2_ELRW_BIT |\
+ CONFIG_HID2_NOKS_BIT |\
+ CONFIG_HID2_HBE_BIT |\
+ CONFIG_HID2_IWLCK |\
+ CONFIG_HID2_ICWP_BIT |\
+ CONFIG_HID2_DWLCK |\
+ CONFIG_HID2_SPECIAL \
+)
diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
new file mode 100644
index 0000000..c657a47
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
@@ -0,0 +1,816 @@
+menu "Reset Configuration Word"
+
+choice
+ prompt "Local bus memory controller clock mode"
+
+config LBMC_CLOCK_MODE_1_1
+ bool "1 : 1"
+
+config LBMC_CLOCK_MODE_1_2
+ depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
+ bool "1 : 2"
+
+endchoice
+
+choice
+ prompt "DDR SDRAM memory controller clock mode"
+
+config DDR_MC_CLOCK_MODE_1_2
+ bool "1 : 2"
+
+config DDR_MC_CLOCK_MODE_1_1
+ depends on ARCH_MPC8315 || ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
+ bool "1 : 1"
+
+endchoice
+
+if !ARCH_MPC8313 && !ARCH_MPC832X && !ARCH_MPC8349
+
+choice
+ prompt "System PLL VCO division"
+
+config SYSTEM_PLL_VCO_DIV_1
+ depends on !ARCH_MPC837X
+ bool "1"
+
+config SYSTEM_PLL_VCO_DIV_2
+ bool "2"
+
+config SYSTEM_PLL_VCO_DIV_4
+ depends on !ARCH_MPC831X
+ bool "4"
+
+config SYSTEM_PLL_VCO_DIV_8
+ depends on !ARCH_MPC831X
+ bool "8"
+
+endchoice
+
+endif
+
+choice
+ prompt "System PLL multiplication factor"
+
+config SYSTEM_PLL_FACTOR_2_1
+ bool "2 : 1"
+
+config SYSTEM_PLL_FACTOR_3_1
+ bool "3 : 1"
+
+config SYSTEM_PLL_FACTOR_4_1
+ bool "4 : 1"
+
+config SYSTEM_PLL_FACTOR_5_1
+ bool "5 : 1"
+
+config SYSTEM_PLL_FACTOR_6_1
+ bool "6 : 1"
+
+config SYSTEM_PLL_FACTOR_7_1
+ depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ bool "7 : 1"
+
+config SYSTEM_PLL_FACTOR_8_1
+ depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ bool "8 : 1"
+
+config SYSTEM_PLL_FACTOR_9_1
+ depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ bool "9 : 1"
+
+config SYSTEM_PLL_FACTOR_10_1
+ depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ bool "10 : 1"
+
+config SYSTEM_PLL_FACTOR_11_1
+ depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ bool "11 : 1"
+
+config SYSTEM_PLL_FACTOR_12_1
+ depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ bool "12 : 1"
+
+config SYSTEM_PLL_FACTOR_13_1
+ depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ bool "13 : 1"
+
+config SYSTEM_PLL_FACTOR_14_1
+ depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ bool "14 : 1"
+
+config SYSTEM_PLL_FACTOR_15_1
+ depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+ bool "15 : 1"
+
+config SYSTEM_PLL_FACTOR_16_1
+ depends on ARCH_MPC8349 || ARCH_MPV8360
+ bool "16 : 1"
+
+endchoice
+
+config CORE_PLL_BYPASS
+ bool "Core PLL bypassed"
+
+if !CORE_PLL_BYPASS
+
+choice
+ prompt "Core PLL Ratio"
+
+config CORE_PLL_RATIO_1_1
+ bool "1 : 1"
+
+config CORE_PLL_RATIO_15_1
+ bool "1.5 : 1"
+
+config CORE_PLL_RATIO_2_1
+ bool "2 : 1"
+
+config CORE_PLL_RATIO_25_1
+ bool "2.5 : 1"
+
+config CORE_PLL_RATIO_3_1
+ bool "3 : 1"
+
+endchoice
+
+choice
+ prompt "Core PLL VCO Divider"
+
+config CORE_PLL_VCO_DIVIDER_2
+ bool "2"
+
+config CORE_PLL_VCO_DIVIDER_4
+ bool "4"
+
+config CORE_PLL_VCO_DIVIDER_8
+ depends on !ARCH_MPC8315
+ bool "8"
+
+endchoice
+
+endif
+
+if MPC83XX_QUICC_ENGINE
+
+choice
+ prompt "QUICC Engine PLL VCO Divider"
+
+config QUICC_VCO_DIVIDER_2
+ bool "2"
+
+config QUICC_VCO_DIVIDER_4
+ bool "4"
+
+config QUICC_VCO_DIVIDER_8
+ depends on ARCH_MPC8309
+ bool "8"
+
+endchoice
+
+choice
+ prompt "QUICC Engine PLL division factor"
+
+config QUICC_DIV_FACTOR_1
+ bool "1"
+
+config QUICC_DIV_FACTOR_2
+ bool "2"
+
+endchoice
+
+choice
+ prompt "QUICC Engine PLL multiplication factor"
+
+config QUICC_MULT_FACTOR_2
+ bool "2"
+
+config QUICC_MULT_FACTOR_3
+ bool "3"
+
+config QUICC_MULT_FACTOR_4
+ bool "4"
+
+config QUICC_MULT_FACTOR_5
+ bool "5"
+
+config QUICC_MULT_FACTOR_6
+ bool "6"
+
+config QUICC_MULT_FACTOR_7
+ bool "7"
+
+config QUICC_MULT_FACTOR_8
+ bool "8"
+
+config QUICC_MULT_FACTOR_9
+ depends on ARCH_MPC8360
+ bool "9"
+
+config QUICC_MULT_FACTOR_10
+ depends on ARCH_MPC8360
+ bool "10"
+
+config QUICC_MULT_FACTOR_11
+ depends on ARCH_MPC8360
+ bool "11"
+
+config QUICC_MULT_FACTOR_12
+ depends on ARCH_MPC8360
+ bool "12"
+
+config QUICC_MULT_FACTOR_13
+ depends on ARCH_MPC8360
+ bool "13"
+
+config QUICC_MULT_FACTOR_14
+ depends on ARCH_MPC8360
+ bool "14"
+
+config QUICC_MULT_FACTOR_15
+ depends on ARCH_MPC8360
+ bool "15"
+
+config QUICC_MULT_FACTOR_16
+ depends on ARCH_MPC8360
+ bool "16"
+
+config QUICC_MULT_FACTOR_17
+ depends on ARCH_MPC8360
+ bool "17"
+
+config QUICC_MULT_FACTOR_18
+ depends on ARCH_MPC8360
+ bool "18"
+
+config QUICC_MULT_FACTOR_19
+ depends on ARCH_MPC8360
+ bool "19"
+
+config QUICC_MULT_FACTOR_20
+ depends on ARCH_MPC8360
+ bool "20"
+
+config QUICC_MULT_FACTOR_21
+ depends on ARCH_MPC8360
+ bool "21"
+
+config QUICC_MULT_FACTOR_22
+ depends on ARCH_MPC8360
+ bool "22"
+
+config QUICC_MULT_FACTOR_23
+ depends on ARCH_MPC8360
+ bool "23"
+
+config QUICC_MULT_FACTOR_24
+ depends on ARCH_MPC8360
+ bool "24"
+
+config QUICC_MULT_FACTOR_25
+ depends on ARCH_MPC8360
+ bool "25"
+
+config QUICC_MULT_FACTOR_26
+ depends on ARCH_MPC8360
+ bool "26"
+
+config QUICC_MULT_FACTOR_27
+ depends on ARCH_MPC8360
+ bool "27"
+
+config QUICC_MULT_FACTOR_28
+ depends on ARCH_MPC8360
+ bool "28"
+
+config QUICC_MULT_FACTOR_29
+ depends on ARCH_MPC8360
+ bool "29"
+
+config QUICC_MULT_FACTOR_30
+ depends on ARCH_MPC8360
+ bool "30"
+
+config QUICC_MULT_FACTOR_31
+ depends on ARCH_MPC8360
+ bool "31"
+
+endchoice
+
+endif
+
+if MPC83XX_PCI_SUPPORT
+
+choice
+ prompt "PCI host mode"
+
+config PCI_HOST_MODE_DISABLE
+ bool "Disabled"
+
+config PCI_HOST_MODE_ENABLE
+ bool "Enabled"
+
+endchoice
+
+if ARCH_MPC8349
+
+choice
+ prompt "PCI 64-bit mode"
+
+config PCI_64BIT_MODE_DISABLE
+ bool "Disabled"
+
+config PCI_64BIT_MODE_ENABLE
+ bool "Enabled"
+
+endchoice
+
+endif
+
+choice
+ prompt "PCI internal arbiter 1 mode"
+
+config PCI_INT_ARBITER1_DISABLE
+ bool "Disabled"
+
+config PCI_INT_ARBITER1_ENABLE
+ bool "Enabled"
+
+endchoice
+
+if ARCH_MPC8349
+
+choice
+ prompt "PCI internal arbiter 2 mode"
+
+config PCI_INT_ARBITER2_DISABLE
+ bool "Disabled"
+
+config PCI_INT_ARBITER2_ENABLE
+ bool "Enabled"
+
+endchoice
+
+endif
+
+if ARCH_MPC8360
+
+choice
+ prompt "PCI clock output drive"
+
+config PCI_CLOCK_OUTPUT_DRIVE_DISABLE
+ bool "Disabled"
+
+config PCI_CLOCK_OUTPUT_DRIVE_ENABLE
+ bool "Enabled"
+
+endchoice
+
+endif
+
+endif
+
+choice
+ prompt "Core disable mode"
+
+config CORE_DISABLE_MODE_OFF
+ bool "Off"
+
+config CORE_DISABLE_MODE_ON
+ bool "On"
+
+endchoice
+
+choice
+ prompt "Boot Memory Space"
+
+config BOOT_MEMORY_SPACE_HIGH
+ bool "High"
+
+config BOOT_MEMORY_SPACE_LOW
+ bool "Low"
+
+endchoice
+
+choice
+ prompt "Boot Sequencer Configuration"
+
+config BOOT_SEQUENCER_DISABLED
+ bool "Disabled"
+
+config BOOT_SEQUENCER_NORMAL_I2C
+ bool "Normal I2C"
+
+config BOOT_SEQUENCER_EXTENDED_I2C
+ bool "Extended I2C"
+
+endchoice
+
+choice
+ prompt "Software Watchdog"
+
+config SOFTWARE_WATCHDOG_DISABLED
+ bool "Disabled"
+
+config SOFTWARE_WATCHDOG_ENABLED
+ bool "Enabled"
+
+endchoice
+
+choice
+ prompt "Boot ROM interface location"
+
+config BOOT_ROM_INTERFACE_DDR_SDRAM
+ bool "DDR_SDRAM"
+
+config BOOT_ROM_INTERFACE_PCI1
+ depends on MPC83XX_PCI_SUPPORT
+ bool "PCI1"
+
+config BOOT_ROM_INTERFACE_PCI2
+ depends on MPC83XX_PCI_SUPPORT && ARCH_MPC8349
+ bool "PCI2"
+
+config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
+ depends on ARCH_MPC837X
+ bool "PCI2"
+
+config BOOT_ROM_INTERFACE_ESDHC
+ depends on ARCH_MPC8309
+ bool "eSDHC"
+
+config BOOT_ROM_INTERFACE_SPI
+ depends on ARCH_MPC8309
+ bool "SPI"
+
+config BOOT_ROM_INTERFACE_GPCM_8BIT
+ bool "Local bus GPCM - 8-bit ROM"
+
+config BOOT_ROM_INTERFACE_GPCM_16BIT
+ bool "Local bus GPCM - 16-bit ROM"
+
+config BOOT_ROM_INTERFACE_GPCM_32BIT
+ depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
+ bool "Local bus GPCM - 32-bit ROM"
+
+config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
+ depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ bool "Local bus NAND Flash- 8-bit small page ROM"
+
+config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE
+ depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+ bool "Local bus NAND Flash- 8-bit large page ROM"
+
+endchoice
+
+if MPC83XX_TSEC1_SUPPORT
+
+choice
+ prompt "TSEC1 mode"
+
+config TSEC1_MODE_MII
+ depends on !ARCH_MPC8349
+ bool "MII"
+
+config TSEC1_MODE_RMII
+ depends on ARCH_MPC831X && !ARCH_MPC8349
+ bool "RMII"
+
+config TSEC1_MODE_RGMII
+ bool "RGMII"
+
+config TSEC1_MODE_RTBI
+ depends on ARCH_MPC831X || ARCH_MPC837X
+ bool "RTBI"
+
+config TSEC1_MODE_GMII
+ depends on ARCH_MPC8349
+ bool "GMII"
+
+config TSEC1_MODE_TBI
+ depends on ARCH_MPC8349
+ bool "TBI"
+
+config TSEC1_MODE_SGMII
+ depends on ARCH_MPC831X || ARCH_MPC837X
+ bool "SGMII"
+
+endchoice
+
+endif
+
+if MPC83XX_TSEC2_SUPPORT
+
+choice
+ prompt "TSEC2 mode"
+
+config TSEC2_MODE_MII
+ depends on !ARCH_MPC8349
+ bool "MII"
+
+config TSEC2_MODE_RMII
+ depends on ARCH_MPC831X && !ARCH_MPC8349
+ bool "RMII"
+
+config TSEC2_MODE_RGMII
+ bool "RGMII"
+
+config TSEC2_MODE_RTBI
+ depends on ARCH_MPC831X || ARCH_MPC837X
+ bool "RTBI"
+
+config TSEC2_MODE_GMII
+ depends on ARCH_MPC8349
+ bool "GMII"
+
+config TSEC2_MODE_TBI
+ depends on ARCH_MPC8349
+ bool "TBI"
+
+config TSEC2_MODE_SGMII
+ depends on ARCH_MPC831X || ARCH_MPC837X
+ bool "SGMII"
+
+endchoice
+
+endif
+
+choice
+ prompt "True litle-endian mode"
+
+config TRUE_LITTLE_ENDIAN_BIG_ENDIAN
+ bool "Big-endian"
+
+config TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN
+ bool "Little-endian"
+
+endchoice
+
+if ARCH_MPC8360
+
+choice
+ prompt "Secondary DDR IO"
+
+config SECONDARY_DDR_IO_DISABLE
+ bool "Disable"
+
+config SECONDARY_DDR_IO_ENABLE
+ bool "Enable"
+
+endchoice
+
+endif
+
+if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8349 || ARCH_MPC8360
+
+choice
+ prompt "LALE timing"
+
+config LALE_TIMING_NORMAL
+ bool "Normal"
+
+config LALE_TIMING_EARLIER
+ bool "Earlier"
+
+endchoice
+
+endif
+
+if MPC83XX_LDP_PIN
+
+choice
+ prompt "LDP pin mux state"
+
+config LDP_PIN_MUX_STATE_1
+ bool "Inital value 1"
+
+config LDP_PIN_MUX_STATE_0
+ bool "Inital value 0"
+
+endchoice
+
+endif
+
+endmenu
+
+config LBMC_CLOCK_MODE
+ int
+ default 0 if LBMC_CLOCK_MODE_1_1
+ default 1 if LBMC_CLOCK_MODE_1_2
+
+config DDR_MC_CLOCK_MODE
+ int
+ default 1 if DDR_MC_CLOCK_MODE_1_2
+ default 0 if DDR_MC_CLOCK_MODE_1_1
+
+config SYSTEM_PLL_VCO_DIV
+ int
+ default 0 if ARCH_MPC8349 || ARCH_MPC832X
+ default 2 if ARCH_MPC8313
+ default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X
+ default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X
+ default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360 && !ARCH_MPC837X
+ default 0 if SYSTEM_PLL_VCO_DIV_4 && (ARCH_MPC8360 || ARCH_MPC837X)
+ default 1 if SYSTEM_PLL_VCO_DIV_8 && (ARCH_MPC8360 || ARCH_MPC837X)
+ default 2 if SYSTEM_PLL_VCO_DIV_2 && (ARCH_MPC8360 || ARCH_MPC837X)
+ default 3 if SYSTEM_PLL_VCO_DIV_1
+
+config SYSTEM_PLL_FACTOR
+ int
+ default 2 if SYSTEM_PLL_FACTOR_2_1
+ default 3 if SYSTEM_PLL_FACTOR_3_1
+ default 4 if SYSTEM_PLL_FACTOR_4_1
+ default 5 if SYSTEM_PLL_FACTOR_5_1
+ default 6 if SYSTEM_PLL_FACTOR_6_1
+ default 7 if SYSTEM_PLL_FACTOR_7_1
+ default 8 if SYSTEM_PLL_FACTOR_8_1
+ default 9 if SYSTEM_PLL_FACTOR_9_1
+ default 10 if SYSTEM_PLL_FACTOR_10_1
+ default 11 if SYSTEM_PLL_FACTOR_11_1
+ default 12 if SYSTEM_PLL_FACTOR_12_1
+ default 13 if SYSTEM_PLL_FACTOR_13_1
+ default 14 if SYSTEM_PLL_FACTOR_14_1
+ default 15 if SYSTEM_PLL_FACTOR_15_1
+ default 0 if SYSTEM_PLL_FACTOR_16_1
+
+config CORE_PLL_RATIO
+ hex
+ default 0x0 if CORE_PLL_BYPASS
+ default 0x02 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_2
+ default 0x22 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_4
+ default 0x42 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_8
+ default 0x03 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_2
+ default 0x23 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_4
+ default 0x43 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_8
+ default 0x04 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_2
+ default 0x24 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_4
+ default 0x44 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_8
+ default 0x05 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_2
+ default 0x25 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_4
+ default 0x45 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_8
+ default 0x06 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_2
+ default 0x26 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_4
+ default 0x46 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_8
+
+config CORE_DISABLE_MODE
+ int
+ default 0 if CORE_DISABLE_MODE_OFF
+ default 1 if CORE_DISABLE_MODE_ON
+
+config BOOT_MEMORY_SPACE
+ int
+ default 0 if BOOT_MEMORY_SPACE_LOW
+ default 1 if BOOT_MEMORY_SPACE_HIGH
+
+config BOOT_SEQUENCER
+ int
+ default 0 if BOOT_SEQUENCER_DISABLED
+ default 1 if BOOT_SEQUENCER_NORMAL_I2C
+ default 2 if BOOT_SEQUENCER_EXTENDED_I2C
+
+config SOFTWARE_WATCHDOG
+ int
+ default 0 if SOFTWARE_WATCHDOG_DISABLED
+ default 1 if SOFTWARE_WATCHDOG_ENABLED
+
+config BOOT_ROM_INTERFACE
+ hex
+ default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM
+ default 0x4 if BOOT_ROM_INTERFACE_PCI1
+ default 0x8 if BOOT_ROM_INTERFACE_PCI2
+ default 0x8 if BOOT_ROM_INTERFACE_ESDHC
+ default 0xc if BOOT_ROM_INTERFACE_SPI
+ default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
+ default 0x14 if BOOT_ROM_INTERFACE_GPCM_8BIT
+ default 0x18 if BOOT_ROM_INTERFACE_GPCM_16BIT
+ default 0x1c if BOOT_ROM_INTERFACE_GPCM_32BIT
+ default 0x5 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
+ default 0x15 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE
+
+config TSEC1_MODE
+ hex
+ default 0x0 if !MPC83XX_TSEC1_SUPPORT
+ default 0x0 if TSEC1_MODE_MII
+ default 0x1 if TSEC1_MODE_RMII
+ default 0x3 if TSEC1_MODE_RGMII && !ARCH_MPC8349
+ default 0x5 if TSEC1_MODE_RTBI && !ARCH_MPC8349
+ default 0x6 if TSEC1_MODE_SGMII
+ default 0x0 if TSEC1_MODE_RGMII && ARCH_MPC8349
+ default 0x1 if TSEC1_MODE_RTBI && ARCH_MPC8349
+ default 0x2 if TSEC1_MODE_GMII
+ default 0x3 if TSEC1_MODE_TBI
+
+config TSEC2_MODE
+ hex
+ default 0x0 if !MPC83XX_TSEC2_SUPPORT
+ default 0x0 if TSEC2_MODE_MII
+ default 0x1 if TSEC2_MODE_RMII
+ default 0x3 if TSEC2_MODE_RGMII && !ARCH_MPC8349
+ default 0x5 if TSEC2_MODE_RTBI && !ARCH_MPC8349
+ default 0x6 if TSEC2_MODE_SGMII
+ default 0x0 if TSEC2_MODE_RGMII && ARCH_MPC8349
+ default 0x1 if TSEC2_MODE_RTBI && ARCH_MPC8349
+ default 0x2 if TSEC2_MODE_GMII
+ default 0x3 if TSEC2_MODE_TBI
+
+config SECONDARY_DDR_IO
+ int
+ default 0 if !ARCH_MPC8360
+ default 0 if SECONDARY_DDR_IO_DISABLE
+ default 1 if SECONDARY_DDR_IO_ENABLE
+
+config TRUE_LITTLE_ENDIAN
+ int
+ default 0 if TRUE_LITTLE_ENDIAN_BIG_ENDIAN
+ default 1 if TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN
+
+config LALE_TIMING
+ int
+ default 0 if ARCH_MPC830X || ARCH_MPC837X
+ default 0 if LALE_TIMING_NORMAL
+ default 1 if LALE_TIMING_EARLIER
+
+config LDP_PIN_MUX_STATE
+ int
+ default 0 if !MPC83XX_LDP_PIN
+ default 0 if LDP_PIN_MUX_STATE_1
+ default 1 if LDP_PIN_MUX_STATE_0
+
+config QUICC_VCO_DIVIDER
+ int
+ default 0 if !MPC83XX_QUICC_ENGINE
+ default 0 if QUICC_VCO_DIVIDER_2 && ARCH_MPC8309
+ default 1 if QUICC_VCO_DIVIDER_4 && ARCH_MPC8309
+ default 2 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8309
+ default 2 if QUICC_VCO_DIVIDER_2 && (ARCH_MPC832X || ARCH_MPC8360)
+ default 0 if QUICC_VCO_DIVIDER_4 && (ARCH_MPC832X || ARCH_MPC8360)
+ default 1 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8360
+
+config QUICC_DIV_FACTOR
+ int
+ default 0 if !MPC83XX_QUICC_ENGINE
+ default 0 if QUICC_DIV_FACTOR_1
+ default 1 if QUICC_DIV_FACTOR_2
+
+config QUICC_MULT_FACTOR
+ int
+ default 0 if !MPC83XX_QUICC_ENGINE
+ default 2 if QUICC_MULT_FACTOR_2
+ default 3 if QUICC_MULT_FACTOR_3
+ default 4 if QUICC_MULT_FACTOR_4
+ default 5 if QUICC_MULT_FACTOR_5
+ default 6 if QUICC_MULT_FACTOR_6
+ default 7 if QUICC_MULT_FACTOR_7
+ default 8 if QUICC_MULT_FACTOR_8
+ default 9 if QUICC_MULT_FACTOR_9
+ default 10 if QUICC_MULT_FACTOR_10
+ default 11 if QUICC_MULT_FACTOR_11
+ default 12 if QUICC_MULT_FACTOR_12
+ default 13 if QUICC_MULT_FACTOR_13
+ default 14 if QUICC_MULT_FACTOR_14
+ default 15 if QUICC_MULT_FACTOR_15
+ default 16 if QUICC_MULT_FACTOR_16
+ default 17 if QUICC_MULT_FACTOR_17
+ default 18 if QUICC_MULT_FACTOR_18
+ default 19 if QUICC_MULT_FACTOR_19
+ default 20 if QUICC_MULT_FACTOR_20
+ default 21 if QUICC_MULT_FACTOR_21
+ default 22 if QUICC_MULT_FACTOR_22
+ default 23 if QUICC_MULT_FACTOR_23
+ default 24 if QUICC_MULT_FACTOR_24
+ default 25 if QUICC_MULT_FACTOR_25
+ default 26 if QUICC_MULT_FACTOR_26
+ default 27 if QUICC_MULT_FACTOR_27
+ default 28 if QUICC_MULT_FACTOR_28
+ default 29 if QUICC_MULT_FACTOR_29
+ default 30 if QUICC_MULT_FACTOR_30
+ default 31 if QUICC_MULT_FACTOR_31
+
+config PCI_HOST_MODE
+ int
+ default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308
+ default 0 if PCI_HOST_MODE_DISABLE
+ default 1 if PCI_HOST_MODE_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless
+
+config PCI_64BIT_MODE
+ int
+ default 0 if !ARCH_MPC8349
+ default 0 if PCI_64BIT_MODE_DISABLE
+ default 1 if PCI_64BIT_MODE_ENABLE
+
+config PCI_INT_ARBITER1
+ int
+ default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308
+ default 0 if PCI_INT_ARBITER1_DISABLE
+ default 1 if PCI_INT_ARBITER1_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless
+
+config PCI_INT_ARBITER2
+ int
+ default 0 if !ARCH_MPC8349
+ default 0 if PCI_INT_ARBITER2_DISABLE
+ default 1 if PCI_INT_ARBITER2_ENABLE
+
+config PCI_CLOCK_OUTPUT_DRIVE
+ int
+ default 0 if !ARCH_MPC8360
+ default 0 if PCI_CLOCK_OUTPUT_DRIVE_DISABLE
+ default 1 if PCI_CLOCK_OUTPUT_DRIVE_ENABLE
diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h b/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h
new file mode 100644
index 0000000..7d66ba7
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h
@@ -0,0 +1,37 @@
+#ifdef CONFIG_ARCH_MPC8349
+#define TSEC1_MODE_SHIFT 17
+#define TSEC2_MODE_SHIFT 19
+#else
+#define TSEC1_MODE_SHIFT 18
+#define TSEC2_MODE_SHIFT 21
+#endif
+
+#define CONFIG_SYS_HRCW_LOW (\
+ (CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\
+ (CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\
+ (CONFIG_SYSTEM_PLL_VCO_DIV << (31 - 3)) |\
+ (CONFIG_SYSTEM_PLL_FACTOR << (31 - 7)) |\
+ (CONFIG_CORE_PLL_RATIO << (31 - 15)) |\
+ (CONFIG_QUICC_VCO_DIVIDER << (31 - 25)) |\
+ (CONFIG_QUICC_DIV_FACTOR << (31 - 26)) |\
+ (CONFIG_QUICC_MULT_FACTOR << (31 - 31)) \
+ )
+
+#define CONFIG_SYS_HRCW_HIGH (\
+ (CONFIG_PCI_HOST_MODE << (31 - 0)) |\
+ (CONFIG_PCI_64BIT_MODE << (31 - 1)) |\
+ (CONFIG_PCI_INT_ARBITER1 << (31 - 2)) |\
+ (CONFIG_PCI_INT_ARBITER2 << (31 - 3)) |\
+ (CONFIG_PCI_CLOCK_OUTPUT_DRIVE << (31 - 3)) |\
+ (CONFIG_CORE_DISABLE_MODE << (31 - 4)) |\
+ (CONFIG_BOOT_MEMORY_SPACE << (31 - 5)) |\
+ (CONFIG_BOOT_SEQUENCER << (31 - 7)) |\
+ (CONFIG_SOFTWARE_WATCHDOG << (31 - 8)) |\
+ (CONFIG_BOOT_ROM_INTERFACE << (31 - 13)) |\
+ (CONFIG_TSEC1_MODE << (31 - TSEC1_MODE_SHIFT)) |\
+ (CONFIG_TSEC2_MODE << (31 - TSEC2_MODE_SHIFT)) |\
+ (CONFIG_SECONDARY_DDR_IO << (31 - 27)) |\
+ (CONFIG_TRUE_LITTLE_ENDIAN << (31 - 28)) |\
+ (CONFIG_LALE_TIMING << (31 - 29)) |\
+ (CONFIG_LDP_PIN_MUX_STATE << (31 - 30)) \
+ )
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig
new file mode 100644
index 0000000..a6b42a2
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig
@@ -0,0 +1,6 @@
+menu "Initial register configuration"
+
+source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr"
+source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr"
+
+endmenu
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
new file mode 100644
index 0000000..e6b6130
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
@@ -0,0 +1,139 @@
+menu "LCRR - Clock Ratio Register register"
+
+if !ARCH_MPC8309 && !ARCH_MPC831X && !ARCH_MPC832X
+
+choice
+ prompt "DLL bypass"
+
+config LCRR_DBYP_UNSET
+ bool "Don't set value"
+
+config LCRR_DBYP_PLL_ENABLED
+ bool "PLL enabled"
+
+config LCRR_DBYP_PLL_BYPASSED
+ bool "PLL bypassed"
+
+endchoice
+
+endif
+
+if ARCH_MPC834X || ARCH_MPC8360
+
+choice
+ prompt "Additional delay cycles for SDRAM control signals"
+
+config LCRR_BUFCMDC_UNSET
+ bool "Don't set value"
+
+config LCRR_BUFCMDC_4
+ bool "4"
+
+config LCRR_BUFCMDC_1
+ bool "1"
+
+config LCRR_BUFCMDC_2
+ bool "2"
+
+config LCRR_BUFCMDC_3
+ bool "3"
+
+endchoice
+
+choice
+ prompt "Extended CAS latency"
+
+config LCRR_ECL_UNSET
+ bool "Don't set value"
+
+config LCRR_ECL_4
+ bool "4"
+
+config LCRR_ECL_5
+ bool "5"
+
+config LCRR_ECL_6
+ bool "6"
+
+config LCRR_ECL_7
+ bool "7"
+
+endchoice
+
+endif # ARCH_MPC834X || ARCH_MPC8360
+
+if !ARCH_MPC8308
+
+choice
+ prompt "External address delay cycles"
+
+config LCRR_EADC_UNSET
+ bool "Don't set value"
+
+config LCRR_EADC_4
+ bool "4"
+
+config LCRR_EADC_1
+ bool "1"
+
+config LCRR_EADC_2
+ bool "2"
+
+config LCRR_EADC_3
+ bool "3"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+choice
+ prompt "System clock divider"
+
+config LCRR_CLKDIV_UNSET
+ bool "Don't set value"
+
+config LCRR_CLKDIV_2
+ bool "2"
+
+config LCRR_CLKDIV_4
+ bool "4"
+
+config LCRR_CLKDIV_8
+ bool "8"
+
+endchoice
+
+config LCRR_DBYP
+ hex
+ default 0x0 if LCRR_DBYP_UNSET || LCRR_DBYP_PLL_ENABLED
+ default 0x80000000 if LCRR_DBYP_PLL_BYPASSED
+
+config LCRR_BUFCMDC
+ hex
+ default 0x0 if LCRR_BUFCMDC_4 || LCRR_BUFCMDC_UNSET
+ default 0x10000000 if LCRR_BUFCMDC_1
+ default 0x20000000 if LCRR_BUFCMDC_2
+ default 0x30000000 if LCRR_BUFCMDC_3
+
+config LCRR_ECL
+ hex
+ default 0x0 if LCRR_ECL_4 || LCRR_ECL_UNSET
+ default 0x1000000 if LCRR_ECL_5
+ default 0x2000000 if LCRR_ECL_6
+ default 0x3000000 if LCRR_ECL_7
+
+config LCRR_EADC
+ hex
+ default 0x0 if LCRR_EADC_4 || LCRR_EADC_UNSET
+ default 0x10000 if LCRR_EADC_1
+ default 0x20000 if LCRR_EADC_2
+ default 0x30000 if LCRR_EADC_3
+
+config LCRR_CLKDIV
+ hex
+ default 0x0 if LCRR_CLKDIV_UNSET
+ default 0x2 if LCRR_CLKDIV_2
+ default 0x4 if LCRR_CLKDIV_4
+ default 0x8 if LCRR_CLKDIV_8
+
+endmenu
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr
new file mode 100644
index 0000000..f32309e
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr
@@ -0,0 +1,115 @@
+menu "SPCR - System priority and configuration register"
+
+choice
+ prompt "Optimize"
+
+config SPCR_OPT_UNSET
+ bool "Don't set value"
+
+config SPCR_OPT_NONE
+ bool "No performance enhancement"
+
+config SPCR_OPT_SPEC_READ
+ bool "Performance enhancement by speculative read"
+
+endchoice
+
+if ARCH_MPC8308 || ARCH_MPC831X || ARCH_MPC837X
+
+choice
+ prompt "TSEC emergency priority"
+
+config SPCR_TSECEP_UNSET
+ bool "Don't set value"
+
+config SPCR_TSECEP_0
+ bool "Level 0 (lowest priority)"
+
+config SPCR_TSECEP_1
+ bool "Level 1"
+
+config SPCR_TSECEP_2
+ bool "Level 2"
+
+config SPCR_TSECEP_3
+ bool "Level 3 (highest priority)"
+
+endchoice
+
+endif
+
+if ARCH_MPC8349
+
+choice
+ prompt "TSEC1 emergency priority"
+
+config SPCR_TSEC1EP_UNSET
+ bool "Don't set value"
+
+config SPCR_TSEC1EP_0
+ bool "Level 0 (lowest priority)"
+
+config SPCR_TSEC1EP_1
+ bool "Level 1"
+
+config SPCR_TSEC1EP_2
+ bool "Level 2"
+
+config SPCR_TSEC1EP_3
+ bool "Level 3 (highest priority)"
+
+endchoice
+
+choice
+ prompt "TSEC2 emergency priority"
+
+config SPCR_TSEC2EP_UNSET
+ bool "Don't set value"
+
+config SPCR_TSEC2EP_0
+ bool "Level 0 (lowest priority)"
+
+config SPCR_TSEC2EP_1
+ bool "Level 1"
+
+config SPCR_TSEC2EP_2
+ bool "Level 2"
+
+config SPCR_TSEC2EP_3
+ bool "Level 3 (highest priority)"
+
+endchoice
+
+endif
+
+config SPCR_OPT
+ hex
+ default 0x0 if SPCR_OPT_UNSET
+ default 0x0 if SPCR_OPT_NONE
+ default 0x800000 if SPCR_OPT_SPEC_READ
+
+config SPCR_TSECEP
+ hex
+ default 0x0 if SPCR_TSECEP_UNSET
+ default 0x0 if SPCR_TSECEP_0
+ default 0x100 if SPCR_TSECEP_1
+ default 0x200 if SPCR_TSECEP_2
+ default 0x300 if SPCR_TSECEP_3
+
+config SPCR_TSEC1EP
+ hex
+ default 0x0 if SPCR_TSEC1EP_UNSET
+ default 0x0 if SPCR_TSEC1EP_0
+ default 0x100 if SPCR_TSEC1EP_1
+ default 0x200 if SPCR_TSEC1EP_2
+ default 0x300 if SPCR_TSEC1EP_3
+
+config SPCR_TSEC2EP
+ hex
+ default 0x0 if SPCR_TSEC2EP_UNSET
+ default 0x0 if SPCR_TSEC2EP_0
+ default 0x1 if SPCR_TSEC2EP_1
+ default 0x2 if SPCR_TSEC2EP_2
+ default 0x3 if SPCR_TSEC2EP_3
+
+endmenu
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/initreg.h b/arch/powerpc/cpu/mpc83xx/initreg/initreg.h
new file mode 100644
index 0000000..63aa5c9
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/initreg/initreg.h
@@ -0,0 +1,79 @@
+#define SPCR_PCIHPE_MASK 0x10000000
+#define SPCR_PCIPR_MASK 0x03000000
+#define SPCR_OPT_MASK 0x00800000
+#define SPCR_TBEN_MASK 0x00400000
+#define SPCR_COREPR_MASK 0x00300000
+#define SPCR_TSEC1DP_MASK 0x00003000
+#define SPCR_TSEC1BDP_MASK 0x00000C00
+#define SPCR_TSEC1EP_MASK 0x00000300
+#define SPCR_TSEC2DP_MASK 0x00000030
+#define SPCR_TSEC2BDP_MASK 0x0000000C
+#define SPCR_TSEC2EP_MASK 0x00000003
+#define SPCR_TSECDP_MASK 0x00003000
+#define SPCR_TSECBDP_MASK 0x00000C00
+#define SPCR_TSECEP_MASK 0x00000300
+
+ const __be32 spcr_mask =
+#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET)
+ SPCR_OPT_MASK |
+#endif
+#if defined(CONFIG_SPCR_TSECEP) && !defined(CONFIG_SPCR_TSECEP_UNSET)
+ SPCR_TSECEP_MASK |
+#endif
+#if defined(CONFIG_SPCR_TSEC1EP) && !defined(CONFIG_SPCR_TSEC1EP_UNSET)
+ SPCR_TSEC1EP_MASK |
+#endif
+#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET)
+ SPCR_TSEC2EP_MASK |
+#endif
+ 0;
+ const __be32 spcr_val =
+#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET)
+ CONFIG_SPCR_OPT |
+#endif
+#if defined(CONFIG_SPCR_TSECEP) && !defined(CONFIG_SPCR_TSECEP_UNSET)
+ CONFIG_SPCR_TSECEP |
+#endif
+#if defined(CONFIG_SPCR_TSEC1EP) && !defined(CONFIG_SPCR_TSEC1EP_UNSET)
+ CONFIG_SPCR_TSEC1EP |
+#endif
+#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET)
+ CONFIG_SPCR_TSEC2EP |
+#endif
+ 0;
+
+ const __be32 lcrr_mask =
+#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET)
+ LCRR_DBYP |
+#endif
+#if defined(CONFIG_LCRR_BUFCMDC) && !defined(CONFIG_LCRR_BUFCMDC_UNSET)
+ LCRR_BUFCMDC |
+#endif
+#if defined(CONFIG_LCRR_ECL) && !defined(CONFIG_LCRR_ECL_UNSET)
+ LCRR_ECL |
+#endif
+#if defined(CONFIG_LCRR_EADC) && !defined(CONFIG_LCRR_EADC_UNSET)
+ LCRR_EADC |
+#endif
+#if defined(CONFIG_LCRR_CLKDIV) && !defined(CONFIG_LCRR_CLKDIV_UNSET)
+ LCRR_CLKDIV |
+#endif
+ 0;
+
+ const __be32 lcrr_val =
+#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET)
+ CONFIG_LCRR_DBYP |
+#endif
+#if defined(CONFIG_LCRR_BUFCMDC) && !defined(CONFIG_LCRR_BUFCMDC_UNSET)
+ CONFIG_LCRR_BUFCMDC |
+#endif
+#if defined(CONFIG_LCRR_ECL) && !defined(CONFIG_LCRR_ECL_UNSET)
+ CONFIG_LCRR_ECL |
+#endif
+#if defined(CONFIG_LCRR_EADC) && !defined(CONFIG_LCRR_EADC_UNSET)
+ CONFIG_LCRR_EADC |
+#endif
+#if defined(CONFIG_LCRR_CLKDIV) && !defined(CONFIG_LCRR_CLKDIV_UNSET)
+ CONFIG_LCRR_CLKDIV |
+#endif
+ 0;
diff --git a/arch/powerpc/cpu/mpc83xx/lblaw/Kconfig b/arch/powerpc/cpu/mpc83xx/lblaw/Kconfig
new file mode 100644
index 0000000..b20f68b
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/lblaw/Kconfig
@@ -0,0 +1,519 @@
+menu "LBLAW setup"
+
+choice
+ prompt "NAND LAWBAR for NAND SPL"
+
+config NAND_LBLAWBAR_PRELIM_NONE
+ bool "None"
+
+config NAND_LBLAWBAR_PRELIM_0
+ bool "0"
+ depends on LBLAW0
+
+config NAND_LBLAWBAR_PRELIM_1
+ bool "1"
+ depends on LBLAW1
+
+config NAND_LBLAWBAR_PRELIM_2
+ bool "2"
+ depends on LBLAW2
+
+config NAND_LBLAWBAR_PRELIM_3
+ bool "3"
+ depends on LBLAW3
+
+endchoice
+
+menuconfig LBLAW0
+ bool "LBLAW0"
+
+if LBLAW0
+
+config LBLAW0_ENABLE
+ bool "Window enable"
+ default "y"
+
+if !LBLAW0_ENABLE
+
+config LBLAW0_BASE
+ hex
+ default 0x0
+
+endif
+
+if LBLAW0_ENABLE
+
+config LBLAW0_NAME
+ string "Identifier"
+
+config LBLAW0_BASE
+ hex "Window base"
+
+choice
+ prompt "Window size"
+
+config LBLAW0_LENGTH_4_KBYTES
+ bool "4 kb"
+
+config LBLAW0_LENGTH_8_KBYTES
+ bool "8 kb"
+
+config LBLAW0_LENGTH_16_KBYTES
+ bool "16 kb"
+
+config LBLAW0_LENGTH_32_KBYTES
+ bool "32 kb"
+
+config LBLAW0_LENGTH_64_KBYTES
+ bool "64 kb"
+
+config LBLAW0_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config LBLAW0_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config LBLAW0_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config LBLAW0_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config LBLAW0_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config LBLAW0_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config LBLAW0_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config LBLAW0_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config LBLAW0_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config LBLAW0_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config LBLAW0_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config LBLAW0_LENGTH_256_MBYTES
+ bool "256 mb"
+
+config LBLAW0_LENGTH_512_MBYTES
+ bool "512 mb"
+
+config LBLAW0_LENGTH_1_GBYTES
+ bool "1 gb"
+
+config LBLAW0_LENGTH_2_GBYTES
+ bool "2 gb"
+
+endchoice
+
+endif # LBLAW0_ENABLE
+
+endif # LBLAW0
+
+config LBLAW0_ENABLE_BIT
+ hex
+ default 0x0 if !LBLAW0_ENABLE
+ default 0x80000000 if LBLAW0_ENABLE
+
+config LBLAW0_LENGTH
+ hex
+ default 0x0 if !LBLAW0_ENABLE
+ default 0x0000000B if LBLAW0_LENGTH_4_KBYTES
+ default 0x0000000C if LBLAW0_LENGTH_8_KBYTES
+ default 0x0000000D if LBLAW0_LENGTH_16_KBYTES
+ default 0x0000000E if LBLAW0_LENGTH_32_KBYTES
+ default 0x0000000F if LBLAW0_LENGTH_64_KBYTES
+ default 0x00000010 if LBLAW0_LENGTH_128_KBYTES
+ default 0x00000011 if LBLAW0_LENGTH_256_KBYTES
+ default 0x00000012 if LBLAW0_LENGTH_512_KBYTES
+ default 0x00000013 if LBLAW0_LENGTH_1_MBYTES
+ default 0x00000014 if LBLAW0_LENGTH_2_MBYTES
+ default 0x00000015 if LBLAW0_LENGTH_4_MBYTES
+ default 0x00000016 if LBLAW0_LENGTH_8_MBYTES
+ default 0x00000017 if LBLAW0_LENGTH_16_MBYTES
+ default 0x00000018 if LBLAW0_LENGTH_32_MBYTES
+ default 0x00000019 if LBLAW0_LENGTH_64_MBYTES
+ default 0x0000001A if LBLAW0_LENGTH_128_MBYTES
+ default 0x0000001B if LBLAW0_LENGTH_256_MBYTES
+ default 0x0000001C if LBLAW0_LENGTH_512_MBYTES
+ default 0x0000001D if LBLAW0_LENGTH_1_GBYTES
+ default 0x0000001E if LBLAW0_LENGTH_2_GBYTES
+
+menuconfig LBLAW1
+ bool "LBLAW1"
+
+if LBLAW1
+
+config LBLAW1_ENABLE
+ bool "Window enable"
+ default "y"
+
+if !LBLAW1_ENABLE
+
+config LBLAW1_BASE
+ hex
+ default 0x0
+
+endif
+
+if LBLAW1_ENABLE
+
+config LBLAW1_NAME
+ string "Identifier"
+
+config LBLAW1_BASE
+ hex "Window base"
+
+choice
+ prompt "Window size"
+
+config LBLAW1_LENGTH_4_KBYTES
+ bool "4 kb"
+
+config LBLAW1_LENGTH_8_KBYTES
+ bool "8 kb"
+
+config LBLAW1_LENGTH_16_KBYTES
+ bool "16 kb"
+
+config LBLAW1_LENGTH_32_KBYTES
+ bool "32 kb"
+
+config LBLAW1_LENGTH_64_KBYTES
+ bool "64 kb"
+
+config LBLAW1_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config LBLAW1_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config LBLAW1_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config LBLAW1_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config LBLAW1_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config LBLAW1_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config LBLAW1_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config LBLAW1_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config LBLAW1_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config LBLAW1_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config LBLAW1_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config LBLAW1_LENGTH_256_MBYTES
+ bool "256 mb"
+
+config LBLAW1_LENGTH_512_MBYTES
+ bool "512 mb"
+
+config LBLAW1_LENGTH_1_GBYTES
+ bool "1 gb"
+
+config LBLAW1_LENGTH_2_GBYTES
+ bool "2 gb"
+
+endchoice
+
+endif # LBLAW1_ENABLE
+
+endif # LBLAW1
+
+config LBLAW1_ENABLE_BIT
+ hex
+ default 0x0 if !LBLAW1_ENABLE
+ default 0x80000000 if LBLAW1_ENABLE
+
+config LBLAW1_LENGTH
+ hex
+ default 0x0 if !LBLAW1_ENABLE
+ default 0x0000000B if LBLAW1_LENGTH_4_KBYTES
+ default 0x0000000C if LBLAW1_LENGTH_8_KBYTES
+ default 0x0000000D if LBLAW1_LENGTH_16_KBYTES
+ default 0x0000000E if LBLAW1_LENGTH_32_KBYTES
+ default 0x0000000F if LBLAW1_LENGTH_64_KBYTES
+ default 0x00000010 if LBLAW1_LENGTH_128_KBYTES
+ default 0x00000011 if LBLAW1_LENGTH_256_KBYTES
+ default 0x00000012 if LBLAW1_LENGTH_512_KBYTES
+ default 0x00000013 if LBLAW1_LENGTH_1_MBYTES
+ default 0x00000014 if LBLAW1_LENGTH_2_MBYTES
+ default 0x00000015 if LBLAW1_LENGTH_4_MBYTES
+ default 0x00000016 if LBLAW1_LENGTH_8_MBYTES
+ default 0x00000017 if LBLAW1_LENGTH_16_MBYTES
+ default 0x00000018 if LBLAW1_LENGTH_32_MBYTES
+ default 0x00000019 if LBLAW1_LENGTH_64_MBYTES
+ default 0x0000001A if LBLAW1_LENGTH_128_MBYTES
+ default 0x0000001B if LBLAW1_LENGTH_256_MBYTES
+ default 0x0000001C if LBLAW1_LENGTH_512_MBYTES
+ default 0x0000001D if LBLAW1_LENGTH_1_GBYTES
+ default 0x0000001E if LBLAW1_LENGTH_2_GBYTES
+
+menuconfig LBLAW2
+ bool "LBLAW2"
+
+if LBLAW2
+
+config LBLAW2_ENABLE
+ bool "Window enable"
+ default "y"
+
+if !LBLAW2_ENABLE
+
+config LBLAW2_BASE
+ hex
+ default 0x0
+
+endif
+
+if LBLAW2_ENABLE
+
+config LBLAW2_NAME
+ string "Identifier"
+
+config LBLAW2_BASE
+ hex "Window base"
+
+choice
+ prompt "Window size"
+
+config LBLAW2_LENGTH_4_KBYTES
+ bool "4 kb"
+
+config LBLAW2_LENGTH_8_KBYTES
+ bool "8 kb"
+
+config LBLAW2_LENGTH_16_KBYTES
+ bool "16 kb"
+
+config LBLAW2_LENGTH_32_KBYTES
+ bool "32 kb"
+
+config LBLAW2_LENGTH_64_KBYTES
+ bool "64 kb"
+
+config LBLAW2_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config LBLAW2_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config LBLAW2_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config LBLAW2_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config LBLAW2_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config LBLAW2_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config LBLAW2_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config LBLAW2_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config LBLAW2_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config LBLAW2_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config LBLAW2_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config LBLAW2_LENGTH_256_MBYTES
+ bool "256 mb"
+
+config LBLAW2_LENGTH_512_MBYTES
+ bool "512 mb"
+
+config LBLAW2_LENGTH_1_GBYTES
+ bool "1 gb"
+
+config LBLAW2_LENGTH_2_GBYTES
+ bool "2 gb"
+
+endchoice
+
+endif # LBLAW2_ENABLE
+
+endif # LBLAW2
+
+config LBLAW2_ENABLE_BIT
+ hex
+ default 0x0 if !LBLAW2_ENABLE
+ default 0x80000000 if LBLAW2_ENABLE
+
+config LBLAW2_LENGTH
+ hex
+ default 0x0 if !LBLAW2_ENABLE
+ default 0x0000000B if LBLAW2_LENGTH_4_KBYTES
+ default 0x0000000C if LBLAW2_LENGTH_8_KBYTES
+ default 0x0000000D if LBLAW2_LENGTH_16_KBYTES
+ default 0x0000000E if LBLAW2_LENGTH_32_KBYTES
+ default 0x0000000F if LBLAW2_LENGTH_64_KBYTES
+ default 0x00000010 if LBLAW2_LENGTH_128_KBYTES
+ default 0x00000011 if LBLAW2_LENGTH_256_KBYTES
+ default 0x00000012 if LBLAW2_LENGTH_512_KBYTES
+ default 0x00000013 if LBLAW2_LENGTH_1_MBYTES
+ default 0x00000014 if LBLAW2_LENGTH_2_MBYTES
+ default 0x00000015 if LBLAW2_LENGTH_4_MBYTES
+ default 0x00000016 if LBLAW2_LENGTH_8_MBYTES
+ default 0x00000017 if LBLAW2_LENGTH_16_MBYTES
+ default 0x00000018 if LBLAW2_LENGTH_32_MBYTES
+ default 0x00000019 if LBLAW2_LENGTH_64_MBYTES
+ default 0x0000001A if LBLAW2_LENGTH_128_MBYTES
+ default 0x0000001B if LBLAW2_LENGTH_256_MBYTES
+ default 0x0000001C if LBLAW2_LENGTH_512_MBYTES
+ default 0x0000001D if LBLAW2_LENGTH_1_GBYTES
+ default 0x0000001E if LBLAW2_LENGTH_2_GBYTES
+
+menuconfig LBLAW3
+ bool "LBLAW3"
+
+if LBLAW3
+
+config LBLAW3_ENABLE
+ bool "Window enable"
+ default "y"
+
+if !LBLAW3_ENABLE
+
+config LBLAW3_BASE
+ hex
+ default 0x0
+
+endif
+
+if LBLAW3_ENABLE
+
+config LBLAW3_NAME
+ string "Identifier"
+
+config LBLAW3_BASE
+ hex "Window base"
+
+choice
+ prompt "Window size"
+
+config LBLAW3_LENGTH_4_KBYTES
+ bool "4 kb"
+
+config LBLAW3_LENGTH_8_KBYTES
+ bool "8 kb"
+
+config LBLAW3_LENGTH_16_KBYTES
+ bool "16 kb"
+
+config LBLAW3_LENGTH_32_KBYTES
+ bool "32 kb"
+
+config LBLAW3_LENGTH_64_KBYTES
+ bool "64 kb"
+
+config LBLAW3_LENGTH_128_KBYTES
+ bool "128 kb"
+
+config LBLAW3_LENGTH_256_KBYTES
+ bool "256 kb"
+
+config LBLAW3_LENGTH_512_KBYTES
+ bool "512 kb"
+
+config LBLAW3_LENGTH_1_MBYTES
+ bool "1 mb"
+
+config LBLAW3_LENGTH_2_MBYTES
+ bool "2 mb"
+
+config LBLAW3_LENGTH_4_MBYTES
+ bool "4 mb"
+
+config LBLAW3_LENGTH_8_MBYTES
+ bool "8 mb"
+
+config LBLAW3_LENGTH_16_MBYTES
+ bool "16 mb"
+
+config LBLAW3_LENGTH_32_MBYTES
+ bool "32 mb"
+
+config LBLAW3_LENGTH_64_MBYTES
+ bool "64 mb"
+
+config LBLAW3_LENGTH_128_MBYTES
+ bool "128 mb"
+
+config LBLAW3_LENGTH_256_MBYTES
+ bool "256 mb"
+
+config LBLAW3_LENGTH_512_MBYTES
+ bool "512 mb"
+
+config LBLAW3_LENGTH_1_GBYTES
+ bool "1 gb"
+
+config LBLAW3_LENGTH_2_GBYTES
+ bool "2 gb"
+
+endchoice
+
+endif # LBLAW3_ENABLE
+
+endif # LBLAW3
+
+config LBLAW3_ENABLE_BIT
+ hex
+ default 0x0 if !LBLAW3_ENABLE
+ default 0x80000000 if LBLAW3_ENABLE
+
+config LBLAW3_LENGTH
+ hex
+ default 0x0 if !LBLAW3_ENABLE
+ default 0x0000000B if LBLAW3_LENGTH_4_KBYTES
+ default 0x0000000C if LBLAW3_LENGTH_8_KBYTES
+ default 0x0000000D if LBLAW3_LENGTH_16_KBYTES
+ default 0x0000000E if LBLAW3_LENGTH_32_KBYTES
+ default 0x0000000F if LBLAW3_LENGTH_64_KBYTES
+ default 0x00000010 if LBLAW3_LENGTH_128_KBYTES
+ default 0x00000011 if LBLAW3_LENGTH_256_KBYTES
+ default 0x00000012 if LBLAW3_LENGTH_512_KBYTES
+ default 0x00000013 if LBLAW3_LENGTH_1_MBYTES
+ default 0x00000014 if LBLAW3_LENGTH_2_MBYTES
+ default 0x00000015 if LBLAW3_LENGTH_4_MBYTES
+ default 0x00000016 if LBLAW3_LENGTH_8_MBYTES
+ default 0x00000017 if LBLAW3_LENGTH_16_MBYTES
+ default 0x00000018 if LBLAW3_LENGTH_32_MBYTES
+ default 0x00000019 if LBLAW3_LENGTH_64_MBYTES
+ default 0x0000001A if LBLAW3_LENGTH_128_MBYTES
+ default 0x0000001B if LBLAW3_LENGTH_256_MBYTES
+ default 0x0000001C if LBLAW3_LENGTH_512_MBYTES
+ default 0x0000001D if LBLAW3_LENGTH_1_GBYTES
+ default 0x0000001E if LBLAW3_LENGTH_2_GBYTES
+
+endmenu
diff --git a/arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h b/arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h
new file mode 100644
index 0000000..6972afc
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h
@@ -0,0 +1,55 @@
+#if defined(CONFIG_LBLAW0)
+#define CONFIG_SYS_LBLAWBAR0_PRELIM \
+ CONFIG_LBLAW0_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM (\
+ CONFIG_LBLAW0_ENABLE_BIT |\
+ CONFIG_LBLAW0_LENGTH \
+)
+#endif
+
+#if defined(CONFIG_LBLAW1)
+#define CONFIG_SYS_LBLAWBAR1_PRELIM \
+ CONFIG_LBLAW1_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM (\
+ CONFIG_LBLAW1_ENABLE_BIT |\
+ CONFIG_LBLAW1_LENGTH \
+)
+#endif
+
+#if defined(CONFIG_LBLAW2)
+#define CONFIG_SYS_LBLAWBAR2_PRELIM \
+ CONFIG_LBLAW2_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM (\
+ CONFIG_LBLAW2_ENABLE_BIT |\
+ CONFIG_LBLAW2_LENGTH \
+)
+#endif
+
+#if defined(CONFIG_LBLAW3)
+#define CONFIG_SYS_LBLAWBAR3_PRELIM \
+ CONFIG_LBLAW3_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM (\
+ CONFIG_LBLAW3_ENABLE_BIT |\
+ CONFIG_LBLAW3_LENGTH \
+)
+#endif
+
+#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_0
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
+#endif
+
+#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_1
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
+#endif
+
+#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_2
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR2_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR2_PRELIM
+#endif
+
+#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_3
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR3_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR3_PRELIM
+#endif
diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index d3f979f..b500ddd 100644
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -174,6 +174,41 @@
#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */
+int get_pcie_clk(int index)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 pci_sync_in;
+ u8 spmf;
+ u8 clkin_div;
+ u32 sccr;
+ u32 csb_clk;
+ u32 testval;
+
+ clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
+ sccr = im->clk.sccr;
+ pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
+ spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
+ csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
+
+ if (index)
+ testval = (sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT;
+ else
+ testval = (sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT;
+
+ switch (testval) {
+ case 0:
+ return 0;
+ case 1:
+ return csb_clk;
+ case 2:
+ return csb_clk / 2;
+ case 3:
+ return csb_clk / 3;
+ }
+
+ return 0;
+}
+
static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
{
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
@@ -269,11 +304,9 @@
/* Hose configure header is memory-mapped */
hose_cfg_base = (void *)pex;
- get_clocks();
/* Configure the PCIE controller core clock ratio */
out_le32(hose_cfg_base + PEX_GCLK_RATIO,
- (((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk)
- / 1000000) * 16) / 333);
+ ((get_pcie_clk(bus) / 1000000) * 16) / 333);
udelay(1000000);
/* Do Type 1 bridge configuration */
diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index 328a018..8b5ecdb 100644
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -31,7 +31,7 @@
printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
>> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
puts(", 16-bit");
else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
@@ -281,7 +281,7 @@
/*
* Set up LAWBAR for all of DDR.
*/
- ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
debug("DDR:bar=0x%08x\n", ecm->bar);
debug("DDR:ar=0x%08x\n", ecm->ar);
@@ -426,7 +426,7 @@
/*
* Errata DDR6 work around: input enable 2 cycles earlier.
- * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
+ * including MPC834X Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
*/
if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
if (caslat == 2)
@@ -436,7 +436,7 @@
else if (caslat == 4)
ddr->debug_reg = 0x202c0000; /* CL=3.0 */
- __asm__ __volatile__ ("sync");
+ sync();
debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
}
@@ -765,7 +765,8 @@
#endif
debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
- asm("sync;isync");
+ sync();
+ isync();
udelay(600);
@@ -834,7 +835,8 @@
#endif
/* Enable controller, and GO! */
ddr->sdram_cfg = sdram_cfg;
- asm("sync;isync");
+ sync();
+ isync();
udelay(500);
debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
@@ -843,6 +845,22 @@
#endif /* CONFIG_SPD_EEPROM */
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+static inline u32 mftbu(void)
+{
+ u32 rval;
+
+ asm volatile("mftbu %0" : "=r" (rval));
+ return rval;
+}
+
+static inline u32 mftb(void)
+{
+ u32 rval;
+
+ asm volatile("mftb %0" : "=r" (rval));
+ return rval;
+}
+
/*
* Use timebase counter, get_timer() is not available
* at this point of initialization yet.
@@ -858,9 +876,9 @@
/* get the timebase ticks */
do {
- asm volatile ("mftbu %0":"=r" (tbu1):);
- asm volatile ("mftb %0":"=r" (tbl):);
- asm volatile ("mftbu %0":"=r" (tbu2):);
+ tbu1 = mftbu();
+ tbl = mftb();
+ tbu2 = mftbu();
} while (tbu1 != tbu2);
/* convert ticks to ms */
@@ -897,7 +915,7 @@
for (p = 0; p < (u64*)(size); p++) {
ppcDWstore((u32*)p, pattern);
}
- __asm__ __volatile__ ("sync");
+ sync();
#endif
t_end = get_tbms();
@@ -922,8 +940,8 @@
/* Enable errors for ECC */
ddr->err_disable &= ECC_ERROR_ENABLE;
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
+ sync();
+ isync();
}
#endif /* CONFIG_DDR_ECC */
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index 39bc1c5..e118a10 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -85,35 +85,35 @@
u32 lcrr;
u32 csb_clk;
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
-#elif defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC8309)
u32 usbdr_clk;
#endif
-#ifdef CONFIG_MPC834x
+#ifdef CONFIG_ARCH_MPC834X
u32 usbmph_clk;
#endif
u32 core_clk;
u32 i2c1_clk;
-#if !defined(CONFIG_MPC832x)
+#if !defined(CONFIG_ARCH_MPC832X)
u32 i2c2_clk;
#endif
-#if defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC8315)
u32 tdm_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
#endif
-#if !defined(CONFIG_MPC8309)
+#if !defined(CONFIG_ARCH_MPC8309)
u32 enc_clk;
#endif
u32 lbiu_clk;
u32 lclk_clk;
u32 mem_clk;
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
u32 mem_sec_clk;
#endif
#if defined(CONFIG_QE)
@@ -122,12 +122,12 @@
u32 qe_clk;
u32 brg_clk;
#endif
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
u32 pciexp1_clk;
u32 pciexp2_clk;
#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
u32 sata_clk;
#endif
@@ -137,8 +137,8 @@
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
if (im->reset.rcwh & HRCWH_PCI_HOST) {
-#if defined(CONFIG_83XX_CLKIN)
- pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
+#if defined(CONFIG_SYS_CLK_FREQ)
+ pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
#else
pci_sync_in = 0xDEADBEEF;
#endif
@@ -155,8 +155,8 @@
sccr = im->clk.sccr;
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
case 0:
tsec1_clk = 0;
@@ -176,8 +176,8 @@
}
#endif
-#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
case 0:
usbdr_clk = 0;
@@ -197,8 +197,8 @@
}
#endif
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \
- defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
case 0:
tsec2_clk = 0;
@@ -216,7 +216,7 @@
/* unknown SCCR_TSEC2CM value */
return -4;
}
-#elif defined(CONFIG_MPC8313)
+#elif defined(CONFIG_ARCH_MPC8313)
tsec2_clk = tsec1_clk;
if (!(sccr & SCCR_TSEC1ON))
@@ -225,7 +225,7 @@
tsec2_clk = 0;
#endif
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
case 0:
usbmph_clk = 0;
@@ -252,7 +252,7 @@
return -6;
}
#endif
-#if !defined(CONFIG_MPC8309)
+#if !defined(CONFIG_ARCH_MPC8309)
switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
case 0:
enc_clk = 0;
@@ -291,7 +291,7 @@
return -8;
}
#endif
-#if defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC8315)
switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
case 0:
tdm_clk = 0;
@@ -311,27 +311,27 @@
}
#endif
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
i2c1_clk = tsec2_clk;
-#elif defined(CONFIG_MPC8360)
+#elif defined(CONFIG_ARCH_MPC8360)
i2c1_clk = csb_clk;
-#elif defined(CONFIG_MPC832x)
+#elif defined(CONFIG_ARCH_MPC832X)
i2c1_clk = enc_clk;
-#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
+#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
i2c1_clk = enc_clk;
#elif defined(CONFIG_FSL_ESDHC)
i2c1_clk = sdhc_clk;
-#elif defined(CONFIG_MPC837x)
+#elif defined(CONFIG_ARCH_MPC837X)
i2c1_clk = enc_clk;
-#elif defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC8309)
i2c1_clk = csb_clk;
#endif
-#if !defined(CONFIG_MPC832x)
+#if !defined(CONFIG_ARCH_MPC832X)
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
#endif
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
case 0:
pciexp1_clk = 0;
@@ -369,7 +369,7 @@
}
#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
case 0:
sata_clk = 0;
@@ -407,7 +407,7 @@
(1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
mem_sec_clk = csb_clk * (1 +
((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
#endif
@@ -448,18 +448,18 @@
#endif
gd->arch.csb_clk = csb_clk;
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
gd->arch.tsec1_clk = tsec1_clk;
gd->arch.tsec2_clk = tsec2_clk;
gd->arch.usbdr_clk = usbdr_clk;
-#elif defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC8309)
gd->arch.usbdr_clk = usbdr_clk;
#endif
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
gd->arch.usbmph_clk = usbmph_clk;
#endif
-#if defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC8315)
gd->arch.tdm_clk = tdm_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
@@ -467,28 +467,28 @@
#endif
gd->arch.core_clk = core_clk;
gd->arch.i2c1_clk = i2c1_clk;
-#if !defined(CONFIG_MPC832x)
+#if !defined(CONFIG_ARCH_MPC832X)
gd->arch.i2c2_clk = i2c2_clk;
#endif
-#if !defined(CONFIG_MPC8309)
+#if !defined(CONFIG_ARCH_MPC8309)
gd->arch.enc_clk = enc_clk;
#endif
gd->arch.lbiu_clk = lbiu_clk;
gd->arch.lclk_clk = lclk_clk;
gd->mem_clk = mem_clk;
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
gd->arch.mem_sec_clk = mem_sec_clk;
#endif
#if defined(CONFIG_QE)
gd->arch.qe_clk = qe_clk;
gd->arch.brg_clk = brg_clk;
#endif
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
gd->arch.pciexp1_clk = pciexp1_clk;
gd->arch.pciexp2_clk = pciexp2_clk;
#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
gd->arch.sata_clk = sata_clk;
#endif
gd->pci_clk = pci_sync_in;
@@ -516,6 +516,11 @@
return gd->mem_clk;
}
+int get_serial_clock(void)
+{
+ return get_bus_freq(0);
+}
+
static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char buf[32];
@@ -536,21 +541,21 @@
printf(" Local Bus: %-4s MHz\n",
strmhz(buf, gd->arch.lclk_clk));
printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
printf(" DDR Secondary: %-4s MHz\n",
strmhz(buf, gd->arch.mem_sec_clk));
#endif
-#if !defined(CONFIG_MPC8309)
+#if !defined(CONFIG_ARCH_MPC8309)
printf(" SEC: %-4s MHz\n",
strmhz(buf, gd->arch.enc_clk));
#endif
printf(" I2C1: %-4s MHz\n",
strmhz(buf, gd->arch.i2c1_clk));
-#if !defined(CONFIG_MPC832x)
+#if !defined(CONFIG_ARCH_MPC832X)
printf(" I2C2: %-4s MHz\n",
strmhz(buf, gd->arch.i2c2_clk));
#endif
-#if defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC8315)
printf(" TDM: %-4s MHz\n",
strmhz(buf, gd->arch.tdm_clk));
#endif
@@ -558,30 +563,30 @@
printf(" SDHC: %-4s MHz\n",
strmhz(buf, gd->arch.sdhc_clk));
#endif
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
printf(" TSEC1: %-4s MHz\n",
strmhz(buf, gd->arch.tsec1_clk));
printf(" TSEC2: %-4s MHz\n",
strmhz(buf, gd->arch.tsec2_clk));
printf(" USB DR: %-4s MHz\n",
strmhz(buf, gd->arch.usbdr_clk));
-#elif defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC8309)
printf(" USB DR: %-4s MHz\n",
strmhz(buf, gd->arch.usbdr_clk));
#endif
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
printf(" USB MPH: %-4s MHz\n",
strmhz(buf, gd->arch.usbmph_clk));
#endif
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
printf(" PCIEXP1: %-4s MHz\n",
strmhz(buf, gd->arch.pciexp1_clk));
printf(" PCIEXP2: %-4s MHz\n",
strmhz(buf, gd->arch.pciexp2_clk));
#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
printf(" SATA: %-4s MHz\n",
strmhz(buf, gd->arch.sata_clk));
#endif
diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
index 746f1fe..133f7ab 100644
--- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
@@ -6,6 +6,9 @@
#include <common.h>
#include <mpc83xx.h>
+#include "lblaw/lblaw.h"
+#include "elbc/elbc.h"
+
DECLARE_GLOBAL_DATA_PTR;
/*
@@ -24,16 +27,16 @@
/* system performance tweaking */
-#ifdef CONFIG_SYS_ACR_PIPE_DEP
+#ifndef CONFIG_ACR_PIPE_DEP_UNSET
/* Arbiter pipeline depth */
im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
- (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
+ CONFIG_ACR_PIPE_DEP;
#endif
-#ifdef CONFIG_SYS_ACR_RPTCNT
+#ifndef CONFIG_ACR_RPTCNT_UNSET
/* Arbiter repeat count */
im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
- (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
+ CONFIG_ACR_RPTCNT;
#endif
#ifdef CONFIG_SYS_SPCR_OPT
@@ -89,3 +92,11 @@
while (*str)
putc(*str++);
}
+
+ulong get_bus_freq(ulong dummy)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
+
+ return CONFIG_SYS_CLK_FREQ * spmf;
+}
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index c00bb31..f4a8a76 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -24,6 +24,10 @@
#include <asm/mmu.h>
#include <asm/u-boot.h>
+#include "hrcw/hrcw.h"
+#include "bats/bats.h"
+#include "hid/hid.h"
+
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
@@ -115,18 +119,6 @@
mtspr SRR1, r3
rfi
- .globl ppcDWstore
-ppcDWstore:
- lfd 1, 0(r4)
- stfd 1, 0(r3)
- blr
-
- .globl ppcDWload
-ppcDWload:
- lfd 1, 0(r3)
- stfd 1, 0(r4)
- blr
-
#ifndef CONFIG_DEFAULT_IMMR
#error CONFIG_DEFAULT_IMMR must be defined
#endif /* CONFIG_DEFAULT_IMMR */
diff --git a/arch/powerpc/cpu/mpc83xx/sysio/Kconfig b/arch/powerpc/cpu/mpc83xx/sysio/Kconfig
new file mode 100644
index 0000000..9e1f158
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/sysio/Kconfig
@@ -0,0 +1,7 @@
+menu "System I/O configuration"
+
+if ARCH_MPC8308
+source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308"
+endif
+
+endmenu
diff --git a/arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308 b/arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308
new file mode 100644
index 0000000..de62171
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308
@@ -0,0 +1,323 @@
+choice
+ prompt "SPI group"
+
+config SICR_SPI_SPI
+ bool "SPI"
+
+config SICR_SPI_MSRCID
+ bool "MSRCID"
+
+config SICR_SPI_LSRCID
+ bool "LSRCID"
+
+endchoice
+
+choice
+ prompt "UART group"
+
+config SICR_UART_SPI
+ bool "UART"
+
+config SICR_UART_MSRCID
+ bool "MSRCID"
+
+config SICR_UART_LSRCID
+ bool "LSRCID"
+
+endchoice
+
+choice
+ prompt "IRQ group"
+
+config SICR_IRQ_SPI
+ bool "IRQ"
+
+config SICR_IRQ_MCP_CKSTOP
+ bool "MCP/CKSTOP"
+
+config SICR_IRQ_INTA
+ bool "INTA"
+
+endchoice
+
+choice
+ prompt "I2C2 group"
+
+config SICR_I2C2_I2C
+ bool "IRQ"
+
+config SICR_I2C2_CKSTOP
+ bool "CKSTOP"
+
+endchoice
+
+choice
+ prompt "ETSEC1 A group"
+
+config SICR_ETSEC1_A_TSEC2
+ bool "TSEC1"
+
+config SICR_ETSEC1_A_TSEC_GTX_CLK125
+ bool "TSEC1 GTX_CLK125"
+
+endchoice
+
+choice
+ prompt "eSDHC A group"
+
+config SICR_ESDHC_A_SD
+ bool "SD"
+
+config SICR_ESDHC_A_GTM
+ bool "GTM"
+
+config SICR_ESDHC_A_GPIO
+ bool "GPIO"
+
+endchoice
+
+choice
+ prompt "eSDHC B group"
+
+config SICR_ESDHC_B_SD
+ bool "SD"
+
+config SICR_ESDHC_B_GTM
+ bool "GTM"
+
+config SICR_ESDHC_B_GPIO
+ bool "GPIO"
+
+endchoice
+
+choice
+ prompt "eSDHC C group"
+
+config SICR_ESDHC_C_SD
+ bool "SD"
+
+config SICR_ESDHC_C_GTM
+ bool "GTM"
+
+config SICR_ESDHC_C_GPIO
+ bool "GPIO"
+
+endchoice
+
+choice
+ prompt "GPIO A group"
+
+config SICR_GPIO_A_GPIO
+ bool "GPIO"
+
+config SICR_GPIO_A_TSEC2
+ bool "TSEC2"
+
+endchoice
+
+choice
+ prompt "GPIO B group"
+
+config SICR_GPIO_B_GPIO
+ bool "GPIO"
+
+config SICR_GPIO_B_TSEC2
+ bool "TSEC2"
+
+config SICR_GPIO_B_TSEC_GTX_CLK125
+ bool "TSEC2 GTX_CLK125"
+
+endchoice
+
+choice
+ prompt "IEEE1588 A group"
+
+config SICR_IEEE1588_A_TSEC
+ bool "TSEC"
+
+config SICR_IEEE1588_A_GPIO
+ bool "GPIO"
+
+endchoice
+
+choice
+ prompt "USB group"
+
+config SICR_USB_TSEC
+ bool "USB"
+
+endchoice
+
+choice
+ prompt "GTM group"
+
+config SICR_GTM_TSEC
+ bool "GTM"
+
+config SICR_GTM_GPIO
+ bool "GPIO"
+
+endchoice
+
+choice
+ prompt "IEEE1588 B group"
+
+config SICR_IEEE1588_B_GPIO
+ bool "GPIO"
+
+endchoice
+
+choice
+ prompt "ETSEC2 group"
+
+config SICR_ETSEC2_TSEC2
+ bool "TSEC2"
+
+config SICR_ETSEC2_GPIO
+ bool "GPIO"
+
+endchoice
+
+choice
+ prompt "GPIO selection"
+
+config SICR_GPIOSEL_GPIO
+ bool "GPIO_A, GPIO_B"
+
+config SICR_GPIOSEL_IEEE1588
+ bool "IEEE1588_A, IEEE1588_B, ETSEC2"
+
+endchoice
+
+choice
+ prompt "IEEE1588 timer output buffer impedance"
+
+config SICR_TMROBI_3_3_V
+ bool "40 Ohm, 3.3V"
+
+config SICR_TMROBI_2_5_V
+ bool "40 Ohm, 2.5V"
+
+endchoice
+
+choice
+ prompt "TSEC1 output buffer impedance"
+
+config SICR_TMSOBI1_3_3_V
+ bool "40 Ohm, 3.3V"
+
+config SICR_TMSOBI1_2_5_V
+ bool "40 Ohm, 2.5V"
+
+endchoice
+
+choice
+ prompt "TSEC2 output buffer impedance"
+
+config SICR_TMSOBI2_3_3_V
+ bool "40 Ohm, 3.3V"
+
+config SICR_TMSOBI2_2_5_V
+ bool "40 Ohm, 2.5V"
+
+endchoice
+
+config SICRL_SPI
+ hex
+ default 0x0 if SICR_SPI_SPI
+ default 0x10000000 if SICR_SPI_MSRCID
+ default 0x30000000 if SICR_SPI_LSRCID
+
+config SICRL_UART
+ hex
+ default 0x0 if SICR_UART_SPI
+ default 0x4000000 if SICR_UART_MSRCID
+ default 0xc000000 if SICR_UART_LSRCID
+
+config SICRL_IRQ
+ hex
+ default 0x0 if SICR_IRQ_SPI
+ default 0x1000000 if SICR_IRQ_MCP_CKSTOP
+ default 0x3000000 if SICR_IRQ_INTA
+
+config SICRL_I2C2
+ hex
+ default 0x0 if SICR_I2C2_I2C
+ default 0x100000 if SICR_I2C2_CKSTOP
+
+config SICRL_ETSEC1_A
+ hex
+ default 0x0 if SICR_ETSEC1_A_TSEC2
+ default 0x40 if SICR_ETSEC1_A_TSEC_GTX_CLK125
+
+config SICRH_ESDHC_A
+ hex
+ default 0x0 if SICR_ESDHC_A_SD
+ default 0x40000000 if SICR_ESDHC_A_GTM
+ default 0xc0000000 if SICR_ESDHC_A_GPIO
+
+config SICRH_ESDHC_B
+ hex
+ default 0x0 if SICR_ESDHC_B_SD
+ default 0x10000000 if SICR_ESDHC_B_GTM
+ default 0x30000000 if SICR_ESDHC_B_GPIO
+
+config SICRH_ESDHC_C
+ hex
+ default 0x0 if SICR_ESDHC_C_SD
+ default 0x4000000 if SICR_ESDHC_C_GTM
+ default 0xc000000 if SICR_ESDHC_C_GPIO
+
+config SICRH_GPIO_A
+ hex
+ default 0x0 if SICR_GPIO_A_GPIO
+ default 0x1000000 if SICR_GPIO_A_TSEC2
+
+config SICRH_GPIO_B
+ hex
+ default 0x0 if SICR_GPIO_B_GPIO
+ default 0x400000 if SICR_GPIO_B_TSEC2
+ default 0x800000 if SICR_GPIO_B_TSEC_GTX_CLK125
+
+config SICRH_IEEE1588_A
+ hex
+ default 0x100000 if SICR_IEEE1588_A_TSEC
+ default 0x300000 if SICR_IEEE1588_A_GPIO
+
+config SICRH_USB
+ hex
+ default 0x40000 if SICR_USB_TSEC
+
+config SICRH_GTM
+ hex
+ default 0x10000 if SICR_GTM_TSEC
+ default 0x30000 if SICR_GTM_GPIO
+
+config SICRH_IEEE1588_B
+ hex
+ default 0xc000 if SICR_IEEE1588_B_GPIO
+
+config SICRH_ETSEC2
+ hex
+ default 0x1000 if SICR_ETSEC2_TSEC2
+ default 0x3000 if SICR_ETSEC2_GPIO
+
+config SICRH_GPIOSEL
+ hex
+ default 0x0 if SICR_GPIOSEL_GPIO
+ default 0x100 if SICR_GPIOSEL_IEEE1588
+
+config SICRH_TMROBI
+ hex
+ default 0x0 if SICR_TMROBI_3_3_V
+ default 0x10 if SICR_TMROBI_2_5_V
+
+config SICRH_TMSOBI1
+ hex
+ default 0x0 if SICR_TMSOBI1_3_3_V
+ default 0x2 if SICR_TMSOBI1_2_5_V
+
+config SICRH_TMSOBI2
+ hex
+ default 0x0 if SICR_TMSOBI2_3_3_V
+ default 0x1 if SICR_TMSOBI2_2_5_V
diff --git a/arch/powerpc/cpu/mpc83xx/sysio/sysio.h b/arch/powerpc/cpu/mpc83xx/sysio/sysio.h
new file mode 100644
index 0000000..f8c2f10
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/sysio/sysio.h
@@ -0,0 +1,32 @@
+#ifdef CONFIG_ARCH_MPC8308
+
+#ifndef CONFIG_SYS_SICRL
+#define CONFIG_SYS_SICRL (\
+ CONFIG_SICRL_SPI |\
+ CONFIG_SICRL_UART |\
+ CONFIG_SICRL_IRQ |\
+ CONFIG_SICRL_I2C2 |\
+ CONFIG_SICRL_ETSEC1_A \
+)
+#endif
+
+#ifndef CONFIG_SYS_SICRH
+#define CONFIG_SYS_SICRH (\
+ CONFIG_SICRH_ESDHC_A |\
+ CONFIG_SICRH_ESDHC_B |\
+ CONFIG_SICRH_ESDHC_C |\
+ CONFIG_SICRH_GPIO_A |\
+ CONFIG_SICRH_GPIO_B |\
+ CONFIG_SICRH_IEEE1588_A |\
+ CONFIG_SICRH_USB |\
+ CONFIG_SICRH_GTM |\
+ CONFIG_SICRH_IEEE1588_B |\
+ CONFIG_SICRH_ETSEC2 |\
+ CONFIG_SICRH_GPIOSEL |\
+ CONFIG_SICRH_TMROBI |\
+ CONFIG_SICRH_TMSOBI1 |\
+ CONFIG_SICRH_TMSOBI2 \
+)
+#endif
+
+#endif
diff --git a/arch/powerpc/cpu/mpc83xx/u-boot.lds b/arch/powerpc/cpu/mpc83xx/u-boot.lds
index 37a13fd..d10f528 100644
--- a/arch/powerpc/cpu/mpc83xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc83xx/u-boot.lds
@@ -52,6 +52,12 @@
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
+ /*
+ * _end - This is end of u-boot.bin image.
+ * dtb will be appended here to make u-boot-dtb.bin
+ */
+ _end = .;
+
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
index 13545fc..c43732f 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
@@ -6,6 +6,10 @@
#include <common.h>
#include <asm/fsl_lbc.h>
+#ifdef CONFIG_MPC83xx
+#include "../mpc83xx/elbc/elbc.h"
+#endif
+
#ifdef CONFIG_MPC85xx
/* Boards should provide their own version of this if they use lbc sdram */
static void __lbc_sdram_init(void)
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
index 23cc5a3..d81af70 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
@@ -131,10 +131,10 @@
set_bf(ppaace->addr_bitfields, PAACE_AF_AP, PAACE_AP_PERMS_ALL);
}
- asm volatile("sync" : : : "memory");
+ sync();
/* Mark the ppace entry valid */
ppaace->addr_bitfields |= PAACE_V_VALID;
- asm volatile("sync" : : : "memory");
+ sync();
return 0;
}
@@ -279,7 +279,7 @@
out_be32(®s->splah, spaact_lim >> 32);
out_be32(®s->splal, (uint32_t)spaact_lim);
}
- asm volatile("sync" : : : "memory");
+ sync();
base_addr += PAMU_OFFSET;
}
@@ -294,7 +294,7 @@
for (i = 0; i < CONFIG_NUM_PAMU; i++) {
setbits_be32((void *)base_addr + PAMU_PCR_OFFSET,
PAMU_PCR_PE);
- asm volatile("sync" : : : "memory");
+ sync();
base_addr += PAMU_OFFSET;
}
}
@@ -318,7 +318,7 @@
out_be32(®s->splal, 0);
clrbits_be32((void *)regs + PAMU_PCR_OFFSET, PAMU_PCR_PE);
- asm volatile("sync" : : : "memory");
+ sync();
base_addr += PAMU_OFFSET;
}
}
@@ -331,7 +331,7 @@
for (i = 0; i < CONFIG_NUM_PAMU; i++) {
clrbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE);
- asm volatile("sync" : : : "memory");
+ sync();
base_addr += PAMU_OFFSET;
}
}
diff --git a/arch/powerpc/dts/.gitignore b/arch/powerpc/dts/.gitignore
new file mode 100644
index 0000000..b60ed20
--- /dev/null
+++ b/arch/powerpc/dts/.gitignore
@@ -0,0 +1 @@
+*.dtb
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index f080a96..6a28f80 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -2,6 +2,7 @@
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
+dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb
targets += $(dtb-y)
diff --git a/arch/powerpc/dts/gazerbeam.dts b/arch/powerpc/dts/gazerbeam.dts
new file mode 100644
index 0000000..96c03c7
--- /dev/null
+++ b/arch/powerpc/dts/gazerbeam.dts
@@ -0,0 +1,602 @@
+/*
+ * Gazerbeam CON Device Tree Source
+ *
+ * (C) Copyright 2015
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include "gdsys/mpc8308.dtsi"
+
+/include/ "gdsys/gazerbeam-base.dtsi"
+
+/include/ "gdsys/soc/i2c/cirrus-audio-codec.dtsi"
+/include/ "gdsys/soc/i2c/dallas-rtc.dtsi"
+/include/ "gdsys/soc/lbc/gazerbeam.dtsi"
+/include/ "gdsys/soc/nor/flash-80k-partition.dtsi"
+
+&board_lbc {
+ FPGA0:iocon_uart@1,0 {
+ reg = <0x1 0x0 0x100000>;
+ little-endian;
+ interrupts = <48 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
+ FPGA1:iocon_uart@2,0 {
+ reg = <0x2 0x0 0x100000>;
+ little-endian;
+ interrupts = <17 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+};
+
+&FPGA0 {
+ compatible = "gdsys,iocon_fpga";
+ #gpio-cells = <2>;
+ gpio-controller;
+ bus = <&FPGA0BUS>;
+ unit_id = <0>;
+ fpga-type = <1>;
+ usb_base = <0x0080>;
+ audio_base = <0x0040>;
+ timebase_base = <0x013c>;
+
+ /*
+ * for every interrupt source there must be a dataset specifying
+ * 1. type (1: standard)
+ * 2. status register offset
+ * 3. mask register offset
+ * 4. default mask
+ */
+ fpga_interrupt_sources =
+ <1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */
+ <1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */
+ /*
+ * for every interrupt there must be a dataset specifying
+ * 1. type (1: status, 2: event)
+ * 2. interrupt source index
+ * 3. interrupt register bit
+ * 4. mask register bit
+ */
+ #fpga_interrupt_map-cells = <4>;
+ fpga_interrupt_map =
+ <1 0 14 14>, /* 0: EXTENDED_INTERRUPT */
+ <1 0 0 0>, /* 1: VIDEO 0 */
+ <1 0 1 1>, /* 2: VIDEO 1 */
+ <1 0 2 2>, /* 3: VIDEO IC 0 */
+ <1 0 3 3>, /* 4: VIDEO IC 1 */
+ <1 0 4 4>, /* 5: IIC MAIN */
+ <1 0 6 6>, /* 6: IIC VIDEO 0 */
+ <1 0 7 7>, /* 7: IIC VIDEO 1 */
+ <1 1 0 0>, /* 8: OSD 0 */
+ <1 1 1 1>, /* 9: OSD 1 */
+ <1 1 2 2>, /* 10: SPDIF 0 */
+ <1 1 3 3>, /* 11: SPDIF 1 */
+ <1 0 12 12>, /* 12: COMM 0 */
+ <1 0 13 13>, /* 13: COMM 1 */
+ <1 0 10 10>, /* 14: COMM 2 */
+ <1 0 11 11>, /* 15: COMM 3 */
+ <2 0 5 5>, /* 16: MDIO */
+ <1 0 8 8>, /* 17: PHY */
+ <1 1 4 4>, /* 18: RS232 */
+ <1 1 5 5>, /* 19: AUDIO */
+ <1 1 8 8>, /* 20: PROC_AUDIO */
+ <1 1 7 7>, /* 21: USB/ETH-UART INT */
+ <2 1 10 10>, /* 22: AXI Bridge 0 */
+ <2 1 11 11>, /* 23: AXI Bridge 1 */
+ <2 1 9 9>, /* 24: USB/ETH-Secondary IIC */
+ <>;
+};
+
+&FPGA1 {
+ compatible = "gdsys,iocon_fpga";
+ #gpio-cells = <2>;
+ gpio-controller;
+ bus = <&FPGA1BUS>;
+ unit_id = <1>;
+ fpga-type = <1>;
+ usb_base = <0x0070>;
+ audio_base = <0x0040>;
+ timebase_base = <0x013c>;
+
+ /*
+ * for every interrupt source there must be a dataset specifying
+ * 1. type (1: standard)
+ * 2. status register offset
+ * 3. mask register offset
+ * 4. default mask
+ */
+ fpga_interrupt_sources =
+ <1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */
+ <1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */
+ /*
+ * for every interrupt there must be a dataset specifying
+ * 1. type (1: status, 2: event)
+ * 2. interrupt source index
+ * 3. interrupt register bit
+ * 4. mask register bit
+ */
+ #fpga_interrupt_map-cells = <4>;
+ fpga_interrupt_map =
+ <1 0 14 14>, /* 0: EXTENDED_INTERRUPT */
+ <1 0 0 0>, /* 1: VIDEO 0 */
+ <1 0 1 1>, /* 2: VIDEO 1 */
+ <1 0 2 2>, /* 3: VIDEO IC 0 */
+ <1 0 3 3>, /* 4: VIDEO IC 1 */
+ <1 0 4 4>, /* 5: IIC MAIN */
+ <1 0 6 6>, /* 6: IIC VIDEO 0 */
+ <1 0 7 7>, /* 7: IIC VIDEO 1 */
+ <1 1 0 0>, /* 8: OSD 0 */
+ <1 1 1 1>, /* 9: OSD 1 */
+ <1 1 2 2>, /* 10: SPDIF 0 */
+ <1 1 3 3>, /* 11: SPDIF 1 */
+ <1 0 12 12>, /* 12: COMM 0 */
+ <1 0 13 13>, /* 13: COMM 1 */
+ <1 0 10 10>, /* 14: COMM 2 */
+ <1 0 11 11>, /* 15: COMM 3 */
+ <2 0 5 5>, /* 16: MDIO */
+ <1 0 8 8>, /* 17: PHY */
+ <1 1 4 4>, /* 18: RS232 */
+ <1 1 5 5>, /* 19: AUDIO */
+ <1 1 8 8>, /* 20: PROC_AUDIO */
+ <1 1 7 7>, /* 21: USB/ETH-UART INT */
+ <2 1 10 10>, /* 22: AXI Bridge 0 */
+ <2 1 11 11>, /* 23: AXI Bridge 1 */
+ <2 1 9 9>, /* 24: USB/ETH-Secondary IIC */
+ <>;
+};
+
+/ {
+ FPGA0BUS: fpga0bus {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x00002000>;
+
+ compatible = "gdsys,soc";
+
+ fpga0_rs232 {
+ compatible = "gdsys,ihs_trans_rs232";
+ reg = <0x50 0x08>;
+ little-endian;
+ };
+
+ fpga0_uart_usb {
+ compatible = "gdsys,ihs_simple_uart";
+ reg = <0xa0 0x08>;
+ little-endian;
+ fpga_interrupts = <21>;
+ line = <0>;
+ };
+
+ fpga0_iic_main {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0x60 0x10>;
+ little-endian;
+ fpga_interrupts = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga0_dp_video0_redriver: fpga0_dp_video0_redriver {
+ compatible = "ti,sn75dp130";
+ reg = <0x2c>;
+ eq-i2c-enable = <3 2 1 0
+ 3 2 1 0
+ 3 2 1 0
+ 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
+ };
+ fpga0_dp_video1_redriver: fpga0_dp_video1_redriver {
+ compatible = "ti,sn75dp130";
+ reg = <0x2e>;
+ eq-i2c-enable = <3 2 1 0
+ 3 2 1 0
+ 3 2 1 0
+ 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
+ };
+ lm77@48 {
+ compatible = "national,lm77";
+ reg = <0x48>;
+ };
+ ads1015@49 {
+ compatible = "ti,ads1015";
+ reg = <0x49>;
+ };
+ ads1015@4b {
+ compatible = "ti,ads1015";
+ reg = <0x4b>;
+ };
+ };
+
+ fpga0_video0 {
+ compatible = "gdsys,ihs_video_out";
+ reg = <0x100 0x40>;
+ little-endian;
+ fpga_interrupts = <1 8>; /* VIDEO OSD */
+ osd_base = <0x180>;
+ osd_buffer_base = <0x1000>;
+ spdif_audio_base = <0x1e0>;
+ video_index = <0>;
+ video_id = <0>;
+ fpga-force-pos-pol;
+ sync-source;
+ fpga-pb-pixels = <2730>; /* 8192 / 3 */
+ fpga-ra-lines = <2>;
+ video_tx = <&fpga0_dp_video0>;
+ clk_gen = <&fpga0_video0_clkgen>;
+ ddc_ci = <&fpga0_dp_video0>;
+ };
+
+ fpga0_iic_video0 {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0x1c0 0x10>;
+ little-endian;
+ fpga_interrupts = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga0_video0_clkgen: fpga0_video0_clkgen {
+ compatible = "idt,ics8n3qv01";
+ reg = <0x6e>;
+ channel = <0>;
+ };
+ };
+
+ fpga0_axi_video0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "gdsys,ihs_axi";
+ reg = <0x170 0x10>;
+ little-endian;
+ fpga_interrupts = <22>;
+
+ fpga0_dp_video0: fpga0_dp_video0 {
+ compatible = "gdsys,logicore_dp_tx";
+ reg = <0x44a10000 0x1000>;
+ little-endian;
+ redriver = <&fpga0_dp_video0_redriver>;
+ video_id = <0>;
+ };
+ };
+
+ fpga0_video1 {
+ compatible = "gdsys,ihs_video_out";
+ reg = <0x200 0x40>;
+ little-endian;
+ fpga_interrupts = <2 9>; /* VIDEO OSD */
+ osd_base = <0x280>;
+ osd_buffer_base = <0x2000>;
+ spdif_audio_base = <0x2e0>;
+ video_index = <1>;
+ video_id = <1>;
+ fpga-force-pos-pol;
+ sync-source;
+ fpga-pb-pixels = <2730>; /* 8192 / 3 */
+ fpga-ra-lines = <2>;
+ video_tx = <&fpga0_dp_video1>;
+ clk_gen = <&fpga0_video1_clkgen>;
+ ddc_ci = <&fpga0_dp_video1>;
+ };
+
+ fpga0_iic_video1 {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0x2c0 0x10>;
+ little-endian;
+ fpga_interrupts = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga0_video1_clkgen: fpga0_video1_clkgen {
+ compatible = "idt,ics8n3qv01";
+ reg = <0x6e>;
+ channel = <1>;
+ };
+ };
+
+ fpga0_axi_video1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "gdsys,ihs_axi";
+ reg = <0x270 0x10>;
+ little-endian;
+ fpga_interrupts = <23>;
+
+ fpga0_dp_video1: fpga0_dp_video1 {
+ compatible = "gdsys,logicore_dp_tx";
+ reg = <0x44a10000 0x1000>;
+ little-endian;
+ redriver = <&fpga0_dp_video1_redriver>;
+ video_id = <1>;
+ };
+ };
+
+ fpga0_iic_usb {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0xb0 0x10>;
+ little-endian;
+ fpga_interrupts = <24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9555@20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+ };
+
+ fpga0_ep0 {
+ compatible = "gdsys,io-endpoint";
+ reg = < 0x020 0x10
+ 0x320 0x10
+ 0x340 0x10
+ 0x360 0x10>;
+ little-endian;
+ irq-model-local;
+ fpga_interrupts = <12 13 14 15>;
+ pollcycle = <200>;
+ nprot_channel = <16>;
+ uart_line = <0>;
+ ep_index = <0>;
+ line_protocol = <1>;
+ };
+
+ fpga0_mdio {
+ compatible = "gdsys,ihs_mdiomaster";
+ reg = <0x0058 0x10>;
+ little-endian;
+ fpga_interrupts = <16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga0_phy0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <0>;
+ };
+ fpga0_phy1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <1>;
+ };
+ fpga0_phy2 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <2>;
+ };
+ fpga0_phy3 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <3>;
+ };
+ };
+
+ };
+
+
+ FPGA1BUS: fpga1bus {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x00002000>;
+
+ compatible = "gdsys,soc";
+
+ fpga1_uart_usb {
+ compatible = "gdsys,ihs_simple_uart";
+ reg = <0xa0 0x08>;
+ little-endian;
+ fpga_interrupts = <21>;
+ line = <4>; /* TODO check and FIX */
+ };
+
+ fpga1_iic_main {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0x60 0x10>;
+ little-endian;
+ fpga_interrupts = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga1_dp_video0_redriver: fpga1_dp_video0_redriver {
+ compatible = "ti,sn75dp130";
+ reg = <0x2c>;
+ eq-i2c-enable = <3 2 1 0
+ 3 2 1 0
+ 3 2 1 0
+ 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
+ };
+ fpga1_dp_video1_redriver: fpga1_dp_video1_redriver {
+ compatible = "ti,sn75dp130";
+ reg = <0x2e>;
+ eq-i2c-enable = <3 2 1 0
+ 3 2 1 0
+ 3 2 1 0
+ 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
+ };
+ lm77@48 {
+ compatible = "national,lm77";
+ reg = <0x48>;
+ };
+ ads1015@49 {
+ compatible = "ti,ads1015";
+ reg = <0x49>;
+ };
+ ads1015@4b {
+ compatible = "ti,ads1015";
+ reg = <0x4b>;
+ };
+ };
+
+ fpga1_video0 {
+ compatible = "gdsys,ihs_video_out";
+ reg = <0x100 0x40>;
+ little-endian;
+ fpga_interrupts = <1 8>; /* VIDEO OSD */
+ osd_base = <0x180>;
+ osd_buffer_base = <0x1000>;
+ spdif_audio_base = <0x1e0>;
+ video_index = <0>;
+ video_id = <4>;
+ fpga-force-pos-pol;
+ sync-source;
+ fpga-pb-pixels = <2730>; /* 8192 / 3 */
+ fpga-ra-lines = <2>;
+ video_tx = <&fpga1_dp_video0>;
+ clk_gen = <&fpga1_video0_clkgen>;
+ ddc_ci = <&fpga1_dp_video0>;
+ };
+
+ fpga1_iic_video0 {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0x1c0 0x10>;
+ little-endian;
+ fpga_interrupts = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga1_video0_clkgen: fpga1_video0_clkgen {
+ compatible = "idt,ics8n3qv01";
+ reg = <0x6e>;
+ channel = <4>;
+ };
+ };
+
+ fpga1_axi_video0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "gdsys,ihs_axi";
+ reg = <0x170 0x10>;
+ little-endian;
+ fpga_interrupts = <22>;
+
+ fpga1_dp_video0: fpga1_dp_video0 {
+ compatible = "gdsys,logicore_dp_tx";
+ reg = <0x44a10000 0x1000>;
+ little-endian;
+ redriver = <&fpga1_dp_video0_redriver>;
+ video_id = <4>;
+ };
+ };
+
+ fpga1_video1 {
+ compatible = "gdsys,ihs_video_out";
+ reg = <0x200 0x40>;
+ little-endian;
+ fpga_interrupts = <2 9>; /* VIDEO OSD */
+ osd_base = <0x280>;
+ osd_buffer_base = <0x2000>;
+ spdif_audio_base = <0x2e0>;
+ video_index = <1>;
+ video_id = <5>;
+ fpga-force-pos-pol;
+ sync-source;
+ fpga-pb-pixels = <2730>; /* 8192 / 3 */
+ fpga-ra-lines = <2>;
+ video_tx = <&fpga1_dp_video1>;
+ clk_gen = <&fpga1_video1_clkgen>;
+ ddc_ci = <&fpga1_dp_video1>;
+ };
+
+ fpga1_iic_video1 {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0x2c0 0x10>;
+ little-endian;
+ fpga_interrupts = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga1_video1_clkgen: fpga1_video1_clkgen {
+ compatible = "idt,ics8n3qv01";
+ reg = <0x6e>;
+ channel = <5>;
+ };
+ };
+
+ fpga1_axi_video1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "gdsys,ihs_axi";
+ reg = <0x270 0x10>;
+ little-endian;
+ fpga_interrupts = <23>;
+
+ fpga1_dp_video1: fpga1_dp_video1 {
+ compatible = "gdsys,logicore_dp_tx";
+ reg = <0x44a10000 0x1000>;
+ little-endian;
+ redriver = <&fpga1_dp_video1_redriver>;
+ video_id = <5>;
+ };
+ };
+
+ fpga1_iic_usb {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0xb0 0x10>;
+ little-endian;
+ fpga_interrupts = <24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9555@20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+ };
+
+ fpga1_ep0 {
+ compatible = "gdsys,io-endpoint";
+ reg = < 0x020 0x10
+ 0x320 0x10
+ 0x340 0x10
+ 0x360 0x10>;
+ little-endian;
+ irq-model-local;
+ fpga_interrupts = <12 13 14 15>;
+ pollcycle = <200>;
+ nprot_channel = <17>;
+ uart_line = <1>;
+ ep_index = <0>;
+ line_protocol = <1>;
+ };
+
+ fpga1_mdio {
+ compatible = "gdsys,ihs_mdiomaster";
+ reg = <0x0058 0x10>;
+ little-endian;
+ fpga_interrupts = <16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga1_phy0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <0>;
+ };
+ fpga1_phy1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <1>;
+ };
+ fpga1_phy2 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <2>;
+ };
+ fpga1_phy3 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <3>;
+ };
+ };
+
+ };
+
+};
+
+#include "gdsys/gazerbeam-uboot.dtsi"
diff --git a/arch/powerpc/dts/gdsys/gazerbeam-base.dtsi b/arch/powerpc/dts/gdsys/gazerbeam-base.dtsi
new file mode 100644
index 0000000..aca05f2
--- /dev/null
+++ b/arch/powerpc/dts/gdsys/gazerbeam-base.dtsi
@@ -0,0 +1,185 @@
+/*
+ * Gazerbeam Device Tree Source
+ *
+ * (C) Copyright 2015
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/ {
+ model = "gdsys,gazerbeam";
+ compatible = "fsl,mpc8308rdb";
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ };
+
+ memory {
+ device_type = "memory";
+ };
+};
+
+&enet1 {
+ status = "okay";
+};
+
+&IIC {
+ fsl,preserve-clocking;
+
+ at97sc3205t@29 {
+ compatible = "atmel,at97sc3204t";
+ reg = <0x29>;
+ };
+
+ lm77@48 {
+ compatible = "national,lm77";
+ reg = <0x48>;
+ };
+
+ ads1015@49 {
+ compatible = "ti,ads1015";
+ reg = <0x49>;
+ };
+
+ lm77@4a {
+ compatible = "national,lm77";
+ reg = <0x4a>;
+ };
+
+ emc2305@2e {
+ compatible = "smsc,emc2305";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2e>;
+ fan@0 {
+ reg = <0>;
+ };
+ fan@1 {
+ reg = <1>;
+ };
+ fan@2 {
+ reg = <2>;
+ };
+ fan@3 {
+ reg = <3>;
+ };
+ fan@4 {
+ reg = <4>;
+ };
+ };
+
+ emc2305@4c {
+ compatible = "smsc,emc2305";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4c>;
+ fan@0 {
+ reg = <0>;
+ };
+ fan@1 {
+ reg = <1>;
+ };
+ fan@2 {
+ reg = <2>;
+ };
+ fan@3 {
+ reg = <3>;
+ };
+ fan@4 {
+ reg = <4>;
+ };
+ };
+
+ at24c512@54 {
+ compatible = "atmel,24c512";
+ reg = <0x54>;
+ };
+
+ /* PPC-Board */
+ pca9698@22 {
+ compatible = "nxp,pca9698";
+ reg = <0x22>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ /* IO-Board */
+ pca9698@20 {
+ compatible = "nxp,pca9698";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+};
+
+&IIC2 {
+ fsl,preserve-clocking;
+
+ status = "okay";
+
+ /* MC2/SC-Board */
+ GPIO_VB0: pca9698@20 {
+ compatible = "nxp,pca9698";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ /* MC4-Board */
+ GPIO_VB1: pca9698@22 {
+ compatible = "nxp,pca9698";
+ reg = <0x22>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+};
+
+&SPI {
+ gpios = < /*SPI-CSS-FPGA-U-FLASH#*/ &gpio0 8 0
+ /*SPI-CSS-FPGA-O-FLASH#*/ &gpio0 6 0
+ /*SPI-CSS-STDP1_U-FLASH#*/ &gpio0 12 0
+ /*SPI-CSS-STDP2_U-FLASH#*/ &gpio0 11 0
+ /*SPI-CSS-STDP1_O-FLASH#*/ &gpio0 15 0
+ /*SPI-CSS-STDP2_O-FLASH#*/ &gpio0 3 0>;
+
+ m25p16@0 {
+ compatible = "st,n25q128a11";
+ reg = <0x0>;
+ spi-max-frequency = <20000000>;
+ };
+
+ m25p16@1 {
+ compatible = "st,n25q128a11";
+ reg = <0x1>;
+ spi-max-frequency = <20000000>;
+ };
+
+ m25p16@2 {
+ compatible = "st,m25p40";
+ reg = <0x2>;
+ spi-max-frequency = <20000000>;
+ };
+
+ m25p16@3 {
+ compatible = "st,m25p40";
+ reg = <0x3>;
+ spi-max-frequency = <20000000>;
+ };
+
+ m25p16@4 {
+ compatible = "st,m25p40";
+ reg = <0x4>;
+ spi-max-frequency = <20000000>;
+ };
+
+ m25p16@5 {
+ compatible = "st,m25p40";
+ reg = <0x5>;
+ spi-max-frequency = <20000000>;
+ };
+};
diff --git a/arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi b/arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi
new file mode 100644
index 0000000..1c4977f
--- /dev/null
+++ b/arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi
@@ -0,0 +1,250 @@
+#include <dt-bindings/memory/mpc83xx-sdram.h>
+#include <dt-bindings/clk/mpc83xx-clk.h>
+
+/ {
+ aliases {
+ i2c0 = &IIC;
+ i2c1 = &IIC2;
+ i2c2 = "/fpga0bus/fpga0_iic_main";
+ i2c3 = "/fpga0bus/fpga0_iic_video0";
+ i2c4 = "/fpga0bus/fpga0_iic_video1";
+ i2c5 = "/fpga0bus/fpga0_iic_usb";
+ gdsys_soc0 = "/fpga0bus";
+ gdsys_soc1 = "/fpga1bus";
+ ioep0 = "/fpga0bus/fpga0_ep0";
+ ioep1 = "/fpga0bus/fpga1_ep0";
+ };
+
+ chosen {
+ stdout-path = &serial1;
+ };
+
+ cpus {
+ compatible = "cpu_bus";
+ u-boot,dm-pre-reloc;
+
+ PowerPC,8308@0 {
+ compatible = "fsl,mpc8308";
+ clocks = <&socclocks MPC83XX_CLK_CORE
+ &socclocks MPC83XX_CLK_CSB>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ board {
+ compatible = "gdsys,board_gazerbeam";
+ csb = <&board_soc>;
+ serdes = <&SERDES>;
+ rxaui0 = <&RXAUI0_0>;
+ rxaui1 = <&RXAUI0_1>;
+ rxaui2 = <&RXAUI0_2>;
+ rxaui3 = <&RXAUI0_3>;
+ rxaui4 = <&RXAUI1_0>;
+ rxaui5 = <&RXAUI1_1>;
+ rxaui6 = <&RXAUI1_2>;
+ rxaui7 = <&RXAUI1_3>;
+ fpga0 = <&FPGA0>;
+ fpga1 = <&FPGA1>;
+ ioep0 = <&IOEP0>;
+ ioep1 = <&IOEP1>;
+
+ ver-gpios = <&PPCPCA 12 0
+ &PPCPCA 13 0
+ &PPCPCA 14 0
+ &PPCPCA 15 0>;
+
+ /* MC2/SC-Board */
+ var-gpios-mc2 = <&GPIO_VB0 0 0 /* VAR-MC_SC */
+ &GPIO_VB0 11 0>; /* VAR-CON */
+ /* MC4-Board */
+ var-gpios-mc4 = <&GPIO_VB1 0 0 /* VAR-MC_SC */
+ &GPIO_VB1 11 0>; /* VAR-CON */
+
+ reset-gpios = <&gpio0 1 0 &gpio0 2 1>;
+ };
+
+ socclocks: clocks {
+ compatible = "fsl,mpc8308-clk";
+ #clock-cells = <1>;
+ u-boot,dm-pre-reloc;
+ };
+
+ timer {
+ compatible = "fsl,mpc83xx-timer";
+ clocks = <&socclocks MPC83XX_CLK_CSB>;
+ };
+};
+
+&FPGA0 {
+ reset-gpios = <&PPCPCA 26 0>;
+ done-gpios = <&GPIO_VB0 19 0>;
+};
+
+&FPGA1 {
+ status = "disable";
+};
+
+&FPGA0BUS {
+ ranges = <0x0 0xe0600000 0x00004000>;
+ fpga = <&FPGA0>;
+
+ fpga0_video0 {
+ mode = "640_480_60";
+
+ status = "disabled";
+ };
+
+ RXAUI0_0: fpga0_rxaui@fc0 {
+ compatible = "gdsys,rxaui_ctrl";
+ reg = <0x0fc0 0x10>;
+ };
+
+ fpga0_iic_video0 {
+ status = "disabled";
+ };
+
+ fpga0_axi_video0 {
+ status = "disabled";
+ };
+
+ fpga0_video1 {
+ mode = "640_480_60";
+ status = "disabled";
+ };
+
+ fpga0_iic_video1 {
+ status = "disabled";
+ };
+
+ fpga0_axi_video1 {
+ status = "disabled";
+ };
+
+ IOEP0: fpga0_ep0 {
+ };
+
+ RXAUI0_1: fpga0_rxaui@fd0 {
+ compatible = "gdsys,rxaui_ctrl";
+ reg = <0x0fd0 0x10>;
+ };
+
+ RXAUI0_2: fpga0_rxaui@fe0 {
+ compatible = "gdsys,rxaui_ctrl";
+ reg = <0x0fe0 0x10>;
+ };
+
+ RXAUI0_3: fpga0_rxaui@ff0 {
+ compatible = "gdsys,rxaui_ctrl";
+ reg = <0x0ff0 0x10>;
+ };
+};
+
+&FPGA1BUS {
+ ranges = <0x0 0xe0700000 0x00004000>;
+ fpga = <&FPGA1>;
+
+ status = "disable";
+
+ fpga1_video0 {
+ mode = "640_480_60";
+ };
+
+ RXAUI1_0: fpga0_rxaui@fc0 {
+ compatible = "gdsys,rxaui_ctrl";
+ reg = <0x0fc0 0x10>;
+ };
+
+ fpga1_video1 {
+ mode = "640_480_60";
+ };
+
+ IOEP1: fpga1_ep0 {
+ };
+
+ RXAUI1_1: fpga0_rxaui@fd0 {
+ compatible = "gdsys,rxaui_ctrl";
+ reg = <0x0fd0 0x10>;
+ };
+
+ RXAUI1_2: fpga0_rxaui@fe0 {
+ compatible = "gdsys,rxaui_ctrl";
+ reg = <0x0fe0 0x10>;
+ };
+
+ RXAUI1_3: fpga0_rxaui@ff0 {
+ compatible = "gdsys,rxaui_ctrl";
+ reg = <0x0ff0 0x10>;
+ };
+};
+
+&board_soc {
+ u-boot,dm-pre-reloc;
+ clocks = <&socclocks MPC83XX_CLK_CSB>;
+
+ memory@2000 {
+ u-boot,dm-pre-reloc;
+ };
+
+ sdhc@2e000 {
+ clocks = <&socclocks MPC83XX_CLK_SDHC>;
+ clock-names = "per";
+ };
+
+ SERDES: serdes@e3000 {
+ reg = <0xe3000 0x200>;
+ compatible = "fsl,mpc83xx-serdes";
+ proto = "pex";
+ serdes-clk = <100>;
+ vdd;
+ };
+};
+
+&IIC {
+ clocks = <&socclocks MPC83XX_CLK_I2C1>;
+
+ PPCPCA: pca9698@20 {
+ label = "ppc";
+ };
+
+ IOPCA: pca9698@22 {
+ label = "io";
+ };
+
+ at97sc3205t@29 {
+ u-boot,i2c-offset-len = <0>;
+ };
+};
+
+&IIC2 {
+ clocks = <&socclocks MPC83XX_CLK_I2C2>;
+
+ GPIO_VB0: pca9698@20 {
+ label = "mc2-sc";
+ };
+
+ GPIO_VB1: pca9698@22 {
+ label = "mc4";
+ };
+};
+
+&board_soc {
+ u-boot,dm-pre-reloc;
+};
+
+&GPIO_VB0 {
+ u-boot,dm-pre-reloc;
+};
+
+&serial0 {
+ clocks = <&socclocks MPC83XX_CLK_CSB>;
+ u-boot,dm-pre-reloc;
+};
+
+&serial1 {
+ clocks = <&socclocks MPC83XX_CLK_CSB>;
+ u-boot,dm-pre-reloc;
+};
+
+&pci0 {
+ clocks = <&socclocks MPC83XX_CLK_PCIEXP1>;
+};
diff --git a/arch/powerpc/dts/gdsys/mpc8308.dtsi b/arch/powerpc/dts/gdsys/mpc8308.dtsi
new file mode 100644
index 0000000..23e7403
--- /dev/null
+++ b/arch/powerpc/dts/gdsys/mpc8308.dtsi
@@ -0,0 +1,354 @@
+/*
+ * Basic platform for gdsys mpc8308 based devices
+ *
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * based on mpc8308rdb
+ * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/memory/mpc83xx-sdram.h>
+
+/ {
+ compatible = "fsl,mpc8308rdb";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8308@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <16384>;
+ i-cache-size = <16384>;
+ timebase-frequency = <0>; // from bootloader
+ bus-frequency = <0>; // from bootloader
+ clock-frequency = <0>; // from bootloader
+ };
+ };
+
+ board_lbc: localbus@e0005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
+ reg = <0xe0005000 0x1000>;
+ interrupts = <77 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
+ board_soc: immr@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,mpc8308-immr", "simple-bus";
+ ranges = <0 0xe0000000 0x00100000>;
+ reg = <0xe0000000 0x00000200>;
+ bus-frequency = <0>;
+
+ wdt@200 {
+ device_type = "watchdog";
+ compatible = "mpc83xx_wdt";
+ reg = <0x200 0x100>;
+ };
+
+ memory@2000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc83xx-mem-controller";
+ reg = <0x2000 0x1000>;
+ device_type = "memory";
+
+ driver_software_override = <DSO_ENABLE>;
+ p_impedance_override = <DSO_P_IMPEDANCE_NOMINAL>;
+ n_impedance_override = <DSO_N_IMPEDANCE_NOMINAL>;
+ odt_termination_value = <ODT_TERMINATION_150_OHM>;
+ ddr_type = <DDR_TYPE_DDR2_1_8_VOLT>;
+
+ clock_adjust = <CLOCK_ADJUST_05>;
+
+ read_to_write = <0>;
+ write_to_read = <0>;
+ read_to_read = <0>;
+ write_to_write = <0>;
+ active_powerdown_exit = <2>;
+ precharge_powerdown_exit = <6>;
+ odt_powerdown_exit = <8>;
+ mode_reg_set_cycle = <2>;
+
+ precharge_to_activate = <2>;
+ activate_to_precharge = <6>;
+ activate_to_readwrite = <2>;
+ mcas_latency = <CASLAT_40>;
+ refresh_recovery = <17>;
+ last_data_to_precharge = <2>;
+ activate_to_activate = <2>;
+ last_write_data_to_read = <2>;
+
+ additive_latency = <0>;
+ mcas_to_preamble_override = <READ_LAT_PLUS_1_2>;
+ write_latency = <3>;
+ read_to_precharge = <2>;
+ write_cmd_to_write_data = <CLOCK_DELAY_1_2>;
+ minimum_cke_pulse_width = <3>;
+ four_activates_window = <5>;
+
+ self_refresh = <SREN_ENABLE>;
+ sdram_type = <TYPE_DDR2>;
+ databus_width = <DATA_BUS_WIDTH_32>;
+
+ force_self_refresh = <MODE_NORMAL>;
+ dll_reset = <DLL_RESET_ENABLE>;
+ dqs_config = <DQS_TRUE>;
+ odt_config = <ODT_ASSERT_READS>;
+ posted_refreshes = <1>;
+
+ refresh_interval = <2084>;
+ precharge_interval = <256>;
+
+ sdmode = <0x0242>;
+ esdmode = <0x0440>;
+
+ ram@0 {
+ reg = <0x0 0x0 0x8000000>;
+ compatible = "nanya,nt5tu64m16hg";
+
+ odt_rd_cfg = <ODT_RD_NEVER>;
+ odt_wr_cfg = <ODT_WR_ONLY_CURRENT>;
+ bank_bits = <3>;
+ row_bits = <13>;
+ col_bits = <10>;
+ };
+ };
+
+ IIC:i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <14 0x8>;
+ interrupt-parent = <&ipic>;
+ dfsrr;
+ };
+
+ IIC2: i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <15 0x8>;
+ interrupt-parent = <&ipic>;
+ dfsrr;
+ status = "disabled";
+ };
+
+ SPI:spi@7000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl,spi";
+ reg = <0x7000 0x1000>;
+ interrupts = <16 0x8>;
+ interrupt-parent = <&ipic>;
+ mode = "cpu";
+ };
+
+ sdhc@2e000 {
+ compatible = "fsl,esdhc", "fsl,mpc8308-esdhc";
+ reg = <0x2e000 0x1000>;
+ interrupts = <42 0x8>;
+ interrupt-parent = <&ipic>;
+ sdhci,auto-cmd12;
+ /* Filled in by U-Boot */
+ clock-frequency = <0>;
+ };
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <133333333>;
+ interrupts = <9 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <133333333>;
+ interrupts = <10 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
+ gpio0: gpio@c00 {
+ #gpio-cells = <2>;
+ device_type = "gpio";
+ compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
+ reg = <0xc00 0x18>;
+ interrupts = <74 0x8>;
+ interrupt-parent = <&ipic>;
+ gpio-controller;
+ };
+
+ /* IPIC
+ * interrupts cell = <intr #, sense>
+ * sense values match linux IORESOURCE_IRQ_* defines:
+ * sense == 8: Level, low assertion
+ * sense == 2: Edge, high-to-low change
+ */
+ ipic: interrupt-controller@700 {
+ compatible = "fsl,ipic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x700 0x100>;
+ device_type = "ipic";
+ };
+
+ ipic-msi@7c0 {
+ compatible = "fsl,ipic-msi";
+ reg = <0x7c0 0x40>;
+ msi-available-ranges = <0x0 0x100>;
+ interrupts = < 0x43 0x8
+ 0x4 0x8
+ 0x51 0x8
+ 0x52 0x8
+ 0x56 0x8
+ 0x57 0x8
+ 0x58 0x8
+ 0x59 0x8 >;
+ interrupt-parent = < &ipic >;
+ };
+
+ dma@2c000 {
+ compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";
+ reg = <0x2c000 0x1800>;
+ interrupts = <3 0x8
+ 94 0x8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ enet0: ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x24000 0x1000>;
+
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar", "fsl,tsec";
+ reg = <0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <32 0x8 33 0x8 34 0x8>;
+ interrupt-parent = <&ipic>;
+ tbi-handle = < &tbi0 >;
+ phy-handle = < &phy1 >;
+ fsl,magic-packet;
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x520 0x20>;
+ phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ phy2: ethernet-phy@0 {
+ reg = <0x0>;
+ device_type = "ethernet-phy";
+ };
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ enet1: ethernet@25000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar", "fsl,tsec";
+ reg = <0x25000 0x1000>;
+ ranges = <0x0 0x25000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 0x8 36 0x8 37 0x8>;
+ interrupt-parent = <&ipic>;
+ phy-handle = < &phy2 >;
+ status = "disabled";
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+ };
+
+ pci0: pcie@e0009000 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
+ reg = <0xe0009000 0x00001000
+ 0xb0000000 0x01000000>;
+ ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
+ 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
+ bus-range = <0 0>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0 0 0 1 &ipic 1 8
+ 0 0 0 2 &ipic 1 8
+ 0 0 0 3 &ipic 1 8
+ 0 0 0 4 &ipic 1 8>;
+ interrupts = <0x1 0x8>;
+ interrupt-parent = <&ipic>;
+ clock-frequency = <0>;
+
+ pcie@0 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ reg = <0 0 0 0 0>;
+ ranges = <0x02000000 0 0xa0000000
+ 0x02000000 0 0xa0000000
+ 0 0x10000000
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00800000>;
+ };
+ };
+};
diff --git a/arch/powerpc/dts/gdsys/soc/i2c/cirrus-audio-codec.dtsi b/arch/powerpc/dts/gdsys/soc/i2c/cirrus-audio-codec.dtsi
new file mode 100644
index 0000000..9787e09
--- /dev/null
+++ b/arch/powerpc/dts/gdsys/soc/i2c/cirrus-audio-codec.dtsi
@@ -0,0 +1,6 @@
+&IIC {
+ cs4265@4f {
+ compatible = "cirrus,cs4265";
+ reg = <0x0000004f>;
+ };
+};
diff --git a/arch/powerpc/dts/gdsys/soc/i2c/dallas-rtc.dtsi b/arch/powerpc/dts/gdsys/soc/i2c/dallas-rtc.dtsi
new file mode 100644
index 0000000..336bdca
--- /dev/null
+++ b/arch/powerpc/dts/gdsys/soc/i2c/dallas-rtc.dtsi
@@ -0,0 +1,6 @@
+&IIC {
+ ds1339@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
diff --git a/arch/powerpc/dts/gdsys/soc/lbc/gazerbeam.dtsi b/arch/powerpc/dts/gdsys/soc/lbc/gazerbeam.dtsi
new file mode 100644
index 0000000..5ff58c2
--- /dev/null
+++ b/arch/powerpc/dts/gdsys/soc/lbc/gazerbeam.dtsi
@@ -0,0 +1,5 @@
+&board_lbc {
+ ranges = <0x0 0x0 0xfe000000 0x00800000
+ 0x1 0x0 0xe0600000 0x00003000
+ 0x2 0x0 0xe0700000 0x00003000>;
+};
diff --git a/arch/powerpc/dts/gdsys/soc/nor/flash-80k-partition.dtsi b/arch/powerpc/dts/gdsys/soc/nor/flash-80k-partition.dtsi
new file mode 100644
index 0000000..c6cc140
--- /dev/null
+++ b/arch/powerpc/dts/gdsys/soc/nor/flash-80k-partition.dtsi
@@ -0,0 +1,20 @@
+&board_lbc {
+ flash@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x100000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ u-boot@0 {
+ reg = <0x0 0x80000>;
+ };
+ env@80000 {
+ reg = <0x80000 0x10000>;
+ };
+ env1@90000 {
+ reg = <0x90000 0x10000>;
+ };
+ };
+};
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/clock.h b/arch/powerpc/include/asm/arch-mpc83xx/clock.h
new file mode 100644
index 0000000..d57e93c
--- /dev/null
+++ b/arch/powerpc/include/asm/arch-mpc83xx/clock.h
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_POWERPC_CLOCK_H
+#define __ASM_POWERPC_CLOCK_H
+
+/* Make fsl_esdhc driver happy */
+enum mxc_clock {
+ MXC_ESDHC_CLK,
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+uint mxc_get_clock(int clk)
+{
+ return gd->arch.sdhc_clk;
+}
+#endif /* __ASM_POWERPC_CLOCK_H */
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
index 57f783b..385d651 100644
--- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
@@ -6,10 +6,10 @@
/*
* The MCP83xx's 1-2 GPIO controllers each with 32 bits.
*/
-#if defined(CONFIG_MPC8313) || defined(CONFIG_MPC8308) || \
- defined(CONFIG_MPC8315)
+#if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \
+ defined(CONFIG_ARCH_MPC8315)
#define MPC83XX_GPIO_CTRLRS 1
-#elif defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
+#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
#define MPC83XX_GPIO_CTRLRS 2
#else
#define MPC83XX_GPIO_CTRLRS 0
@@ -17,7 +17,15 @@
#define MAX_NUM_GPIOS (32 * MPC83XX_GPIO_CTRLRS)
+struct mpc8xxx_gpio_plat {
+ ulong addr;
+ unsigned long size;
+ uint ngpios;
+};
+
+#ifndef DM_GPIO
void mpc83xx_gpio_init_f(void);
void mpc83xx_gpio_init_r(void);
+#endif /* DM_GPIO */
#endif /* MPC83XX_GPIO_H_ */
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index b076d5e..bf352d9 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -43,10 +43,10 @@
#define BR_MSEL 0x000000E0
#define BR_MSEL_SHIFT 5
#define BR_MS_GPCM 0x00000000 /* GPCM */
-#if !defined(CONFIG_MPC834x) && !defined(CONFIG_MPC8360)
+#if !defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_ARCH_MPC8360)
#define BR_MS_FCM 0x00000020 /* FCM */
#endif
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8360)
#define BR_MS_SDRAM 0x00000060 /* SDRAM */
#elif defined(CONFIG_MPC85xx)
#define BR_MS_SDRAM 0x00000000 /* SDRAM */
@@ -54,7 +54,7 @@
#define BR_MS_UPMA 0x00000080 /* UPMA */
#define BR_MS_UPMB 0x000000A0 /* UPMB */
#define BR_MS_UPMC 0x000000C0 /* UPMC */
-#if !defined(CONFIG_MPC834x)
+#if !defined(CONFIG_ARCH_MPC834X)
#define BR_ATOM 0x0000000C
#define BR_ATOM_SHIFT 2
#endif
@@ -67,7 +67,7 @@
#define UPMB 1
#define UPMC 2
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
#else
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
@@ -133,7 +133,7 @@
#define OR_GPCM_EHTR_SHIFT 1
#define OR_GPCM_EHTR_CLEAR 0x00000000
#define OR_GPCM_EHTR_SET 0x00000002
-#if !defined(CONFIG_MPC8308)
+#if !defined(CONFIG_ARCH_MPC8308)
#define OR_GPCM_EAD 0x00000001
#define OR_GPCM_EAD_SHIFT 0
#endif
@@ -428,14 +428,17 @@
#define LSDMR_BSMA1516 (3 << (31 - 10))
#define LSDMR_BSMA1617 (4 << (31 - 10))
#define LSDMR_RFCR5 (3 << (31 - 16))
+#define LSDMR_RFCR8 (5 << (31 - 16))
#define LSDMR_RFCR16 (7 << (31 - 16))
#define LSDMR_PRETOACT3 (3 << (31 - 19))
+#define LSDMR_PRETOACT6 (5 << (31 - 19))
#define LSDMR_PRETOACT7 (7 << (31 - 19))
#define LSDMR_ACTTORW3 (3 << (31 - 22))
#define LSDMR_ACTTORW7 (7 << (31 - 22))
#define LSDMR_ACTTORW6 (6 << (31 - 22))
#define LSDMR_BL8 (1 << (31 - 23))
#define LSDMR_WRC2 (2 << (31 - 27))
+#define LSDMR_WRC3 (3 << (31 - 27))
#define LSDMR_WRC4 (0 << (31 - 27))
#define LSDMR_BUFCMD (1 << (31 - 29))
#define LSDMR_CL3 (3 << (31 - 31))
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index d00cee9..b6e4dd6 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -35,35 +35,35 @@
#else
/* There are other clocks in the MPC83XX */
u32 csb_clk;
-# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
+# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
-# elif defined(CONFIG_MPC8309)
+# elif defined(CONFIG_ARCH_MPC8309)
u32 usbdr_clk;
# endif
-# if defined(CONFIG_MPC834x)
+# if defined(CONFIG_ARCH_MPC834X)
u32 usbmph_clk;
-# endif /* CONFIG_MPC834x */
-# if defined(CONFIG_MPC8315)
+# endif /* CONFIG_ARCH_MPC834X */
+# if defined(CONFIG_ARCH_MPC8315)
u32 tdm_clk;
# endif
u32 core_clk;
u32 enc_clk;
u32 lbiu_clk;
u32 lclk_clk;
-# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC837x)
+# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
u32 pciexp1_clk;
u32 pciexp2_clk;
# endif
-# if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+# if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
u32 sata_clk;
# endif
-# if defined(CONFIG_MPC8360)
+# if defined(CONFIG_ARCH_MPC8360)
u32 mem_sec_clk;
-# endif /* CONFIG_MPC8360 */
+# endif /* CONFIG_ARCH_MPC8360 */
#endif
#endif
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index afef36f..d02da64 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -59,12 +59,12 @@
u32 obir; /* Output Buffer Impedance Register */
u8 res8[0xC];
u32 pecr1; /* PCI Express control register 1 */
-#if defined(CONFIG_MPC830x)
+#if defined(CONFIG_ARCH_MPC830X)
u32 sdhccr; /* eSDHC Control Registers for MPC830x */
#else
u32 pecr2; /* PCI Express control register 2 */
#endif
-#if defined(CONFIG_MPC8309)
+#if defined(CONFIG_ARCH_MPC8309)
u32 can_dbg_ctrl;
u32 res9a;
u32 gpr1;
@@ -604,7 +604,7 @@
* On Chip ROM
*/
typedef struct rom83xx {
-#if defined(CONFIG_MPC8309)
+#if defined(CONFIG_ARCH_MPC8309)
u8 mem[0x8000];
#else
u8 mem[0x10000];
@@ -625,7 +625,7 @@
u8 fixme[0x2000];
} tdmdmac83xx_t;
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
@@ -666,7 +666,7 @@
u8 res7[0xC0000];
} immap_t;
-#ifndef CONFIG_MPC834x
+#ifndef CONFIG_ARCH_MPC834X
#ifdef CONFIG_HAS_FSL_MPH_USB
#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */
#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0
@@ -679,7 +679,7 @@
#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000
#endif
-#elif defined(CONFIG_MPC8313)
+#elif defined(CONFIG_ARCH_MPC8313)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
@@ -714,7 +714,7 @@
u8 res7[0xC0000];
} immap_t;
-#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
+#elif defined(CONFIG_ARCH_MPC8315)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
@@ -729,8 +729,8 @@
gpio83xx_t gpio[1]; /* General purpose I/O module */
u8 res0[0x1300];
ddr83xx_t ddr; /* DDR Memory Controller Memory */
- fsl_i2c_t i2c[2]; /* I2C Controllers */
- u8 res1[0x1300];
+ fsl_i2c_t i2c[1]; /* I2C Controllers */
+ u8 res1[0x1400];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
@@ -759,7 +759,43 @@
u8 res12[0x1CF00];
} immap_t;
+#elif defined(CONFIG_ARCH_MPC8308)
+typedef struct immap {
+ sysconf83xx_t sysconf; /* System configuration */
+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
+ rtclk83xx_t pit; /* Periodic Interval Timer */
+ gtm83xx_t gtm[1]; /* Global Timers Module */
+ u8 res0[0x100];
+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter83xx_t arbiter; /* System Arbiter Registers */
+ reset83xx_t reset; /* Reset Module */
+ clk83xx_t clk; /* System Clock Module */
+ pmc83xx_t pmc; /* Power Management Control Module */
+ gpio83xx_t gpio[1]; /* General purpose I/O module */
+ u8 res1[0x1300];
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
+ fsl_i2c_t i2c[2]; /* I2C Controllers */
+ u8 res2[0x1300];
+ duart83xx_t duart[2]; /* DUART */
+ u8 res3[0x900];
+ fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
+ u8 res4[0x1000];
+ spi8xxx_t spi; /* Serial Peripheral Interface */
+ u8 res5[0x1000];
+ pex83xx_t pciexp[1]; /* PCI Express Controller */
+ u8 res6[0x19000];
+ usb83xx_t usb[1]; /* USB DR Controller */
+ tsec83xx_t tsec[2];
+ u8 res7[0x6000];
+ tdmdmac83xx_t tdmdmac; /* TDM DMAC */
+ sdhc83xx_t sdhc; /* SDHC Controller */
+ u8 res8[0xb4000];
+ serdes83xx_t serdes[1]; /* SerDes Registers */
+ u8 res9[0x1CF00];
+} immap_t;
+
-#elif defined(CONFIG_MPC837x)
+#elif defined(CONFIG_ARCH_MPC837X)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
@@ -803,7 +839,7 @@
rom83xx_t rom; /* On Chip ROM */
} immap_t;
-#elif defined(CONFIG_MPC8360)
+#elif defined(CONFIG_ARCH_MPC8360)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
@@ -843,7 +879,7 @@
u8 qe[0x100000]; /* QE block */
} immap_t;
-#elif defined(CONFIG_MPC832x)
+#elif defined(CONFIG_ARCH_MPC832X)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
@@ -879,7 +915,7 @@
u8 res8[0xC0000];
u8 qe[0x100000]; /* QE block */
} immap_t;
-#elif defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC8309)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
@@ -946,7 +982,7 @@
#endif
#define CONFIG_SYS_MPC83xx_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET)
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
#define CONFIG_SYS_MPC83xx_USB2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET)
#endif
diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h
index 432be05..b583a32 100644
--- a/arch/powerpc/include/asm/mpc8xxx_spi.h
+++ b/arch/powerpc/include/asm/mpc8xxx_spi.h
@@ -10,11 +10,11 @@
#include <asm/types.h>
-#if defined(CONFIG_MPC8308) || \
- defined(CONFIG_MPC8313) || \
- defined(CONFIG_MPC8315) || \
- defined(CONFIG_MPC834x) || \
- defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || \
+ defined(CONFIG_ARCH_MPC8313) || \
+ defined(CONFIG_ARCH_MPC8315) || \
+ defined(CONFIG_ARCH_MPC834X) || \
+ defined(CONFIG_ARCH_MPC837X)
typedef struct spi8xxx {
u8 res0[0x20]; /* 0x0-0x01f reserved */
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index f97ce48..e03ab21 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1203,127 +1203,7 @@
#endif
#endif
-
-/* what kind of prep workstation we are */
-extern int _prep_type;
-/*
- * This is used to identify the board type from a given PReP board
- * vendor. Board revision is also made available.
- */
-extern unsigned char ucSystemType;
-extern unsigned char ucBoardRev;
-extern unsigned char ucBoardRevMaj, ucBoardRevMin;
-
struct task_struct;
-void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
-void release_thread(struct task_struct *);
-
-/*
- * Create a new kernel thread.
- */
-extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
-
-/*
- * Bus types
- */
-#define EISA_bus 0
-#define EISA_bus__is_a_macro /* for versions in ksyms.c */
-#define MCA_bus 0
-#define MCA_bus__is_a_macro /* for versions in ksyms.c */
-
-/* Lazy FPU handling on uni-processor */
-extern struct task_struct *last_task_used_math;
-extern struct task_struct *last_task_used_altivec;
-
-/*
- * this is the minimum allowable io space due to the location
- * of the io areas on prep (first one at 0x80000000) but
- * as soon as I get around to remapping the io areas with the BATs
- * to match the mac we can raise this. -- Cort
- */
-#define TASK_SIZE (0x80000000UL)
-
-/* This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
-
-typedef struct {
- unsigned long seg;
-} mm_segment_t;
-
-struct thread_struct {
- unsigned long ksp; /* Kernel stack pointer */
- unsigned long wchan; /* Event task is sleeping on */
- struct pt_regs *regs; /* Pointer to saved register state */
- mm_segment_t fs; /* for get_fs() validation */
- void *pgdir; /* root of page-table tree */
- signed long last_syscall;
- double fpr[32]; /* Complete floating point set */
- unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */
- unsigned long fpscr; /* Floating point status */
-#ifdef CONFIG_ALTIVEC
- vector128 vr[32]; /* Complete AltiVec set */
- vector128 vscr; /* AltiVec status */
- unsigned long vrsave;
-#endif /* CONFIG_ALTIVEC */
-};
-
-#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
-
-#define INIT_THREAD { \
- INIT_SP, /* ksp */ \
- 0, /* wchan */ \
- (struct pt_regs *)INIT_SP - 1, /* regs */ \
- KERNEL_DS, /*fs*/ \
- swapper_pg_dir, /* pgdir */ \
- 0, /* last_syscall */ \
- {0}, 0, 0 \
-}
-
-/*
- * Note: the vm_start and vm_end fields here should *not*
- * be in kernel space. (Could vm_end == vm_start perhaps?)
- */
-#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
- PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
- 1, NULL, NULL }
-
-/*
- * Return saved PC of a blocked thread. For now, this is the "user" PC
- */
-static inline unsigned long thread_saved_pc(struct thread_struct *t)
-{
- return (t->regs) ? t->regs->nip : 0;
-}
-
-#define copy_segments(tsk, mm) do { } while (0)
-#define release_segments(mm) do { } while (0)
-#define forget_segments() do { } while (0)
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_EIP(tsk) ((tsk)->thread.regs->nip)
-#define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1])
-
-/*
- * NOTE! The task struct and the stack go together
- */
-#define THREAD_SIZE (2*PAGE_SIZE)
-#define alloc_task_struct() \
- ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
-#define free_task_struct(p) free_pages((unsigned long)(p),1)
-#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count)
-
-/* in process.c - for early bootup debug -- Cort */
-int ll_printk(const char *, ...);
-void ll_puts(const char *);
-
-#define init_task (init_task_union.task)
-#define init_stack (init_task_union.stack)
-
-/* In misc.c */
-void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
#ifndef CONFIG_CPU_MPC83XX
int prt_83xx_rsr(void);
diff --git a/board/esd/vme8349/Kconfig b/board/esd/vme8349/Kconfig
index b8d9432..ef2af40 100644
--- a/board/esd/vme8349/Kconfig
+++ b/board/esd/vme8349/Kconfig
@@ -10,3 +10,16 @@
default "vme8349"
endif
+
+if TARGET_CADDY2
+
+config SYS_BOARD
+ default "vme8349"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "caddy2"
+
+endif
diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c
index 45ad3a8..4c220fa 100644
--- a/board/esd/vme8349/vme8349.c
+++ b/board/esd/vme8349/vme8349.c
@@ -38,7 +38,7 @@
return -ENXIO;
/* DDR SDRAM - Main memory */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
msize = spd_sdram();
@@ -60,7 +60,7 @@
int checkboard(void)
{
-#ifdef VME_CADDY2
+#ifdef CONFIG_TARGET_CADDY2
puts("Board: esd VME-CADDY/2\n");
#else
puts("Board: esd VME-CPU/8349\n");
@@ -69,7 +69,7 @@
return 0;
}
-#ifdef VME_CADDY2
+#ifdef CONFIG_TARGET_CADDY2
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
@@ -102,7 +102,7 @@
* Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
* and VME-CADDY/2) have different SDRAM configurations.
*/
-#ifdef VME_CADDY2
+#ifdef CONFIG_TARGET_CADDY2
#define SMALL_RAM 0xff
#define LARGE_RAM 0x00
#else
@@ -165,7 +165,7 @@
SPD_VAL(0x7e, 0x1d), /* 63 */
{ 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
SPD_VAL(0x00, 0x00), /* 72 */
-#ifdef VME_CADDY2
+#ifdef CONFIG_TARGET_CADDY2
{ "vme-caddy/2 ram " }
#else
{ "vme-cpu/2 ram " }
diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c
index d152a78..ae66039 100644
--- a/board/freescale/common/pq-mds-pib.c
+++ b/board/freescale/common/pq-mds-pib.c
@@ -36,7 +36,7 @@
i2c_write(0x26, 0x6, 1, &val8, 1);
val8 = 0x34;
i2c_write(0x26, 0x7, 1, &val8, 1);
-#if defined(CONFIG_MPC832XEMDS)
+#if defined(CONFIG_TARGET_MPC832XEMDS)
val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
#else
val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */
@@ -55,7 +55,7 @@
eieio();
-#if defined(CONFIG_MPC832XEMDS)
+#if defined(CONFIG_TARGET_MPC832XEMDS)
printf("PCI 32bit bus on PMC2 &PMC3\n");
#else
printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
@@ -76,7 +76,7 @@
eieio();
printf("QOC3 ATM card on PMC0\n");
-#elif defined(CONFIG_MPC832XEMDS)
+#elif defined(CONFIG_TARGET_MPC832XEMDS)
val8 = 0;
i2c_write(0x26, 0x7, 1, &val8, 1);
val8 = 0xf7;
diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c
index e64b310..317e63e 100644
--- a/board/freescale/mpc8308rdb/sdram.c
+++ b/board/freescale/mpc8308rdb/sdram.c
@@ -33,7 +33,7 @@
u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar,
- CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
+ CONFIG_SYS_SDRAM_BASE & 0xfffff000);
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
@@ -61,7 +61,7 @@
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
sync();
- return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+ return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
}
int dram_init(void)
diff --git a/board/freescale/mpc8313erdb/Kconfig b/board/freescale/mpc8313erdb/Kconfig
index 145608f..b6332a1 100644
--- a/board/freescale/mpc8313erdb/Kconfig
+++ b/board/freescale/mpc8313erdb/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_MPC8313ERDB
+if TARGET_MPC8313ERDB_NOR
config SYS_BOARD
default "mpc8313erdb"
@@ -7,6 +7,19 @@
default "freescale"
config SYS_CONFIG_NAME
- default "MPC8313ERDB"
+ default "MPC8313ERDB_NOR"
+
+endif
+
+if TARGET_MPC8313ERDB_NAND
+
+config SYS_BOARD
+ default "mpc8313erdb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8313ERDB_NAND"
endif
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
index 5e074e3..c8e30a0 100644
--- a/board/freescale/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -47,7 +47,7 @@
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
@@ -57,12 +57,12 @@
*/
__udelay(50000);
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
im->ddr.csbnds[0].csbnds =
- ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+ ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
CSBNDS_EA);
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
@@ -109,8 +109,9 @@
msize = fixed_sdram();
/* Local Bus setup lbcr and mrtpr */
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+ lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF);
+ /* LB refresh timer prescal, 266MHz/32 */
+ lbc->mrtpr = 0x20000000;
sync();
#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
diff --git a/board/freescale/mpc8315erdb/MAINTAINERS b/board/freescale/mpc8315erdb/MAINTAINERS
index 5a67b40..cdac1ac 100644
--- a/board/freescale/mpc8315erdb/MAINTAINERS
+++ b/board/freescale/mpc8315erdb/MAINTAINERS
@@ -4,3 +4,4 @@
F: board/freescale/mpc8315erdb/
F: include/configs/MPC8315ERDB.h
F: configs/MPC8315ERDB_defconfig
+F: configs/MPC8315ERDB_NANDSPL_defconfig
diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c
index b9f94c8..2f0f29a 100644
--- a/board/freescale/mpc8315erdb/sdram.c
+++ b/board/freescale/mpc8315erdb/sdram.c
@@ -44,7 +44,7 @@
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
index 7726881..2dc6d7f 100644
--- a/board/freescale/mpc8323erdb/mpc8323erdb.c
+++ b/board/freescale/mpc8323erdb/mpc8323erdb.c
@@ -79,7 +79,7 @@
return -ENXIO;
/* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
msize = fixed_sdram();
diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c
index 869538f..61b95c6 100644
--- a/board/freescale/mpc832xemds/mpc832xemds.c
+++ b/board/freescale/mpc832xemds/mpc832xemds.c
@@ -98,7 +98,7 @@
return -ENXIO;
/* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
msize = fixed_sdram();
diff --git a/board/freescale/mpc8349emds/Kconfig b/board/freescale/mpc8349emds/Kconfig
index 51f0b34..d154118 100644
--- a/board/freescale/mpc8349emds/Kconfig
+++ b/board/freescale/mpc8349emds/Kconfig
@@ -10,3 +10,16 @@
default "MPC8349EMDS"
endif
+
+if TARGET_MPC8349EMDS_SDRAM
+
+config SYS_BOARD
+ default "mpc8349emds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8349EMDS_SDRAM"
+
+endif
diff --git a/board/freescale/mpc8349emds/MAINTAINERS b/board/freescale/mpc8349emds/MAINTAINERS
index e6648d6..a8f26a9 100644
--- a/board/freescale/mpc8349emds/MAINTAINERS
+++ b/board/freescale/mpc8349emds/MAINTAINERS
@@ -4,3 +4,6 @@
F: board/freescale/mpc8349emds/
F: include/configs/MPC8349EMDS.h
F: configs/MPC8349EMDS_defconfig
+F: configs/MPC8349EMDS_SDRAM_defconfig
+F: configs/MPC8349EMDS_PCI64_defconfig
+F: configs/MPC8349EMDS_SLAVE_defconfig
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index d40ed37..913b584 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -56,7 +56,7 @@
return -ENXIO;
/* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
#ifndef CONFIG_SYS_FSL_DDR2
msize = spd_sdram() * 1024 * 1024;
@@ -91,7 +91,7 @@
u32 ddr_size = msize << 20; /* DDR size in bytes */
u32 ddr_size_log2 = __ilog2(ddr_size);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256)
@@ -112,12 +112,12 @@
im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
#else
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
im->ddr.csbnds[2].csbnds =
- ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+ ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
CSBNDS_EA_SHIFT) & CSBNDS_EA);
im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
@@ -183,28 +183,36 @@
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbc_t *lbc = &immap->im_lbc;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-
+ const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
+ LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
+ LSDMR_WRC3 | LSDMR_CL3;
/*
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
*/
/* setup mtrpt, lsrt and lbcr for LB bus */
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
- lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ lbc->lbcr = 0x00000000;
+ /* LB refresh timer prescal, 266MHz/32 */
+ lbc->mrtpr = 0x20000000;
+ /* LB sdram refresh timer, about 6us */
+ lbc->lsrt = 0x32000000;
asm("sync");
/*
* Configure the SDRAM controller Machine Mode Register.
*/
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+ /* 0x40636733; normal operation */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+
+ /* 0x68636733; precharge all the banks */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+ /* 0x48636733; auto refresh */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync");
/*1 times*/
*sdram_addr = 0xff;
@@ -232,12 +240,13 @@
udelay(100);
/* 0x58636733; mode register write operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+ /* 0x40636733; normal operation */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c
index a2feda8..005190e 100644
--- a/board/freescale/mpc8349emds/pci.c
+++ b/board/freescale/mpc8349emds/pci.c
@@ -77,11 +77,11 @@
i2c_write(0x26, 0x6, 1, &val8, 1);
val8 = 0x34;
i2c_write(0x26, 0x7, 1, &val8, 1);
-#if defined(PCI_64BIT)
+#if defined(CONFIG_PCI_64BIT)
val8 = 0xf4; /* PMC2:PCI1/64-bit */
-#elif defined(PCI_ALL_PCI1)
+#elif defined(CONFIG_PCI_ALL_PCI1)
val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
-#elif defined(PCI_ONE_PCI1)
+#elif defined(CONFIG_PCI_ONE_PCI1)
val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
#else
val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
@@ -98,11 +98,11 @@
i2c_write(0x27, 0x3, 1, &val8, 1);
asm("eieio");
-#if defined(PCI_64BIT)
+#if defined(CONFIG_PCI_64BIT)
printf("PCI1: 64-bit on PMC2\n");
-#elif defined(PCI_ALL_PCI1)
+#elif defined(CONFIG_PCI_ALL_PCI1)
printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
-#elif defined(PCI_ONE_PCI1)
+#elif defined(CONFIG_PCI_ONE_PCI1)
printf("PCI1: 32-bit on PMC1\n");
printf("PCI2: 32-bit on PMC2, PMC3\n");
#else
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index 3bdec1c..81b3f00 100644
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -19,6 +19,9 @@
#include <linux/libfdt.h>
#endif
+#include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h"
+#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
+
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SPD_EEPROM
@@ -34,14 +37,14 @@
im->sysconf.ddrlaw[0].ar =
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
im->ddr.csbnds[0].csbnds =
- ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+ ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
CSBNDS_EA_SHIFT) & CSBNDS_EA);
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
@@ -129,7 +132,7 @@
return -ENXIO;
/* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
#ifdef CONFIG_SPD_EEPROM
msize = spd_sdram();
#else
@@ -152,7 +155,7 @@
int checkboard(void)
{
-#ifdef CONFIG_MPC8349ITX
+#ifdef CONFIG_TARGET_MPC8349ITX
puts("Board: Freescale MPC8349E-mITX\n");
#else
puts("Board: Freescale MPC8349E-mITX-GP\n");
diff --git a/board/freescale/mpc837xemds/MAINTAINERS b/board/freescale/mpc837xemds/MAINTAINERS
index 8386aa7..ce9c446 100644
--- a/board/freescale/mpc837xemds/MAINTAINERS
+++ b/board/freescale/mpc837xemds/MAINTAINERS
@@ -4,4 +4,5 @@
F: board/freescale/mpc837xemds/
F: include/configs/MPC837XEMDS.h
F: configs/MPC837XEMDS_defconfig
+F: configs/MPC837XEMDS_SLAVE_defconfig
F: configs/MPC837XEMDS_HOST_defconfig
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
index 09a046d..1692208 100644
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -252,7 +252,7 @@
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
#if (CONFIG_SYS_DDR_SIZE != 512)
diff --git a/board/freescale/mpc837xerdb/MAINTAINERS b/board/freescale/mpc837xerdb/MAINTAINERS
index 81b4eed..9f44a37 100644
--- a/board/freescale/mpc837xerdb/MAINTAINERS
+++ b/board/freescale/mpc837xerdb/MAINTAINERS
@@ -4,3 +4,4 @@
F: board/freescale/mpc837xerdb/
F: include/configs/MPC837XERDB.h
F: configs/MPC837XERDB_defconfig
+F: configs/MPC837XERDB_SLAVE_defconfig
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index d9a47b9..18f396a 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -95,7 +95,7 @@
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
index af9058a..7dfe104 100644
--- a/board/gdsys/common/Makefile
+++ b/board/gdsys/common/Makefile
@@ -5,16 +5,13 @@
obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o
-obj-$(CONFIG_IO) += miiphybb.o
-obj-$(CONFIG_IO64) += miiphybb.o
-obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o ch7301.o
-obj-$(CONFIG_DLVISION_10G) += osd.o dp501.o
obj-$(CONFIG_CONTROLCENTERD) += dp501.o
-obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o
-obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
-obj-$(CONFIG_STRIDER) += fanctrl.o
+obj-$(CONFIG_TARGET_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o
+obj-$(CONFIG_TARGET_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
+obj-$(CONFIG_TARGET_STRIDER) += fanctrl.o
obj-$(CONFIG_STRIDER_CON) += osd.o
obj-$(CONFIG_STRIDER_CON_DP) += osd.o
+obj-$(CONFIG_TARGET_GAZERBEAM) += osd.o ihs_mdio.o ioep-fpga.o
ifdef CONFIG_OSD
obj-$(CONFIG_GDSYS_LEGACY_OSD_CMDS) += osd_cmd.o
diff --git a/board/gdsys/common/adv7611.c b/board/gdsys/common/adv7611.c
index c416bf1..06cdc05 100644
--- a/board/gdsys/common/adv7611.c
+++ b/board/gdsys/common/adv7611.c
@@ -4,6 +4,8 @@
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+
#include <common.h>
#include <i2c.h>
@@ -174,3 +176,5 @@
return res;
}
+
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
diff --git a/board/gdsys/common/ch7301.c b/board/gdsys/common/ch7301.c
index 1234149..5e42467 100644
--- a/board/gdsys/common/ch7301.c
+++ b/board/gdsys/common/ch7301.c
@@ -6,6 +6,8 @@
/* Chrontel CH7301C DVI Transmitter */
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+
#include <common.h>
#include <asm/io.h>
#include <errno.h>
@@ -61,3 +63,5 @@
return 0;
}
+
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
diff --git a/board/gdsys/common/cmd_ioloop.c b/board/gdsys/common/cmd_ioloop.c
index 8e2f407..05a14ff 100644
--- a/board/gdsys/common/cmd_ioloop.c
+++ b/board/gdsys/common/cmd_ioloop.c
@@ -10,34 +10,53 @@
#include <gdsys_fpga.h>
+#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
+#include <dm.h>
+#include <misc.h>
+#include <regmap.h>
+#include <board.h>
+
+#include "../../../drivers/misc/gdsys_soc.h"
+#include "../../../drivers/misc/gdsys_ioep.h"
+#include "../../../drivers/misc/ihs_fpga.h"
+
+const int HEADER_WORDS = sizeof(struct io_generic_packet) / 2;
+#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
+
+enum status_print_type {
+ STATUS_LOUD = 0,
+ STATUS_SILENT = 1,
+};
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
enum {
- STATE_TX_PACKET_BUILDING = 1<<0,
- STATE_TX_TRANSMITTING = 1<<1,
- STATE_TX_BUFFER_FULL = 1<<2,
- STATE_TX_ERR = 1<<3,
- STATE_RECEIVE_TIMEOUT = 1<<4,
- STATE_PROC_RX_STORE_TIMEOUT = 1<<5,
- STATE_PROC_RX_RECEIVE_TIMEOUT = 1<<6,
- STATE_RX_DIST_ERR = 1<<7,
- STATE_RX_LENGTH_ERR = 1<<8,
- STATE_RX_FRAME_CTR_ERR = 1<<9,
- STATE_RX_FCS_ERR = 1<<10,
- STATE_RX_PACKET_DROPPED = 1<<11,
- STATE_RX_DATA_LAST = 1<<12,
- STATE_RX_DATA_FIRST = 1<<13,
- STATE_RX_DATA_AVAILABLE = 1<<15,
+ STATE_TX_PACKET_BUILDING = BIT(0),
+ STATE_TX_TRANSMITTING = BIT(1),
+ STATE_TX_BUFFER_FULL = BIT(2),
+ STATE_TX_ERR = BIT(3),
+ STATE_RECEIVE_TIMEOUT = BIT(4),
+ STATE_PROC_RX_STORE_TIMEOUT = BIT(5),
+ STATE_PROC_RX_RECEIVE_TIMEOUT = BIT(6),
+ STATE_RX_DIST_ERR = BIT(7),
+ STATE_RX_LENGTH_ERR = BIT(8),
+ STATE_RX_FRAME_CTR_ERR = BIT(9),
+ STATE_RX_FCS_ERR = BIT(10),
+ STATE_RX_PACKET_DROPPED = BIT(11),
+ STATE_RX_DATA_LAST = BIT(12),
+ STATE_RX_DATA_FIRST = BIT(13),
+ STATE_RX_DATA_AVAILABLE = BIT(15),
};
enum {
- CTRL_PROC_RECEIVE_ENABLE = 1<<12,
- CTRL_FLUSH_TRANSMIT_BUFFER = 1<<15,
+ IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = BIT(5),
+ IRQ_CPU_PACKET_TRANSMITTED_EVENT = BIT(6),
+ IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = BIT(7),
+ IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = BIT(8),
};
enum {
- IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = 1<<5,
- IRQ_CPU_PACKET_TRANSMITTED_EVENT = 1<<6,
- IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = 1<<7,
- IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = 1<<8,
+ CTRL_PROC_RECEIVE_ENABLE = BIT(12),
+ CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15),
};
struct io_generic_packet {
@@ -47,12 +66,17 @@
u8 bc;
u16 packet_length;
} __attribute__((__packed__));
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
unsigned long long rx_ctr;
unsigned long long tx_ctr;
unsigned long long err_ctr;
+#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
+struct udevice *dev;
+#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
-static void io_check_status(unsigned int fpga, u16 status, bool silent)
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+static void io_check_status(uint fpga, u16 status, enum status_print_type type)
{
u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR |
STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR |
@@ -66,7 +90,7 @@
err_ctr++;
FPGA_SET_REG(fpga, ep.rx_tx_status, status);
- if (silent)
+ if (type == STATUS_SILENT)
return;
if (status & STATE_RX_PACKET_DROPPED)
@@ -84,10 +108,42 @@
if (status & STATE_TX_ERR)
printf("TX_ERR\n");
}
+#else
+static void io_check_status(struct udevice *dev, enum status_print_type type)
+{
+ u16 status = 0;
+ int ret;
-static void io_send(unsigned int fpga, unsigned int size)
+ ret = misc_call(dev, 0, NULL, 0, &status, 0);
+ if (!ret)
+ return;
+
+ err_ctr++;
+
+ if (type != STATUS_LOUD)
+ return;
+
+ if (status & STATE_RX_PACKET_DROPPED)
+ printf("RX_PACKET_DROPPED, status %04x\n", status);
+
+ if (status & STATE_RX_DIST_ERR)
+ printf("RX_DIST_ERR\n");
+ if (status & STATE_RX_LENGTH_ERR)
+ printf("RX_LENGTH_ERR\n");
+ if (status & STATE_RX_FRAME_CTR_ERR)
+ printf("RX_FRAME_CTR_ERR\n");
+ if (status & STATE_RX_FCS_ERR)
+ printf("RX_FCS_ERR\n");
+
+ if (status & STATE_TX_ERR)
+ printf("TX_ERR\n");
+}
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+static void io_send(uint fpga, uint size)
{
- unsigned int k;
+ uint k;
struct io_generic_packet packet = {
.source_address = 1,
.packet_type = 1,
@@ -106,10 +162,31 @@
tx_ctr++;
}
+#else
+static void io_send(struct udevice *dev, uint size)
+{
+ uint k;
+ u16 buffer[HEADER_WORDS + 128];
+ struct io_generic_packet header = {
+ .source_address = 1,
+ .packet_type = 1,
+ .packet_length = size,
+ };
+ const uint words = (size + 1) / 2;
+
+ memcpy(buffer, &header, 2 * HEADER_WORDS);
+ for (k = 0; k < words; ++k)
+ buffer[k + HEADER_WORDS] = (2 * k + 1) + ((2 * k) << 8);
+
+ misc_write(dev, 0, buffer, HEADER_WORDS + words);
+
+ tx_ctr++;
+}
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
-static void io_receive(unsigned int fpga)
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+static void io_receive(uint fpga)
{
- unsigned int k = 0;
u16 rx_tx_status;
FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
@@ -123,17 +200,25 @@
FPGA_GET_REG(fpga, ep.receive_data, &rx);
FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
-
- ++k;
}
}
+#else
+static void io_receive(struct udevice *dev)
+{
+ u16 buffer[HEADER_WORDS + 128];
-static void io_reflect(unsigned int fpga)
+ if (!misc_read(dev, 0, buffer, 0))
+ rx_ctr++;
+}
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+static void io_reflect(uint fpga)
{
u16 buffer[128];
- unsigned int k = 0;
- unsigned int n;
+ uint k = 0;
+ uint n;
u16 rx_tx_status;
FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
@@ -157,7 +242,22 @@
tx_ctr++;
}
+#else
+static void io_reflect(struct udevice *dev)
+{
+ u16 buffer[HEADER_WORDS + 128];
+ struct io_generic_packet *header;
+
+ if (misc_read(dev, 0, buffer, 0))
+ return;
+
+ header = (struct io_generic_packet *)&buffer;
+
+ misc_write(dev, 0, buffer, HEADER_WORDS + header->packet_length);
+}
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
/*
* FPGA io-endpoint reflector
*
@@ -166,8 +266,8 @@
*/
int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- unsigned int fpga;
- unsigned int rate = 0;
+ uint fpga;
+ uint rate = 0;
unsigned long long last_seen = 0;
if (argc < 2)
@@ -181,10 +281,10 @@
if (argc > 2)
rate = simple_strtoul(argv[2], NULL, 10);
- /* enable receive path */
+ /* Enable receive path */
FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
- /* set device address to dummy 1*/
+ /* Set device address to dummy 1*/
FPGA_SET_REG(fpga, ep.device_address, 1);
rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
@@ -196,7 +296,7 @@
FPGA_GET_REG(fpga, top_interrupt, &top_int);
FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
- io_check_status(fpga, rx_tx_status, true);
+ io_check_status(fpga, rx_tx_status, STATUS_SILENT);
if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
(top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
io_reflect(fpga);
@@ -214,19 +314,71 @@
return 0;
}
+#else
+/*
+ * FPGA io-endpoint reflector
+ *
+ * Syntax:
+ * ioreflect {reportrate}
+ */
+int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct udevice *fpga;
+ struct regmap *map;
+ uint rate = 0;
+ unsigned long long last_seen = 0;
+
+ if (!dev) {
+ printf("No device selected\n");
+ return 1;
+ }
+
+ gdsys_soc_get_fpga(dev, &fpga);
+ regmap_init_mem(dev_ofnode(dev), &map);
+ /* Enable receive path */
+ misc_set_enabled(dev, true);
+
+ rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
+
+ while (1) {
+ uint top_int;
+
+ ihs_fpga_get(map, top_interrupt, &top_int);
+ io_check_status(dev, STATUS_SILENT);
+ if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
+ (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
+ io_reflect(dev);
+
+ if (rate) {
+ if (!(tx_ctr % rate) && (tx_ctr != last_seen))
+ printf("refl %llu, err %llu\n", tx_ctr,
+ err_ctr);
+ last_seen = tx_ctr;
+ }
+
+ if (ctrlc())
+ break;
+ }
+
+ return 0;
+}
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
+
+#define DISP_LINE_LEN 16
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
/*
* FPGA io-endpoint looptest
*
* Syntax:
* ioloop {fpga} {size} {rate}
*/
-#define DISP_LINE_LEN 16
int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- unsigned int fpga;
- unsigned int size;
- unsigned int rate = 0;
+ uint fpga;
+ uint size;
+ uint rate = 0;
if (argc < 3)
return CMD_RET_USAGE;
@@ -262,7 +414,7 @@
FPGA_GET_REG(fpga, top_interrupt, &top_int);
FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
- io_check_status(fpga, rx_tx_status, false);
+ io_check_status(fpga, rx_tx_status, STATUS_LOUD);
if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
io_send(fpga, size);
if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
@@ -273,15 +425,130 @@
break;
udelay(1000000 / rate);
if (!(tx_ctr % rate))
+ printf("d %llu, tx %llu, rx %llu, err %llu\n",
+ tx_ctr - rx_ctr, tx_ctr, rx_ctr,
+ err_ctr);
+ }
+ }
+
+ return 0;
+}
+#else
+/*
+ * FPGA io-endpoint looptest
+ *
+ * Syntax:
+ * ioloop {size} {rate}
+ */
+int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ uint size;
+ uint rate = 0;
+ struct udevice *fpga;
+ struct regmap *map;
+
+ if (!dev) {
+ printf("No device selected\n");
+ return 1;
+ }
+
+ gdsys_soc_get_fpga(dev, &fpga);
+ regmap_init_mem(dev_ofnode(dev), &map);
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ /*
+ * packet size is specified since argc > 1
+ */
+ size = simple_strtoul(argv[2], NULL, 10);
+
+ /*
+ * If another parameter, it is the test rate in packets per second.
+ */
+ if (argc > 2)
+ rate = simple_strtoul(argv[3], NULL, 10);
+
+ /* Enable receive path */
+ misc_set_enabled(dev, true);
+
+ rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
+
+ while (1) {
+ uint top_int;
+
+ if (ctrlc())
+ break;
+
+ ihs_fpga_get(map, top_interrupt, &top_int);
+
+ io_check_status(dev, STATUS_LOUD);
+ if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
+ io_send(dev, size);
+ if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
+ io_receive(dev);
+
+ if (rate) {
+ udelay(1000000 / rate);
+ if (!(tx_ctr % rate))
- printf("d %lld, tx %llu, rx %llu, err %llu\n",
+ printf("d %llu, tx %llu, rx %llu, err %llu\n",
tx_ctr - rx_ctr, tx_ctr, rx_ctr,
err_ctr);
}
+ }
+ return 0;
+}
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
+
+#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
+int do_iodev(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct udevice *ioep = NULL;
+ struct udevice *board;
+ char name[8];
+ int ret;
+
+ if (board_get(&board))
+ return CMD_RET_FAILURE;
+
+ if (argc > 1) {
+ int i = simple_strtoul(argv[1], NULL, 10);
+
+ snprintf(name, sizeof(name), "ioep%d", i);
+
+ ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &ioep);
+
+ if (ret || !ioep) {
+ printf("Invalid IOEP %d\n", i);
+ return CMD_RET_FAILURE;
+ }
+
+ dev = ioep;
+ } else {
+ int i = 0;
+
+ while (1) {
+ snprintf(name, sizeof(name), "ioep%d", i);
+
+ ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &ioep);
+
+ if (ret || !ioep)
+ break;
+
+ printf("IOEP %d:\t%s\n", i++, ioep->name);
+ }
+
+ if (dev)
+ printf("\nSelected IOEP: %s\n", dev->name);
+ else
+ puts("\nNo IOEP selected.\n");
}
return 0;
}
+#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
U_BOOT_CMD(
ioloop, 4, 0, do_ioloop,
"fpga io-endpoint looptest",
@@ -293,3 +560,22 @@
"fpga io-endpoint reflector",
"fpga reportrate"
);
+#else
+U_BOOT_CMD(
+ ioloop, 3, 0, do_ioloop,
+ "fpga io-endpoint looptest",
+ "packetsize [packets/sec]"
+);
+
+U_BOOT_CMD(
+ ioreflect, 2, 0, do_ioreflect,
+ "fpga io-endpoint reflector",
+ "reportrate"
+);
+
+U_BOOT_CMD(
+ iodev, 2, 0, do_iodev,
+ "fpga io-endpoint listing/selection",
+ "[ioep device to select]"
+);
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c
index 69d4b8c..9ca69eb 100644
--- a/board/gdsys/common/dp501.c
+++ b/board/gdsys/common/dp501.c
@@ -6,6 +6,8 @@
/* Parade Technologies Inc. DP501 DisplayPort DVI/HDMI Transmitter */
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+
#include <common.h>
#include <asm/io.h>
#include <errno.h>
@@ -155,3 +157,5 @@
return 0;
}
+
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
diff --git a/board/gdsys/common/fanctrl.c b/board/gdsys/common/fanctrl.c
index 5e77683..27c875c 100644
--- a/board/gdsys/common/fanctrl.c
+++ b/board/gdsys/common/fanctrl.c
@@ -4,6 +4,8 @@
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+
#include <common.h>
#include <i2c.h>
@@ -29,3 +31,5 @@
val = i2c_reg_read(addr, FAN_CONFIG) | 0x04;
i2c_reg_write(addr, FAN_CONFIG, val);
}
+
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
diff --git a/board/gdsys/common/fpga.c b/board/gdsys/common/fpga.c
index f189e5f..5ba6613 100644
--- a/board/gdsys/common/fpga.c
+++ b/board/gdsys/common/fpga.c
@@ -4,6 +4,8 @@
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+
#include <common.h>
#include <gdsys_fpga.h>
@@ -22,3 +24,5 @@
return 0;
}
+
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
diff --git a/board/gdsys/common/ihs_mdio.c b/board/gdsys/common/ihs_mdio.c
index b17e8db..f160a57 100644
--- a/board/gdsys/common/ihs_mdio.c
+++ b/board/gdsys/common/ihs_mdio.c
@@ -11,6 +11,7 @@
#include <gdsys_fpga.h>
#else
#include <fdtdec.h>
+#include <dm.h>
#include <regmap.h>
#endif
@@ -28,7 +29,7 @@
struct regmap *map;
u8 *ptr;
- regmap_init_mem(fpga, &map);
+ regmap_init_mem(dev_ofnode(fpga), &map);
ptr = regmap_get_range(map, 0);
return in_le16((u16 *)(ptr + base + addr));
@@ -40,7 +41,7 @@
struct regmap *map;
u8 *ptr;
- regmap_init_mem(fpga, &map);
+ regmap_init_mem(dev_ofnode(fpga), &map);
ptr = regmap_get_range(map, 0);
out_le16((u16 *)(ptr + base + addr), val);
diff --git a/board/gdsys/common/ioep-fpga.c b/board/gdsys/common/ioep-fpga.c
index 8e10501..066222c 100644
--- a/board/gdsys/common/ioep-fpga.c
+++ b/board/gdsys/common/ioep-fpga.c
@@ -4,233 +4,586 @@
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+
#include <common.h>
#include <gdsys_fpga.h>
-enum {
- UNITTYPE_MAIN_SERVER = 0,
- UNITTYPE_MAIN_USER = 1,
- UNITTYPE_VIDEO_SERVER = 2,
- UNITTYPE_VIDEO_USER = 3,
+enum pcb_video_type {
+ PCB_DVI_SL,
+ PCB_DP_165MPIX,
+ PCB_DP_300MPIX,
+ PCB_HDMI,
+ PCB_DP_1_2,
+ PCB_HDMI_2_0,
};
-enum {
- UNITTYPEPCB_DVI = 0,
- UNITTYPEPCB_DP_165 = 1,
- UNITTYPEPCB_DP_300 = 2,
- UNITTYPEPCB_HDMI = 3,
+enum pcb_transmission_type {
+ PCB_CAT_1G,
+ PCB_FIBER_3G,
+ PCB_CAT_10G,
+ PCB_FIBER_10G,
};
-enum {
- COMPRESSION_NONE = 0,
- COMPRESSION_TYPE_1 = 1,
- COMPRESSION_TYPE_1_2 = 3,
- COMPRESSION_TYPE_1_2_3 = 7,
+enum carrier_speed {
+ CARRIER_SPEED_1G,
+ CARRIER_SPEED_3G,
+ CARRIER_SPEED_2_5G = CARRIER_SPEED_3G,
+ CARRIER_SPEED_10G,
};
-enum {
- AUDIO_NONE = 0,
- AUDIO_TX = 1,
- AUDIO_RX = 2,
- AUDIO_RXTX = 3,
+enum ram_config {
+ RAM_DDR2_32BIT_295MBPS,
+ RAM_DDR3_32BIT_590MBPS,
+ RAM_DDR3_48BIT_590MBPS,
+ RAM_DDR3_64BIT_1800MBPS,
+ RAM_DDR3_48BIT_1800MBPS,
};
-enum {
- SYSCLK_147456 = 0,
+enum sysclock {
+ SYSCLK_147456,
};
-enum {
- RAM_DDR2_32 = 0,
- RAM_DDR3_32 = 1,
- RAM_DDR3_48 = 2,
+struct fpga_versions {
+ bool video_channel;
+ bool con_side;
+ enum pcb_video_type pcb_video_type;
+ enum pcb_transmission_type pcb_transmission_type;
+ unsigned int hw_version;
};
-enum {
- CARRIER_SPEED_1G = 0,
- CARRIER_SPEED_2_5G = 1,
+struct fpga_features {
+ u8 video_channels;
+ u8 carriers;
+ enum carrier_speed carrier_speed;
+ enum ram_config ram_config;
+ enum sysclock sysclock;
+
+ bool pcm_tx;
+ bool pcm_rx;
+ bool spdif_tx;
+ bool spdif_rx;
+ bool usb2;
+ bool rs232;
+ bool compression_type1;
+ bool compression_type2;
+ bool compression_type3;
+ bool interlace;
+ bool osd;
+ bool compression_pipes;
};
-bool ioep_fpga_has_osd(unsigned int fpga)
+#ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM
+
+static int get_versions(unsigned int fpga, struct fpga_versions *versions)
{
- u16 fpga_features;
- unsigned feature_osd;
+ enum {
+ VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12),
+ VERSIONS_FPGA_CON_SIDE = BIT(13),
+ VERSIONS_FPGA_SC = BIT(14),
+ VERSIONS_PCB_CON = BIT(9),
+ VERSIONS_PCB_SC = BIT(8),
+ VERSIONS_PCB_VIDEO_MASK = 0x3 << 6,
+ VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6,
+ VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6,
+ VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4,
+ VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4,
+ VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4,
+ VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4,
+ VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4,
+ VERSIONS_HW_VER_MASK = 0xf << 0,
+ };
+ u16 raw_versions;
+
+ memset(versions, 0, sizeof(struct fpga_versions));
+
+ FPGA_GET_REG(fpga, versions, &raw_versions);
+
+ versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL;
+ versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE;
+
+ switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) {
+ case VERSIONS_PCB_VIDEO_DP_1_2:
+ versions->pcb_video_type = PCB_DP_1_2;
+ break;
+
+ case VERSIONS_PCB_VIDEO_HDMI_2_0:
+ versions->pcb_video_type = PCB_HDMI_2_0;
+ break;
+ }
+
+ switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) {
+ case VERSIONS_PCB_TRANSMISSION_FIBER_10G:
+ versions->pcb_transmission_type = PCB_FIBER_10G;
+ break;
+
+ case VERSIONS_PCB_TRANSMISSION_CAT_10G:
+ versions->pcb_transmission_type = PCB_CAT_10G;
+ break;
+
+ case VERSIONS_PCB_TRANSMISSION_FIBER_3G:
+ versions->pcb_transmission_type = PCB_FIBER_3G;
+ break;
- FPGA_GET_REG(0, fpga_features, &fpga_features);
- feature_osd = fpga_features & (1<<11);
+ case VERSIONS_PCB_TRANSMISSION_CAT_1G:
+ versions->pcb_transmission_type = PCB_CAT_1G;
+ break;
+
+ }
- return feature_osd;
+ versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
+
+ return 0;
}
-void ioep_fpga_print_info(unsigned int fpga)
+static int get_features(unsigned int fpga, struct fpga_features *features)
{
- u16 versions;
- u16 fpga_version;
- u16 fpga_features;
- unsigned unit_type;
- unsigned unit_type_pcb_video;
- unsigned feature_compression;
- unsigned feature_osd;
- unsigned feature_audio;
- unsigned feature_sysclock;
- unsigned feature_ramconfig;
- unsigned feature_carrier_speed;
- unsigned feature_carriers;
- unsigned feature_video_channels;
+ enum {
+ FEATURE_SPDIF_RX = BIT(15),
+ FEATURE_SPDIF_TX = BIT(14),
+ FEATURE_PCM_RX = BIT(13),
+ FEATURE_PCM_TX = BIT(12),
+ FEATURE_RAM_MASK = GENMASK(11, 8),
+ FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8,
+ FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8,
+ FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8,
+ FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8,
+ FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8,
+ FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6),
+ FEATURE_CARRIER_SPEED_1G = 0x0 << 6,
+ FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6,
+ FEATURE_CARRIER_SPEED_10G = 0x2 << 6,
+ FEATURE_CARRIERS_MASK = GENMASK(5, 4),
+ FEATURE_CARRIERS_0 = 0x0 << 4,
+ FEATURE_CARRIERS_1 = 0x1 << 4,
+ FEATURE_CARRIERS_2 = 0x2 << 4,
+ FEATURE_CARRIERS_4 = 0x3 << 4,
+ FEATURE_USB2 = BIT(3),
+ FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0),
+ FEATURE_VIDEOCHANNELS_0 = 0x0 << 0,
+ FEATURE_VIDEOCHANNELS_1 = 0x1 << 0,
+ FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0,
+ FEATURE_VIDEOCHANNELS_2 = 0x3 << 0,
+ };
- FPGA_GET_REG(fpga, versions, &versions);
- FPGA_GET_REG(fpga, fpga_version, &fpga_version);
- FPGA_GET_REG(fpga, fpga_features, &fpga_features);
+ enum {
+ EXT_FEATURE_OSD = BIT(15),
+ EXT_FEATURE_ETHERNET = BIT(9),
+ EXT_FEATURE_INTERLACE = BIT(8),
+ EXT_FEATURE_RS232 = BIT(7),
+ EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4),
+ EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4,
+ EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4,
+ EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4,
+ EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0),
+ EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1),
+ EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2),
+ };
- unit_type = (versions & 0xf000) >> 12;
- unit_type_pcb_video = (versions & 0x01c0) >> 6;
- feature_compression = (fpga_features & 0xe000) >> 13;
- feature_osd = fpga_features & (1<<11);
- feature_audio = (fpga_features & 0x0600) >> 9;
- feature_sysclock = (fpga_features & 0x0180) >> 7;
- feature_ramconfig = (fpga_features & 0x0060) >> 5;
- feature_carrier_speed = fpga_features & (1<<4);
- feature_carriers = (fpga_features & 0x000c) >> 2;
- feature_video_channels = fpga_features & 0x0003;
+ u16 raw_features;
+ u16 raw_extended_features;
- switch (unit_type) {
- case UNITTYPE_MAIN_SERVER:
- case UNITTYPE_MAIN_USER:
- printf("Mainchannel");
+ memset(features, 0, sizeof(struct fpga_features));
+
+ FPGA_GET_REG(fpga, fpga_features, &raw_features);
+ FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
+
+ switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) {
+ case FEATURE_VIDEOCHANNELS_0:
+ features->video_channels = 0;
break;
- case UNITTYPE_VIDEO_SERVER:
- case UNITTYPE_VIDEO_USER:
- printf("Videochannel");
+ case FEATURE_VIDEOCHANNELS_1:
+ features->video_channels = 1;
break;
- default:
- printf("UnitType %d(not supported)", unit_type);
+ case FEATURE_VIDEOCHANNELS_1_1:
+ case FEATURE_VIDEOCHANNELS_2:
+ features->video_channels = 2;
break;
- }
+ };
- switch (unit_type) {
- case UNITTYPE_MAIN_SERVER:
- case UNITTYPE_VIDEO_SERVER:
- printf(" Server");
- if (versions & (1<<4))
- printf(" UC");
+ switch (raw_features & FEATURE_CARRIERS_MASK) {
+ case FEATURE_CARRIERS_0:
+ features->carriers = 0;
break;
- case UNITTYPE_MAIN_USER:
- case UNITTYPE_VIDEO_USER:
- printf(" User");
+ case FEATURE_CARRIERS_1:
+ features->carriers = 1;
break;
- default:
+ case FEATURE_CARRIERS_2:
+ features->carriers = 2;
+ break;
+
+ case FEATURE_CARRIERS_4:
+ features->carriers = 4;
break;
}
- if (versions & (1<<5))
- printf(" Fiber");
- else
- printf(" CAT");
+ switch (raw_features & FEATURE_CARRIER_SPEED_MASK) {
+ case FEATURE_CARRIER_SPEED_1G:
+ features->carrier_speed = CARRIER_SPEED_1G;
+ break;
+ case FEATURE_CARRIER_SPEED_2_5G:
+ features->carrier_speed = CARRIER_SPEED_2_5G;
+ break;
+ case FEATURE_CARRIER_SPEED_10G:
+ features->carrier_speed = CARRIER_SPEED_10G;
+ break;
+ }
- switch (unit_type_pcb_video) {
- case UNITTYPEPCB_DVI:
- printf(" DVI,");
+ switch (raw_features & FEATURE_RAM_MASK) {
+ case FEATURE_RAM_DDR2_32BIT_295MBPS:
+ features->ram_config = RAM_DDR2_32BIT_295MBPS;
break;
- case UNITTYPEPCB_DP_165:
- printf(" DP 165MPix/s,");
+ case FEATURE_RAM_DDR3_32BIT_590MBPS:
+ features->ram_config = RAM_DDR3_32BIT_590MBPS;
break;
- case UNITTYPEPCB_DP_300:
- printf(" DP 300MPix/s,");
+ case FEATURE_RAM_DDR3_48BIT_590MBPS:
+ features->ram_config = RAM_DDR3_48BIT_590MBPS;
break;
- case UNITTYPEPCB_HDMI:
- printf(" HDMI,");
+ case FEATURE_RAM_DDR3_64BIT_1800MBPS:
+ features->ram_config = RAM_DDR3_64BIT_1800MBPS;
+ break;
+
+ case FEATURE_RAM_DDR3_48BIT_1800MBPS:
+ features->ram_config = RAM_DDR3_48BIT_1800MBPS;
break;
}
- printf(" FPGA V %d.%02d\n features:",
- fpga_version / 100, fpga_version % 100);
+ features->pcm_tx = raw_features & FEATURE_PCM_TX;
+ features->pcm_rx = raw_features & FEATURE_PCM_RX;
+ features->spdif_tx = raw_features & FEATURE_SPDIF_TX;
+ features->spdif_rx = raw_features & FEATURE_SPDIF_RX;
+ features->usb2 = raw_features & FEATURE_USB2;
+ features->rs232 = raw_extended_features & EXT_FEATURE_RS232;
+ features->compression_type1 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE1;
+ features->compression_type2 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE2;
+ features->compression_type3 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE3;
+ features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE;
+ features->osd = raw_extended_features & EXT_FEATURE_OSD;
+ features->compression_pipes = raw_extended_features & EXT_FEATURE_COMPRESSION_PERF_MASK;
+ return 0;
+}
+
+#else
+
+static int get_versions(unsigned int fpga, struct fpga_versions *versions)
+{
+ enum {
+ /* HW version encoding is a mess, leave it for the moment */
+ VERSIONS_HW_VER_MASK = 0xf << 0,
+ VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4),
+ VERSIONS_SFP = BIT(5),
+ VERSIONS_VIDEO_MASK = 0x7 << 6,
+ VERSIONS_VIDEO_DVI = 0x0 << 6,
+ VERSIONS_VIDEO_DP_165 = 0x1 << 6,
+ VERSIONS_VIDEO_DP_300 = 0x2 << 6,
+ VERSIONS_VIDEO_HDMI = 0x3 << 6,
+ VERSIONS_UT_MASK = 0xf << 12,
+ VERSIONS_UT_MAIN_SERVER = 0x0 << 12,
+ VERSIONS_UT_MAIN_USER = 0x1 << 12,
+ VERSIONS_UT_VIDEO_SERVER = 0x2 << 12,
+ VERSIONS_UT_VIDEO_USER = 0x3 << 12,
+ };
+ u16 raw_versions;
- switch (feature_compression) {
- case COMPRESSION_NONE:
- printf(" no compression");
+ memset(versions, 0, sizeof(struct fpga_versions));
+
+ FPGA_GET_REG(fpga, versions, &raw_versions);
+
+ switch (raw_versions & VERSIONS_UT_MASK) {
+ case VERSIONS_UT_MAIN_SERVER:
+ versions->video_channel = false;
+ versions->con_side = false;
break;
- case COMPRESSION_TYPE_1:
- printf(" compression type1(delta)");
+ case VERSIONS_UT_MAIN_USER:
+ versions->video_channel = false;
+ versions->con_side = true;
break;
- case COMPRESSION_TYPE_1_2:
- printf(" compression type1(delta), type2(inline)");
+ case VERSIONS_UT_VIDEO_SERVER:
+ versions->video_channel = true;
+ versions->con_side = false;
break;
- case COMPRESSION_TYPE_1_2_3:
- printf(" compression type1(delta), type2(inline), type3(intempo)");
+ case VERSIONS_UT_VIDEO_USER:
+ versions->video_channel = true;
+ versions->con_side = true;
break;
- default:
- printf(" compression %d(not supported)", feature_compression);
+ }
+
+ switch (raw_versions & VERSIONS_VIDEO_MASK) {
+ case VERSIONS_VIDEO_DVI:
+ versions->pcb_video_type = PCB_DVI_SL;
+ break;
+
+ case VERSIONS_VIDEO_DP_165:
+ versions->pcb_video_type = PCB_DP_165MPIX;
+ break;
+
+ case VERSIONS_VIDEO_DP_300:
+ versions->pcb_video_type = PCB_DP_300MPIX;
+ break;
+
+ case VERSIONS_VIDEO_HDMI:
+ versions->pcb_video_type = PCB_HDMI;
break;
}
+ versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
+
+ if (raw_versions & VERSIONS_SFP)
+ versions->pcb_transmission_type = PCB_FIBER_3G;
+ else
+ versions->pcb_transmission_type = PCB_CAT_1G;
+
- printf(", %sosd", feature_osd ? "" : "no ");
+ return 0;
+}
+
+static int get_features(unsigned int fpga, struct fpga_features *features)
+{
+ enum {
+ FEATURE_CARRIER_SPEED_2_5 = BIT(4),
+ FEATURE_RAM_MASK = 0x7 << 5,
+ FEATURE_RAM_DDR2_32BIT = 0x0 << 5,
+ FEATURE_RAM_DDR3_32BIT = 0x1 << 5,
+ FEATURE_RAM_DDR3_48BIT = 0x2 << 5,
+ FEATURE_PCM_AUDIO_TX = BIT(9),
+ FEATURE_PCM_AUDIO_RX = BIT(10),
+ FEATURE_OSD = BIT(11),
+ FEATURE_USB20 = BIT(12),
+ FEATURE_COMPRESSION_MASK = 7 << 13,
+ FEATURE_COMPRESSION_TYPE1 = 0x1 << 13,
+ FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13,
+ FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13,
+ };
+
+ enum {
+ EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0),
+ EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1),
+ EXTENDED_FEATURE_RS232 = BIT(2),
+ EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3),
+ EXTENDED_FEATURE_INTERLACE = BIT(4),
+ };
- switch (feature_audio) {
- case AUDIO_NONE:
- printf(", no audio");
+ u16 raw_features;
+#ifdef GDSYS_LEGACY_DRIVERS
+ u16 raw_extended_features;
+#endif
+
+ memset(features, 0, sizeof(struct fpga_features));
+
+ FPGA_GET_REG(fpga, fpga_features, &raw_features);
+#ifdef GDSYS_LEGACY_DRIVERS
+ FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
+#endif
+
+ features->video_channels = raw_features & 0x3;
+ features->carriers = (raw_features >> 2) & 0x3;
+
+ features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5)
+ ? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G;
+
+ switch (raw_features & FEATURE_RAM_MASK) {
+ case FEATURE_RAM_DDR2_32BIT:
+ features->ram_config = RAM_DDR2_32BIT_295MBPS;
break;
- case AUDIO_TX:
- printf(", audio tx");
+ case FEATURE_RAM_DDR3_32BIT:
+ features->ram_config = RAM_DDR3_32BIT_590MBPS;
break;
+ case FEATURE_RAM_DDR3_48BIT:
+ features->ram_config = RAM_DDR3_48BIT_590MBPS;
+ break;
+ }
+
+ features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX;
+ features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX;
+#ifdef GDSYS_LEGACY_DRIVERS
+ features->spdif_tx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_TX;
+ features->spdif_rx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_RX;
+#endif
+
- case AUDIO_RX:
- printf(", audio rx");
+ features->usb2 = raw_features & FEATURE_USB20;
+#ifdef GDSYS_LEGACY_DRIVERS
+ features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232;
+#endif
+
+ features->compression_type1 = false;
+ features->compression_type2 = false;
+ features->compression_type3 = false;
+ switch (raw_features & FEATURE_COMPRESSION_MASK) {
+ case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3:
+ features->compression_type3 = true;
+ case FEATURE_COMPRESSION_TYPE1_TYPE2:
+ features->compression_type2 = true;
+ case FEATURE_COMPRESSION_TYPE1:
+ features->compression_type1 = true;
break;
+ }
+
+#ifdef GDSYS_LEGACY_DRIVERS
+ features->interlace = raw_extended_features & EXTENDED_FEATURE_INTERLACE;
+#endif
+ features->osd = raw_features & FEATURE_OSD;
+#ifdef GDSYS_LEGACY_DRIVERS
+ features->compression_pipes = raw_extended_features & EXTENDED_FEATURE_COMPRESSION_PIPES;
+#endif
+
+ return 0;
+}
+
+#endif
+
+bool ioep_fpga_has_osd(unsigned int fpga)
+{
+ struct fpga_features features;
+
+ get_features(fpga, &features);
+
+ return features.osd;
+}
+
+void ioep_fpga_print_info(unsigned int fpga)
+{
+ u16 fpga_version;
+ struct fpga_versions versions;
+ struct fpga_features features;
+
+ FPGA_GET_REG(fpga, fpga_version, &fpga_version);
+ get_versions(fpga, &versions);
+ get_features(fpga, &features);
+
+ if (versions.video_channel)
+ printf("Videochannel");
+ else
+ printf("Mainchannel");
+
+ if (versions.con_side)
+ printf(" User");
+ else
+ printf(" Server");
- case AUDIO_RXTX:
- printf(", audio rx+tx");
+// FIXME
+#if 0
+ if (versions & (1<<4))
+ printf(" UC");
+#endif
+
+ switch(versions.pcb_transmission_type) {
+ case PCB_CAT_1G:
+ case PCB_CAT_10G:
+ printf(" CAT");
break;
+ case PCB_FIBER_3G:
+ case PCB_FIBER_10G:
+ printf(" Fiber");
+ break;
+ };
- default:
- printf(", audio %d(not supported)", feature_audio);
+ switch (versions.pcb_video_type) {
+ case PCB_DVI_SL:
+ printf(" DVI,");
+ break;
+ case PCB_DP_165MPIX:
+ printf(" DP 165MPix/s,");
+ break;
+ case PCB_DP_300MPIX:
+ printf(" DP 300MPix/s,");
+ break;
+ case PCB_HDMI:
+ printf(" HDMI,");
+ break;
+ case PCB_DP_1_2:
+ printf(" DP 1.2,");
+ break;
+ case PCB_HDMI_2_0:
+ printf(" HDMI 2.0,");
break;
}
+ printf(" FPGA V %d.%02d\n features: ",
+ fpga_version / 100, fpga_version % 100);
+
+ if (!features.compression_type1 &&
+ !features.compression_type2 &&
+ !features.compression_type3)
+ printf("no compression, ");
+
+ if (features.compression_type1)
+ printf("type1, ");
+
+ if (features.compression_type2)
+ printf("type2, ");
+
+ if (features.compression_type3)
+ printf("type3, ");
+
+ printf("%sosd", features.osd ? "" : "no ");
+
+ if (features.pcm_rx && features.pcm_tx)
+ printf(", pcm rx+tx");
+ else if(features.pcm_rx)
+ printf(", pcm rx");
+ else if(features.pcm_tx)
+ printf(", pcm tx");
+
+ if (features.spdif_rx && features.spdif_tx)
+ printf(", spdif rx+tx");
+ else if(features.spdif_rx)
+ printf(", spdif rx");
+ else if(features.spdif_tx)
+ printf(", spdif tx");
+
puts(",\n ");
- switch (feature_sysclock) {
+ switch (features.sysclock) {
case SYSCLK_147456:
printf("clock 147.456 MHz");
break;
-
- default:
- printf("clock %d(not supported)", feature_sysclock);
- break;
}
- switch (feature_ramconfig) {
- case RAM_DDR2_32:
+ switch (features.ram_config) {
+ case RAM_DDR2_32BIT_295MBPS:
printf(", RAM 32 bit DDR2");
break;
-
- case RAM_DDR3_32:
+ case RAM_DDR3_32BIT_590MBPS:
printf(", RAM 32 bit DDR3");
break;
-
- case RAM_DDR3_48:
+ case RAM_DDR3_48BIT_590MBPS:
+ case RAM_DDR3_48BIT_1800MBPS:
printf(", RAM 48 bit DDR3");
break;
-
- default:
- printf(", RAM %d(not supported)", feature_ramconfig);
+ case RAM_DDR3_64BIT_1800MBPS:
+ printf(", RAM 64 bit DDR3");
break;
}
- printf(", %d carrier(s) %s", feature_carriers,
- feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
+ printf(", %d carrier(s)", features.carriers);
+
+ switch(features.carrier_speed) {
+ case CARRIER_SPEED_1G:
+ printf(", 1Gbit/s");
+ break;
+ case CARRIER_SPEED_3G:
+ printf(", 3Gbit/s");
+ break;
+ case CARRIER_SPEED_10G:
+ printf(", 10Gbit/s");
+ break;
+ }
- printf(", %d video channel(s)\n", feature_video_channels);
+ printf(", %d video channel(s)\n", features.video_channels);
}
+
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
diff --git a/board/gdsys/common/mclink.c b/board/gdsys/common/mclink.c
index bf89d4e..c43d24b 100644
--- a/board/gdsys/common/mclink.c
+++ b/board/gdsys/common/mclink.c
@@ -4,6 +4,8 @@
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+
#include <common.h>
#include <asm/io.h>
#include <errno.h>
@@ -134,3 +136,5 @@
return 0;
}
+
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
diff --git a/board/gdsys/common/miiphybb.c b/board/gdsys/common/miiphybb.c
deleted file mode 100644
index 042835d..0000000
--- a/board/gdsys/common/miiphybb.c
+++ /dev/null
@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
- */
-
-#include <common.h>
-#include <miiphy.h>
-
-#include <asm/io.h>
-
-struct io_bb_pinset {
- int mdio;
- int mdc;
-};
-
-static int io_bb_mii_init(struct bb_miiphy_bus *bus)
-{
- return 0;
-}
-
-static int io_bb_mdio_active(struct bb_miiphy_bus *bus)
-{
- struct io_bb_pinset *pins = bus->priv;
-
- out_be32((void *)GPIO0_TCR,
- in_be32((void *)GPIO0_TCR) | pins->mdio);
-
- return 0;
-}
-
-static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus)
-{
- struct io_bb_pinset *pins = bus->priv;
-
- out_be32((void *)GPIO0_TCR,
- in_be32((void *)GPIO0_TCR) & ~pins->mdio);
-
- return 0;
-}
-
-static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
-{
- struct io_bb_pinset *pins = bus->priv;
-
- if (v)
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | pins->mdio);
- else
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~pins->mdio);
-
- return 0;
-}
-
-static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
-{
- struct io_bb_pinset *pins = bus->priv;
-
- *v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0);
-
- return 0;
-}
-
-static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
-{
- struct io_bb_pinset *pins = bus->priv;
-
- if (v)
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | pins->mdc);
- else
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~pins->mdc);
-
- return 0;
-}
-
-static int io_bb_delay(struct bb_miiphy_bus *bus)
-{
- udelay(1);
-
- return 0;
-}
-
-struct io_bb_pinset io_bb_pinsets[] = {
- {
- .mdio = CONFIG_SYS_MDIO_PIN,
- .mdc = CONFIG_SYS_MDC_PIN,
- },
-#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
- {
- .mdio = CONFIG_SYS_MDIO1_PIN,
- .mdc = CONFIG_SYS_MDC1_PIN,
- },
-#endif
-};
-
-struct bb_miiphy_bus bb_miiphy_buses[] = {
- {
- .name = CONFIG_SYS_GBIT_MII_BUSNAME,
- .init = io_bb_mii_init,
- .mdio_active = io_bb_mdio_active,
- .mdio_tristate = io_bb_mdio_tristate,
- .set_mdio = io_bb_set_mdio,
- .get_mdio = io_bb_get_mdio,
- .set_mdc = io_bb_set_mdc,
- .delay = io_bb_delay,
- .priv = &io_bb_pinsets[0],
- },
-#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
- {
- .name = CONFIG_SYS_GBIT_MII1_BUSNAME,
- .init = io_bb_mii_init,
- .mdio_active = io_bb_mdio_active,
- .mdio_tristate = io_bb_mdio_tristate,
- .set_mdio = io_bb_set_mdio,
- .get_mdio = io_bb_get_mdio,
- .set_mdc = io_bb_set_mdc,
- .delay = io_bb_delay,
- .priv = &io_bb_pinsets[1],
- },
-#endif
-};
-
-int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
- sizeof(bb_miiphy_buses[0]);
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index 392d005..10c4329 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -4,6 +4,8 @@
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+
#include <common.h>
#include <i2c.h>
#include <malloc.h>
@@ -497,3 +499,5 @@
"size_x(max. " __stringify(MAX_X_CHARS)
") size_y(max. " __stringify(MAX_Y_CHARS) ")\n"
);
+
+#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
\ No newline at end of file
diff --git a/board/gdsys/common/phy.c b/board/gdsys/common/phy.c
index c4b2256..d40c08d 100644
--- a/board/gdsys/common/phy.c
+++ b/board/gdsys/common/phy.c
@@ -45,8 +45,6 @@
{ MIICMD_SET, 16, 0x214d },
{ MIICMD_SET, 17, 0xcc0c },
{ MIICMD_SET, 16, 0x2159 },
- { MIICMD_SET, 22, 0x00fb },
- { MIICMD_SET, 7, 0xc00d },
{ MIICMD_SET, 22, 0x0000 },
};
diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig
index 9d99f68..3081188 100644
--- a/board/gdsys/mpc8308/Kconfig
+++ b/board/gdsys/mpc8308/Kconfig
@@ -4,6 +4,35 @@
Use the 'osdw', 'osdp', and 'osdsize' legacy commands required by
gdsys devices.
+config GDSYS_LEGACY_DRIVERS
+ bool
+ help
+ Enable the gdsys legacy drivers under board/gdsys/common. If this
+ option is not set, all relevant DM drivers must be configured for the
+ device in question.
+
+config SYS_FPGA0_BASE
+ hex
+ default E0600000
+ help
+ The base address of the first FPGA's register map.
+
+config SYS_FPGA0_SIZE
+ hex
+ default 1
+ help
+ The base address of the first FPGA's register map.
+
+config SYS_FPGA1_BASE
+ hex
+ help
+ The base address of the second FPGA's register map.
+
+config SYS_FPGA1_SIZE
+ hex
+ help
+ The base address of the second FPGA's register map.
+
if TARGET_HRCON
config SYS_BOARD
@@ -18,6 +47,9 @@
config GDSYS_LEGACY_OSD_CMDS
default y
+config GDSYS_LEGACY_DRIVERS
+ default y
+
endif
if TARGET_STRIDER
@@ -33,9 +65,60 @@
config GDSYS_LEGACY_OSD_CMDS
default y
+
+config GDSYS_LEGACY_DRIVERS
+ default y
+
endif
+if TARGET_GAZERBEAM
+
+config SYS_BOARD
+ default "mpc8308"
+
+config SYS_VENDOR
+ default "gdsys"
+
+config SYS_CONFIG_NAME
+ default "gazerbeam"
+
+config SYS_FPGA1_BASE
+ default E0700000
+
+config SYS_FPGA1_SIZE
+ default 1
+
+config GDSYS_LEGACY_OSD_CMDS
+ default y
+endif
+
+if TARGET_HRCON || TARGET_STRIDER || TARGET_GAZERBEAM
+
+choice
+ prompt "FPGA flavor selection"
+
+config SYS_FPGA_FLAVOR_LEGACY
+ bool "Legacy flavor"
+ help
+ This enables support for the gdsys pre-Gazerbeam FPGA memory layout.
+
+config SYS_FPGA_FLAVOR_GAZERBEAM
+ bool "Gazerbeam flavor"
+ help
+ This enables support for the gdsys FPGA memory layout of the
+ Gazerbeam board.
+
+endchoice
+
+config EXTENDED_FEATURES
+ bool "FPGA extended features"
+ depends on GDSYS_LEGACY_DRIVERS
+ help
+ Enable support for the extended features field of the IHS FPGA.
+
config CMD_IOLOOP
bool "Enable 'ioloop' and 'ioreflect' commands"
help
These commands provide FPGA tests.
+
+endif
diff --git a/board/gdsys/mpc8308/MAINTAINERS b/board/gdsys/mpc8308/MAINTAINERS
index 755b9a2..ed1b6fa 100644
--- a/board/gdsys/mpc8308/MAINTAINERS
+++ b/board/gdsys/mpc8308/MAINTAINERS
@@ -6,7 +6,9 @@
F: configs/hrcon_defconfig
F: configs/hrcon_dh_defconfig
F: include/configs/strider.h
+F: configs/strider_defconfig
F: configs/strider_cpu_defconfig
F: configs/strider_cpu_dp_defconfig
F: configs/strider_con_defconfig
F: configs/strider_con_dp_defconfig
+F: configs/gazerbeam_defconfig
diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile
index 60d2232..9af5fe0 100644
--- a/board/gdsys/mpc8308/Makefile
+++ b/board/gdsys/mpc8308/Makefile
@@ -4,5 +4,6 @@
# Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
obj-y := mpc8308.o sdram.o
-obj-$(CONFIG_HRCON) += hrcon.o
-obj-$(CONFIG_STRIDER) += strider.o
+obj-$(CONFIG_TARGET_HRCON) += hrcon.o
+obj-$(CONFIG_TARGET_STRIDER) += strider.o
+obj-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.o
diff --git a/board/gdsys/mpc8308/gazerbeam.c b/board/gdsys/mpc8308/gazerbeam.c
new file mode 100644
index 0000000..cd62174
--- /dev/null
+++ b/board/gdsys/mpc8308/gazerbeam.c
@@ -0,0 +1,179 @@
+/*
+ * (C) Copyright 2015
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <board.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <misc.h>
+#include <tpm-v1.h>
+#include <video_osd.h>
+
+#include "../common/ihs_mdio.h"
+#include "../../../drivers/board/gazerbeam.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ihs_mdio_info ihs_mdio_info[] = {
+ { .fpga = NULL, .name = "ihs0", .base = 0x58 },
+ { .fpga = NULL, .name = "ihs1", .base = 0x58 },
+};
+
+static int get_tpm(struct udevice **devp)
+{
+ int rc;
+
+ rc = uclass_first_device_err(UCLASS_TPM, devp);
+ if (rc) {
+ printf("Could not find TPM (ret=%d)\n", rc);
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ struct udevice *board;
+ struct udevice *serdes;
+ int mc = 0;
+ int con = 0;
+
+ if (board_get(&board))
+ puts("Could not find board information device.\n");
+
+ /* Initialize serdes */
+ uclass_get_device_by_phandle(UCLASS_MISC, board, "serdes", &serdes);
+
+ if (board_detect(board))
+ puts("Device information detection failed.\n");
+
+ board_get_int(board, BOARD_MULTICHANNEL, &mc);
+ board_get_int(board, BOARD_VARIANT, &con);
+
+ if (mc == 2 || mc == 1)
+ dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@22");
+
+ if (mc == 4) {
+ dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@20");
+ dev_enable_by_path("/localbus@e0005000/iocon_uart@2,0");
+ dev_enable_by_path("/fpga1bus");
+ }
+
+ if (mc == 2 || con == VAR_CON) {
+ dev_enable_by_path("/fpga0bus/fpga0_video1");
+ dev_enable_by_path("/fpga0bus/fpga0_iic_video1");
+ dev_enable_by_path("/fpga0bus/fpga0_axi_video1");
+ }
+
+ if (con == VAR_CON) {
+ dev_enable_by_path("/fpga0bus/fpga0_video0");
+ dev_enable_by_path("/fpga0bus/fpga0_iic_video0");
+ dev_enable_by_path("/fpga0bus/fpga0_axi_video0");
+ }
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ struct udevice *board;
+ char *s = env_get("serial#");
+ int mc = 0;
+ int con = 0;
+
+ if (board_get(&board))
+ puts("Could not find board information device.\n");
+
+ board_get_int(board, BOARD_MULTICHANNEL, &mc);
+ board_get_int(board, BOARD_VARIANT, &con);
+
+ puts("Board: Gazerbeam ");
+ printf("%s ", mc == 4 ? "MC4" : mc == 2 ? "MC2" : "SC");
+ printf("%s", con == VAR_CON ? "CON" : "CPU");
+
+ if (s) {
+ puts(", serial# ");
+ puts(s);
+ }
+
+ puts("\n");
+
+ return 0;
+}
+
+static void display_osd_info(struct udevice *osd,
+ struct video_osd_info *osd_info)
+{
+ printf("OSD-%s: Digital-OSD version %01d.%02d, %d x %d characters\n",
+ osd->name, osd_info->major_version, osd_info->minor_version,
+ osd_info->width, osd_info->height);
+}
+
+int last_stage_init(void)
+{
+ int fpga_hw_rev = 0;
+ int i;
+ struct udevice *board;
+ struct udevice *osd;
+ struct video_osd_info osd_info;
+ struct udevice *tpm;
+ int ret;
+
+ if (board_get(&board))
+ puts("Could not find board information device.\n");
+
+ if (board) {
+ int res = board_get_int(board, BOARD_HWVERSION, &fpga_hw_rev);
+
+ if (res)
+ printf("Could not determind FPGA HW revision (res = %d)\n", res);
+ }
+
+ env_set_ulong("fpga_hw_rev", fpga_hw_rev);
+
+ ret = get_tpm(&tpm);
+ if (ret || tpm_init(tpm) || tpm_startup(tpm, TPM_ST_CLEAR) ||
+ tpm_continue_self_test(tpm)) {
+ printf("TPM init failed\n");
+ }
+
+ if (fpga_hw_rev >= 4) {
+ for (i = 0; i < 4; i++) {
+ struct udevice *rxaui;
+ char name[8];
+
+ snprintf(name, sizeof(name), "rxaui%d", i);
+ /* Disable RXAUI polarity inversion */
+ ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &rxaui);
+ if (!ret)
+ misc_set_enabled(rxaui, false);
+ }
+ }
+
+ for (uclass_first_device(UCLASS_VIDEO_OSD, &osd);
+ osd;
+ uclass_next_device(&osd)) {
+ video_osd_get_info(osd, &osd_info);
+ display_osd_info(osd, &osd_info);
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
+ fdt_fixup_esdhc(blob, bd);
+
+ return 0;
+}
+#endif
diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c
index 2d709de..d14a28e 100644
--- a/board/gdsys/mpc8308/hrcon.c
+++ b/board/gdsys/mpc8308/hrcon.c
@@ -35,11 +35,11 @@
#define MAX_MUX_CHANNELS 2
enum {
- MCFPGA_DONE = 1 << 0,
- MCFPGA_INIT_N = 1 << 1,
- MCFPGA_PROGRAM_N = 1 << 2,
- MCFPGA_UPDATE_ENABLE_N = 1 << 3,
- MCFPGA_RESET_N = 1 << 4,
+ MCFPGA_DONE = BIT(0),
+ MCFPGA_INIT_N = BIT(1),
+ MCFPGA_PROGRAM_N = BIT(2),
+ MCFPGA_UPDATE_ENABLE_N = BIT(3),
+ MCFPGA_RESET_N = BIT(4),
};
enum {
@@ -47,7 +47,7 @@
GPIO_MDIO = 1 << 15,
};
-unsigned int mclink_fpgacount;
+uint mclink_fpgacount;
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
struct {
@@ -107,7 +107,7 @@
printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber");
- if (s != NULL) {
+ if (s) {
puts(", serial# ");
puts(s);
}
@@ -120,12 +120,11 @@
int last_stage_init(void)
{
int slaves;
- unsigned int k;
- unsigned int mux_ch;
- unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
+ uint k;
+ uchar mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
u16 fpga_features;
bool hw_type_cat = pca9698_get_value(0x20, 20);
- bool ch0_rgmii2_present = false;
+ bool ch0_rgmii2_present;
FPGA_GET_REG(0, fpga_features, &fpga_features);
@@ -137,16 +136,16 @@
/* wait for FPGA done, then reset FPGA */
for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
- unsigned int ctr = 0;
+ uint ctr = 0;
if (i2c_probe(mclink_controllers[k]))
continue;
while (!(pca953x_get_val(mclink_controllers[k])
& MCFPGA_DONE)) {
- udelay(100000);
+ mdelay(100);
if (ctr++ > 5) {
- printf("no done for mclink_controller %d\n", k);
+ printf("no done for mclink_controller %u\n", k);
break;
}
}
@@ -159,8 +158,10 @@
}
if (hw_type_cat) {
+ uint mux_ch;
int retval;
struct mii_dev *mdiodev = mdio_alloc();
+
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
@@ -179,7 +180,7 @@
}
/* give slave-PLLs and Parade DP501 some time to be up and running */
- udelay(500000);
+ mdelay(500);
mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
slaves = mclink_probe();
@@ -207,6 +208,7 @@
if (hw_type_cat) {
int retval;
struct mii_dev *mdiodev = mdio_alloc();
+
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, bb_miiphy_buses[k].name,
@@ -233,17 +235,17 @@
* provide access to fpga gpios and controls (for I2C bitbang)
* (these may look all too simple but make iocon.h much more readable)
*/
-void fpga_gpio_set(unsigned int bus, int pin)
+void fpga_gpio_set(uint bus, int pin)
{
FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin);
}
-void fpga_gpio_clear(unsigned int bus, int pin)
+void fpga_gpio_clear(uint bus, int pin)
{
FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin);
}
-int fpga_gpio_get(unsigned int bus, int pin)
+int fpga_gpio_get(uint bus, int pin)
{
u16 val;
@@ -252,7 +254,7 @@
return val & pin;
}
-void fpga_control_set(unsigned int bus, int pin)
+void fpga_control_set(uint bus, int pin)
{
u16 val;
@@ -260,7 +262,7 @@
FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin);
}
-void fpga_control_clear(unsigned int bus, int pin)
+void fpga_control_clear(uint bus, int pin)
{
u16 val;
@@ -273,7 +275,7 @@
pca9698_direction_output(0x20, 4, 1);
}
-void mpc8308_set_fpga_reset(unsigned state)
+void mpc8308_set_fpga_reset(uint state)
{
pca9698_set_value(0x20, 4, state ? 0 : 1);
}
@@ -285,11 +287,11 @@
/*
* set "startup-finished"-gpios
*/
- setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
- setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
+ setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12));
+ setbits_gpio0_out(BIT(31 - 12));
}
-int mpc8308_get_fpga_done(unsigned fpga)
+int mpc8308_get_fpga_done(uint fpga)
{
return pca9698_get_value(0x20, 19);
}
@@ -367,7 +369,7 @@
*/
struct fpga_mii {
- unsigned fpga;
+ uint fpga;
int mdio;
} fpga_mii[] = {
{ 0, 1},
@@ -494,5 +496,4 @@
},
};
-int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
- sizeof(bb_miiphy_buses[0]);
+int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c
index 0112244..ae77fc2 100644
--- a/board/gdsys/mpc8308/mpc8308.c
+++ b/board/gdsys/mpc8308/mpc8308.c
@@ -24,14 +24,34 @@
DECLARE_GLOBAL_DATA_PTR;
-int get_fpga_state(unsigned dev)
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+/* as gpio output status cannot be read back, we have to buffer it locally */
+u32 gpio0_out;
+
+void setbits_gpio0_out(u32 mask)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ gpio0_out |= mask;
+ out_be32(&immr->gpio[0].dat, gpio0_out);
+}
+
+void clrbits_gpio0_out(u32 mask)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ gpio0_out &= ~mask;
+ out_be32(&immr->gpio[0].dat, gpio0_out);
+}
+
+int get_fpga_state(uint dev)
{
return gd->arch.fpga_state[dev];
}
int board_early_init_f(void)
{
- unsigned k;
+ uint k;
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
gd->arch.fpga_state[k] = 0;
@@ -41,8 +61,8 @@
int board_early_init_r(void)
{
- unsigned k;
- unsigned ctr;
+ uint k;
+ uint ctr;
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
gd->arch.fpga_state[k] = 0;
@@ -59,7 +79,7 @@
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
ctr = 0;
while (!mpc8308_get_fpga_done(k)) {
- udelay(100000);
+ mdelay(100);
if (ctr++ > 5) {
gd->arch.fpga_state[k] |=
FPGA_STATE_DONE_FAILED;
@@ -86,7 +106,7 @@
if (val == REFLECTION_TESTPATTERN_INV)
break;
- udelay(100000);
+ mdelay(100);
if (ctr++ > 5) {
gd->arch.fpga_state[k] |=
FPGA_STATE_REFLECTION_FAILED;
@@ -97,3 +117,4 @@
return 0;
}
+#endif
diff --git a/board/gdsys/mpc8308/mpc8308.h b/board/gdsys/mpc8308/mpc8308.h
index dc07d56..1e4f24f 100644
--- a/board/gdsys/mpc8308/mpc8308.h
+++ b/board/gdsys/mpc8308/mpc8308.h
@@ -1,6 +1,9 @@
#ifndef __MPC8308_H_
#define __MPC8308_H_
+void setbits_gpio0_out(u32 mask);
+void clrbits_gpio0_out(u32 mask);
+
/* functions to be provided by board implementation */
void mpc8308_init(void);
void mpc8308_set_fpga_reset(unsigned state);
diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c
index 5ced8eb..2a77fed 100644
--- a/board/gdsys/mpc8308/sdram.c
+++ b/board/gdsys/mpc8308/sdram.c
@@ -11,6 +11,8 @@
* board\freescale\mpc8315erdb\sdram.c
*/
+#ifndef CONFIG_MPC83XX_SDRAM
+
#include <common.h>
#include <mpc83xx.h>
#include <spd_sdram.h>
@@ -34,7 +36,7 @@
u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar,
- CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
+ CONFIG_SYS_SDRAM_BASE & 0xfffff000);
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
@@ -62,7 +64,7 @@
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
sync();
- return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+ return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
}
int dram_init(void)
@@ -81,3 +83,5 @@
return 0;
}
+
+#endif /* !CONFIG_MPC83XX_SDRAM */
diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c
index fa26585..1fdea67 100644
--- a/board/gdsys/mpc8308/strider.c
+++ b/board/gdsys/mpc8308/strider.c
@@ -50,7 +50,7 @@
GPIO_MDIO = 1 << 15,
};
-unsigned int mclink_fpgacount;
+uint mclink_fpgacount;
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
struct {
@@ -110,7 +110,7 @@
printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
- if (s != NULL) {
+ if (s) {
puts(", serial# ");
puts(s);
}
@@ -123,17 +123,17 @@
int last_stage_init(void)
{
int slaves;
- unsigned int k;
- unsigned int mux_ch;
- unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
+ uint k;
+ uint mux_ch;
+ uchar mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
#ifdef CONFIG_STRIDER_CPU
- unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
+ uchar mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
#endif
bool hw_type_cat = pca9698_get_value(0x20, 18);
#ifdef CONFIG_STRIDER_CON_DP
bool is_dh = pca9698_get_value(0x20, 25);
#endif
- bool ch0_sgmii2_present = false;
+ bool ch0_sgmii2_present;
/* Turn on Analog Devices ADV7611 */
pca9698_direction_output(0x20, 8, 0);
@@ -146,8 +146,8 @@
/* wait for FPGA done, then reset FPGA */
for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
- unsigned int ctr = 0;
- unsigned char *mclink_controllers = mclink_controllers_dvi;
+ uint ctr = 0;
+ uchar *mclink_controllers = mclink_controllers_dvi;
#ifdef CONFIG_STRIDER_CPU
if (i2c_probe(mclink_controllers[k])) {
@@ -161,7 +161,7 @@
#endif
while (!(pca953x_get_val(mclink_controllers[k])
& MCFPGA_DONE)) {
- udelay(100000);
+ mdelay(100);
if (ctr++ > 5) {
printf("no done for mclink_controller %d\n", k);
break;
@@ -178,6 +178,7 @@
if (hw_type_cat) {
int retval;
struct mii_dev *mdiodev = mdio_alloc();
+
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
@@ -196,7 +197,7 @@
}
/* give slave-PLLs and Parade DP501 some time to be up and running */
- udelay(500000);
+ mdelay(500);
mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
slaves = mclink_probe();
@@ -235,7 +236,7 @@
for (k = 1; k <= slaves; ++k)
FPGA_SET_REG(k, extended_control, 0x10); /* enable video */
- udelay(500000);
+ mdelay(500);
#endif
for (k = 1; k <= slaves; ++k) {
@@ -260,6 +261,7 @@
if (hw_type_cat) {
int retval;
struct mii_dev *mdiodev = mdio_alloc();
+
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, bb_miiphy_buses[k].name,
@@ -286,17 +288,17 @@
* provide access to fpga gpios (for I2C bitbang)
* (these may look all too simple but make iocon.h much more readable)
*/
-void fpga_gpio_set(unsigned int bus, int pin)
+void fpga_gpio_set(uint bus, int pin)
{
FPGA_SET_REG(bus, gpio.set, pin);
}
-void fpga_gpio_clear(unsigned int bus, int pin)
+void fpga_gpio_clear(uint bus, int pin)
{
FPGA_SET_REG(bus, gpio.clear, pin);
}
-int fpga_gpio_get(unsigned int bus, int pin)
+int fpga_gpio_get(uint bus, int pin)
{
u16 val;
@@ -306,7 +308,7 @@
}
#ifdef CONFIG_STRIDER_CON_DP
-void fpga_control_set(unsigned int bus, int pin)
+void fpga_control_set(uint bus, int pin)
{
u16 val;
@@ -314,7 +316,7 @@
FPGA_SET_REG(bus, control, val | pin);
}
-void fpga_control_clear(unsigned int bus, int pin)
+void fpga_control_clear(uint bus, int pin)
{
u16 val;
@@ -328,7 +330,7 @@
pca9698_direction_output(0x20, 26, 1);
}
-void mpc8308_set_fpga_reset(unsigned state)
+void mpc8308_set_fpga_reset(uint state)
{
pca9698_set_value(0x20, 26, state ? 0 : 1);
}
@@ -340,11 +342,11 @@
/*
* set "startup-finished"-gpios
*/
- setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
- setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
+ setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12));
+ setbits_gpio0_out(BIT(31 - 12));
}
-int mpc8308_get_fpga_done(unsigned fpga)
+int mpc8308_get_fpga_done(uint fpga)
{
return pca9698_get_value(0x20, 20);
}
@@ -422,7 +424,7 @@
*/
struct fpga_mii {
- unsigned fpga;
+ uint fpga;
int mdio;
} fpga_mii[] = {
{ 0, 1},
@@ -549,5 +551,4 @@
},
};
-int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
- sizeof(bb_miiphy_buses[0]);
+int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
diff --git a/board/gdsys/p1022/Kconfig b/board/gdsys/p1022/Kconfig
index 8514d08..f515427 100644
--- a/board/gdsys/p1022/Kconfig
+++ b/board/gdsys/p1022/Kconfig
@@ -1,3 +1,10 @@
+config GDSYS_LEGACY_DRIVERS
+ bool
+ help
+ Enable the gdsys legacy drivers under board/gdsys/common. If this
+ option is not set, all relevant DM drivers must be configured for the
+ device in question.
+
if TARGET_CONTROLCENTERD
config SYS_BOARD
@@ -9,4 +16,7 @@
config SYS_CONFIG_NAME
default "controlcenterd"
+config GDSYS_LEGACY_DRIVERS
+ default y
+
endif
diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c
index d547af4..caa3606 100644
--- a/board/ids/ids8313/ids8313.c
+++ b/board/ids/ids8313/ids8313.c
@@ -57,7 +57,7 @@
u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar,
- (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
+ (CONFIG_SYS_SDRAM_BASE & 0xfffff000));
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
sync();
@@ -96,7 +96,7 @@
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
/* now check the real size */
disable_addr_trans();
- msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
+ msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
enable_addr_trans();
#endif
return msize;
@@ -129,8 +129,8 @@
msize = setup_sdram();
- out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
- out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
+ out_be32(&lbc->lbcr, (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF));
+ out_be32(&lbc->mrtpr, 0x20000000);
sync();
gd->ram_size = msize;
diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig
index d6c594c..fbbbb17 100644
--- a/board/keymile/km83xx/Kconfig
+++ b/board/keymile/km83xx/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_KM8360
+if TARGET_KMETER1
config SYS_BOARD
default "km83xx"
@@ -7,10 +7,49 @@
default "keymile"
config SYS_CONFIG_NAME
- default "km8360"
+ default "kmeter1"
endif
+if TARGET_KMCOGE5NE
+
+config SYS_BOARD
+ default "km83xx"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "kmcoge5ne"
+
+endif
+
+if TARGET_KMVECT1
+
+config SYS_BOARD
+ default "km83xx"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "kmvect1"
+
+endif
+
+if TARGET_KMTEGR1
+
+config SYS_BOARD
+ default "km83xx"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "kmtegr1"
+
+endif
+
if TARGET_SUVD3
config SYS_BOARD
@@ -36,3 +75,55 @@
default "tuxx1"
endif
+
+if TARGET_KMSUPX5
+
+config SYS_BOARD
+ default "km83xx"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "kmsupx5"
+
+endif
+
+if TARGET_TUGE1
+
+config SYS_BOARD
+ default "km83xx"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "tuge1"
+
+endif
+
+if TARGET_KMOPTI2
+
+config SYS_BOARD
+ default "km83xx"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "kmopti2"
+
+endif
+
+if TARGET_KMTEPR2
+
+config SYS_BOARD
+ default "km83xx"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "kmtepr2"
+
+endif
diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index 4818a49..880ce67 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -33,7 +33,7 @@
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* port pin dir open_drain assign */
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
/* MDIO */
{0, 1, 3, 0, 2}, /* MDIO */
{0, 2, 1, 0, 1}, /* MDC */
@@ -56,7 +56,7 @@
{5, 2, 1, 0, 1}, /* UART2_RTS */
{5, 3, 2, 0, 2}, /* UART2_SIN */
{5, 1, 2, 0, 3}, /* UART2_CTS */
-#elif !defined(CONFIG_MPC8309)
+#elif !defined(CONFIG_ARCH_MPC8309)
/* Local Bus */
{0, 16, 1, 0, 3}, /* LA00 */
{0, 17, 1, 0, 3}, /* LA01 */
@@ -148,7 +148,7 @@
u32 *mxmr = &lbc->mamr;
#endif
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
unsigned short svid;
/*
* Because of errata in the UCCs, we have to write to the reserved
@@ -271,7 +271,7 @@
}
#endif
-#if defined(CONFIG_KMCOGE5NE)
+#if defined(CONFIG_TARGET_KMCOGE5NE)
struct bfticu_iomap *base =
(struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
@@ -311,7 +311,7 @@
msize = CONFIG_SYS_DDR_SIZE << 20;
disable_addr_trans();
- msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
+ msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
enable_addr_trans();
msize /= (1024 * 1024);
if (CONFIG_SYS_DDR_SIZE != msize) {
@@ -338,7 +338,7 @@
return -ENXIO;
out_be32(&im->sysconf.ddrlaw[0].bar,
- CONFIG_SYS_DDR_BASE & LAWBAR_BAR);
+ CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR);
msize = fixed_sdram();
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
diff --git a/board/mpc8308_p1m/sdram.c b/board/mpc8308_p1m/sdram.c
index 4118c01..baf70d8 100644
--- a/board/mpc8308_p1m/sdram.c
+++ b/board/mpc8308_p1m/sdram.c
@@ -29,7 +29,7 @@
u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar,
- CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
+ CONFIG_SYS_SDRAM_BASE & 0xfffff000);
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
@@ -57,7 +57,7 @@
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
sync();
- return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+ return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
}
int dram_init(void)
diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index b8ba29a..a647de6 100644
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -45,7 +45,7 @@
return -1;
/* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
msize = spd_sdram();
#else
@@ -79,19 +79,19 @@
u32 ddr_size = msize << 20; /* DDR size in bytes */
u32 ddr_size_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256)
#warning Currently any ddr size other than 256 is not supported
#endif
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
im->ddr.csbnds[2].csbnds =
- ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+ ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
CSBNDS_EA_SHIFT) & CSBNDS_EA);
im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
@@ -147,6 +147,9 @@
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbc_t *lbc = &immap->im_lbc;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+ const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
+ LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
+ LSDMR_WRC3 | LSDMR_CL3;
puts("\n SDRAM on Local Bus: ");
print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
@@ -156,22 +159,27 @@
*/
/* setup mtrpt, lsrt and lbcr for LB bus */
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
- lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ lbc->lbcr = 0x00000000;
+ /* LB refresh timer prescal, 266MHz/32 */
+ lbc->mrtpr = 0x20000000;
+ /* LB sdram refresh timer, about 6us */
+ lbc->lsrt = 0x32000000;
asm("sync");
/*
* Configure the SDRAM controller Machine Mode Register.
*/
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+ /* 0x40636733; normal operation */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+ /* 0x68636733; precharge all the banks */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+ /* 0x48636733; auto refresh */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync");
/*1 times*/
*sdram_addr = 0xff;
@@ -199,12 +207,13 @@
udelay(100);
/* 0x58636733; mode register write operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+ /* 0x40636733; normal operation */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
diff --git a/board/tqc/tqm834x/pci.c b/board/tqc/tqm834x/pci.c
index 34c68ac..c9b05e4 100644
--- a/board/tqc/tqm834x/pci.c
+++ b/board/tqc/tqm834x/pci.c
@@ -71,7 +71,7 @@
reg32 = 0xff000000;
#endif
if (clk->spmr & SPMR_CKID) {
- /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR
+ /* PCI Clock is half CONFIG_SYS_CLK_FREQ so need to set up OCCR
* fields accordingly */
reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);
diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c
index 7c92f4f..04941b2 100644
--- a/board/tqc/tqm834x/tqm834x.c
+++ b/board/tqc/tqm834x/tqm834x.c
@@ -72,13 +72,13 @@
int cs;
/* during size detection, set up the max DDRLAW size */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE;
im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
/* set CS bounds to maximum size */
for(cs = 0; cs < 4; ++cs) {
set_cs_bounds(cs,
- CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),
+ CONFIG_SYS_SDRAM_BASE + (cs * DDR_MAX_SIZE_PER_CS),
DDR_MAX_SIZE_PER_CS);
set_cs_config(cs, INITIAL_CS_CONFIG);
@@ -102,7 +102,7 @@
debug("\nDetecting Bank%d\n", cs);
bank_size = get_ddr_bank_size(cs,
- (long *)(CONFIG_SYS_DDR_BASE + size));
+ (long *)(CONFIG_SYS_SDRAM_BASE + size));
size += bank_size;
debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20);
@@ -235,8 +235,8 @@
debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks);
/* set OR0 and BR0 */
- set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH |
- (-(total_size) & OR_GPCM_AM));
+ set_lbc_or(0, OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 |
+ OR_GPCM_TRLX | (-(total_size) & OR_GPCM_AM));
set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) |
(BR_MS_GPCM | BR_PS_32 | BR_V));
diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
index f0fc1fe..1559ff2 100644
--- a/board/ve8313/ve8313.c
+++ b/board/ve8313/ve8313.c
@@ -38,7 +38,7 @@
u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar,
- (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
+ (CONFIG_SYS_SDRAM_BASE & 0xfffff000));
out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
@@ -48,12 +48,12 @@
*/
__udelay(50000);
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
out_be32(&im->ddr.csbnds[0].csbnds,
- ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+ ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
CSBNDS_EA));
out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
@@ -80,7 +80,7 @@
/* now check the real size */
disable_addr_trans ();
- msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
+ msize = get_ram_size (CONFIG_SYS_SDRAM_BASE, msize);
enable_addr_trans ();
#endif
@@ -100,8 +100,8 @@
msize = fixed_sdram();
/* Local Bus setup lbcr and mrtpr */
- out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
- out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
+ out_be32(&lbc->lbcr, 0x00040000);
+ out_be32(&lbc->mrtpr, 0x20000000);
sync();
/* return total bus SDRAM size(bytes) -- DDR */
diff --git a/cmd/binop.c b/cmd/binop.c
index 787f7a2..116a2c0 100644
--- a/cmd/binop.c
+++ b/cmd/binop.c
@@ -2,6 +2,7 @@
#include <common.h>
#include <command.h>
+#include <hexdump.h>
#include <malloc.h>
#include <mapmem.h>
#include <linux/ctype.h>
@@ -26,43 +27,20 @@
str_ptr += 2;
}
*str_ptr = '\0';
- setenv(varname, str_output);
+ env_set(varname, str_output);
free(str_output);
}
-void decode_hexstring(char *hexstr, u8 *result)
-{
- int i;
- int acc = 0;
-
- for (i = 0; i < strlen(hexstr); ++i) {
- char d = hexstr[i];
- int value;
-
- if (isdigit(d))
- value = (d - '0');
- else
- value = (islower(d) ? toupper(d) : d) - 'A' + 10;
-
- if (i % 2 == 0) {
- acc = value * 16;
- } else {
- result[i / 2] = acc + value;
- acc = 0;
- }
- }
-}
-
void read_from_env_var(char *varname, u8 *result)
{
char *str_value;
- str_value = getenv(varname);
+ str_value = env_get(varname);
if (str_value)
- decode_hexstring(str_value, result);
+ hex2bin(result, str_value, strlen(str_value) / 2);
else
- decode_hexstring(varname, result);
+ hex2bin(result, varname, strlen(varname) / 2);
}
void read_from_mem(ulong addr, u8 *result, ulong len)
diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig
index 06657b2..1a38ebd 100644
--- a/configs/MPC8308RDB_defconfig
+++ b/configs/MPC8308RDB_defconfig
@@ -1,7 +1,80 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8308RDB=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_128_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMRBAR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_8_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFE000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="STACK_IN_DCACHE"
+CONFIG_BAT3_BASE=0xE6000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="NAND"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xF0000000
+CONFIG_LBLAW2_NAME="VSC7385"
+CONFIG_LBLAW2_LENGTH_128_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y
+CONFIG_SICR_GPIO_A_TSEC2=y
+CONFIG_SICR_GPIO_B_TSEC_GTX_CLK125=y
+CONFIG_SICR_IEEE1588_A_GPIO=y
+CONFIG_SICR_GTM_GPIO=y
+CONFIG_SICR_GPIOSEL_IEEE1588=y
+CONFIG_SICR_TMSOBI1_2_5_V=y
+CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -30,3 +103,41 @@
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_32_KBYTES=y
+CONFIG_OR1_SCY_1=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385_BASE"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig
index 3bb680c..04eb29a 100644
--- a/configs/MPC8313ERDB_33_defconfig
+++ b/configs/MPC8313ERDB_33_defconfig
@@ -1,7 +1,84 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8313ERDB=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_MPC8313ERDB_NOR=y
+CONFIG_SYSTEM_PLL_FACTOR_5_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO_BASE"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_16_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE2800000
+CONFIG_LBLAW1_NAME="NAND"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xF0000000
+CONFIG_LBLAW2_NAME="VSC7385"
+CONFIG_LBLAW2_LENGTH_128_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xFA000000
+CONFIG_LBLAW3_NAME="BCSR"
+CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
@@ -32,3 +109,55 @@
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_9=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_EHTR_1_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE2800000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_32_KBYTES=y
+CONFIG_OR1_SCY_1=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="BCSR"
+CONFIG_BR3_OR3_BASE=0xFA000000
+CONFIG_BR3_MACHINE_GPCM=y
+CONFIG_BR3_PORTSIZE_8BIT=y
+CONFIG_OR3_AM_32_KBYTES=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig
index bb26a9e..8bbeb97 100644
--- a/configs/MPC8313ERDB_66_defconfig
+++ b/configs/MPC8313ERDB_66_defconfig
@@ -1,7 +1,83 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666667
CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8313ERDB=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_MPC8313ERDB_NOR=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO_BASE"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_16_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE2800000
+CONFIG_LBLAW1_NAME="NAND"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xF0000000
+CONFIG_LBLAW2_NAME="VSC7385"
+CONFIG_LBLAW2_LENGTH_128_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xFA000000
+CONFIG_LBLAW3_NAME="BCSR"
+CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
@@ -32,3 +108,55 @@
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_9=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_EHTR_1_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE2800000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_32_KBYTES=y
+CONFIG_OR1_SCY_1=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="BCSR"
+CONFIG_BR3_OR3_BASE=0xFA000000
+CONFIG_BR3_MACHINE_GPCM=y
+CONFIG_BR3_PORTSIZE_8BIT=y
+CONFIG_OR3_AM_32_KBYTES=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig
index 4486571..29b12d0 100644
--- a/configs/MPC8313ERDB_NAND_33_defconfig
+++ b/configs/MPC8313ERDB_NAND_33_defconfig
@@ -2,8 +2,85 @@
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8313ERDB=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_MPC8313ERDB_NAND=y
+CONFIG_SYSTEM_PLL_FACTOR_5_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO_BASE"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_NAND_LBLAWBAR_PRELIM_1=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_16_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE2800000
+CONFIG_LBLAW1_NAME="NAND"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xF0000000
+CONFIG_LBLAW2_NAME="VSC7385"
+CONFIG_LBLAW2_LENGTH_128_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xFA000000
+CONFIG_LBLAW3_NAME="BCSR"
+CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
@@ -40,3 +117,55 @@
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="NAND"
+CONFIG_BR0_OR0_BASE=0xE2800000
+CONFIG_BR0_ERRORCHECKING_BOTH=y
+CONFIG_BR0_MACHINE_FCM=y
+CONFIG_BR0_PORTSIZE_8BIT=y
+CONFIG_OR0_AM_32_KBYTES=y
+CONFIG_OR0_SCY_1=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_CHT_TWO_CLOCK=y
+CONFIG_OR0_CSCT_8_CYCLE=y
+CONFIG_OR0_CST_ONE_CLOCK=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FLASH"
+CONFIG_BR1_OR1_BASE=0xFE000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_8_MBYTES=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_9=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_EHTR_1_CYCLE=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="BCSR"
+CONFIG_BR3_OR3_BASE=0xFA000000
+CONFIG_BR3_MACHINE_GPCM=y
+CONFIG_BR3_PORTSIZE_8BIT=y
+CONFIG_OR3_AM_32_KBYTES=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig
index 83f0f6d..2dc31ed 100644
--- a/configs/MPC8313ERDB_NAND_66_defconfig
+++ b/configs/MPC8313ERDB_NAND_66_defconfig
@@ -2,8 +2,84 @@
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
+CONFIG_SYS_CLK_FREQ=66666667
CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8313ERDB=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_MPC8313ERDB_NAND=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO_BASE"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_NAND_LBLAWBAR_PRELIM_1=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_16_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE2800000
+CONFIG_LBLAW1_NAME="NAND"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xF0000000
+CONFIG_LBLAW2_NAME="VSC7385"
+CONFIG_LBLAW2_LENGTH_128_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xFA000000
+CONFIG_LBLAW3_NAME="BCSR"
+CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
@@ -40,3 +116,55 @@
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="NAND"
+CONFIG_BR0_OR0_BASE=0xE2800000
+CONFIG_BR0_ERRORCHECKING_BOTH=y
+CONFIG_BR0_MACHINE_FCM=y
+CONFIG_BR0_PORTSIZE_8BIT=y
+CONFIG_OR0_AM_32_KBYTES=y
+CONFIG_OR0_SCY_1=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_CHT_TWO_CLOCK=y
+CONFIG_OR0_CSCT_8_CYCLE=y
+CONFIG_OR0_CST_ONE_CLOCK=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FLASH"
+CONFIG_BR1_OR1_BASE=0xFE000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_8_MBYTES=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_9=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_EHTR_1_CYCLE=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="BCSR"
+CONFIG_BR3_OR3_BASE=0xFA000000
+CONFIG_BR3_MACHINE_GPCM=y
+CONFIG_BR3_PORTSIZE_8BIT=y
+CONFIG_OR3_AM_32_KBYTES=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig
index b45369e..08b5cc5 100644
--- a/configs/MPC8315ERDB_defconfig
+++ b/configs/MPC8315ERDB_defconfig
@@ -1,7 +1,88 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666667
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8315ERDB=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_128_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMRBAR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_8_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFE000000
+CONFIG_BAT2_LENGTH_32_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="STACK_IN_DCACHE"
+CONFIG_BAT3_BASE=0xE6000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="PCI_MEM_PHYS"
+CONFIG_BAT4_BASE=0x80000000
+CONFIG_BAT4_LENGTH_256_MBYTES=y
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT4_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="PCI_MMIO_PHYS"
+CONFIG_BAT5_BASE=0x90000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="NAND"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
@@ -35,3 +116,32 @@
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_32_KBYTES=y
+CONFIG_OR1_SCY_1=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig
index a1227bf..8ea942d 100644
--- a/configs/MPC8323ERDB_defconfig
+++ b/configs/MPC8323ERDB_defconfig
@@ -1,7 +1,81 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666667
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8323ERDB=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFE000000
+CONFIG_BAT2_LENGTH_32_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="PCI_MEM_PHYS"
+CONFIG_BAT5_BASE=0x80000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="PCI1_MMIO_PHYS"
+CONFIG_BAT6_BASE=0x90000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_INHIBITED=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_INHIBITED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_OPT_SPEC_READ=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
@@ -20,3 +94,19 @@
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig
index e4c44d9..c39f449 100644
--- a/configs/MPC832XEMDS_ATM_defconfig
+++ b/configs/MPC832XEMDS_ATM_defconfig
@@ -1,7 +1,76 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC832XEMDS=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="BCSR"
+CONFIG_BAT2_BASE=0xF8000000
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xFE000000
+CONFIG_BAT3_LENGTH_32_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="STACK_IN_DCACHE"
+CONFIG_BAT5_BASE=0xE6000000
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xF8008000
+CONFIG_LBLAW3_NAME="PIB"
+CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
@@ -21,3 +90,58 @@
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_32_KBYTES=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="PIB1"
+CONFIG_BR2_OR2_BASE=0xF8008000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_32_KBYTES=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_XAM_SET=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PIB2"
+CONFIG_BR3_OR3_BASE=0xF8010000
+CONFIG_BR3_MACHINE_GPCM=y
+CONFIG_BR3_PORTSIZE_8BIT=y
+CONFIG_OR3_AM_32_KBYTES=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_XAM_SET=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig
index 2b03a56..0e65d21 100644
--- a/configs/MPC832XEMDS_HOST_33_defconfig
+++ b/configs/MPC832XEMDS_HOST_33_defconfig
@@ -1,7 +1,96 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC832XEMDS=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="BCSR"
+CONFIG_BAT2_BASE=0xF8000000
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xFE000000
+CONFIG_BAT3_LENGTH_32_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="STACK_IN_DCACHE"
+CONFIG_BAT5_BASE=0xE6000000
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="PCI_MEM_PHYS"
+CONFIG_BAT6_BASE=0x80000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT7=y
+CONFIG_BAT7_NAME="PCI1_MMIO_PHYS"
+CONFIG_BAT7_BASE=0x90000000
+CONFIG_BAT7_LENGTH_256_MBYTES=y
+CONFIG_BAT7_ACCESS_RW=y
+CONFIG_BAT7_ICACHE_INHIBITED=y
+CONFIG_BAT7_ICACHE_GUARDED=y
+CONFIG_BAT7_DCACHE_INHIBITED=y
+CONFIG_BAT7_DCACHE_GUARDED=y
+CONFIG_BAT7_USER_MODE_VALID=y
+CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xF8008000
+CONFIG_LBLAW3_NAME="PIB"
+CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI_33M,PQ_MDS_PIB=1"
@@ -21,3 +110,58 @@
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_32_KBYTES=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="PIB1"
+CONFIG_BR2_OR2_BASE=0xF8008000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_32_KBYTES=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_XAM_SET=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PIB2"
+CONFIG_BR3_OR3_BASE=0xF8010000
+CONFIG_BR3_MACHINE_GPCM=y
+CONFIG_BR3_PORTSIZE_8BIT=y
+CONFIG_OR3_AM_32_KBYTES=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_XAM_SET=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig
index 4aa34dc..472384f 100644
--- a/configs/MPC832XEMDS_HOST_66_defconfig
+++ b/configs/MPC832XEMDS_HOST_66_defconfig
@@ -1,7 +1,96 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC832XEMDS=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="BCSR"
+CONFIG_BAT2_BASE=0xF8000000
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xFE000000
+CONFIG_BAT3_LENGTH_32_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="STACK_IN_DCACHE"
+CONFIG_BAT5_BASE=0xE6000000
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="PCI_MEM_PHYS"
+CONFIG_BAT6_BASE=0x80000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT7=y
+CONFIG_BAT7_NAME="PCI1_MMIO_PHYS"
+CONFIG_BAT7_BASE=0x90000000
+CONFIG_BAT7_LENGTH_256_MBYTES=y
+CONFIG_BAT7_ACCESS_RW=y
+CONFIG_BAT7_ICACHE_INHIBITED=y
+CONFIG_BAT7_ICACHE_GUARDED=y
+CONFIG_BAT7_DCACHE_INHIBITED=y
+CONFIG_BAT7_DCACHE_GUARDED=y
+CONFIG_BAT7_USER_MODE_VALID=y
+CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xF8008000
+CONFIG_LBLAW3_NAME="PIB"
+CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI_66M,PQ_MDS_PIB=1"
@@ -21,3 +110,58 @@
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_32_KBYTES=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="PIB1"
+CONFIG_BR2_OR2_BASE=0xF8008000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_32_KBYTES=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_XAM_SET=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PIB2"
+CONFIG_BR3_OR3_BASE=0xF8010000
+CONFIG_BR3_MACHINE_GPCM=y
+CONFIG_BR3_PORTSIZE_8BIT=y
+CONFIG_OR3_AM_32_KBYTES=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_XAM_SET=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig
index 3320889..ec8a94c 100644
--- a/configs/MPC832XEMDS_SLAVE_defconfig
+++ b/configs/MPC832XEMDS_SLAVE_defconfig
@@ -1,7 +1,93 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC832XEMDS=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="BCSR"
+CONFIG_BAT2_BASE=0xF8000000
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xFE000000
+CONFIG_BAT3_LENGTH_32_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="STACK_IN_DCACHE"
+CONFIG_BAT5_BASE=0xE6000000
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="PCI_MEM_PHYS"
+CONFIG_BAT6_BASE=0x80000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT7=y
+CONFIG_BAT7_NAME="PCI1_MMIO_PHYS"
+CONFIG_BAT7_BASE=0x90000000
+CONFIG_BAT7_LENGTH_256_MBYTES=y
+CONFIG_BAT7_ACCESS_RW=y
+CONFIG_BAT7_ICACHE_INHIBITED=y
+CONFIG_BAT7_ICACHE_GUARDED=y
+CONFIG_BAT7_DCACHE_INHIBITED=y
+CONFIG_BAT7_DCACHE_GUARDED=y
+CONFIG_BAT7_USER_MODE_VALID=y
+CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xF8008000
+CONFIG_LBLAW3_NAME="PIB"
+CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
@@ -21,3 +107,58 @@
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_32_KBYTES=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="PIB1"
+CONFIG_BR2_OR2_BASE=0xF8008000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_32_KBYTES=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_XAM_SET=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PIB2"
+CONFIG_BR3_OR3_BASE=0xF8010000
+CONFIG_BR3_MACHINE_GPCM=y
+CONFIG_BR3_PORTSIZE_8BIT=y
+CONFIG_OR3_AM_32_KBYTES=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_XAM_SET=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig
index f3ec967..8a26001 100644
--- a/configs/MPC832XEMDS_defconfig
+++ b/configs/MPC832XEMDS_defconfig
@@ -1,7 +1,76 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC832XEMDS=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="BCSR"
+CONFIG_BAT2_BASE=0xF8000000
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xFE000000
+CONFIG_BAT3_LENGTH_32_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="STACK_IN_DCACHE"
+CONFIG_BAT5_BASE=0xE6000000
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xF8008000
+CONFIG_LBLAW3_NAME="PIB"
+CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
@@ -20,3 +89,58 @@
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_32_KBYTES=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="PIB1"
+CONFIG_BR2_OR2_BASE=0xF8008000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_32_KBYTES=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_XAM_SET=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PIB2"
+CONFIG_BR3_OR3_BASE=0xF8010000
+CONFIG_BR3_MACHINE_GPCM=y
+CONFIG_BR3_PORTSIZE_8BIT=y
+CONFIG_OR3_AM_32_KBYTES=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_XAM_SET=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig
new file mode 100644
index 0000000..35b394b
--- /dev/null
+++ b/configs/MPC8349EMDS_PCI64_defconfig
@@ -0,0 +1,108 @@
+CONFIG_PPC=y
+CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_MPC8349EMDS=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_64BIT_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE2400000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DATE=y
+# CONFIG_MMC is not set
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_TSEC_ENET=y
+# CONFIG_PCI is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xE2400000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_32_KBYTES=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_EHTR_NORMAL=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig
new file mode 100644
index 0000000..936458a
--- /dev/null
+++ b/configs/MPC8349EMDS_SDRAM_defconfig
@@ -0,0 +1,117 @@
+CONFIG_PPC=y
+CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_MPC8349EMDS_SDRAM=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE2400000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xF0000000
+CONFIG_LBLAW2_NAME="SDRAM"
+CONFIG_LBLAW2_LENGTH_64_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xE2400000
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="SDRAM"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_BR2_PORTSIZE_32BIT=y
+CONFIG_BR2_MACHINE_SDRAM=y
+CONFIG_OR2_COLS_9=y
+CONFIG_OR2_ROWS_13=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_PCI_ONE_PCI1=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DATE=y
+# CONFIG_MMC is not set
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_MARVELL=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
+# CONFIG_PCI is not set
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_MPC8XXX_SPI=y
+CONFIG_OF_LIBFDT=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig
new file mode 100644
index 0000000..9649967
--- /dev/null
+++ b/configs/MPC8349EMDS_SLAVE_defconfig
@@ -0,0 +1,108 @@
+CONFIG_PPC=y
+CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666666
+CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_MPC8349EMDS=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_64BIT_MODE_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE2400000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
+CONFIG_PCI_ONE_PCI1=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
+CONFIG_BOOTDELAY=6
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DATE=y
+# CONFIG_MMC is not set
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_NETDEVICES=y
+CONFIG_TSEC_ENET=y
+# CONFIG_PCI is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xE2400000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_32_KBYTES=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_EHTR_NORMAL=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig
index 41a1d96..bb0d166 100644
--- a/configs/MPC8349EMDS_defconfig
+++ b/configs/MPC8349EMDS_defconfig
@@ -1,7 +1,66 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8349EMDS=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE2400000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
+CONFIG_PCI_ONE_PCI1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
@@ -24,3 +83,29 @@
CONFIG_SPI=y
CONFIG_MPC8XXX_SPI=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xE2400000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_32_KBYTES=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_EHTR_NORMAL=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig
index 95d807b..eddb72b 100644
--- a/configs/MPC8349ITXGP_defconfig
+++ b/configs/MPC8349ITXGP_defconfig
@@ -1,9 +1,111 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666666
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8349ITX=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="PCI2_MEM"
+CONFIG_BAT3_BASE=0xA0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="PCI2_MMIO"
+CONFIG_BAT4_BASE=0xB0000000
+CONFIG_BAT4_LENGTH_256_MBYTES=y
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_ICACHE_INHIBITED=y
+CONFIG_BAT4_ICACHE_GUARDED=y
+CONFIG_BAT4_DCACHE_INHIBITED=y
+CONFIG_BAT4_DCACHE_GUARDED=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_16_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="VSC7385"
+CONFIG_LBLAW1_LENGTH_128_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xF0000000
+CONFIG_LBLAW3_NAME="CF"
+CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000"
CONFIG_BOOTDELAY=6
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitxgp:eth0:off console=ttyS0,115200"
@@ -29,3 +131,52 @@
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="VSC7385"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_128_KBYTES=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_SETA_EXTERNAL=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="LED"
+CONFIG_BR2_OR2_BASE=0xF9000000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_2_MBYTES=y
+CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_OR2_SCY_9=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="CF"
+CONFIG_BR3_OR3_BASE=0xF0000000
+CONFIG_BR3_MACHINE_UPMA=y
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_32_KBYTES=y
+CONFIG_OR3_BI_BURSTINHIBIT=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig
index 5166723..b394da3 100644
--- a/configs/MPC8349ITX_LOWBOOT_defconfig
+++ b/configs/MPC8349ITX_LOWBOOT_defconfig
@@ -1,10 +1,110 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666666
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8349ITX=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="PCI2_MEM"
+CONFIG_BAT3_BASE=0xA0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="PCI2_MMIO"
+CONFIG_BAT4_BASE=0xB0000000
+CONFIG_BAT4_LENGTH_256_MBYTES=y
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_ICACHE_INHIBITED=y
+CONFIG_BAT4_ICACHE_GUARDED=y
+CONFIG_BAT4_DCACHE_INHIBITED=y
+CONFIG_BAT4_DCACHE_GUARDED=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_16_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="VSC7385"
+CONFIG_LBLAW1_LENGTH_128_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xF0000000
+CONFIG_LBLAW3_NAME="CF"
+CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX"
CONFIG_BOOTDELAY=6
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitx:eth0:off console=ttyS0,115200"
@@ -39,3 +139,52 @@
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="VSC7385"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_128_KBYTES=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_SETA_EXTERNAL=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="LED"
+CONFIG_BR2_OR2_BASE=0xF9000000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_2_MBYTES=y
+CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_OR2_SCY_9=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="CF"
+CONFIG_BR3_OR3_BASE=0xF0000000
+CONFIG_BR3_MACHINE_UPMA=y
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_32_KBYTES=y
+CONFIG_OR3_BI_BURSTINHIBIT=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig
index 55e593c..274fbdd 100644
--- a/configs/MPC8349ITX_defconfig
+++ b/configs/MPC8349ITX_defconfig
@@ -1,10 +1,109 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFEF00000
+CONFIG_SYS_CLK_FREQ=66666666
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8349ITX=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="PCI2_MEM"
+CONFIG_BAT3_BASE=0xA0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="PCI2_MMIO"
+CONFIG_BAT4_BASE=0xB0000000
+CONFIG_BAT4_LENGTH_256_MBYTES=y
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_ICACHE_INHIBITED=y
+CONFIG_BAT4_ICACHE_GUARDED=y
+CONFIG_BAT4_DCACHE_INHIBITED=y
+CONFIG_BAT4_DCACHE_GUARDED=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="STACK_IN_DCACHE"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_16_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="VSC7385"
+CONFIG_LBLAW1_LENGTH_128_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xF0000000
+CONFIG_LBLAW3_NAME="CF"
+CONFIG_LBLAW3_LENGTH_64_KBYTES=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX"
CONFIG_BOOTDELAY=6
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitx:eth0:off console=ttyS0,115200"
@@ -39,3 +138,52 @@
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_16_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="VSC7385"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_128_KBYTES=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_SETA_EXTERNAL=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="LED"
+CONFIG_BR2_OR2_BASE=0xF9000000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_2_MBYTES=y
+CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_OR2_SCY_9=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="CF"
+CONFIG_BR3_OR3_BASE=0xF0000000
+CONFIG_BR3_MACHINE_UPMA=y
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_32_KBYTES=y
+CONFIG_OR3_BI_BURSTINHIBIT=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig
index 4ac9573..6e6fc54 100644
--- a/configs/MPC837XEMDS_HOST_defconfig
+++ b/configs/MPC837XEMDS_HOST_defconfig
@@ -1,7 +1,112 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC837XEMDS=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_6_1=y
+CONFIG_CORE_PLL_RATIO_15_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM_LOWER"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="SDRAM_UPPER"
+CONFIG_BAT1_BASE=0x10000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="IMMR"
+CONFIG_BAT2_BASE=0xE0000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="BCSR"
+CONFIG_BAT3_BASE=0xF8000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_INHIBITED=y
+CONFIG_BAT3_ICACHE_GUARDED=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="FLASH"
+CONFIG_BAT4_BASE=0xFE000000
+CONFIG_BAT4_LENGTH_32_MBYTES=y
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT4_DCACHE_INHIBITED=y
+CONFIG_BAT4_DCACHE_GUARDED=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="STACK_IN_DCACHE"
+CONFIG_BAT5_BASE=0xE6000000
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="PCI_MEM"
+CONFIG_BAT6_BASE=0x80000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT7=y
+CONFIG_BAT7_NAME="PCI_MMIO"
+CONFIG_BAT7_BASE=0x90000000
+CONFIG_BAT7_LENGTH_256_MBYTES=y
+CONFIG_BAT7_ACCESS_RW=y
+CONFIG_BAT7_ICACHE_INHIBITED=y
+CONFIG_BAT7_ICACHE_GUARDED=y
+CONFIG_BAT7_DCACHE_INHIBITED=y
+CONFIG_BAT7_DCACHE_GUARDED=y
+CONFIG_BAT7_USER_MODE_VALID=y
+CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xE0600000
+CONFIG_LBLAW3_NAME="NAND"
+CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
@@ -32,3 +137,46 @@
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_32_KBYTES=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="NAND"
+CONFIG_BR3_OR3_BASE=0xE0600000
+CONFIG_BR3_ERRORCHECKING_BOTH=y
+CONFIG_BR3_MACHINE_FCM=y
+CONFIG_BR3_PORTSIZE_8BIT=y
+CONFIG_OR3_AM_32_KBYTES=y
+CONFIG_OR3_BCTLD_NOT_ASSERTED=y
+CONFIG_OR3_RST_ONE_CLOCK=y
+CONFIG_OR3_SCY_1=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_CHT_TWO_CLOCK=y
+CONFIG_OR3_CST_ONE_CLOCK=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig
new file mode 100644
index 0000000..421e176
--- /dev/null
+++ b/configs/MPC837XEMDS_SLAVE_defconfig
@@ -0,0 +1,135 @@
+CONFIG_PPC=y
+CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
+CONFIG_MPC83xx=y
+CONFIG_TARGET_MPC837XEMDS=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_6_1=y
+CONFIG_CORE_PLL_RATIO_15_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM_LOWER"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="SDRAM_UPPER"
+CONFIG_BAT1_BASE=0x10000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="IMMR"
+CONFIG_BAT2_BASE=0xE0000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="BCSR"
+CONFIG_BAT3_BASE=0xF8000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_INHIBITED=y
+CONFIG_BAT3_ICACHE_GUARDED=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xE0600000
+CONFIG_LBLAW3_NAME="NAND"
+CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
+CONFIG_BOOTDELAY=6
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DATE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_TSEC_ENET=y
+# CONFIG_PCI is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_32_KBYTES=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="NAND"
+CONFIG_BR3_OR3_BASE=0xE0600000
+CONFIG_BR3_ERRORCHECKING_BOTH=y
+CONFIG_BR3_MACHINE_FCM=y
+CONFIG_BR3_PORTSIZE_8BIT=y
+CONFIG_OR3_AM_32_KBYTES=y
+CONFIG_OR3_BCTLD_NOT_ASSERTED=y
+CONFIG_OR3_RST_ONE_CLOCK=y
+CONFIG_OR3_SCY_1=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_CHT_TWO_CLOCK=y
+CONFIG_OR3_CST_ONE_CLOCK=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig
index 9ee8c7d..cd03f3f 100644
--- a/configs/MPC837XEMDS_defconfig
+++ b/configs/MPC837XEMDS_defconfig
@@ -1,7 +1,92 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC837XEMDS=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_6_1=y
+CONFIG_CORE_PLL_RATIO_15_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM_LOWER"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="SDRAM_UPPER"
+CONFIG_BAT1_BASE=0x10000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="IMMR"
+CONFIG_BAT2_BASE=0xE0000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="BCSR"
+CONFIG_BAT3_BASE=0xF8000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_INHIBITED=y
+CONFIG_BAT3_ICACHE_GUARDED=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="FLASH"
+CONFIG_BAT4_BASE=0xFE000000
+CONFIG_BAT4_LENGTH_32_MBYTES=y
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT4_DCACHE_INHIBITED=y
+CONFIG_BAT4_DCACHE_GUARDED=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="STACK_IN_DCACHE"
+CONFIG_BAT5_BASE=0xE6000000
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF8000000
+CONFIG_LBLAW1_NAME="BCSR"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xE0600000
+CONFIG_LBLAW3_NAME="NAND"
+CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
@@ -28,3 +113,46 @@
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="BCSR"
+CONFIG_BR1_OR1_BASE=0xF8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_32_KBYTES=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="NAND"
+CONFIG_BR3_OR3_BASE=0xE0600000
+CONFIG_BR3_ERRORCHECKING_BOTH=y
+CONFIG_BR3_MACHINE_FCM=y
+CONFIG_BR3_PORTSIZE_8BIT=y
+CONFIG_OR3_AM_32_KBYTES=y
+CONFIG_OR3_BCTLD_NOT_ASSERTED=y
+CONFIG_OR3_RST_ONE_CLOCK=y
+CONFIG_OR3_SCY_1=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_CHT_TWO_CLOCK=y
+CONFIG_OR3_CST_ONE_CLOCK=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig
new file mode 100644
index 0000000..c90ebc8
--- /dev/null
+++ b/configs/MPC837XERDB_SLAVE_defconfig
@@ -0,0 +1,136 @@
+CONFIG_PPC=y
+CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666667
+CONFIG_MPC83xx=y
+CONFIG_TARGET_MPC837XERDB=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_5_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM_LOWER"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="SDRAM_UPPER"
+CONFIG_BAT1_BASE=0x10000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="IMMR"
+CONFIG_BAT2_BASE=0xE0000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="L2_SWITCH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_INHIBITED=y
+CONFIG_BAT3_ICACHE_GUARDED=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="NAND"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xF0000000
+CONFIG_LBLAW2_NAME="VSC7385"
+CONFIG_LBLAW2_LENGTH_128_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE"
+CONFIG_BOOTDELAY=6
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DATE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_FSL_SATA=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_TSEC_ENET=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_9=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_EHTR_1_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_32_KBYTES=y
+CONFIG_OR1_SCY_1=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index 45b68e9..95f4796 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -1,9 +1,115 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=66666667
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC837XERDB=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_5_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM_LOWER"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="SDRAM_UPPER"
+CONFIG_BAT1_BASE=0x10000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="IMMR"
+CONFIG_BAT2_BASE=0xE0000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="L2_SWITCH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_INHIBITED=y
+CONFIG_BAT3_ICACHE_GUARDED=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="FLASH"
+CONFIG_BAT4_BASE=0xFE000000
+CONFIG_BAT4_LENGTH_32_MBYTES=y
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT4_DCACHE_INHIBITED=y
+CONFIG_BAT4_DCACHE_GUARDED=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="STACH_IN_DCACHE"
+CONFIG_BAT5_BASE=0xE6000000
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="PCI_MEM"
+CONFIG_BAT6_BASE=0x80000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT7=y
+CONFIG_BAT7_NAME="PCI_MMIO"
+CONFIG_BAT7_BASE=0x90000000
+CONFIG_BAT7_LENGTH_256_MBYTES=y
+CONFIG_BAT7_ACCESS_RW=y
+CONFIG_BAT7_ICACHE_INHIBITED=y
+CONFIG_BAT7_ICACHE_GUARDED=y
+CONFIG_BAT7_DCACHE_INHIBITED=y
+CONFIG_BAT7_DCACHE_GUARDED=y
+CONFIG_BAT7_USER_MODE_VALID=y
+CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="NAND"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xF0000000
+CONFIG_LBLAW2_NAME="VSC7385"
+CONFIG_LBLAW2_LENGTH_128_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="PCIE"
CONFIG_BOOTDELAY=6
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
@@ -33,3 +139,41 @@
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_9=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_EHTR_1_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_32_KBYTES=y
+CONFIG_OR1_SCY_1=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="VSC7385"
+CONFIG_BR2_OR2_BASE=0xF0000000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_OR2_SCY_15=y
+CONFIG_OR2_SETA_EXTERNAL=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
diff --git a/configs/MPC8610HPCD_defconfig b/configs/MPC8610HPCD_defconfig
index cfdfa90..80ea441 100644
--- a/configs/MPC8610HPCD_defconfig
+++ b/configs/MPC8610HPCD_defconfig
@@ -1,6 +1,7 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xfff00000
CONFIG_MPC86xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8610HPCD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig
index 4b924c0..81901f7 100644
--- a/configs/MPC8641HPCN_36BIT_defconfig
+++ b/configs/MPC8641HPCN_36BIT_defconfig
@@ -1,6 +1,7 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xeff00000
CONFIG_MPC86xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8641HPCN=y
CONFIG_PHYS_64BIT=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig
index 52fba97..497d398 100644
--- a/configs/MPC8641HPCN_defconfig
+++ b/configs/MPC8641HPCN_defconfig
@@ -1,6 +1,7 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xeff00000
CONFIG_MPC86xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8641HPCN=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig
index e1a7a06..9d9f105 100644
--- a/configs/TQM834x_defconfig
+++ b/configs/TQM834x_defconfig
@@ -1,7 +1,110 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x80000000
+CONFIG_SYS_CLK_FREQ=66666000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_TQM834X=y
+CONFIG_SYS_IMMR=0xff400000
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM_LOWER"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="SDRAM_UPPER"
+CONFIG_BAT1_BASE=0x10000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="STACK_IN_DCACHE"
+CONFIG_BAT2_BASE=0x20000000
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="PCI_MEM_BASE"
+CONFIG_BAT3_BASE=0x90000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="PCI_MMIO"
+CONFIG_BAT4_BASE=0xA0000000
+CONFIG_BAT4_LENGTH_256_MBYTES=y
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT4_ICACHE_GUARDED=y
+CONFIG_BAT4_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT4_DCACHE_GUARDED=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="PCI_IO"
+CONFIG_BAT5_BASE=0xE2000000
+CONFIG_BAT5_LENGTH_16_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="IMMR"
+CONFIG_BAT6_BASE=0xFF400000
+CONFIG_BAT6_LENGTH_1_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_INHIBITED=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_INHIBITED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT7=y
+CONFIG_BAT7_NAME="FLASH"
+CONFIG_BAT7_BASE=0x80000000
+CONFIG_BAT7_LENGTH_256_MBYTES=y
+CONFIG_BAT7_ACCESS_RW=y
+CONFIG_BAT7_ICACHE_INHIBITED=y
+CONFIG_BAT7_ICACHE_GUARDED=y
+CONFIG_BAT7_DCACHE_INHIBITED=y
+CONFIG_BAT7_DCACHE_GUARDED=y
+CONFIG_BAT7_USER_MODE_VALID=y
+CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0x80000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_1_GBYTES=y
+CONFIG_LBLAW1=y
+# CONFIG_LBLAW1_ENABLE is not set
+CONFIG_LBLAW2=y
+# CONFIG_LBLAW2_ENABLE is not set
+CONFIG_LBLAW3=y
+# CONFIG_LBLAW3_ENABLE is not set
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
@@ -34,3 +137,15 @@
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0x80000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_32BIT=y
+CONFIG_OR0_AM_1_GBYTES=y
+CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_8=y
diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig
index 5fec4f8..192c344 100644
--- a/configs/caddy2_defconfig
+++ b/configs/caddy2_defconfig
@@ -1,10 +1,81 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF00000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
-CONFIG_TARGET_VME8349=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_CADDY2=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR_PCIIO"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="UNKNOWN"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFFC00000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_4_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF0000000
+CONFIG_LBLAW1_NAME="WINDOW1"
+CONFIG_LBLAW1_LENGTH_256_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="CADDY2"
CONFIG_BOOTDELAY=6
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
@@ -24,3 +95,24 @@
CONFIG_BAUDRATE=9600
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFFC00000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_4_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="WINDOW1"
+CONFIG_BR1_OR1_BASE=0xF0000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_32BIT=y
+CONFIG_OR1_AM_256_KBYTES=y
+CONFIG_OR1_SETA_EXTERNAL=y
diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig
new file mode 100644
index 0000000..346b1b2
--- /dev/null
+++ b/configs/gazerbeam_defconfig
@@ -0,0 +1,196 @@
+CONFIG_PPC=y
+CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_MALLOC_F_LEN=0x600
+CONFIG_IDENT_STRING=" gazerbeam 0.01"
+CONFIG_SYS_CLK_FREQ=33333333
+CONFIG_MPC83xx=y
+CONFIG_TARGET_GAZERBEAM=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_128_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_8_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFE000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="INIT_RAM"
+CONFIG_BAT3_BASE=0xE6000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="FPGA0"
+CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xE0700000
+CONFIG_LBLAW2_NAME="FPGA1"
+CONFIG_LBLAW2_LENGTH_1_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA0"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_SCY_5=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="FPGA1"
+CONFIG_BR2_OR2_BASE=0xE0700000
+CONFIG_BR2_PORTSIZE_16BIT=y
+CONFIG_OR2_AM_1_MBYTES=y
+CONFIG_OR2_SCY_5=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y
+CONFIG_SICR_GPIO_A_TSEC2=y
+CONFIG_SICR_GPIO_B_TSEC_GTX_CLK125=y
+CONFIG_SICR_IEEE1588_A_GPIO=y
+CONFIG_SICR_GTM_GPIO=y
+CONFIG_SICR_ETSEC2_GPIO=y
+CONFIG_SICR_GPIOSEL_IEEE1588=y
+CONFIG_SICR_TMSOBI1_2_5_V=y
+CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
+CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM=y
+CONFIG_CMD_IOLOOP=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=5
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_CPUINFO=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_CPU=y
+CONFIG_CMD_BINOP=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_AXI=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_MII_DRIVER=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_EXT2=y
+CONFIG_DOS_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_DEFAULT_DEVICE_TREE="gazerbeam"
+CONFIG_DM=y
+CONFIG_REGMAP=y
+CONFIG_AXI=y
+CONFIG_IHS_AXI=y
+CONFIG_CLK=y
+CONFIG_ICS8N3QV01=y
+CONFIG_CPU=y
+CONFIG_CPU_MPC83XX=y
+CONFIG_BOARD=y
+CONFIG_BOARD_GAZERBEAM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_MPC8XXX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_I2C_IHS=y
+CONFIG_MISC=y
+CONFIG_GDSYS_RXAUI_CTRL=y
+CONFIG_GDSYS_IOEP=y
+CONFIG_MPC83XX_SERDES=y
+CONFIG_GDSYS_SOC=y
+CONFIG_IHS_FPGA=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_PROTECTION=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_MARVELL=y
+CONFIG_DM_ETH=y
+CONFIG_TSEC_ENET=y
+# CONFIG_PCI is not set
+CONFIG_RAM=y
+CONFIG_MPC83XX_SDRAM=y
+CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_MCP83XX=y
+CONFIG_TIMER=y
+CONFIG_MPC83XX_TIMER=y
+CONFIG_TPM_ATMEL_TWI=y
+CONFIG_TPM_AUTH_SESSIONS=y
+# CONFIG_TPM_V2 is not set
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_LOGICORE_DP_TX=y
+CONFIG_OSD=y
+CONFIG_IHS_VIDEO_OUT=y
+CONFIG_TPM=y
diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig
index 7605c56..bc4c2a9 100644
--- a/configs/hrcon_defconfig
+++ b/configs/hrcon_defconfig
@@ -1,8 +1,75 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_IDENT_STRING=" hrcon 0.01"
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_HRCON=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_128_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMRBAR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_8_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFE000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="STACK_IN_DCACHE"
+CONFIG_BAT3_BASE=0xE6000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="FPGA0"
+CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y
+CONFIG_SICR_GPIO_A_GPIO=y
+CONFIG_SICR_GPIO_B_GPIO=y
+CONFIG_SICR_IEEE1588_A_GPIO=y
+CONFIG_SICR_GTM_GPIO=y
+CONFIG_SICR_ETSEC2_GPIO=y
+CONFIG_SICR_GPIOSEL_IEEE1588=y
+CONFIG_SICR_TMSOBI1_2_5_V=y
+CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -38,3 +105,31 @@
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig
index bc51a5d..af93aef 100644
--- a/configs/hrcon_dh_defconfig
+++ b/configs/hrcon_dh_defconfig
@@ -1,8 +1,75 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_IDENT_STRING=" hrcon dh 0.01"
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_HRCON=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_RGMII=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_128_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMRBAR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_8_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFE000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="STACK_IN_DCACHE"
+CONFIG_BAT3_BASE=0xE6000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="FPGA0"
+CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y
+CONFIG_SICR_GPIO_A_GPIO=y
+CONFIG_SICR_GPIO_B_GPIO=y
+CONFIG_SICR_IEEE1588_A_GPIO=y
+CONFIG_SICR_GTM_GPIO=y
+CONFIG_SICR_ETSEC2_GPIO=y
+CONFIG_SICR_GPIOSEL_IEEE1588=y
+CONFIG_SICR_TMSOBI1_2_5_V=y
+CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -36,3 +103,31 @@
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_SCY_15=y
+CONFIG_OR1_XACS_EXTENDED=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig
index 0d055e39..d9b1642 100644
--- a/configs/ids8313_defconfig
+++ b/configs/ids8313_defconfig
@@ -1,7 +1,81 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF00000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_IDS8313=y
+CONFIG_SYS_IMMR=0xF0000000
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_8BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="INITRAM"
+CONFIG_BAT1_BASE=0xFD000000
+CONFIG_BAT1_LENGTH_256_KBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFF800000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR"
+CONFIG_BAT5_BASE=0xF0000000
+CONFIG_BAT5_LENGTH_128_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="NAND_MRAM_CPLD"
+CONFIG_BAT6_BASE=0xE0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_NAND_LBLAWBAR_PRELIM_1=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFF800000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE1000000
+CONFIG_LBLAW1_NAME="NAND"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xE2000000
+CONFIG_LBLAW2_NAME="MRAM"
+CONFIG_LBLAW2_LENGTH_128_KBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xE3000000
+CONFIG_LBLAW3_NAME="CPLD"
+CONFIG_LBLAW3_LENGTH_32_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_IMAGE_FORMAT_LEGACY=y
@@ -51,3 +125,50 @@
CONFIG_SPI=y
CONFIG_MPC8XXX_SPI=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFF800000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_8BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_10=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0xE1000000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_32_KBYTES=y
+CONFIG_OR1_PGS_LARGE=y
+CONFIG_OR1_RST_ONE_CLOCK=y
+CONFIG_OR1_SCY_4=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_OR1_CSCT_8_CYCLE=y
+CONFIG_OR1_CST_ONE_CLOCK=y
+CONFIG_OR1_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="MRAM"
+CONFIG_BR2_OR2_BASE=0xE2000000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_SCY_7=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="CPLD"
+CONFIG_BR3_OR3_BASE=0xE3000000
+CONFIG_BR3_MACHINE_GPCM=y
+CONFIG_BR3_PORTSIZE_8BIT=y
+CONFIG_OR3_AM_32_KBYTES=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_SCY_1=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig
index cb47b0b..941efcd 100644
--- a/configs/kmcoge5ne_defconfig
+++ b/configs/kmcoge5ne_defconfig
@@ -1,10 +1,118 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
-CONFIG_TARGET_KM8360=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_KMCOGE5NE=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_VCO_DIV_4=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_6=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_LALE_TIMING_EARLIER=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM_LOWER"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_INHIBITED=y
+CONFIG_BAT0_ICACHE_GUARDED=y
+CONFIG_BAT0_DCACHE_INHIBITED=y
+CONFIG_BAT0_DCACHE_GUARDED=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="KMBEC_FPGA"
+CONFIG_BAT2_BASE=0xE8000000
+CONFIG_BAT2_LENGTH_128_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="PAXE"
+CONFIG_BAT5_BASE=0xA0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="BFTIC3"
+CONFIG_BAT6_BASE=0xB0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_INHIBITED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT7=y
+CONFIG_BAT7_NAME="SDRAM_UPPER"
+CONFIG_BAT7_BASE=0x10000000
+CONFIG_BAT7_LENGTH_256_MBYTES=y
+CONFIG_BAT7_ACCESS_RW=y
+CONFIG_BAT7_ICACHE_INHIBITED=y
+CONFIG_BAT7_ICACHE_GUARDED=y
+CONFIG_BAT7_DCACHE_INHIBITED=y
+CONFIG_BAT7_DCACHE_GUARDED=y
+CONFIG_BAT7_USER_MODE_VALID=y
+CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xA0000000
+CONFIG_LBLAW3_NAME="PAXE"
+CONFIG_LBLAW3_LENGTH_512_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="KMCOGE5NE"
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_R=y
@@ -42,3 +150,48 @@
CONFIG_SYS_NS16550=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_64_MBYTES=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PAXE"
+CONFIG_BR3_OR3_BASE=0xA0000000
+CONFIG_BR3_PORTSIZE_8BIT=y
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_OR3_SCY_2=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_ELBC_BR4_OR4=y
+CONFIG_BR4_OR4_NAME="BFTIC3"
+CONFIG_BR4_OR4_BASE=0xB0000000
+CONFIG_BR4_PORTSIZE_8BIT=y
+CONFIG_OR4_AM_256_MBYTES=y
+CONFIG_OR4_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR4_CSNT_EARLIER=y
+CONFIG_OR4_EAD_EXTRA=y
+CONFIG_OR4_SCY_2=y
+CONFIG_OR4_TRLX_RELAXED=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
+CONFIG_LCRR_EADC_2=y
diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig
index 0c3fadf..4929a60 100644
--- a/configs/kmeter1_defconfig
+++ b/configs/kmeter1_defconfig
@@ -1,10 +1,91 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
-CONFIG_TARGET_KM8360=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_KMETER1=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_VCO_DIV_4=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_6=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_LALE_TIMING_EARLIER=y
+CONFIG_LDP_PIN_MUX_STATE_0=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_INHIBITED=y
+CONFIG_BAT0_ICACHE_GUARDED=y
+CONFIG_BAT0_DCACHE_INHIBITED=y
+CONFIG_BAT0_DCACHE_GUARDED=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="KMBEC_FPGA"
+CONFIG_BAT2_BASE=0xE8000000
+CONFIG_BAT2_LENGTH_128_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="PAXE"
+CONFIG_BAT5_BASE=0xA0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xA0000000
+CONFIG_LBLAW3_NAME="PAXE"
+CONFIG_LBLAW3_LENGTH_512_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="KMETER1"
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_R=y
@@ -41,3 +122,38 @@
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_64_MBYTES=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PAXE"
+CONFIG_BR3_OR3_BASE=0xA0000000
+CONFIG_BR3_PORTSIZE_8BIT=y
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_OR3_SCY_2=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
+CONFIG_LCRR_EADC_2=y
diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig
index e8e821f..afe424b 100644
--- a/configs/kmopti2_defconfig
+++ b/configs/kmopti2_defconfig
@@ -1,10 +1,106 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
-CONFIG_TARGET_TUXX1=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_KMOPTI2=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_INHIBITED=y
+CONFIG_BAT0_ICACHE_GUARDED=y
+CONFIG_BAT0_DCACHE_INHIBITED=y
+CONFIG_BAT0_DCACHE_GUARDED=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="KMBEC_FPGA"
+CONFIG_BAT2_BASE=0xE8000000
+CONFIG_BAT2_LENGTH_128_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="APP1"
+CONFIG_BAT5_BASE=0xA0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="APP2"
+CONFIG_BAT6_BASE=0xB0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_INHIBITED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xA0000000
+CONFIG_LBLAW2_NAME="APP1"
+CONFIG_LBLAW2_LENGTH_256_MBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xB0000000
+CONFIG_LBLAW3_NAME="APP2"
+CONFIG_LBLAW3_LENGTH_256_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="KMOPTI2"
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_R=y
@@ -41,3 +137,48 @@
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_OR2_SCY_2=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_4_CYCLE=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="APP2"
+CONFIG_BR3_OR3_BASE=0xB0000000
+CONFIG_BR3_MACHINE_GPCM=y
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_SCY_4=y
+CONFIG_OR3_EHTR_NORMAL=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig
index 86e2bd9..1a78680 100644
--- a/configs/kmsupx5_defconfig
+++ b/configs/kmsupx5_defconfig
@@ -1,10 +1,92 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
-CONFIG_TARGET_TUXX1=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_KMSUPX5=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_INHIBITED=y
+CONFIG_BAT0_ICACHE_GUARDED=y
+CONFIG_BAT0_DCACHE_INHIBITED=y
+CONFIG_BAT0_DCACHE_GUARDED=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="KMBEC_FPGA"
+CONFIG_BAT2_BASE=0xE8000000
+CONFIG_BAT2_LENGTH_128_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="APP1"
+CONFIG_BAT5_BASE=0xA0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xA0000000
+CONFIG_LBLAW2_NAME="APP1"
+CONFIG_LBLAW2_LENGTH_256_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="KMSUPX5"
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_R=y
@@ -41,3 +123,40 @@
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_OR2_SCY_2=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_4_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig
index 4018175..d874149 100644
--- a/configs/kmtegr1_defconfig
+++ b/configs/kmtegr1_defconfig
@@ -1,7 +1,91 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
-CONFIG_TARGET_SUVD3=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_KMTEGR1=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_INHIBITED=y
+CONFIG_BAT0_ICACHE_GUARDED=y
+CONFIG_BAT0_DCACHE_INHIBITED=y
+CONFIG_BAT0_DCACHE_GUARDED=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="KMBEC_FPGA"
+CONFIG_BAT2_BASE=0xE8000000
+CONFIG_BAT2_LENGTH_128_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="APP2"
+CONFIG_BAT6_BASE=0xB0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_INHIBITED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xB0000000
+CONFIG_LBLAW3_NAME="APP2"
+CONFIG_LBLAW3_LENGTH_256_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1"
@@ -43,3 +127,36 @@
CONFIG_SYS_NS16550=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="APP2"
+CONFIG_BR3_OR3_BASE=0xB0000000
+CONFIG_BR3_MACHINE_GPCM=y
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_SCY_5=y
+CONFIG_OR3_EHTR_NORMAL=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig
index 6170dc3..32d0980 100644
--- a/configs/kmtepr2_defconfig
+++ b/configs/kmtepr2_defconfig
@@ -1,10 +1,106 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
-CONFIG_TARGET_TUXX1=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_KMTEPR2=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_INHIBITED=y
+CONFIG_BAT0_ICACHE_GUARDED=y
+CONFIG_BAT0_DCACHE_INHIBITED=y
+CONFIG_BAT0_DCACHE_GUARDED=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="KMBEC_FPGA"
+CONFIG_BAT2_BASE=0xE8000000
+CONFIG_BAT2_LENGTH_128_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="APP1"
+CONFIG_BAT5_BASE=0xA0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="APP2"
+CONFIG_BAT6_BASE=0xB0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_INHIBITED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xA0000000
+CONFIG_LBLAW2_NAME="APP1"
+CONFIG_LBLAW2_LENGTH_256_MBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xB0000000
+CONFIG_LBLAW3_NAME="APP2"
+CONFIG_LBLAW3_LENGTH_256_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="KMTEPR2"
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_R=y
@@ -41,3 +137,48 @@
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_OR2_SCY_2=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_4_CYCLE=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="APP2"
+CONFIG_BR3_OR3_BASE=0xB0000000
+CONFIG_BR3_MACHINE_GPCM=y
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_SCY_4=y
+CONFIG_OR3_EHTR_NORMAL=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig
index 74b688f..26d9a7c 100644
--- a/configs/kmvect1_defconfig
+++ b/configs/kmvect1_defconfig
@@ -1,7 +1,105 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
-CONFIG_TARGET_SUVD3=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_KMVECT1=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_INHIBITED=y
+CONFIG_BAT0_ICACHE_GUARDED=y
+CONFIG_BAT0_DCACHE_INHIBITED=y
+CONFIG_BAT0_DCACHE_GUARDED=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="KMBEC_FPGA"
+CONFIG_BAT2_BASE=0xE8000000
+CONFIG_BAT2_LENGTH_128_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="APP1"
+CONFIG_BAT5_BASE=0xA0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="APP2"
+CONFIG_BAT6_BASE=0xB0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_INHIBITED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xA0000000
+CONFIG_LBLAW2_NAME="APP1"
+CONFIG_LBLAW2_LENGTH_256_MBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xB0000000
+CONFIG_LBLAW3_NAME="APP2"
+CONFIG_LBLAW3_LENGTH_256_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="KMVECT1"
@@ -42,3 +140,43 @@
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_BR2_MACHINE_UPMA=y
+CONFIG_BR2_PORTSIZE_16BIT=y
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="APP2"
+CONFIG_BR3_OR3_BASE=0xB0000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_SCY_3=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig
index 114ffee..0789ecd 100644
--- a/configs/mpc8308_p1m_defconfig
+++ b/configs/mpc8308_p1m_defconfig
@@ -1,7 +1,76 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFC000000
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8308_P1M=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_128_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMRBAR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_8_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFC000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="STACKINDCACHE"
+CONFIG_BAT3_BASE=0xE6000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFC000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_64_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xFBFF0000
+CONFIG_LBLAW1_NAME="SJA1000"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xFBFF8000
+CONFIG_LBLAW2_NAME="CPLD"
+CONFIG_LBLAW2_LENGTH_32_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_SICR_ESDHC_A_GPIO=y
+CONFIG_SICR_ESDHC_B_GPIO=y
+CONFIG_SICR_ESDHC_C_GTM=y
+CONFIG_SICR_GPIO_A_TSEC2=y
+CONFIG_SICR_GPIO_B_TSEC2=y
+CONFIG_SICR_IEEE1588_A_GPIO=y
+CONFIG_SICR_GTM_GPIO=y
+CONFIG_SICR_GPIOSEL_IEEE1588=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=5
@@ -24,3 +93,34 @@
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFC000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_64_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_SCY_4=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="SJA1000"
+CONFIG_BR1_OR1_BASE=0xFBFF0000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_32_KBYTES=y
+CONFIG_OR1_SCY_5=y
+CONFIG_OR1_EHTR_1_CYCLE=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="CPLD"
+CONFIG_BR2_OR2_BASE=0xFBFF8000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_32_KBYTES=y
+CONFIG_OR2_SCY_4=y
+CONFIG_OR2_EHTR_1_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig
index 02d5185..a363070 100644
--- a/configs/sbc8349_PCI_33_defconfig
+++ b/configs/sbc8349_PCI_33_defconfig
@@ -1,7 +1,78 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_SYS_CLK_FREQ=33000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_SBC8349=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_8_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_64BIT_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR_PCIIO"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="LBC_INITRAM_FLASH"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFF800000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_PCI_64BIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI_33M"
@@ -21,3 +92,19 @@
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFF800000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig
index 945c522..215f31d 100644
--- a/configs/sbc8349_PCI_66_defconfig
+++ b/configs/sbc8349_PCI_66_defconfig
@@ -1,7 +1,78 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_SBC8349=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_64BIT_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR_PCIIO"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="LBC_INITRAM_FLASH"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFF800000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_PCI_64BIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI_66M"
@@ -21,3 +92,19 @@
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFF800000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig
index 82379e6..d492b86 100644
--- a/configs/sbc8349_defconfig
+++ b/configs/sbc8349_defconfig
@@ -1,7 +1,57 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_SBC8349=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_PCI_INT_ARBITER2_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR_PCIIO"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="LBC_INITRAM_FLASH"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFF800000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
@@ -20,3 +70,19 @@
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFF800000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/sbc8641d_defconfig b/configs/sbc8641d_defconfig
index d1ffea5..47cec18 100644
--- a/configs/sbc8641d_defconfig
+++ b/configs/sbc8641d_defconfig
@@ -1,6 +1,7 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xfff00000
CONFIG_MPC86xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_SBC8641D=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig
index 24c793d..9f05b56 100644
--- a/configs/strider_con_defconfig
+++ b/configs/strider_con_defconfig
@@ -1,8 +1,74 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_IDENT_STRING=" strider con 0.01"
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_128_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMRBAR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_8_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFE000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="STACK_IN_DCACHE"
+CONFIG_BAT3_BASE=0xE6000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="FPGA0"
+CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_SICR_ETSEC1_A_TSEC2=y
+CONFIG_SICR_GPIO_A_GPIO=y
+CONFIG_SICR_GPIO_B_GPIO=y
+CONFIG_SICR_IEEE1588_A_GPIO=y
+CONFIG_SICR_GTM_GPIO=y
+CONFIG_SICR_ETSEC2_GPIO=y
+CONFIG_SICR_GPIOSEL_IEEE1588=y
+CONFIG_SICR_TMSOBI1_2_5_V=y
+CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -41,3 +107,28 @@
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_SCY_5=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_EHTR_NORMAL=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig
index c70d99a..a1f9662 100644
--- a/configs/strider_con_dp_defconfig
+++ b/configs/strider_con_dp_defconfig
@@ -1,8 +1,74 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_IDENT_STRING=" strider con dp 0.01"
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_128_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMRBAR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_8_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFE000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="STACK_IN_DCACHE"
+CONFIG_BAT3_BASE=0xE6000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="FPGA0"
+CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_SICR_ETSEC1_A_TSEC2=y
+CONFIG_SICR_GPIO_A_GPIO=y
+CONFIG_SICR_GPIO_B_GPIO=y
+CONFIG_SICR_IEEE1588_A_GPIO=y
+CONFIG_SICR_GTM_GPIO=y
+CONFIG_SICR_ETSEC2_GPIO=y
+CONFIG_SICR_GPIOSEL_IEEE1588=y
+CONFIG_SICR_TMSOBI1_2_5_V=y
+CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -41,3 +107,28 @@
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_SCY_5=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_EHTR_NORMAL=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig
index fef5884..2477ee5 100644
--- a/configs/strider_cpu_defconfig
+++ b/configs/strider_cpu_defconfig
@@ -1,8 +1,74 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_IDENT_STRING=" strider cpu 0.01"
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_128_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMRBAR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_8_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFE000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="STACK_IN_DCACHE"
+CONFIG_BAT3_BASE=0xE6000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="FPGA0"
+CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_SICR_ETSEC1_A_TSEC2=y
+CONFIG_SICR_GPIO_A_GPIO=y
+CONFIG_SICR_GPIO_B_GPIO=y
+CONFIG_SICR_IEEE1588_A_GPIO=y
+CONFIG_SICR_GTM_GPIO=y
+CONFIG_SICR_ETSEC2_GPIO=y
+CONFIG_SICR_GPIOSEL_IEEE1588=y
+CONFIG_SICR_TMSOBI1_2_5_V=y
+CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -41,3 +107,28 @@
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_SCY_5=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_EHTR_NORMAL=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig
index fc8f39e..da16d5d 100644
--- a/configs/strider_cpu_dp_defconfig
+++ b/configs/strider_cpu_dp_defconfig
@@ -1,8 +1,74 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_IDENT_STRING=" strider cpu dp 0.01"
+CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
+CONFIG_SYSTEM_PLL_VCO_DIV_2=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_3_1=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC2_MODE_RGMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="DDR"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_128_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMRBAR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_8_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="FLASH"
+CONFIG_BAT2_BASE=0xFE000000
+CONFIG_BAT2_LENGTH_8_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="STACK_IN_DCACHE"
+CONFIG_BAT3_BASE=0xE6000000
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_8_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE0600000
+CONFIG_LBLAW1_NAME="FPGA0"
+CONFIG_LBLAW1_LENGTH_1_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_DPM=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_SICR_ETSEC1_A_TSEC2=y
+CONFIG_SICR_GPIO_A_GPIO=y
+CONFIG_SICR_GPIO_B_GPIO=y
+CONFIG_SICR_IEEE1588_A_GPIO=y
+CONFIG_SICR_GTM_GPIO=y
+CONFIG_SICR_ETSEC2_GPIO=y
+CONFIG_SICR_GPIOSEL_IEEE1588=y
+CONFIG_SICR_TMSOBI1_2_5_V=y
+CONFIG_SICR_TMSOBI2_2_5_V=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -41,3 +107,28 @@
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_8_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="FPGA"
+CONFIG_BR1_OR1_BASE=0xE0600000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_16BIT=y
+CONFIG_OR1_AM_1_MBYTES=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_SCY_5=y
+CONFIG_OR1_XAM_SET=y
+CONFIG_OR1_EHTR_NORMAL=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig
index e6b97b8..c970cde 100644
--- a/configs/suvd3_defconfig
+++ b/configs/suvd3_defconfig
@@ -1,7 +1,104 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_SUVD3=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_INHIBITED=y
+CONFIG_BAT0_ICACHE_GUARDED=y
+CONFIG_BAT0_DCACHE_INHIBITED=y
+CONFIG_BAT0_DCACHE_GUARDED=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="KMBEC_FPGA"
+CONFIG_BAT2_BASE=0xE8000000
+CONFIG_BAT2_LENGTH_128_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="APP1"
+CONFIG_BAT5_BASE=0xA0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="APP2"
+CONFIG_BAT6_BASE=0xB0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_INHIBITED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xA0000000
+CONFIG_LBLAW2_NAME="APP1"
+CONFIG_LBLAW2_LENGTH_256_MBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xB0000000
+CONFIG_LBLAW3_NAME="APP2"
+CONFIG_LBLAW3_LENGTH_256_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SUVD3"
@@ -41,3 +138,43 @@
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_BR2_MACHINE_UPMA=y
+CONFIG_BR2_PORTSIZE_16BIT=y
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="APP2"
+CONFIG_BR3_OR3_BASE=0xB0000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_SCY_3=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig
index e582671..550f524 100644
--- a/configs/tuge1_defconfig
+++ b/configs/tuge1_defconfig
@@ -1,10 +1,92 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
-CONFIG_TARGET_TUXX1=y
+CONFIG_HIGH_BATS=y
+CONFIG_TARGET_TUGE1=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_INHIBITED=y
+CONFIG_BAT0_ICACHE_GUARDED=y
+CONFIG_BAT0_DCACHE_INHIBITED=y
+CONFIG_BAT0_DCACHE_GUARDED=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="KMBEC_FPGA"
+CONFIG_BAT2_BASE=0xE8000000
+CONFIG_BAT2_LENGTH_128_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="APP1"
+CONFIG_BAT5_BASE=0xA0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xA0000000
+CONFIG_LBLAW2_NAME="APP1"
+CONFIG_LBLAW2_LENGTH_256_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="TUGE1"
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_R=y
@@ -41,3 +123,40 @@
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_OR2_SCY_2=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_4_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig
index 204d3e4..d5ec8e5 100644
--- a/configs/tuxx1_defconfig
+++ b/configs/tuxx1_defconfig
@@ -1,10 +1,106 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_TUXX1=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_QUICC_MULT_FACTOR_3=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_INHIBITED=y
+CONFIG_BAT0_ICACHE_GUARDED=y
+CONFIG_BAT0_DCACHE_INHIBITED=y
+CONFIG_BAT0_DCACHE_GUARDED=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="IMMR"
+CONFIG_BAT1_BASE=0xE0000000
+CONFIG_BAT1_LENGTH_4_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_INHIBITED=y
+CONFIG_BAT1_ICACHE_GUARDED=y
+CONFIG_BAT1_DCACHE_INHIBITED=y
+CONFIG_BAT1_DCACHE_GUARDED=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="KMBEC_FPGA"
+CONFIG_BAT2_BASE=0xE8000000
+CONFIG_BAT2_LENGTH_128_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT3=y
+CONFIG_BAT3_NAME="FLASH"
+CONFIG_BAT3_BASE=0xF0000000
+CONFIG_BAT3_LENGTH_256_MBYTES=y
+CONFIG_BAT3_ACCESS_RW=y
+CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT3_DCACHE_INHIBITED=y
+CONFIG_BAT3_DCACHE_GUARDED=y
+CONFIG_BAT3_USER_MODE_VALID=y
+CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT4=y
+CONFIG_BAT4_NAME="STACK_IN_DCACHE"
+CONFIG_BAT4_BASE=0xE6000000
+CONFIG_BAT4_ACCESS_RW=y
+CONFIG_BAT4_USER_MODE_VALID=y
+CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="APP1"
+CONFIG_BAT5_BASE=0xA0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="APP2"
+CONFIG_BAT6_BASE=0xB0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_INHIBITED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW2=y
+CONFIG_LBLAW2_BASE=0xA0000000
+CONFIG_LBLAW2_NAME="APP1"
+CONFIG_LBLAW2_LENGTH_256_MBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xB0000000
+CONFIG_LBLAW3_NAME="APP2"
+CONFIG_LBLAW3_LENGTH_256_MBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="TUXX1"
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_R=y
@@ -41,3 +137,51 @@
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_128_MBYTES=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="APP1"
+CONFIG_BR2_OR2_BASE=0xA0000000
+CONFIG_BR2_MACHINE_GPCM=y
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_256_MBYTES=y
+CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_OR2_SCY_2=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_4_CYCLE=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="APP2"
+CONFIG_BR3_OR3_BASE=0xB0000000
+CONFIG_BR3_MACHINE_GPCM=y
+CONFIG_BR3_PORTSIZE_8BIT=y
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_SCY_2=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_4_CYCLE=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_1=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig
index 584aafb..0a9521b 100644
--- a/configs/ve8313_defconfig
+++ b/configs/ve8313_defconfig
@@ -1,7 +1,84 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
+CONFIG_SYS_CLK_FREQ=32000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_VE8313=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_25_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_LALE_TIMING_EARLIER=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI_MMIO"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR_PCIIO_BCSR"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="INITRAM_FLASH"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_GUARDED=y
+CONFIG_BAT6_DCACHE_GUARDED=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT7=y
+CONFIG_BAT7_NAME="FPGA_SRAM_NAND"
+CONFIG_BAT7_BASE=0x60000000
+CONFIG_BAT7_LENGTH_256_MBYTES=y
+CONFIG_BAT7_ACCESS_RW=y
+CONFIG_BAT7_ICACHE_GUARDED=y
+CONFIG_BAT7_DCACHE_GUARDED=y
+CONFIG_BAT7_USER_MODE_VALID=y
+CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
+CONFIG_NAND_LBLAWBAR_PRELIM_1=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xFE000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_32_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0x61000000
+CONFIG_LBLAW1_NAME="NAND"
+CONFIG_LBLAW1_LENGTH_32_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
@@ -23,3 +100,50 @@
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xFE000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_32_MBYTES=y
+CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="NAND"
+CONFIG_BR1_OR1_BASE=0x61000000
+CONFIG_BR1_ERRORCHECKING_BOTH=y
+CONFIG_BR1_MACHINE_FCM=y
+CONFIG_BR1_PORTSIZE_8BIT=y
+CONFIG_OR1_AM_32_KBYTES=y
+CONFIG_OR1_BCTLD_NOT_ASSERTED=y
+CONFIG_OR1_RST_ONE_CLOCK=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_CHT_TWO_CLOCK=y
+CONFIG_ELBC_BR2_OR2=y
+CONFIG_BR2_OR2_NAME="NVRAM"
+CONFIG_BR2_OR2_BASE=0x60000000
+CONFIG_BR2_PORTSIZE_8BIT=y
+CONFIG_OR2_AM_128_KBYTES=y
+CONFIG_OR2_CSNT_EARLIER=y
+CONFIG_OR2_EAD_EXTRA=y
+CONFIG_OR2_SCY_3=y
+CONFIG_OR2_XACS_EXTENDED=y
+CONFIG_OR2_TRLX_RELAXED=y
+CONFIG_OR2_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="SRAM"
+CONFIG_BR3_OR3_BASE=0x62000000
+CONFIG_BR3_PORTSIZE_16BIT=y
+CONFIG_OR3_AM_32_MBYTES=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_OR3_SCY_15=y
+CONFIG_OR3_XACS_EXTENDED=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EHTR_8_CYCLE=y
+CONFIG_LCRR_EADC_3=y
+CONFIG_LCRR_CLKDIV_2=y
diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig
index a7d81a3..24bbba1 100644
--- a/configs/vme8349_defconfig
+++ b/configs/vme8349_defconfig
@@ -1,7 +1,80 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF00000
+CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_VME8349=y
+CONFIG_DDR_MC_CLOCK_MODE_1_1=y
+CONFIG_SYSTEM_PLL_FACTOR_4_1=y
+CONFIG_CORE_PLL_RATIO_2_1=y
+CONFIG_PCI_HOST_MODE_ENABLE=y
+CONFIG_PCI_64BIT_MODE_ENABLE=y
+CONFIG_PCI_INT_ARBITER1_ENABLE=y
+CONFIG_BOOT_MEMORY_SPACE_LOW=y
+CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
+CONFIG_TSEC1_MODE_GMII=y
+CONFIG_TSEC2_MODE_GMII=y
+CONFIG_BAT0=y
+CONFIG_BAT0_NAME="SDRAM"
+CONFIG_BAT0_BASE=0x00000000
+CONFIG_BAT0_LENGTH_256_MBYTES=y
+CONFIG_BAT0_ACCESS_RW=y
+CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT0_USER_MODE_VALID=y
+CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT1=y
+CONFIG_BAT1_NAME="PCI1_MEM"
+CONFIG_BAT1_BASE=0x80000000
+CONFIG_BAT1_LENGTH_256_MBYTES=y
+CONFIG_BAT1_ACCESS_RW=y
+CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT1_USER_MODE_VALID=y
+CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT2=y
+CONFIG_BAT2_NAME="PCI1_MMIO"
+CONFIG_BAT2_BASE=0x90000000
+CONFIG_BAT2_LENGTH_256_MBYTES=y
+CONFIG_BAT2_ACCESS_RW=y
+CONFIG_BAT2_ICACHE_INHIBITED=y
+CONFIG_BAT2_ICACHE_GUARDED=y
+CONFIG_BAT2_DCACHE_INHIBITED=y
+CONFIG_BAT2_DCACHE_GUARDED=y
+CONFIG_BAT2_USER_MODE_VALID=y
+CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT5=y
+CONFIG_BAT5_NAME="IMMR_PCIIO"
+CONFIG_BAT5_BASE=0xE0000000
+CONFIG_BAT5_LENGTH_256_MBYTES=y
+CONFIG_BAT5_ACCESS_RW=y
+CONFIG_BAT5_ICACHE_INHIBITED=y
+CONFIG_BAT5_ICACHE_GUARDED=y
+CONFIG_BAT5_DCACHE_INHIBITED=y
+CONFIG_BAT5_DCACHE_GUARDED=y
+CONFIG_BAT5_USER_MODE_VALID=y
+CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
+CONFIG_BAT6=y
+CONFIG_BAT6_NAME="UNKNOWN"
+CONFIG_BAT6_BASE=0xF0000000
+CONFIG_BAT6_LENGTH_256_MBYTES=y
+CONFIG_BAT6_ACCESS_RW=y
+CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
+CONFIG_BAT6_USER_MODE_VALID=y
+CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF8000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_128_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xF0000000
+CONFIG_LBLAW1_NAME="WINDOW1"
+CONFIG_LBLAW1_LENGTH_256_KBYTES=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_PCI_64BIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
@@ -24,3 +97,25 @@
CONFIG_BAUDRATE=9600
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF8000000
+CONFIG_BR0_MACHINE_GPCM=y
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_128_MBYTES=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_OR0_SCY_15=y
+CONFIG_OR0_XACS_EXTENDED=y
+CONFIG_OR0_XAM_SET=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EHTR_8_CYCLE=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="WINDOW1"
+CONFIG_BR1_OR1_BASE=0xF0000000
+CONFIG_BR1_MACHINE_GPCM=y
+CONFIG_BR1_PORTSIZE_32BIT=y
+CONFIG_OR1_AM_256_KBYTES=y
+CONFIG_OR1_SETA_EXTERNAL=y
+CONFIG_LCRR_CLKDIV_4=y
diff --git a/configs/xpedite517x_defconfig b/configs/xpedite517x_defconfig
index d2d8313..cad95d3 100644
--- a/configs/xpedite517x_defconfig
+++ b/configs/xpedite517x_defconfig
@@ -1,6 +1,7 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xfff00000
CONFIG_MPC86xx=y
+CONFIG_HIGH_BATS=y
CONFIG_TARGET_XPEDITE517X=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
diff --git a/drivers/board/gazerbeam.c b/drivers/board/gazerbeam.c
index 481cce8..85de4e4 100644
--- a/drivers/board/gazerbeam.c
+++ b/drivers/board/gazerbeam.c
@@ -61,7 +61,7 @@
struct udevice *i2c_bus;
struct udevice *dummy;
char *listname;
- int mc4, mc2, sc, con;
+ int mc4, mc2, sc, mc2_sc, con;
int gpio_num;
int res;
@@ -78,16 +78,16 @@
return -EIO;
}
- mc2 = !dm_i2c_probe(i2c_bus, MC2_EXPANDER_ADDR, 0, &dummy);
+ mc2_sc = !dm_i2c_probe(i2c_bus, MC2_EXPANDER_ADDR, 0, &dummy);
mc4 = !dm_i2c_probe(i2c_bus, MC4_EXPANDER_ADDR, 0, &dummy);
- if (mc2 && mc4) {
+ if (mc2_sc && mc4) {
debug("%s: Board hardware configuration inconsistent.\n",
dev->name);
return -EINVAL;
}
- listname = mc2 ? "var-gpios-mc2" : "var-gpios-mc4";
+ listname = mc2_sc ? "var-gpios-mc2" : "var-gpios-mc4";
gpio_num = gpio_request_list_by_name(dev, listname, priv->var_gpios,
ARRAY_SIZE(priv->var_gpios),
@@ -105,12 +105,7 @@
return sc;
}
- con = dm_gpio_get_value(&priv->var_gpios[CON_GPIO_NO]);
- if (con < 0) {
- debug("%s: Error while reading 'con' GPIO (err = %d)",
- dev->name, con);
- return con;
- }
+ mc2 = mc2_sc ? (sc ? 0 : 1) : 0;
if ((sc && mc2) || (sc && mc4) || (!sc && !mc2 && !mc4)) {
debug("%s: Board hardware configuration inconsistent.\n",
@@ -118,6 +113,13 @@
return -EINVAL;
}
+ con = dm_gpio_get_value(&priv->var_gpios[CON_GPIO_NO]);
+ if (con < 0) {
+ debug("%s: Error while reading 'con' GPIO (err = %d)",
+ dev->name, con);
+ return con;
+ }
+
priv->variant = con ? VAR_CON : VAR_CPU;
priv->multichannel = mc4 ? 4 : (mc2 ? 2 : (sc ? 1 : 0));
diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c
index 4890041..32d2db9 100644
--- a/drivers/clk/mpc83xx_clk.c
+++ b/drivers/clk/mpc83xx_clk.c
@@ -275,6 +275,12 @@
return priv->speed[clk->id];
}
+static int mpc83xx_clk_enable(struct clk *clk)
+{
+ /* MPC83xx clocks are always enabled */
+ return 0;
+}
+
int get_clocks(void)
{
/* Empty implementation to keep the prototype in common.h happy */
@@ -301,6 +307,7 @@
const struct clk_ops mpc83xx_clk_ops = {
.request = mpc83xx_clk_request,
.get_rate = mpc83xx_clk_get_rate,
+ .enable = mpc83xx_clk_enable,
};
static const struct udevice_id mpc83xx_clk_match[] = {
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index 6d018fd..e1f69a1 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -23,8 +23,12 @@
* 0x80_8000_0000 ~ 0xff_ffff_ffff
*/
#ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+#ifdef CONFIG_MPC83xx
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
+#else
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
#endif
+#endif
#ifdef CONFIG_PPC
#include <asm/fsl_law.h>
diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c
index 0922fe9..f7b59d3 100644
--- a/drivers/i2c/ihs_i2c.c
+++ b/drivers/i2c/ihs_i2c.c
@@ -8,8 +8,7 @@
#include <i2c.h>
#ifdef CONFIG_DM_I2C
#include <dm.h>
-#include <fpgamap.h>
-#include "../misc/gdsys_soc.h"
+#include <regmap.h>
#else
#include <gdsys_fpga.h>
#endif
@@ -18,18 +17,24 @@
#ifdef CONFIG_DM_I2C
struct ihs_i2c_priv {
uint speed;
- phys_addr_t addr;
+ struct regmap *map;
};
-enum {
- REG_INTERRUPT_STATUS = 0x00,
- REG_INTERRUPT_ENABLE_CONTROL = 0x02,
- REG_WRITE_MAILBOX_EXT = 0x04,
- REG_WRITE_MAILBOX = 0x06,
- REG_READ_MAILBOX_EXT = 0x08,
- REG_READ_MAILBOX = 0x0A,
+struct ihs_i2c_regs {
+ u16 interrupt_status;
+ u16 interrupt_enable_control;
+ u16 write_mailbox_ext;
+ u16 write_mailbox;
+ u16 read_mailbox_ext;
+ u16 read_mailbox;
};
+#define ihs_i2c_set(map, member, val) \
+ regmap_set(map, struct ihs_i2c_regs, member, val)
+
+#define ihs_i2c_get(map, member, valp) \
+ regmap_get(map, struct ihs_i2c_regs, member, valp)
+
#else /* !CONFIG_DM_I2C */
DECLARE_GLOBAL_DATA_PTR;
@@ -92,14 +97,10 @@
uint ctr = 0;
#ifdef CONFIG_DM_I2C
struct ihs_i2c_priv *priv = dev_get_priv(dev);
- struct udevice *fpga;
-
- gdsys_soc_get_fpga(dev, &fpga);
#endif
#ifdef CONFIG_DM_I2C
- fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
- FPGAMAP_SIZE_16);
+ ihs_i2c_get(priv->map, interrupt_status, &val);
#else
I2C_GET_REG(interrupt_status, &val);
#endif
@@ -107,17 +108,18 @@
while (!(val & (I2CINT_ERROR_EV
| (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
udelay(10);
- if (ctr++ > 5000)
- return 1;
+ if (ctr++ > 5000) {
+ debug("%s: timed out\n", __func__);
+ return -ETIMEDOUT;
+ }
#ifdef CONFIG_DM_I2C
- fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
- FPGAMAP_SIZE_16);
+ ihs_i2c_get(priv->map, interrupt_status, &val);
#else
I2C_GET_REG(interrupt_status, &val);
#endif
}
- return (val & I2CINT_ERROR_EV) ? 1 : 0;
+ return (val & I2CINT_ERROR_EV) ? -EIO : 0;
}
#ifdef CONFIG_DM_I2C
@@ -130,20 +132,16 @@
{
u16 val;
u16 data;
+ int res;
#ifdef CONFIG_DM_I2C
struct ihs_i2c_priv *priv = dev_get_priv(dev);
- struct udevice *fpga;
-
- gdsys_soc_get_fpga(dev, &fpga);
#endif
/* Clear interrupt status */
data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV;
#ifdef CONFIG_DM_I2C
- fpgamap_write(fpga, priv->addr + REG_INTERRUPT_STATUS, &data,
- FPGAMAP_SIZE_16);
- fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
- FPGAMAP_SIZE_16);
+ ihs_i2c_set(priv->map, interrupt_status, data);
+ ihs_i2c_get(priv->map, interrupt_status, &val);
#else
I2C_SET_REG(interrupt_status, data);
I2C_GET_REG(interrupt_status, &val);
@@ -156,8 +154,7 @@
if (len > 1)
val |= buffer[1] << 8;
#ifdef CONFIG_DM_I2C
- fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX_EXT, &val,
- FPGAMAP_SIZE_16);
+ ihs_i2c_set(priv->map, write_mailbox_ext, val);
#else
I2C_SET_REG(write_mailbox_ext, val);
#endif
@@ -170,24 +167,27 @@
| (is_last ? 0 : I2CMB_HOLD_BUS);
#ifdef CONFIG_DM_I2C
- fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX, &data,
- FPGAMAP_SIZE_16);
+ ihs_i2c_set(priv->map, write_mailbox, data);
#else
I2C_SET_REG(write_mailbox, data);
#endif
#ifdef CONFIG_DM_I2C
- if (wait_for_int(dev, read))
+ res = wait_for_int(dev, read);
#else
- if (wait_for_int(read))
+ res = wait_for_int(read);
#endif
- return 1;
+ if (res) {
+ if (res == -ETIMEDOUT)
+ debug("%s: time out while waiting for event\n", __func__);
+
+ return res;
+ }
/* If we want to read, get the bytes from the mailbox */
if (read) {
#ifdef CONFIG_DM_I2C
- fpgamap_read(fpga, priv->addr + REG_READ_MAILBOX_EXT, &val,
- FPGAMAP_SIZE_16);
+ ihs_i2c_get(priv->map, read_mailbox_ext, &val);
#else
I2C_GET_REG(read_mailbox_ext, &val);
#endif
@@ -206,19 +206,21 @@
int read)
#endif
{
+ int res;
+
while (len) {
int transfer = min(len, 2);
bool is_last = len <= transfer;
#ifdef CONFIG_DM_I2C
- if (ihs_i2c_transfer(dev, chip, data, transfer, read,
- hold_bus ? false : is_last))
- return 1;
+ res = ihs_i2c_transfer(dev, chip, data, transfer, read,
+ hold_bus ? false : is_last);
#else
- if (ihs_i2c_transfer(chip, data, transfer, read,
- hold_bus ? false : is_last))
- return 1;
+ res = ihs_i2c_transfer(chip, data, transfer, read,
+ hold_bus ? false : is_last);
#endif
+ if (res)
+ return res;
data += transfer;
len -= transfer;
@@ -249,14 +251,19 @@
int alen, uchar *buffer, int len, int read)
#endif
{
+ int res;
+
/* Don't hold the bus if length of data to send/receive is zero */
+ if (len <= 0)
+ return -EINVAL;
+
#ifdef CONFIG_DM_I2C
- if (len <= 0 || ihs_i2c_address(dev, chip, addr, alen, len))
- return 1;
+ res = ihs_i2c_address(dev, chip, addr, alen, len);
#else
- if (len <= 0 || ihs_i2c_address(chip, addr, alen, len))
- return 1;
+ res = ihs_i2c_address(chip, addr, alen, len);
#endif
+ if (res)
+ return res;
#ifdef CONFIG_DM_I2C
return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read);
@@ -270,11 +277,8 @@
int ihs_i2c_probe(struct udevice *bus)
{
struct ihs_i2c_priv *priv = dev_get_priv(bus);
- int addr;
- addr = dev_read_u32_default(bus, "reg", -1);
-
- priv->addr = addr;
+ regmap_init_mem(dev_ofnode(bus), &priv->map);
return 0;
}
@@ -284,7 +288,7 @@
struct ihs_i2c_priv *priv = dev_get_priv(bus);
if (speed != priv->speed && priv->speed != 0)
- return 1;
+ return -EINVAL;
priv->speed = speed;
@@ -301,8 +305,8 @@
* actucal data) or one message (just data)
*/
if (nmsgs > 2 || nmsgs == 0) {
- debug("%s: Only one or two messages are supported.", __func__);
- return -1;
+ debug("%s: Only one or two messages are supported\n", __func__);
+ return -ENOTSUPP;
}
omsg = nmsgs == 1 ? &dummy : msg;
@@ -322,9 +326,11 @@
u32 chip_flags)
{
uchar buffer[2];
+ int res;
- if (ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true))
- return 1;
+ res = ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true);
+ if (res)
+ return res;
return 0;
}
@@ -366,9 +372,11 @@
static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
{
uchar buffer[2];
+ int res;
- if (ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true))
- return 1;
+ res = ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true);
+ if (res)
+ return res;
return 0;
}
@@ -399,7 +407,7 @@
unsigned int speed)
{
if (speed != adap->speed)
- return 1;
+ return -EINVAL;
return speed;
}
diff --git a/drivers/misc/gdsys_rxaui_ctrl.c b/drivers/misc/gdsys_rxaui_ctrl.c
index 9a63c32..c56abce 100644
--- a/drivers/misc/gdsys_rxaui_ctrl.c
+++ b/drivers/misc/gdsys_rxaui_ctrl.c
@@ -29,6 +29,7 @@
struct gdsys_rxaui_ctrl_priv {
struct regmap *map;
+ bool state;
};
int gdsys_rxaui_set_polarity_inversion(struct udevice *dev, bool val)
@@ -36,6 +37,8 @@
struct gdsys_rxaui_ctrl_priv *priv = dev_get_priv(dev);
u16 state;
+ priv->state = !priv->state;
+
rxaui_ctrl_get(priv->map, ctrl_1, &state);
if (val)
@@ -45,7 +48,7 @@
rxaui_ctrl_set(priv->map, ctrl_1, state);
- return 0;
+ return !priv->state;
}
static const struct misc_ops gdsys_rxaui_ctrl_ops = {
@@ -56,7 +59,9 @@
{
struct gdsys_rxaui_ctrl_priv *priv = dev_get_priv(dev);
- regmap_init_mem(dev, &priv->map);
+ regmap_init_mem(dev_ofnode(dev), &priv->map);
+
+ priv->state = false;
return 0;
}
diff --git a/drivers/mtd/nand/raw/fsl_elbc_spl.c b/drivers/mtd/nand/raw/fsl_elbc_spl.c
index 30c3308..099d864 100644
--- a/drivers/mtd/nand/raw/fsl_elbc_spl.c
+++ b/drivers/mtd/nand/raw/fsl_elbc_spl.c
@@ -14,6 +14,10 @@
#include <asm/fsl_lbc.h>
#include <nand.h>
+#ifdef CONFIG_MPC83xx
+#include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
+#endif
+
#define WINDOW_SIZE 8192
static void nand_wait(void)
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index d7237f6..1a3bf70 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -359,7 +359,8 @@
PCI_DEV(dm_pci_get_bdf(dev)));
break;
#endif
-#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
+#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
+ !defined(CONFIG_TARGET_CADDY2)
case PCI_CLASS_BRIDGE_OTHER:
/*
* The host/PCI bridge 1 seems broken in 8349 - it presents
diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c
index e705a30..b566705 100644
--- a/drivers/pci/pci_auto_old.c
+++ b/drivers/pci/pci_auto_old.c
@@ -376,7 +376,8 @@
PCI_DEV(dev));
break;
#endif
-#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
+#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
+ !defined(CONFIG_TARGET_CADDY2)
case PCI_CLASS_BRIDGE_OTHER:
/*
* The host/PCI bridge 1 seems broken in 8349 - it presents
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 70d02d3..505ae9b 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -119,7 +119,7 @@
*/
static u8 thread_snum[] = {
/* Evthreads 16-29 are not supported in MPC8309 */
-#if !defined(CONFIG_MPC8309)
+#if !defined(CONFIG_ARCH_MPC8309)
0x04, 0x05, 0x0c, 0x0d,
0x14, 0x15, 0x1c, 0x1d,
0x24, 0x25, 0x2c, 0x2d,
diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c
index 441baeb..f03d042 100644
--- a/drivers/ram/mpc83xx_sdram.c
+++ b/drivers/ram/mpc83xx_sdram.c
@@ -169,8 +169,8 @@
odt_rd_cfg = ofnode_read_u32_default(node, "odt_rd_cfg", 0);
switch (odt_rd_cfg) {
case ODT_RD_ONLY_OTHER_DIMM:
- if (!IS_ENABLED(CONFIG_MPC8360) &&
- !IS_ENABLED(CONFIG_MPC837x)) {
+ if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
+ !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
debug("%s: odt_rd_cfg value %d invalid.\n",
ofnode_get_name(node), odt_rd_cfg);
return -EINVAL;
@@ -179,10 +179,10 @@
case ODT_RD_NEVER:
case ODT_RD_ONLY_CURRENT:
case ODT_RD_ONLY_OTHER_CS:
- if (!IS_ENABLED(CONFIG_MPC830x) &&
- !IS_ENABLED(CONFIG_MPC831x) &&
- !IS_ENABLED(CONFIG_MPC8360) &&
- !IS_ENABLED(CONFIG_MPC837x)) {
+ if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
+ !IS_ENABLED(CONFIG_ARCH_MPC831X) &&
+ !IS_ENABLED(CONFIG_ARCH_MPC8360) &&
+ !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
debug("%s: odt_rd_cfg value %d invalid.\n",
ofnode_get_name(node), odt_rd_cfg);
return -EINVAL;
@@ -200,8 +200,8 @@
odt_wr_cfg = ofnode_read_u32_default(node, "odt_wr_cfg", 0);
switch (odt_wr_cfg) {
case ODT_WR_ONLY_OTHER_DIMM:
- if (!IS_ENABLED(CONFIG_MPC8360) &&
- !IS_ENABLED(CONFIG_MPC837x)) {
+ if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
+ !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
debug("%s: odt_wr_cfg value %d invalid.\n",
ofnode_get_name(node), odt_wr_cfg);
return -EINVAL;
@@ -210,10 +210,10 @@
case ODT_WR_NEVER:
case ODT_WR_ONLY_CURRENT:
case ODT_WR_ONLY_OTHER_CS:
- if (!IS_ENABLED(CONFIG_MPC830x) &&
- !IS_ENABLED(CONFIG_MPC831x) &&
- !IS_ENABLED(CONFIG_MPC8360) &&
- !IS_ENABLED(CONFIG_MPC837x)) {
+ if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
+ !IS_ENABLED(CONFIG_ARCH_MPC831X) &&
+ !IS_ENABLED(CONFIG_ARCH_MPC8360) &&
+ !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
debug("%s: odt_wr_cfg value %d invalid.\n",
ofnode_get_name(node), odt_wr_cfg);
return -EINVAL;
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 3827ea4..85d7ff6 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -12,8 +12,6 @@
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC830x 1 /* MPC830x family */
-#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
@@ -30,92 +28,15 @@
#define CONFIG_VSC7385_ENET
/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
- * We choose the A type silicon as default, so the core is 400Mhz.
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_SVCOD_DIV_2 |\
- HRCWL_CSB_TO_CLKIN_4X1 |\
- HRCWL_CORE_TO_CSB_3X1)
-/*
- * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
- * in 8308's HRCWH according to the manual, but original Freescale's
- * code has them and I've expirienced some problems using the board
- * with BDI3000 attached when I've tried to set these bits to zero
- * (UART doesn't work after the 'reset run' command).
- */
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN)
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH (\
- SICRH_ESDHC_A_SD |\
- SICRH_ESDHC_B_SD |\
- SICRH_ESDHC_C_SD |\
- SICRH_GPIO_A_TSEC2 |\
- SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
- SICRH_IEEE1588_A_GPIO |\
- SICRH_USB |\
- SICRH_GTM_GPIO |\
- SICRH_IEEE1588_B_GPIO |\
- SICRH_ETSEC2_CRS |\
- SICRH_GPIOSEL_1 |\
- SICRH_TMROBI_V3P3 |\
- SICRH_TSOBI1_V2P5 |\
- SICRH_TSOBI2_V2P5) /* 0x01b7d103 */
-#define CONFIG_SYS_SICRL (\
- SICRL_SPI_PF0 |\
- SICRL_UART_PF0 |\
- SICRL_IRQ_PF0 |\
- SICRL_I2C2_PF0 |\
- SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
* SERDES
*/
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1 0xe3000
/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
-
-/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
| DDRCDR_PZ_LOZ \
@@ -201,13 +122,6 @@
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR 0x00040000
-
-/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
@@ -215,22 +129,6 @@
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
-/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
/* 127 64KB sectors and 8 8KB top sectors per device */
@@ -244,45 +142,14 @@
*/
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
- | BR_DECC_CHK_GEN /* Use HW ECC */ \
- | BR_PS_8 /* 8 bit Port */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
/* 0xFFFF8396 */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
#ifdef CONFIG_VSC7385_ENET
#define CONFIG_TSEC2
/* VSC7385 Base address on CS2 */
#define CONFIG_SYS_VSC7385_BASE 0xF0000000
#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
- | BR_PS_8 /* 8-bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
- /* 0xF0000801 */
-#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_SETA \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET)
/* 0xFFFE09FF */
-/* Access window base at VSC7385 base */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
-/* Access window size 128K */
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
/* The flash address and size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE 0xFE7FE000
#define CONFIG_VSC7385_IMAGE_SIZE 8192
@@ -419,52 +286,6 @@
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
- BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
* Environment Configuration
*/
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
deleted file mode 100644
index cfa5b56..0000000
--- a/include/configs/MPC8313ERDB.h
+++ /dev/null
@@ -1,650 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
- */
-/*
- * mpc8313epb board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1
-#define CONFIG_MPC831x 1
-#define CONFIG_MPC8313 1
-#define CONFIG_MPC8313ERDB 1
-
-#ifdef CONFIG_NAND
-#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#define CONFIG_SPL_MAX_SIZE (4 * 1024)
-#define CONFIG_SPL_PAD_TO 0x4000
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
-#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#endif
-
-#endif /* CONFIG_NAND */
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_ELBC 1
-
-/*
- * On-board devices
- *
- * TSEC1 is VSC switch
- * TSEC2 is SoC TSEC
- */
-#define CONFIG_VSC7385_ENET
-#define CONFIG_TSEC2
-
-#ifdef CONFIG_SYS_66MHZ
-#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
-#elif defined(CONFIG_SYS_33MHZ)
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#else
-#error Unknown oscillator frequency.
-#endif
-
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-#define CONFIG_SYS_IMMR 0xE0000000
-
-#if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
-#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
-#endif
-
-#define CONFIG_SYS_MEMTEST_START 0x00001000
-#define CONFIG_SYS_MEMTEST_END 0x07f00000
-
-/* Early revs of this board will lock up hard when attempting
- * to access the PMC registers, unless a JTAG debugger is
- * connected, or some resistor modifications are made.
- */
-#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
-
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-
-/*
- * Device configurations
- */
-
-/* Vitesse 7385 */
-
-#ifdef CONFIG_VSC7385_ENET
-
-#define CONFIG_TSEC1
-
-/* The flash address and size of the VSC7385 firmware image */
-#define CONFIG_VSC7385_IMAGE 0xFE7FE000
-#define CONFIG_VSC7385_IMAGE_SIZE 8192
-
-#endif
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-
-/*
- * Manually set up DDR parameters, as this board does not
- * seem to have the SPD connected to I2C.
- */
-#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ODT_RD_NEVER \
- | CSCONFIG_ODT_WR_ONLY_CURRENT \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10)
- /* 0x80010102 */
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
- | (0 << TIMING_CFG0_WRT_SHIFT) \
- | (0 << TIMING_CFG0_RRT_SHIFT) \
- | (0 << TIMING_CFG0_WWT_SHIFT) \
- | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
- | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
- /* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
- | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
- | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
- | (5 << TIMING_CFG1_CASLAT_SHIFT) \
- | (10 << TIMING_CFG1_REFREC_SHIFT) \
- | (3 << TIMING_CFG1_WRREC_SHIFT) \
- | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
- | (2 << TIMING_CFG1_WRTORD_SHIFT))
- /* 0x3835a322 */
-#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
- | (5 << TIMING_CFG2_CPO_SHIFT) \
- | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
- | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
- | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
- | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
- | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
- /* 0x129048c6 */ /* P9-45,may need tuning */
-#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
- | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
- /* 0x05100500 */
-#if defined(CONFIG_DDR_2T_TIMING)
-#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_DBW_32 \
- | SDRAM_CFG_2T_EN)
- /* 0x43088000 */
-#else
-#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_DBW_32)
- /* 0x43080000 */
-#endif
-#define CONFIG_SYS_SDRAM_CFG2 0x00401000
-/* set burst length to 8 for 32-bit data path */
-#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
- | (0x0632 << SDRAM_MODE_SD_SHIFT))
- /* 0x44480632 */
-#define CONFIG_SYS_DDR_MODE_2 0x8000C000
-
-#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
- /*0x02000000*/
-#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
- | DDRCDR_PZ_NOMZ \
- | DDRCDR_NZ_NOMZ \
- | DDRCDR_M_ODR)
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
-
-#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_9 \
- | OR_GPCM_EHTR \
- | OR_GPCM_EAD)
- /* 0xFF006FF7 TODO SLOW 16 MB flash size */
- /* window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
- /* 16 MB window size */
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
- !defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
-
-/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
- | (0xFF << LBCR_BMT_SHIFT) \
- | 0xF) /* 0x0004ff0f */
-
- /* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
-
-/* drivers/mtd/nand/raw/nand.c */
-#if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_NAND_BASE 0xFFF00000
-#else
-#define CONFIG_SYS_NAND_BASE 0xE2800000
-#endif
-
-#define CONFIG_MTD_PARTITION
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
-#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
-
-#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
- | BR_DECC_CHK_GEN /* Use HW ECC */ \
- | BR_PS_8 /* 8 bit port */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM \
- (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
- /* 0xFFFF8396 */
-
-#ifdef CONFIG_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
-#endif
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
-
-/* local bus write LED / read status buffer (BCSR) mapping */
-#define CONFIG_SYS_BCSR_ADDR 0xFA000000
-#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
- /* map at 0xFA000000 on LCS3 */
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \
- | BR_PS_8 /* 8 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
- /* 0xFA000801 */
-#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFFFF8FF7 */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
-/* Vitesse 7385 */
-
-#ifdef CONFIG_VSC7385_ENET
-
- /* VSC7385 Base address on LCS2 */
-#define CONFIG_SYS_VSC7385_BASE 0xF0000000
-#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
-
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
- | BR_PS_8 /* 8 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_SETA \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFFFE09FF */
-
- /* Access window base at VSC7385 base */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
-
-#endif
-
-#define CONFIG_MPC83XX_GPIO 1
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-
-/*
- * TSEC
- */
-
-#define CONFIG_GMII /* MII PHY management */
-
-#ifdef CONFIG_TSEC1
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define TSEC1_PHY_ADDR 0x1c
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC1_PHYIDX 0
-#endif
-
-#ifdef CONFIG_TSEC2
-#define CONFIG_HAS_ETH1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define TSEC2_PHY_ADDR 4
-#define TSEC2_FLAGS TSEC_GIGABIT
-#define TSEC2_PHYIDX 0
-#endif
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC1"
-
-/*
- * Configure on-board RTC
- */
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * Environment
- */
-#if defined(CONFIG_NAND)
- #define CONFIG_ENV_OFFSET (512 * 1024)
- #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
- #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
- #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
- #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
- #define CONFIG_ENV_OFFSET_REDUND \
- (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
-#elif !defined(CONFIG_SYS_RAMBOOT)
- #define CONFIG_ENV_ADDR \
- (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
- #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
- #define CONFIG_ENV_SIZE 0x2000
-
-/* Address and size of Redundant Environment Sector */
-#else
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * Command line configuration.
- */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
- /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-
-#ifdef CONFIG_SYS_66MHZ
-
-/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
-/* 0x62040000 */
-#define CONFIG_SYS_HRCW_LOW (\
- 0x20000000 /* reserved, must be set */ |\
- HRCWL_DDRCM |\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_CSB_TO_CLKIN_2X1 |\
- HRCWL_CORE_TO_CSB_2X1)
-
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
-
-#elif defined(CONFIG_SYS_33MHZ)
-
-/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
-/* 0x65040000 */
-#define CONFIG_SYS_HRCW_LOW (\
- 0x20000000 /* reserved, must be set */ |\
- HRCWL_DDRCM |\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_CSB_TO_CLKIN_5X1 |\
- HRCWL_CORE_TO_CSB_2X1)
-
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
-
-#endif
-
-#define CONFIG_SYS_HRCW_HIGH_BASE (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN)
-
-#ifdef CONFIG_NAND
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_ROM_LOC_NAND_SP_8BIT |\
- HRCWH_RL_EXT_NAND)
-#else
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY)
-#endif
-
-/* System IO Config */
-#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
- /* Enable Internal USB Phy and GPIO on LCD Connector */
-#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
-
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-
-#define CONFIG_SYS_HID2 HID2_HBE
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* PCI @ 0x80000000 */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* PCI2 not supported on 8313 */
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_NETDEV "eth1"
-
-#define CONFIG_HOSTNAME "mpc8313erdb"
-#define CONFIG_ROOTPATH "/nfs/root/path"
-#define CONFIG_BOOTFILE "uImage"
- /* U-Boot image on TFTP server */
-#define CONFIG_UBOOTPATH "u-boot.bin"
-#define CONFIG_FDTFILE "mpc8313erdb.dtb"
-
- /* default location for tftp and bootm */
-#define CONFIG_LOADADDR 800000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" CONFIG_NETDEV "\0" \
- "ethprime=TSEC1\0" \
- "uboot=" CONFIG_UBOOTPATH "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
- "fdtaddr=780000\0" \
- "fdtfile=" CONFIG_FDTFILE "\0" \
- "console=ttyS0\0" \
- "setbootargs=setenv bootargs " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
- "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
- "$netdev:off " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv rootdev /dev/nfs;" \
- "run setbootargs;" \
- "run setipargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv rootdev /dev/ram;" \
- "run setbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h
new file mode 100644
index 0000000..4153d60
--- /dev/null
+++ b/include/configs/MPC8313ERDB_NAND.h
@@ -0,0 +1,404 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
+ */
+/*
+ * mpc8313epb board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1
+
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#define CONFIG_SPL_MAX_SIZE (4 * 1024)
+#define CONFIG_SPL_PAD_TO 0x4000
+
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
+#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_ELBC 1
+
+/*
+ * On-board devices
+ *
+ * TSEC1 is VSC switch
+ * TSEC2 is SoC TSEC
+ */
+#define CONFIG_VSC7385_ENET
+#define CONFIG_TSEC2
+
+#if !defined(CONFIG_SPL_BUILD)
+#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
+#endif
+
+#define CONFIG_SYS_MEMTEST_START 0x00001000
+#define CONFIG_SYS_MEMTEST_END 0x07f00000
+
+/* Early revs of this board will lock up hard when attempting
+ * to access the PMC registers, unless a JTAG debugger is
+ * connected, or some resistor modifications are made.
+ */
+#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
+
+/*
+ * Device configurations
+ */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC1
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE 0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE 8192
+
+#endif
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+
+/*
+ * Manually set up DDR parameters, as this board does not
+ * seem to have the SPD connected to I2C.
+ */
+#define CONFIG_SYS_DDR_SIZE 128 /* MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
+ | CSCONFIG_ODT_RD_NEVER \
+ | CSCONFIG_ODT_WR_ONLY_CURRENT \
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_10)
+ /* 0x80010102 */
+
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
+ | (0 << TIMING_CFG0_WRT_SHIFT) \
+ | (0 << TIMING_CFG0_RRT_SHIFT) \
+ | (0 << TIMING_CFG0_WWT_SHIFT) \
+ | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+ /* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+ | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+ | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
+ | (5 << TIMING_CFG1_CASLAT_SHIFT) \
+ | (10 << TIMING_CFG1_REFREC_SHIFT) \
+ | (3 << TIMING_CFG1_WRREC_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+ | (2 << TIMING_CFG1_WRTORD_SHIFT))
+ /* 0x3835a322 */
+#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+ | (5 << TIMING_CFG2_CPO_SHIFT) \
+ | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+ | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+ | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+ | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+ | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
+ /* 0x129048c6 */ /* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
+ | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+ /* 0x05100500 */
+#if defined(CONFIG_DDR_2T_TIMING)
+#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_DBW_32 \
+ | SDRAM_CFG_2T_EN)
+ /* 0x43088000 */
+#else
+#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_DBW_32)
+ /* 0x43080000 */
+#endif
+#define CONFIG_SYS_SDRAM_CFG2 0x00401000
+/* set burst length to 8 for 32-bit data path */
+#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
+ | (0x0632 << SDRAM_MODE_SD_SHIFT))
+ /* 0x44480632 */
+#define CONFIG_SYS_DDR_MODE_2 0x8000C000
+
+#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+ /*0x02000000*/
+#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
+ | DDRCDR_PZ_NOMZ \
+ | DDRCDR_NZ_NOMZ \
+ | DDRCDR_M_ODR)
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
+ !defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+
+/* drivers/mtd/nand/raw/nand.c */
+#if defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_NAND_BASE 0xFFF00000
+#else
+#define CONFIG_SYS_NAND_BASE 0xE2800000
+#endif
+
+#define CONFIG_MTD_PARTITION
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
+#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
+
+/* Still needed for spl_minimal.c */
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
+
+/* local bus write LED / read status buffer (BCSR) mapping */
+#define CONFIG_SYS_BCSR_ADDR 0xFA000000
+#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
+ /* map at 0xFA000000 on LCS3 */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+ /* VSC7385 Base address on LCS2 */
+#define CONFIG_SYS_VSC7385_BASE 0xF0000000
+#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
+
+
+#endif
+
+#define CONFIG_MPC83XX_GPIO 1
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+
+/*
+ * TSEC
+ */
+
+#define CONFIG_GMII /* MII PHY management */
+
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define TSEC1_PHY_ADDR 0x1c
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC1_PHYIDX 0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME "TSEC1"
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define TSEC2_PHY_ADDR 4
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define TSEC2_PHYIDX 0
+#endif
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC1"
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OFFSET (512 * 1024)
+#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+
+ /* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+ /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
+
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
+ /* Enable Internal USB Phy and GPIO on LCD Connector */
+#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NETDEV "eth1"
+
+#define CONFIG_HOSTNAME "mpc8313erdb"
+#define CONFIG_ROOTPATH "/nfs/root/path"
+#define CONFIG_BOOTFILE "uImage"
+ /* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH "u-boot.bin"
+#define CONFIG_FDTFILE "mpc8313erdb.dtb"
+
+ /* default location for tftp and bootm */
+#define CONFIG_LOADADDR 800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=" CONFIG_NETDEV "\0" \
+ "ethprime=TSEC1\0" \
+ "uboot=" CONFIG_UBOOTPATH "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
+ "fdtaddr=780000\0" \
+ "fdtfile=" CONFIG_FDTFILE "\0" \
+ "console=ttyS0\0" \
+ "setbootargs=setenv bootargs " \
+ "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+ "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
+ "$netdev:off " \
+ "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv rootdev /dev/nfs;" \
+ "run setbootargs;" \
+ "run setipargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv rootdev /dev/ram;" \
+ "run setbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h
new file mode 100644
index 0000000..ff8dedf
--- /dev/null
+++ b/include/configs/MPC8313ERDB_NOR.h
@@ -0,0 +1,377 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
+ */
+/*
+ * mpc8313epb board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_ELBC 1
+
+/*
+ * On-board devices
+ *
+ * TSEC1 is VSC switch
+ * TSEC2 is SoC TSEC
+ */
+#define CONFIG_VSC7385_ENET
+#define CONFIG_TSEC2
+
+#define CONFIG_SYS_MEMTEST_START 0x00001000
+#define CONFIG_SYS_MEMTEST_END 0x07f00000
+
+/* Early revs of this board will lock up hard when attempting
+ * to access the PMC registers, unless a JTAG debugger is
+ * connected, or some resistor modifications are made.
+ */
+#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
+
+/*
+ * Device configurations
+ */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC1
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE 0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE 8192
+
+#endif
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+
+/*
+ * Manually set up DDR parameters, as this board does not
+ * seem to have the SPD connected to I2C.
+ */
+#define CONFIG_SYS_DDR_SIZE 128 /* MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
+ | CSCONFIG_ODT_RD_NEVER \
+ | CSCONFIG_ODT_WR_ONLY_CURRENT \
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_10)
+ /* 0x80010102 */
+
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
+ | (0 << TIMING_CFG0_WRT_SHIFT) \
+ | (0 << TIMING_CFG0_RRT_SHIFT) \
+ | (0 << TIMING_CFG0_WWT_SHIFT) \
+ | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+ | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+ /* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+ | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+ | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
+ | (5 << TIMING_CFG1_CASLAT_SHIFT) \
+ | (10 << TIMING_CFG1_REFREC_SHIFT) \
+ | (3 << TIMING_CFG1_WRREC_SHIFT) \
+ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+ | (2 << TIMING_CFG1_WRTORD_SHIFT))
+ /* 0x3835a322 */
+#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+ | (5 << TIMING_CFG2_CPO_SHIFT) \
+ | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+ | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+ | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+ | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+ | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
+ /* 0x129048c6 */ /* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
+ | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+ /* 0x05100500 */
+#if defined(CONFIG_DDR_2T_TIMING)
+#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_DBW_32 \
+ | SDRAM_CFG_2T_EN)
+ /* 0x43088000 */
+#else
+#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
+ | SDRAM_CFG_DBW_32)
+ /* 0x43080000 */
+#endif
+#define CONFIG_SYS_SDRAM_CFG2 0x00401000
+/* set burst length to 8 for 32-bit data path */
+#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
+ | (0x0632 << SDRAM_MODE_SD_SHIFT))
+ /* 0x44480632 */
+#define CONFIG_SYS_DDR_MODE_2 0x8000C000
+
+#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+ /*0x02000000*/
+#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
+ | DDRCDR_PZ_NOMZ \
+ | DDRCDR_NZ_NOMZ \
+ | DDRCDR_M_ODR)
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
+ !defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+
+/* drivers/mtd/nand/nand.c */
+#define CONFIG_SYS_NAND_BASE 0xE2800000
+
+#define CONFIG_MTD_PARTITION
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
+#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
+
+/* Still needed for spl_minimal.c */
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
+
+/* local bus write LED / read status buffer (BCSR) mapping */
+#define CONFIG_SYS_BCSR_ADDR 0xFA000000
+#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
+ /* map at 0xFA000000 on LCS3 */
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+ /* VSC7385 Base address on LCS2 */
+#define CONFIG_SYS_VSC7385_BASE 0xF0000000
+#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
+
+
+#endif
+
+#define CONFIG_MPC83XX_GPIO 1
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+
+/*
+ * TSEC
+ */
+
+#define CONFIG_GMII /* MII PHY management */
+
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define TSEC1_PHY_ADDR 0x1c
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC1_PHYIDX 0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME "TSEC1"
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define TSEC2_PHY_ADDR 4
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define TSEC2_PHYIDX 0
+#endif
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC1"
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/*
+ * Environment
+ */
+#if !defined(CONFIG_SYS_RAMBOOT)
+ #define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+ #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
+ #define CONFIG_ENV_SIZE 0x2000
+
+/* Address and size of Redundant Environment Sector */
+#else
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+ #define CONFIG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+
+ /* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+ /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
+
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
+ /* Enable Internal USB Phy and GPIO on LCD Connector */
+#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NETDEV "eth1"
+
+#define CONFIG_HOSTNAME "mpc8313erdb"
+#define CONFIG_ROOTPATH "/nfs/root/path"
+#define CONFIG_BOOTFILE "uImage"
+ /* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH "u-boot.bin"
+#define CONFIG_FDTFILE "mpc8313erdb.dtb"
+
+ /* default location for tftp and bootm */
+#define CONFIG_LOADADDR 800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=" CONFIG_NETDEV "\0" \
+ "ethprime=TSEC1\0" \
+ "uboot=" CONFIG_UBOOTPATH "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
+ "fdtaddr=780000\0" \
+ "fdtfile=" CONFIG_FDTFILE "\0" \
+ "console=ttyS0\0" \
+ "setbootargs=setenv bootargs " \
+ "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+ "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
+ "$netdev:off " \
+ "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv rootdev /dev/nfs;" \
+ "run setbootargs;" \
+ "run setipargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv rootdev /dev/ram;" \
+ "run setbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 0ccf4ac..521c5ca 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -22,51 +22,8 @@
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC831x 1 /* MPC831x CPU family */
-#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */
-#define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */
/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_SVCOD_DIV_2 |\
- HRCWL_CSB_TO_CLKIN_2X1 |\
- HRCWL_CORE_TO_CSB_3X1)
-#define CONFIG_SYS_HRCW_HIGH_BASE (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LALE_NORMAL)
-
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_ROM_LOC_NAND_SP_8BIT |\
- HRCWH_RL_EXT_NAND)
-#else
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY)
-#endif
-
-/*
* System IO Config
*/
#define CONFIG_SYS_SICRH 0x00000000
@@ -75,23 +32,9 @@
#define CONFIG_HWCONFIG
/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
-
-/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
| DDRCDR_PZ_LOZ \
@@ -173,13 +116,7 @@
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR 0x00040000
-#define CONFIG_FSL_ELBC 1
+#define CONFIG_FSL_ELBC
/*
* FLASH on the Local Bus
@@ -189,24 +126,6 @@
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
- /* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
-
-#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
-
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
/* 127 64KB sectors and 8 8KB top sectors per device */
#define CONFIG_SYS_MAX_FLASH_SECT 135
@@ -238,31 +157,11 @@
#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
- | BR_DECC_CHK_GEN /* Use HW ECC */ \
- | BR_PS_8 /* 8 bit port */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM \
- (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
- /* 0xFFFF8396 */
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
+/* Still needed for spl_minimal.c */
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
!defined(CONFIG_NAND_SPL)
@@ -276,7 +175,7 @@
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
@@ -438,97 +337,8 @@
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
* MMU Setup
*/
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_128M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
- | BATU_BL_8M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
- | BATU_BL_32M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#define CONFIG_SYS_IBAT6L 0
-#define CONFIG_SYS_IBAT6U 0
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-
-#define CONFIG_SYS_IBAT7L 0
-#define CONFIG_SYS_IBAT7U 0
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 578202f..418c672 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -14,65 +14,16 @@
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-#endif
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_VCO_1X2 |\
- HRCWL_CSB_TO_CLKIN_2X1 |\
- HRCWL_CORE_TO_CSB_2_5X1 |\
- HRCWL_CE_PLL_VCO_DIV_2 |\
- HRCWL_CE_PLL_DIV_1X1 |\
- HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LALE_NORMAL)
-
-/*
* System IO Config
*/
#define CONFIG_SYS_SICRL 0x00000000
/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
- * System performance
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
-#define CONFIG_SYS_SPCR_OPT 1
-
-/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#undef CONFIG_SPD_EEPROM
#if defined(CONFIG_SPD_EEPROM)
@@ -163,36 +114,12 @@
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
-/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
- /* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFE006FF7 */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
@@ -323,109 +250,6 @@
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
- | BATU_BL_4M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
- | BATU_BL_32M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#else
-#define CONFIG_SYS_IBAT5L (0)
-#define CONFIG_SYS_IBAT5U (0)
-#define CONFIG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#endif
-
-/* Nothing in BAT7 */
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
#if (CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 8f11d9b..df9cc48 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -11,75 +11,16 @@
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
-#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
/*
- * System Clock Setup
- */
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
-#else
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 66000000
-#endif
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_VCO_1X2 |\
- HRCWL_CSB_TO_CLKIN_2X1 |\
- HRCWL_CORE_TO_CSB_2X1 |\
- HRCWL_CE_PLL_VCO_DIV_2 |\
- HRCWL_CE_PLL_DIV_1X1 |\
- HRCWL_CE_TO_PLL_1X3)
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_AGENT |\
- HRCWH_PCI1_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LALE_NORMAL)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LALE_NORMAL)
-#endif
-
-/*
* System IO Config
*/
#define CONFIG_SYS_SICRL 0x00000000
/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
#undef CONFIG_SPD_EEPROM
@@ -173,36 +114,11 @@
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
-/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
- /* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xfe006ff7 */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
@@ -214,22 +130,7 @@
*/
#define CONFIG_SYS_BCSR 0xF8000000
/* Access window base at BCSR base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFFFFE9F7 */
/*
* Windows to access PIB via local bus
@@ -237,45 +138,16 @@
/* PIB window base 0xF8008000 */
#define CONFIG_SYS_PIB_BASE 0xF8008000
#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
/*
* CS2 on Local Bus, to PIB
*/
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0xF8008801 */
-#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xffffe9f7 */
+
/*
* CS3 on Local Bus, to PIB
*/
-#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \
- CONFIG_SYS_PIB_WINDOW_SIZE) \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0xF8010801 */
-#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xffffe9f7 */
+
/*
* Serial Port
@@ -404,116 +276,6 @@
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
- | BATU_BL_4M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* BCSR: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
- | BATU_BL_32M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#else
-#define CONFIG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#endif
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index bda477c..7640d76 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -16,31 +16,6 @@
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_MPC834x 1 /* MPC834x family */
-#define CONFIG_MPC8349 1 /* MPC8349 specific */
-
-#define CONFIG_PCI_66M
-#ifdef CONFIG_PCI_66M
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#else
-#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
-#endif
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK 66666666 /* in Hz */
-#endif /* CONFIG_PCISLAVE */
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#ifdef CONFIG_PCI_66M
-#define CONFIG_SYS_CLK_FREQ 66000000
-#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
-#else
-#define CONFIG_SYS_CLK_FREQ 33000000
-#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
-#endif
-#endif
-
-#define CONFIG_SYS_IMMR 0xE0000000
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
@@ -77,9 +52,7 @@
*/
#undef CONFIG_DDR_32BIT
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#undef CONFIG_DDR_2T_TIMING
@@ -146,23 +119,6 @@
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
-
- /* window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
@@ -184,20 +140,7 @@
*/
#define CONFIG_SYS_BCSR 0xE2400000
/* Access window base at BCSR base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0x00000801 */
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_CLEAR \
- | OR_GPCM_EHTR_CLEAR)
- /* 0xFFFFE8F0 */
+
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
@@ -211,92 +154,6 @@
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
/*
- * Local Bus LCRR and LBCR regs
- * LCRR: DLL bypass, Clock divider is 4
- * External Local Bus rate is
- * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
-/*
- * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
- * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
- */
-#undef CONFIG_SYS_LB_SDRAM
-
-#ifdef CONFIG_SYS_LB_SDRAM
-/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR2, need:
- * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- * port-size = 32-bits = BR2[19:20] = 11
- * no parity checking = BR2[21:22] = 00
- * SDRAM for MSEL = BR2[24:26] = 011
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
- */
-
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
- | BR_PS_32 /* 32-bit port */ \
- | BR_MS_SDRAM /* MSEL = SDRAM */ \
- | BR_V) /* Valid */
- /* 0xF0001861 */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
-
-/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR2, need:
- * 64MB mask for AM, OR2[0:7] = 1111 1100
- * XAM, OR2[17:18] = 11
- * 9 columns OR2[19-21] = 010
- * 13 rows OR2[23-25] = 100
- * EAD set for extra time OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
- */
-
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \
- | OR_SDRAM_XAM \
- | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
- | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
- | OR_SDRAM_EAD)
- /* 0xFC006901 */
-
- /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT 0x32000000
- /* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
- | LSDMR_BSMA1516 \
- | LSDMR_RFCR8 \
- | LSDMR_PRETOACT6 \
- | LSDMR_ACTTORW3 \
- | LSDMR_BL8 \
- | LSDMR_WRC3 \
- | LSDMR_CL3)
-
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
-#endif
-
-/*
* Serial Port
*/
#define CONFIG_SYS_NS16550_SERIAL
@@ -363,13 +220,6 @@
#if defined(CONFIG_PCI)
-#define PCI_ONE_PCI1
-#if defined(PCI_64BIT)
-#undef PCI_ALL_PCI1
-#undef PCI_TWO_PCI1
-#undef PCI_ONE_PCI1
-#endif
-
#define CONFIG_83XX_PCI_STREAMING
#undef CONFIG_EEPRO100
@@ -463,93 +313,9 @@
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#if 1 /*528/264*/
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X2 |\
- HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*396/132*/
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X4 |\
- HRCWL_CORE_TO_CSB_3X1)
-#elif 0 /*264/132*/
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X4 |\
- HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*132/132*/
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X4 |\
- HRCWL_CORE_TO_CSB_1X1)
-#elif 0 /*264/264 */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X4 |\
- HRCWL_CORE_TO_CSB_1X1)
-#endif
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_AGENT |\
- HRCWH_64_BIT_PCI |\
- HRCWH_PCI1_ARBITER_DISABLE |\
- HRCWH_PCI2_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#else
-#if defined(PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_64_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_32_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#endif /* PCI_64BIT */
-#endif /* CONFIG_PCISLAVE */
-
/*
* System performance
*/
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
-#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
@@ -557,115 +323,10 @@
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
- | HID0_ENABLE_INSTRUCTION_CACHE)
-
-/* #define CONFIG_SYS_HID0_FINAL (\
- HID0_ENABLE_INSTRUCTION_CACHE |\
- HID0_ENABLE_M_BIT |\
- HID0_ENABLE_ADDRESS_BROADCAST) */
-
-#define CONFIG_SYS_HID2 HID2_HBE
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* PCI @ 0x80000000 */
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT1L (0)
-#define CONFIG_SYS_IBAT1U (0)
-#define CONFIG_SYS_IBAT2L (0)
-#define CONFIG_SYS_IBAT2U (0)
#endif
-#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
-#endif
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h
new file mode 100644
index 0000000..493f6df
--- /dev/null
+++ b/include/configs/MPC8349EMDS_SDRAM.h
@@ -0,0 +1,455 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+/*
+ * mpc8349emds board configuration file
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 Family */
+
+#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END 0x00100000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_DDR_ECC /* support DDR ECC function */
+#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
+#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
+
+/*
+ * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
+ * unselect it to use old spd_sdram.c
+ */
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS1 0x52
+#define SPD_EEPROM_ADDRESS2 0x51
+#define CONFIG_DIMM_SLOTS_PER_CTLR 2
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
+/*
+ * 32-bit data path mode.
+ *
+ * Please note that using this mode for devices with the real density of 64-bit
+ * effectively reduces the amount of available memory due to the effect of
+ * wrapping around while translating address to row/columns, for example in the
+ * 256MB module the upper 128MB get aliased with contents of the lower
+ * 128MB); normally this define should be used for devices with real 32-bit
+ * data path.
+ */
+#undef CONFIG_DDR_32BIT
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
+ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#undef CONFIG_DDR_2T_TIMING
+
+/*
+ * DDRCDR - DDR Control Driver Register
+ */
+#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
+
+#if defined(CONFIG_SPD_EEPROM)
+/*
+ * Determine DDR configuration from I2C interface.
+ */
+#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
+#else
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_SYS_DDR_SIZE 256 /* MB */
+#if defined(CONFIG_DDR_II)
+#define CONFIG_SYS_DDRCDR 0x80080001
+#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
+#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
+#define CONFIG_SYS_DDR_TIMING_0 0x00220802
+#define CONFIG_SYS_DDR_TIMING_1 0x38357322
+#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
+#define CONFIG_SYS_DDR_MODE 0x47d00432
+#define CONFIG_SYS_DDR_MODE2 0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
+#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
+#else
+#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
+ | CSCONFIG_ROW_BIT_13 \
+ | CSCONFIG_COL_BIT_10)
+#define CONFIG_SYS_DDR_TIMING_1 0x36332321
+#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
+
+#if defined(CONFIG_DDR_32BIT)
+/* set burst length to 8 for 32-bit data path */
+ /* DLL,normal,seq,4/2.5, 8 burst len */
+#define CONFIG_SYS_DDR_MODE 0x00000023
+#else
+/* the default burst length is 4 - for 64-bit data path */
+ /* DLL,normal,seq,4/2.5, 4 burst len */
+#define CONFIG_SYS_DDR_MODE 0x00000022
+#endif
+#endif
+#endif
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+/*
+ * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
+ */
+#define CONFIG_SYS_BCSR 0xE2400000
+ /* Access window base at BCSR base */
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
+
+/*
+ * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
+ */
+
+/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ * port-size = 32-bits = BR2[19:20] = 11
+ * no parity checking = BR2[21:22] = 00
+ * SDRAM for MSEL = BR2[24:26] = 011
+ * Valid = BR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
+ */
+
+/*
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ * 64MB mask for AM, OR2[0:7] = 1111 1100
+ * XAM, OR2[17:18] = 11
+ * 9 columns OR2[19-21] = 010
+ * 13 rows OR2[23-25] = 100
+ * EAD set for extra time OR[31] = 1
+ *
+ * 0 4 8 12 16 20 24 28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
+ */
+
+
+ /* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_LSRT 0x32000000
+ /* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR 0x20000000
+
+#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
+ | LSDMR_BSMA1516 \
+ | LSDMR_RFCR8 \
+ | LSDMR_PRETOACT6 \
+ | LSDMR_ACTTORW3 \
+ | LSDMR_BL8 \
+ | LSDMR_WRC3 \
+ | LSDMR_CL3)
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
+
+/* SPI */
+#undef CONFIG_SOFT_SPI /* SPI bit-banged */
+
+/* GPIOs. Used as SPI chip selects */
+#define CONFIG_SYS_GPIO1_PRELIM
+#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
+#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
+
+/* TSEC */
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/* USB */
+#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
+#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_83XX_PCI_STREAMING
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xFIXME
+ #define PCI_ENET0_MEMADDR 0xFIXME
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
+
+#endif /* CONFIG_PCI */
+
+/*
+ * TSEC configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_GMII 1 /* MII PHY management */
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
+#define TSEC1_PHY_ADDR 0
+#define TSEC2_PHY_ADDR 1
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC0"
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+ #define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+ #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+ #define CONFIG_ENV_SIZE 0x2000
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+#else
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+ #define CONFIG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+ /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
+
+/*
+ * System performance
+ */
+#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
+#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
+#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH 0
+#define CONFIG_SYS_SICRL SICRL_LDP_A
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH0
+#endif
+
+#define CONFIG_HOSTNAME "mpc8349emds"
+#define CONFIG_ROOTPATH "/nfsroot/rootfs"
+#define CONFIG_BOOTFILE "uImage"
+
+#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+ "echo"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=mpc8349emds\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
+ "update=protect off fe000000 fe03ffff; " \
+ "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
+ "upd=run load update\0" \
+ "fdtaddr=780000\0" \
+ "fdtfile=mpc834x_mds.dtb\0" \
+ ""
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
+ "$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 111023b..a3f704c 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -39,25 +39,13 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
-#define CONFIG_SYS_LOWBOOT
-#endif
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */
-#define CONFIG_MPC8349 /* MPC8349 specific */
-
-#define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
-
#define CONFIG_MISC_INIT_F
/*
* On-board devices
*/
-#ifdef CONFIG_MPC8349ITX
+#ifdef CONFIG_TARGET_MPC8349ITX
/* The CF card interface on the back of the board */
#define CONFIG_COMPACT_FLASH
#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
@@ -154,9 +142,7 @@
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_83XX_DDR_USES_CS0
#define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x2000
@@ -218,23 +204,6 @@
* BRx, ORx, LBLAWBARx, and LBLAWARx
*/
-/* Flash */
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 \
- | BR_MS_GPCM \
- | BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
/* Vitesse 7385 */
@@ -242,39 +211,12 @@
#ifdef CONFIG_VSC7385_ENET
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_SETA \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
#endif
-/* LED */
#define CONFIG_SYS_LED_BASE 0xF9000000
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_9 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
+
/* Compact Flash */
@@ -282,14 +224,6 @@
#define CONFIG_SYS_CF_BASE 0xF0000000
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \
- | BR_PS_16 \
- | BR_MS_UPMA \
- | BR_V)
-#define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
-
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
#endif
@@ -317,21 +251,6 @@
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
/*
- * Local Bus LCRR and LBCR regs
- * LCRR: DLL bypass, Clock divider is 4
- * External Local Bus rate is
- * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
- /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT 0x32000000
- /* LB refresh timer prescal, 266MHz/32*/
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
-/*
* Serial Port
*/
#define CONFIG_SYS_NS16550_SERIAL
@@ -394,13 +313,6 @@
#endif
-#define CONFIG_PCI_66M
-#ifdef CONFIG_PCI_66M
-#define CONFIG_83XX_CLKIN 66666666 /* in Hz */
-#else
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#endif
-
/* TSEC */
#ifdef CONFIG_TSEC_ENET
@@ -471,48 +383,9 @@
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN_4X1 |\
- HRCWL_VCO_1X2 |\
- HRCWL_CORE_TO_CSB_2X1)
-
-#ifdef CONFIG_SYS_LOWBOOT
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_32_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_32_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#endif
-
/*
* System performance
*/
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
-#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
@@ -526,108 +399,6 @@
/* USB DR as device + USB MPH as host */
#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
-#define CONFIG_SYS_HID0_INIT 0x00000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
-
-#define CONFIG_SYS_HID2 HID2_HBE
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* PCI */
-#ifdef CONFIG_PCI
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT1L 0
-#define CONFIG_SYS_IBAT1U 0
-#define CONFIG_SYS_IBAT2L 0
-#define CONFIG_SYS_IBAT2U 0
-#endif
-
-#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT3L 0
-#define CONFIG_SYS_IBAT3U 0
-#define CONFIG_SYS_IBAT4L 0
-#define CONFIG_SYS_IBAT4U 0
-#endif
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-#define CONFIG_SYS_IBAT7L 0
-#define CONFIG_SYS_IBAT7U 0
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
@@ -645,7 +416,7 @@
/* U-Boot image on TFTP server */
#define CONFIG_UBOOTPATH "u-boot.bin"
-#ifdef CONFIG_MPC8349ITX
+#ifdef CONFIG_TARGET_MPC8349ITX
#define CONFIG_FDTFILE "mpc8349emitx.dtb"
#else
#define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 50f6df5..724f8af 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -11,72 +11,8 @@
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
-#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
/*
- * System Clock Setup
- */
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
-#else
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 66000000
-#endif
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66MHz, then
- * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_SVCOD_DIV_2 |\
- HRCWL_CSB_TO_CLKIN_6X1 |\
- HRCWL_CORE_TO_CSB_1_5X1)
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_AGENT |\
- HRCWH_PCI1_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LDP_CLEAR)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LDP_CLEAR)
-#endif
-
-/* Arbiter Configuration Register */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
-
-/* System Priority Control Register */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
-
-/*
* IP blocks clock configuration
*/
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
@@ -97,16 +33,9 @@
#define CONFIG_HWCONFIG
/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_83XX_DDR_USES_CS0
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
@@ -205,12 +134,6 @@
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
-#define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_FSL_ELBC 1
/*
@@ -219,24 +142,6 @@
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
- /* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFE000FF7 */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
@@ -250,23 +155,6 @@
*/
#define CONFIG_SYS_BCSR 0xF8000000
/* Access window base at BCSR base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0xF8000801 */
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFFFFE9F7 */
/*
* NAND Flash on the Local Bus
@@ -275,23 +163,7 @@
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BASE 0xE0600000
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
- | BR_DECC_CHK_GEN /* Use HW ECC */ \
- | BR_PS_8 /* 8 bit port */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
- | OR_FCM_BCTLD \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_RST \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
- /* 0xFFFF919E */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
/*
* Serial Port
@@ -469,123 +341,6 @@
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
-
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
- | BATU_BL_8M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* BCSR: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
- | BATU_BL_32M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#else
-#define CONFIG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#endif
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 4ddd62d..13a7682 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -12,8 +12,6 @@
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
-#define CONFIG_MPC837XERDB 1
#define CONFIG_HWCONFIG
@@ -22,70 +20,9 @@
*/
#define CONFIG_VSC7385_ENET
-/*
- * System Clock Setup
- */
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK 66666667 /* in HZ */
-#else
-#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
-#define CONFIG_PCIE
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-#endif
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_SVCOD_DIV_2 |\
- HRCWL_CSB_TO_CLKIN_5X1 |\
- HRCWL_CORE_TO_CSB_2X1)
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_AGENT |\
- HRCWH_PCI1_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LDP_CLEAR)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LDP_CLEAR)
-#endif
-
/* System performance - define the value i.e. CONFIG_SYS_XXX
*/
-/* Arbiter Configuration Register */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-
-/* System Priority Control Regsiter */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
-
/* System Clock Configuration Register */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
@@ -103,11 +40,6 @@
#define CONFIG_SYS_OBIR 0x30100000
/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
* Device configurations
*/
@@ -126,9 +58,7 @@
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
#define CONFIG_SYS_83XX_DDR_USES_CS0
@@ -228,12 +158,6 @@
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
-#define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_FSL_ELBC 1
/*
@@ -244,20 +168,6 @@
#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
- /* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_9 \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFF800191 */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
@@ -270,20 +180,7 @@
* NAND Flash on the Local Bus
*/
#define CONFIG_SYS_NAND_BASE 0xE0600000
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
- | BR_DECC_CHK_GEN /* Use HW ECC */ \
- | BR_PS_8 /* 8 bit port */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
+
/* Vitesse 7385 */
@@ -291,24 +188,6 @@
#ifdef CONFIG_VSC7385_ENET
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0xF0000801 */
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_SETA \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xfffe09ff */
-
- /* Access Base */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
#endif
@@ -483,124 +362,6 @@
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
- | HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
-
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
- | BATU_BL_8M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* L2 Switch: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
- | BATU_BL_32M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#else
-#define CONFIG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#endif
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index b534d47..04f55e3 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -43,7 +43,6 @@
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */
#define CONFIG_ALTIVEC 1
/*
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 9318b19..8c01891 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -45,7 +45,6 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
#define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */
#define CONFIG_ALTIVEC 1
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 0942b87..0da34d0 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -15,26 +15,6 @@
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_MPC834x 1 /* MPC834x specific */
-#define CONFIG_MPC8349 1 /* MPC8349 specific */
-
-/* IMMR Base Address Register, use Freescale default: 0xff400000 */
-#define CONFIG_SYS_IMMR 0xff400000
-
-/* System clock. Primary input clock when in PCI host mode */
-#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
-
-/*
- * Local Bus LCRR
- * LCRR: DLL bypass, Clock divider is 8
- *
- * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
- *
- * External Local Bus rate is
- * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
/* board pre init: do not call, nothing to do */
@@ -44,9 +24,7 @@
* DDR Setup
*/
/* DDR is system memory*/
-#define CONFIG_SYS_DDR_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
@@ -81,43 +59,16 @@
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
-/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \
- | BR_MS_GPCM \
- | BR_PS_32 \
- | BR_V)
-
-/* FLASH timing (0x0000_0c54) */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV4 \
- | OR_GPCM_SCY_5 \
- | OR_GPCM_TRLX)
-
-#define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */
-
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \
- | CONFIG_SYS_OR_TIMING_FLASH)
-
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB)
-
- /* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
/* disable remaining mappings */
#define CONFIG_SYS_BR1_PRELIM 0x00000000
#define CONFIG_SYS_OR1_PRELIM 0x00000000
-#define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000
-#define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000
#define CONFIG_SYS_BR2_PRELIM 0x00000000
#define CONFIG_SYS_OR2_PRELIM 0x00000000
-#define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000
-#define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000
#define CONFIG_SYS_BR3_PRELIM 0x00000000
#define CONFIG_SYS_OR3_PRELIM 0x00000000
-#define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000
-#define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000
/*
* Monitor config
@@ -265,150 +216,15 @@
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN_4X1 |\
- HRCWL_VCO_1X2 |\
- HRCWL_CORE_TO_CSB_2X1)
-
-#if defined(PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_64_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_32_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#endif
-
/* System IO Config */
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A
-/* i-cache and d-cache disabled */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR 0 - 512M */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* stack in DCACHE @ 512M (no backing mem) */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-
/* PCI */
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \
- | BATU_BL_16M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
-#define CONFIG_SYS_IBAT5L (0)
-#define CONFIG_SYS_IBAT5U (0)
#endif
-/* IMMRBAR */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \
- | BATU_BL_1M \
- | BATU_VS \
- | BATU_VP)
-
-/* FLASH */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h
new file mode 100644
index 0000000..15ac179
--- /dev/null
+++ b/include/configs/caddy2.h
@@ -0,0 +1,334 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * esd vme8349 U-Boot configuration file
+ * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
+ *
+ * (C) Copyright 2006-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * reinhard.arlt@esd-electronics.de
+ * Based on the MPC8349EMDS config.
+ */
+
+/*
+ * vme8349 board configuration file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 Family */
+
+/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
+#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
+
+#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END 0x00100000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
+#define CONFIG_SPD_EEPROM
+#define SPD_EEPROM_ADDRESS 0x54
+#define CONFIG_SYS_READ_SPD vme8349_read_spd
+#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
+
+/*
+ * 32-bit data path mode.
+ *
+ * Please note that using this mode for devices with the real density of 64-bit
+ * effectively reduces the amount of available memory due to the effect of
+ * wrapping around while translating address to row/columns, for example in the
+ * 256MB module the upper 128MB get aliased with contents of the lower
+ * 128MB); normally this define should be used for devices with real 32-bit
+ * data path.
+ */
+#undef CONFIG_DDR_32BIT
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
+ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
+#define CONFIG_DDR_2T_TIMING
+#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
+ | DDRCDR_ODT \
+ | DDRCDR_Q_DRN)
+ /* 0x80080001 */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
+
+
+#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
+
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
+#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
+
+#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
+/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
+
+#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
+
+/* TSEC */
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
+#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
+
+#if defined(CONFIG_PCI)
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xFIXME
+ #define PCI_ENET0_MEMADDR 0xFIXME
+ #define PCI_IDSEL_NUMBER 0xFIXME
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
+
+#endif /* CONFIG_PCI */
+
+/*
+ * TSEC configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_GMII /* MII PHY management */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2
+#define CONFIG_TSEC2_NAME "TSEC1"
+#define CONFIG_PHY_M88E1111
+#define TSEC1_PHY_ADDR 0x08
+#define TSEC2_PHY_ADDR 0x10
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC0"
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
+ #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+ #define CONFIG_ENV_SIZE 0x2000
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+#else
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+ #define CONFIG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_SYS_RTC_BUS_NUM 0x01
+#define CONFIG_SYS_I2C_RTC_ADDR 0x32
+#define CONFIG_RTC_RX8025
+
+/* Pass Ethernet MAC to VxWorks */
+#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH 0
+#define CONFIG_SYS_SICRL SICRL_LDP_A
+
+#define CONFIG_SYS_GPIO1_PRELIM
+#define CONFIG_SYS_GPIO1_DIR 0x00100000
+#define CONFIG_SYS_GPIO1_DAT 0x00100000
+
+#define CONFIG_SYS_GPIO2_PRELIM
+#define CONFIG_SYS_GPIO2_DIR 0x78900000
+#define CONFIG_SYS_GPIO2_DAT 0x70100000
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_HOSTNAME "VME8349"
+#define CONFIG_ROOTPATH "/tftpboot/rootfs"
+#define CONFIG_BOOTFILE "uImage"
+
+#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=vme8349\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
+ "update=protect off fff00000 fff3ffff; " \
+ "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
+ "upd=run load update\0" \
+ "fdtaddr=780000\0" \
+ "fdtfile=vme8349.dtb\0" \
+ ""
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
+ "$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#ifndef __ASSEMBLY__
+int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
+ unsigned char *buffer, int len);
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h
new file mode 100644
index 0000000..11d367a
--- /dev/null
+++ b/include/configs/gazerbeam.h
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2015
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
+/* TODO: Check: Can this be unified with CONFIG_SYS_SDRAM_BASE? */
+#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
+
+/*
+ * Memory test
+ * TODO: Migrate!
+ */
+#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END 0x07e00000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 135
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
+
+/* TODO: Turn into string option and migrate to Kconfig */
+#define CONFIG_HOSTNAME "gazerbeam"
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+
+#define CONFIG_PREBOOT /* enable preboot variable */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyS1\0" \
+ "u-boot=u-boot.bin\0" \
+ "kernel_addr=1000000\0" \
+ "fdt_addr=C00000\0" \
+ "fdtfile=hrcon.dtb\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
+ " +${filesize};cp.b ${fileaddr} " \
+ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
+ "upd=run load update\0" \
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp ${kernel_addr} $bootfile;" \
+ "tftp ${fdt_addr} $fdtfile;" \
+ "bootm ${kernel_addr} - ${fdt_addr}"
+
+#define CONFIG_MMCBOOTCOMMAND \
+ "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
+ "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
+ "bootm ${kernel_addr} - ${fdt_addr}"
+
+#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index 52e6277..6e6c171 100644
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -12,100 +12,19 @@
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC83xx 1 /* MPC83xx family */
-#define CONFIG_MPC830x 1 /* MPC830x family */
-#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
-#define CONFIG_HRCON 1 /* HRCON board specific */
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
- * We choose the A type silicon as default, so the core is 400Mhz.
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_SVCOD_DIV_2 |\
- HRCWL_CSB_TO_CLKIN_4X1 |\
- HRCWL_CORE_TO_CSB_3X1)
-/*
- * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
- * in 8308's HRCWH according to the manual, but original Freescale's
- * code has them and I've expirienced some problems using the board
- * with BDI3000 attached when I've tried to set these bits to zero
- * (UART doesn't work after the 'reset run' command).
- */
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_RGMII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN)
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH (\
- SICRH_ESDHC_A_SD |\
- SICRH_ESDHC_B_SD |\
- SICRH_ESDHC_C_SD |\
- SICRH_GPIO_A_GPIO |\
- SICRH_GPIO_B_GPIO |\
- SICRH_IEEE1588_A_GPIO |\
- SICRH_USB |\
- SICRH_GTM_GPIO |\
- SICRH_IEEE1588_B_GPIO |\
- SICRH_ETSEC2_GPIO |\
- SICRH_GPIOSEL_1 |\
- SICRH_TMROBI_V3P3 |\
- SICRH_TSOBI1_V2P5 |\
- SICRH_TSOBI2_V2P5) /* 0x0037f103 */
-#define CONFIG_SYS_SICRL (\
- SICRL_SPI_PF0 |\
- SICRL_UART_PF0 |\
- SICRL_IRQ_PF0 |\
- SICRL_I2C2_PF0 |\
- SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
* SERDES
*/
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1 0xe3000
/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
-
-/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
| DDRCDR_PZ_LOZ \
@@ -192,13 +111,6 @@
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR 0x00040000
-
-/*
* FLASH on the Local Bus
*/
#if 1
@@ -210,22 +122,6 @@
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
-/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 135
@@ -233,30 +129,6 @@
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-/*
- * FPGA
- */
-#define CONFIG_SYS_FPGA0_BASE 0xE0600000
-#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
-
-/* Window base at FPGA base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
-
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET)
-
-#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
#define CONFIG_SYS_FPGA_DONE(k) 0x0010
#define CONFIG_SYS_FPGA_COUNT 1
@@ -515,52 +387,6 @@
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
- BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
* Environment Configuration
*/
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index 7e4c497..b1d01c5 100644
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -14,56 +14,17 @@
/*
* High Level Configuration Options
*/
-#define CONFIG_MPC831x
-#define CONFIG_MPC8313
-
#define CONFIG_FSL_ELBC
#define CONFIG_BOOT_RETRY_TIME 900
#define CONFIG_BOOT_RETRY_MIN 30
#define CONFIG_RESET_TO_RETRY
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-#define CONFIG_SYS_IMMR 0xF0000000
-
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.000MHz, then
- * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
- */
-#define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_CSB_TO_CLKIN_2X1 |\
- HRCWL_CORE_TO_CSB_2X1)
-
-#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_8BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_MII |\
- HRCWH_TSEC2M_IN_MII |\
- HRCWH_BIG_ENDIAN)
-
#define CONFIG_SYS_SICRH 0x00000000
#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
#define CONFIG_HWCONFIG
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\
- HID0_ENABLE_INSTRUCTION_CACHE |\
- HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
-
-#define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
-
/*
* Definitions for initial stack pointer and data area (in DCACHE )
*/
@@ -76,25 +37,12 @@
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR (0x00040000 |\
- (0xFF << LBCR_BMT_SHIFT) |\
- 0xF)
-
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
-/*
* Internal Definitions
*/
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
/*
* Manually set up DDR parameters,
@@ -169,20 +117,7 @@
#define CONFIG_SYS_FLASH_BASE 0xFF800000
#define CONFIG_SYS_FLASH_SIZE 8
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
- BR_PS_8 |\
- BR_MS_GPCM |\
- BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
- OR_GPCM_SCY_10 |\
- OR_GPCM_EHTR |\
- OR_GPCM_TRLX |\
- OR_GPCM_CSNT |\
- OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 128
@@ -200,60 +135,24 @@
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
#define NAND_CACHE_PAGES 64
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
-
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\
- (2<<BR_DECC_SHIFT) |\
- BR_PS_8 |\
- BR_MS_FCM |\
- BR_V)
-
-#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\
- OR_FCM_PGS |\
- OR_FCM_CSCT |\
- OR_FCM_CST |\
- OR_FCM_CHT |\
- OR_FCM_SCY_4 |\
- OR_FCM_TRLX |\
- OR_FCM_EHTR |\
- OR_FCM_RST)
/*
* MRAM setup
*/
#define CONFIG_SYS_MRAM_BASE 0xE2000000
#define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_MRAM_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* 128 Kb */
#define CONFIG_SYS_OR_TIMING_MRAM
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\
- BR_PS_8 |\
- BR_MS_GPCM |\
- BR_V)
-
-#define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74
/*
* CPLD setup
*/
#define CONFIG_SYS_CPLD_BASE 0xE3000000
#define CONFIG_SYS_CPLD_SIZE 0x8000
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CPLD_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E
#define CONFIG_SYS_OR_TIMING_MRAM
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\
- BR_PS_8 |\
- BR_MS_GPCM |\
- BR_V)
-
-#define CONFIG_SYS_OR3_PRELIM 0xFFFF8814
/*
* HW-Watchdog
@@ -304,90 +203,12 @@
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_SYS_SCCR_USBDRCM 3
/*
- * BAT's
- */
-#define CONFIG_HIGH_BATS
-
-/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\
- BATL_PP_10)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE |\
- BATU_BL_256M |\
- BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* Initial RAM @ 0xFD000000 */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR |\
- BATL_PP_10 |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR |\
- BATU_BL_256K |\
- BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* FLASH @ 0xFF800000 */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE |\
- BATL_PP_10 |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE |\
- BATU_BL_8M |\
- BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE |\
- BATL_PP_10 |\
- BATL_CACHEINHIBIT |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* IMMRBAR @ 0xF0000000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR |\
- BATL_PP_10 |\
- BATL_CACHEINHIBIT |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR |\
- BATU_BL_128M |\
- BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-/* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
-#define CONFIG_SYS_IBAT6L (0xE0000000 |\
- BATL_PP_10 |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xE0000000 |\
- BATU_BL_256M |\
- BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-/*
* U-Boot environment setup
*/
#define CONFIG_BOOTP_BOOTFILESIZE
diff --git a/include/configs/km/km8309-common.h b/include/configs/km/km-mpc8309.h
similarity index 70%
rename from include/configs/km/km8309-common.h
rename to include/configs/km/km-mpc8309.h
index 0e0b1b4..e89b7af 100644
--- a/include/configs/km/km8309-common.h
+++ b/include/configs/km/km-mpc8309.h
@@ -1,26 +1,17 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012 Keymile AG
- * Gerlando Falauto <gerlando.falauto@keymile.com>
- *
- * Based on km8321-common.h, see respective copyright notice for credits
- */
-
-#ifndef __CONFIG_KM8309_COMMON_H
-#define __CONFIG_KM8309_COMMON_H
-
/*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC830x 1 /* MPC830x family */
-#define CONFIG_MPC8309 1 /* MPC8309 CPU specific */
#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
-/* include common defines/options for all 83xx Keymile boards */
-#include "km83xx-common.h"
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN 66000000
+#define CONFIG_SYS_CLK_FREQ 66000000
+#define CONFIG_83XX_PCICLK 66000000
/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
@@ -74,28 +65,6 @@
#define CONFIG_SYS_GP2DIR 0xFF000000
#define CONFIG_SYS_GP2ODR 0x00000000
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
- HRCWL_DDR_TO_SCB_CLK_2X1 | \
- HRCWL_CSB_TO_CLKIN_2X1 | \
- HRCWL_CORE_TO_CSB_2X1 | \
- HRCWL_CE_PLL_VCO_DIV_2 | \
- HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_AGENT | \
- HRCWH_PCI_ARBITER_DISABLE | \
- HRCWH_CORE_ENABLE | \
- HRCWH_FROM_0X00000100 | \
- HRCWH_BOOTSEQ_DISABLE | \
- HRCWH_SW_WATCHDOG_DISABLE | \
- HRCWH_ROM_LOC_LOCAL_16BIT | \
- HRCWH_BIG_ENDIAN | \
- HRCWH_LALE_NORMAL)
-
#define CONFIG_SYS_DDRCDR (\
DDRCDR_EN | \
DDRCDR_PZ_MAXZ | \
@@ -156,21 +125,13 @@
/* EEprom support */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP 0x80000000
-#define CONFIG_SYS_LCRR_EADC 0x00010000
-#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
-
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
-/*
- * MMU Setup
- */
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-#endif /* __CONFIG_KM8309_COMMON_H */
+/* ethernet port connected to piggy (UEC2) */
+#define CONFIG_HAS_ETH1
+#define CONFIG_UEC_ETH2
+#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */
+#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
+#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12
+#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR 0
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
diff --git a/include/configs/km/km-mpc832x.h b/include/configs/km/km-mpc832x.h
new file mode 100644
index 0000000..3c2173d
--- /dev/null
+++ b/include/configs/km/km-mpc832x.h
@@ -0,0 +1,91 @@
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_QE /* Has QE */
+#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN 66000000
+#define CONFIG_SYS_CLK_FREQ 66000000
+#define CONFIG_83XX_PCICLK 66000000
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH1 /* GETH1 */
+#define UEC_VERBOSE_DEBUG 1
+
+#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
+#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
+#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
+#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR 0
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRL SICRL_IRQ_CKS
+
+#define CONFIG_SYS_DDRCDR (\
+ DDRCDR_EN | \
+ DDRCDR_PZ_MAXZ | \
+ DDRCDR_NZ_MAXZ | \
+ DDRCDR_M_ODR)
+
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
+#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+ SDRAM_CFG_32_BE | \
+ SDRAM_CFG_SREN | \
+ SDRAM_CFG_HSE)
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
+#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+ (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
+ CSCONFIG_ODT_WR_CFG | \
+ CSCONFIG_ROW_BIT_13 | \
+ CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_MODE 0x47860242
+#define CONFIG_SYS_DDR_MODE2 0x8080c000
+
+#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+ (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+ (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+ (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+ (0 << TIMING_CFG0_WWT_SHIFT) | \
+ (0 << TIMING_CFG0_RRT_SHIFT) | \
+ (0 << TIMING_CFG0_WRT_SHIFT) | \
+ (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
+ (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+ (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+ (3 << TIMING_CFG1_WRREC_SHIFT) | \
+ (7 << TIMING_CFG1_REFREC_SHIFT) | \
+ (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+ (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+ (3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+ (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+ (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+ (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+ (5 << TIMING_CFG2_CPO_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+
+#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h
new file mode 100644
index 0000000..8f26e05
--- /dev/null
+++ b/include/configs/km/km-mpc8360.h
@@ -0,0 +1,91 @@
+/* KMBEC FPGA (PRIO) */
+#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE 64
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_QE /* Has QE */
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH1 /* GETH1 */
+#define UEC_VERBOSE_DEBUG 1
+
+#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
+#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
+#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
+#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR 0
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
+
+/*
+ * System IO Setup
+ */
+#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
+
+/**
+ * DDR RAM settings
+ */
+#define CONFIG_SYS_DDR_SDRAM_CFG (\
+ SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+ SDRAM_CFG_SREN | \
+ SDRAM_CFG_HSE)
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
+
+#define CONFIG_SYS_DDR_CLK_CNTL (\
+ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
+#define CONFIG_SYS_DDR_INTERVAL (\
+ (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+ (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
+
+#define CONFIG_SYS_DDRCDR (\
+ DDRCDR_EN | \
+ DDRCDR_Q_DRN)
+#define CONFIG_SYS_DDR_MODE 0x47860452
+#define CONFIG_SYS_DDR_MODE2 0x8080c000
+
+#define CONFIG_SYS_DDR_TIMING_0 (\
+ (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+ (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+ (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+ (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+ (0 << TIMING_CFG0_WWT_SHIFT) | \
+ (0 << TIMING_CFG0_RRT_SHIFT) | \
+ (0 << TIMING_CFG0_WRT_SHIFT) | \
+ (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
+ (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+ (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+ (3 << TIMING_CFG1_WRREC_SHIFT) | \
+ (7 << TIMING_CFG1_REFREC_SHIFT) | \
+ (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+ (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+ (3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2 (\
+ (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+ (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+ (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+ (5 << TIMING_CFG2_CPO_SHIFT) | \
+ (0 << TIMING_CFG2_ADD_LAT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+/*
+ * PAXE on the local bus CS3
+ */
+#define CONFIG_SYS_PAXE_BASE 0xA0000000
+#define CONFIG_SYS_PAXE_SIZE 256
diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h
new file mode 100644
index 0000000..455e523
--- /dev/null
+++ b/include/configs/km/km-mpc83xx.h
@@ -0,0 +1,160 @@
+/*
+ * Internal Definitions
+ */
+#define BOOTFLASH_START 0xF0000000
+
+#define CONFIG_KM_CONSOLE_TTY "ttyS0"
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
+
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
+ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
+#define CFG_83XX_DDR_USES_CS0
+
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_DDR_II
+#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_FLASH_BASE 0xF0000000
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+/* Reserve 768 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+/*
+ * Init Local Bus Memory Controller:
+ *
+ * Bank Bus Machine PortSz Size Device
+ * ---- --- ------- ------ ----- ------
+ * 0 Local GPCM 16 bit 256MB FLASH
+ * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
+ *
+ */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_NUM_I2C_BUSES 4
+#define CONFIG_SYS_I2C_MAX_HOPS 1
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 200000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 200000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
+ {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
+ {1, {I2C_NULL_HOP} } }
+
+#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_KMETER1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+
+/*
+ * Environment
+ */
+
+#ifndef CONFIG_SYS_RAMBOOT
+#ifndef CONFIG_ENV_ADDR
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#endif
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+#ifndef CONFIG_ENV_OFFSET
+#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
+#endif
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
+ CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+#else /* CFG_SYS_RAMBOOT */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE 0x2000
+#endif /* CFG_SYS_RAMBOOT */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV "km-common=empty\0"
+#endif
+
+#ifndef CONFIG_KM_DEF_ARCH
+#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_KM_DEF_ENV \
+ CONFIG_KM_DEF_ARCH \
+ "newenv=" \
+ "prot off " __stringify(CONFIG_ENV_ADDR) " +0x40000 && " \
+ "era " __stringify(CONFIG_ENV_ADDR) " +0x40000\0" \
+ "unlock=yes\0" \
+ ""
+
+#if defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
+#endif
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME "UEC0"
diff --git a/include/configs/km/km8321-common.h b/include/configs/km/km8321-common.h
deleted file mode 100644
index 41b3ba2..0000000
--- a/include/configs/km/km8321-common.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * Copyright (C) 2007 Logic Product Development, Inc.
- * Peter Barada <peterb@logicpd.com>
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- * Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * (C) Copyright 2008
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * (C) Copyright 2010
- * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
- *
- * (C) Copyright 2010-2011
- * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com
- */
-
-#ifndef __CONFIG_KM8321_COMMON_H
-#define __CONFIG_KM8321_COMMON_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_QE /* Has QE */
-#define CONFIG_MPC832x /* MPC832x CPU specific */
-#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */
-
-#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
-
-/* include common defines/options for all 83xx Keymile boards */
-#include "km83xx-common.h"
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRL SICRL_IRQ_CKS
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
- HRCWL_DDR_TO_SCB_CLK_2X1 | \
- HRCWL_CSB_TO_CLKIN_2X1 | \
- HRCWL_CORE_TO_CSB_2_5X1 | \
- HRCWL_CE_PLL_VCO_DIV_2 | \
- HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_AGENT | \
- HRCWH_PCI_ARBITER_DISABLE | \
- HRCWH_CORE_ENABLE | \
- HRCWH_FROM_0X00000100 | \
- HRCWH_BOOTSEQ_DISABLE | \
- HRCWH_SW_WATCHDOG_DISABLE | \
- HRCWH_ROM_LOC_LOCAL_16BIT | \
- HRCWH_BIG_ENDIAN | \
- HRCWH_LALE_NORMAL)
-
-#define CONFIG_SYS_DDRCDR (\
- DDRCDR_EN | \
- DDRCDR_PZ_MAXZ | \
- DDRCDR_NZ_MAXZ | \
- DDRCDR_M_ODR)
-
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
- SDRAM_CFG_32_BE | \
- SDRAM_CFG_SREN | \
- SDRAM_CFG_HSE)
-
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
- (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
-
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
- CSCONFIG_ODT_WR_CFG | \
- CSCONFIG_ROW_BIT_13 | \
- CSCONFIG_COL_BIT_10)
-
-#define CONFIG_SYS_DDR_MODE 0x47860242
-#define CONFIG_SYS_DDR_MODE2 0x8080c000
-
-#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
- (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
- (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
- (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
- (0 << TIMING_CFG0_WWT_SHIFT) | \
- (0 << TIMING_CFG0_RRT_SHIFT) | \
- (0 << TIMING_CFG0_WRT_SHIFT) | \
- (0 << TIMING_CFG0_RWT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
- (2 << TIMING_CFG1_WRTORD_SHIFT) | \
- (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
- (3 << TIMING_CFG1_WRREC_SHIFT) | \
- (7 << TIMING_CFG1_REFREC_SHIFT) | \
- (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
- (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
- (3 << TIMING_CFG1_PRETOACT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
- (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
- (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
- (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
- (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
- (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
- (5 << TIMING_CFG2_CPO_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-
-#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
-#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
-
-/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP 0x80000000
-#define CONFIG_SYS_LCRR_EADC 0x00010000
-#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
-
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
-/*
- * MMU Setup
- */
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-#endif /* __CONFIG_KM8321_COMMON_H */
diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h
deleted file mode 100644
index a76f606..0000000
--- a/include/configs/km/km83xx-common.h
+++ /dev/null
@@ -1,296 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- */
-
-#ifndef __CONFIG_KM83XX_H
-#define __CONFIG_KM83XX_H
-
-/* include common defines/options for all Keymile boards */
-#include "keymile-common.h"
-#include "km-powerpc.h"
-
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 66000000
-#define CONFIG_SYS_CLK_FREQ 66000000
-#define CONFIG_83XX_PCICLK 66000000
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
- * Bus Arbitration Configuration Register (ACR)
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
-#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
-#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
- DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-
-#define CFG_83XX_DDR_USES_CS0
-
-/*
- * Manually set up DDR parameters
- */
-#define CONFIG_DDR_II
-#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#define CONFIG_SYS_FLASH_BASE 0xF0000000
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-/* Reserve 768 kB for Mon */
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-/*
- * Init Local Bus Memory Controller:
- *
- * Bank Bus Machine PortSz Size Device
- * ---- --- ------- ------ ----- ------
- * 0 Local GPCM 16 bit 256MB FLASH
- * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
- *
- */
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
- BR_PS_16 | /* 16 bit port size */ \
- BR_MS_GPCM | /* MSEL = GPCM */ \
- BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
- OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
- OR_GPCM_SCY_5 | \
- OR_GPCM_TRLX_SET | OR_GPCM_EAD)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-/*
- * PRIO1/PIGGY on the local bus CS1
- */
-/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
-
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \
- BR_PS_8 | /* 8 bit port size */ \
- BR_MS_GPCM | /* MSEL = GPCM */ \
- BR_V)
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
- OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
- OR_GPCM_SCY_2 | \
- OR_GPCM_TRLX_SET | OR_GPCM_EAD)
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME "UEC0"
-
-#if !defined(CONFIG_MPC8309)
-#define CONFIG_UEC_ETH1 /* GETH1 */
-#define UEC_VERBOSE_DEBUG 1
-#endif
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
-#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 0
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
-#endif
-
-/*
- * Environment
- */
-
-#ifndef CONFIG_SYS_RAMBOOT
-#ifndef CONFIG_ENV_ADDR
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
- CONFIG_SYS_MONITOR_LEN)
-#endif
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
-#ifndef CONFIG_ENV_OFFSET
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
-#endif
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
- CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-#else /* CFG_SYS_RAMBOOT */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-#define CONFIG_ENV_SIZE 0x2000
-#endif /* CFG_SYS_RAMBOOT */
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_NUM_I2C_BUSES 4
-#define CONFIG_SYS_I2C_MAX_HOPS 1
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 200000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 200000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
- {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
- {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
- {1, {I2C_NULL_HOP} } }
-
-#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
-
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_NAND_KMETER1
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
-#endif
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/*
- * Internal Definitions
- */
-#define BOOTFLASH_START 0xF0000000
-
-#define CONFIG_KM_CONSOLE_TTY "ttyS0"
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
-#define CONFIG_KM_DEF_ENV "km-common=empty\0"
-#endif
-
-#ifndef CONFIG_KM_DEF_ARCH
-#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_KM_DEF_ENV \
- CONFIG_KM_DEF_ARCH \
- "newenv=" \
- "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \
- "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \
- "unlock=yes\0" \
- ""
-
-#if defined(CONFIG_UEC_ETH)
-#define CONFIG_HAS_ETH0
-#endif
-
-#endif /* __CONFIG_KM83XX_H */
diff --git a/include/configs/km8360.h b/include/configs/km8360.h
deleted file mode 100644
index feb8a9a..0000000
--- a/include/configs/km8360.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2012
- * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
- * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* KMBEC FPGA (PRIO) */
-#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
-#define CONFIG_SYS_KMBEC_FPGA_SIZE 64
-
-#if defined CONFIG_KMETER1
-#define CONFIG_HOSTNAME "kmeter1"
-#define CONFIG_KM_BOARD_NAME "kmeter1"
-#define CONFIG_KM_DEF_NETDEV "netdev=eth2\0"
-#elif defined CONFIG_KMCOGE5NE
-#define CONFIG_HOSTNAME "kmcoge5ne"
-#define CONFIG_KM_BOARD_NAME "kmcoge5ne"
-#define CONFIG_KM_DEF_NETDEV "netdev=eth1\0"
-#define CONFIG_NAND_ECC_BCH
-#define CONFIG_NAND_KMETER1
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
-#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
-
-#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
-#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
-#else
-#error ("Board not supported")
-#endif
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_QE /* Has QE */
-#define CONFIG_MPC8360 /* MPC8360 CPU specific */
-
-/* include common defines/options for all 83xx Keymile boards */
-#include "km/km83xx-common.h"
-
-/*
- * System IO Setup
- */
-#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_CSB_TO_CLKIN_4X1 | \
- HRCWL_CORE_TO_CSB_2X1 | \
- HRCWL_CE_PLL_VCO_DIV_2 | \
- HRCWL_CE_TO_PLL_1X6)
-
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_CORE_ENABLE | \
- HRCWH_FROM_0X00000100 | \
- HRCWH_BOOTSEQ_DISABLE | \
- HRCWH_SW_WATCHDOG_DISABLE | \
- HRCWH_ROM_LOC_LOCAL_16BIT | \
- HRCWH_BIG_ENDIAN | \
- HRCWH_LALE_EARLY | \
- HRCWH_LDP_CLEAR)
-
-/**
- * DDR RAM settings
- */
-#define CONFIG_SYS_DDR_SDRAM_CFG (\
- SDRAM_CFG_SDRAM_TYPE_DDR2 | \
- SDRAM_CFG_SREN | \
- SDRAM_CFG_HSE)
-
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-
-#ifdef CONFIG_KMCOGE5NE
-/**
- * KMCOGE5NE has 512 MB RAM
- */
-#define CONFIG_SYS_DDR_CS0_CONFIG (\
- CSCONFIG_EN | \
- CSCONFIG_AP | \
- CSCONFIG_ODT_WR_ONLY_CURRENT | \
- CSCONFIG_BANK_BIT_3 | \
- CSCONFIG_ROW_BIT_13 | \
- CSCONFIG_COL_BIT_10)
-#else
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
- CSCONFIG_ROW_BIT_13 | \
- CSCONFIG_COL_BIT_10 | \
- CSCONFIG_ODT_WR_ONLY_CURRENT)
-#endif
-
-#define CONFIG_SYS_DDR_CLK_CNTL (\
- DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-
-#define CONFIG_SYS_DDR_INTERVAL (\
- (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
- (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
-
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
-
-#define CONFIG_SYS_DDRCDR (\
- DDRCDR_EN | \
- DDRCDR_Q_DRN)
-#define CONFIG_SYS_DDR_MODE 0x47860452
-#define CONFIG_SYS_DDR_MODE2 0x8080c000
-
-#define CONFIG_SYS_DDR_TIMING_0 (\
- (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
- (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
- (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
- (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
- (0 << TIMING_CFG0_WWT_SHIFT) | \
- (0 << TIMING_CFG0_RRT_SHIFT) | \
- (0 << TIMING_CFG0_WRT_SHIFT) | \
- (0 << TIMING_CFG0_RWT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
- (2 << TIMING_CFG1_WRTORD_SHIFT) | \
- (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
- (3 << TIMING_CFG1_WRREC_SHIFT) | \
- (7 << TIMING_CFG1_REFREC_SHIFT) | \
- (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
- (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
- (3 << TIMING_CFG1_PRETOACT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_2 (\
- (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
- (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
- (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
- (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
- (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
- (5 << TIMING_CFG2_CPO_SHIFT) | \
- (0 << TIMING_CFG2_ADD_LAT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-
-/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-
-/*
- * PAXE on the local bus CS3
- */
-#define CONFIG_SYS_PAXE_BASE 0xA0000000
-#define CONFIG_SYS_PAXE_SIZE 256
-
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
-
-#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
-
-#define CONFIG_SYS_BR3_PRELIM (\
- CONFIG_SYS_PAXE_BASE | \
- (1 << BR_PS_SHIFT) | \
- BR_V)
-
-#define CONFIG_SYS_OR3_PRELIM (\
- MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
- OR_GPCM_CSNT | \
- OR_GPCM_ACS_DIV2 | \
- OR_GPCM_SCY_2 | \
- OR_GPCM_TRLX | \
- OR_GPCM_EAD)
-
-#ifdef CONFIG_KMCOGE5NE
-/*
- * BFTIC3 on the local bus CS4
- */
-#define CONFIG_SYS_BFTIC3_BASE 0xB0000000
-#define CONFIG_SYS_BFTIC3_SIZE 256
-
-#define CONFIG_SYS_BR4_PRELIM (\
- CONFIG_SYS_BFTIC3_BASE |\
- (1 << BR_PS_SHIFT) | \
- BR_V)
-
-#define CONFIG_SYS_OR4_PRELIM (\
- MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\
- OR_GPCM_CSNT | \
- OR_GPCM_ACS_DIV2 |\
- OR_GPCM_SCY_2 |\
- OR_GPCM_TRLX |\
- OR_GPCM_EAD)
-#endif
-
-/*
- * MMU Setup
- */
-
-/* PAXE: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L (\
- CONFIG_SYS_PAXE_BASE | \
- BATL_PP_10 | \
- BATL_MEMCOHERENCE)
-
-#define CONFIG_SYS_IBAT5U (\
- CONFIG_SYS_PAXE_BASE | \
- BATU_BL_256M | \
- BATU_VS | \
- BATU_VP)
-
-#define CONFIG_SYS_DBAT5L (\
- CONFIG_SYS_PAXE_BASE | \
- BATL_PP_10 | \
- BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#ifdef CONFIG_KMCOGE5NE
-/* BFTIC3: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT6L (\
- CONFIG_SYS_BFTIC3_BASE | \
- BATL_PP_10 | \
- BATL_MEMCOHERENCE)
-
-#define CONFIG_SYS_IBAT6U (\
- CONFIG_SYS_BFTIC3_BASE | \
- BATU_BL_256M | \
- BATU_VS | \
- BATU_VP)
-
-#define CONFIG_SYS_DBAT6L (\
- CONFIG_SYS_BFTIC3_BASE | \
- BATL_PP_10 | \
- BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-
-/* DDR/LBC SDRAM next 256M: cacheable */
-#define CONFIG_SYS_IBAT7L (\
- CONFIG_SYS_SDRAM_BASE2 |\
- BATL_PP_10 |\
- BATL_CACHEINHIBIT |\
- BATL_GUARDEDSTORAGE)
-
-#define CONFIG_SYS_IBAT7U (\
- CONFIG_SYS_SDRAM_BASE2 |\
- BATU_BL_256M |\
- BATU_VS |\
- BATU_VP)
-/* enable POST tests */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
-#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
-#define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END
-#define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */
-#define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */
-
-#else
-#define CONFIG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#endif
-
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-#endif /* CONFIG */
diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h
new file mode 100644
index 0000000..fc78b27c
--- /dev/null
+++ b/include/configs/kmcoge5ne.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
+ * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_HOSTNAME "kmcoge5ne"
+#define CONFIG_KM_BOARD_NAME "kmcoge5ne"
+#define CONFIG_KM_DEF_NETDEV "netdev=eth1\0"
+#define CONFIG_NAND_ECC_BCH
+#define CONFIG_NAND_KMETER1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
+
+#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
+#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc8360.h"
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN 66000000
+#define CONFIG_SYS_CLK_FREQ 66000000
+#define CONFIG_83XX_PCICLK 66000000
+
+/**
+ * KMCOGE5NE has 512 MB RAM
+ */
+#define CONFIG_SYS_DDR_CS0_CONFIG (\
+ CSCONFIG_EN | \
+ CSCONFIG_AP | \
+ CSCONFIG_ODT_WR_ONLY_CURRENT | \
+ CSCONFIG_BANK_BIT_3 | \
+ CSCONFIG_ROW_BIT_13 | \
+ CSCONFIG_COL_BIT_10)
+
+/*
+ * BFTIC3 on the local bus CS4
+ */
+#define CONFIG_SYS_BFTIC3_BASE 0xB0000000
+#define CONFIG_SYS_BFTIC3_SIZE 256
+
+/* enable POST tests */
+#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
+#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
+#define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END
+#define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */
+#define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */
+
+#endif /* CONFIG */
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
new file mode 100644
index 0000000..bfa7ca2
--- /dev/null
+++ b/include/configs/kmeter1.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
+ * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_HOSTNAME "kmeter1"
+#define CONFIG_KM_BOARD_NAME "kmeter1"
+#define CONFIG_KM_DEF_NETDEV "netdev=eth2\0"
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc8360.h"
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
+ CSCONFIG_ROW_BIT_13 | \
+ CSCONFIG_COL_BIT_10 | \
+ CSCONFIG_ODT_WR_ONLY_CURRENT)
+#endif /* CONFIG */
diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h
new file mode 100644
index 0000000..67e864f
--- /dev/null
+++ b/include/configs/kmopti2.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ * Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2010-2013
+ * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
+ * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_KM_BOARD_NAME "kmopti2"
+#define CONFIG_HOSTNAME "kmopti2"
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc832x.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h
new file mode 100644
index 0000000..ba33e60
--- /dev/null
+++ b/include/configs/kmsupx5.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ * Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2010-2013
+ * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
+ * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_KM_BOARD_NAME "kmsupx5"
+#define CONFIG_HOSTNAME "kmsupx5"
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc832x.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h
new file mode 100644
index 0000000..701eb53
--- /dev/null
+++ b/include/configs/kmtegr1.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ * Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_HOSTNAME "kmtegr1"
+#define CONFIG_KM_BOARD_NAME "kmtegr1"
+#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
+#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
+
+#define CONFIG_ENV_ADDR 0xF0100000
+#define CONFIG_ENV_OFFSET 0x100000
+
+#define CONFIG_NAND_ECC_BCH
+#define CONFIG_NAND_KMETER1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc8309.h"
+
+/* must be after the include because KMBEC_FPGA is otherwise undefined */
+#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h
new file mode 100644
index 0000000..e0c907d
--- /dev/null
+++ b/include/configs/kmtepr2.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ * Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2010-2013
+ * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
+ * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_KM_BOARD_NAME "kmtepr2"
+#define CONFIG_HOSTNAME "kmtepr2"
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc832x.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h
new file mode 100644
index 0000000..6e5d507
--- /dev/null
+++ b/include/configs/kmvect1.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ * Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_HOSTNAME "kmvect1"
+#define CONFIG_KM_BOARD_NAME "kmvect1"
+/* at end of uboot partition, before env */
+#define CONFIG_SYS_QE_FW_ADDR 0xF00B0000
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc8309.h"
+
+#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
+ 0x0000c000 | \
+ MxMR_WLFx_2X)
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_MV88E6352_SWITCH
+#define CONFIG_KM_MVEXTSW_ADDR 0x10
+
+/* ethernet port connected to simple switch 88e6122 (UEC0) */
+#define CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
+#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
+
+#define CONFIG_FIXED_PHY 0xFFFFFFFF
+#define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */
+#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
+ {devnum, speed, duplex}
+#define CONFIG_SYS_FIXED_PHY_PORTS \
+ CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
+
+#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index 98f0303..3ce4b70 100644
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -12,8 +12,6 @@
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC830x 1 /* MPC830x family */
-#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
/*
* On-board devices
@@ -23,69 +21,6 @@
#define CONFIG_TSEC1
#define CONFIG_TSEC2
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
- * We choose the A type silicon as default, so the core is 400Mhz.
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_SVCOD_DIV_2 |\
- HRCWL_CSB_TO_CLKIN_4X1 |\
- HRCWL_CORE_TO_CSB_3X1)
-/*
- * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
- * in 8308's HRCWH according to the manual, but original Freescale's
- * code has them and I've expirienced some problems using the board
- * with BDI3000 attached when I've tried to set these bits to zero
- * (UART doesn't work after the 'reset run' command).
- */
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_MII |\
- HRCWH_TSEC2M_IN_MII |\
- HRCWH_BIG_ENDIAN)
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH (\
- SICRH_ESDHC_A_GPIO |\
- SICRH_ESDHC_B_GPIO |\
- SICRH_ESDHC_C_GTM |\
- SICRH_GPIO_A_TSEC2 |\
- SICRH_GPIO_B_TSEC2_TX_CLK |\
- SICRH_IEEE1588_A_GPIO |\
- SICRH_USB |\
- SICRH_GTM_GPIO |\
- SICRH_IEEE1588_B_GPIO |\
- SICRH_ETSEC2_CRS |\
- SICRH_GPIOSEL_1 |\
- SICRH_TMROBI_V3P3 |\
- SICRH_TSOBI1_V3P3 |\
- SICRH_TSOBI2_V3P3) /* 0xf577d100 */
-#define CONFIG_SYS_SICRL (\
- SICRL_SPI_PF0 |\
- SICRL_UART_PF0 |\
- SICRL_IRQ_PF0 |\
- SICRL_I2C2_PF0 |\
- SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
-
#define CONFIG_SYS_GPIO1_PRELIM
/* GPIO Default input/output settings */
#define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00
@@ -96,29 +31,15 @@
#define CONFIG_SYS_GPIO1_DAT 0x08008C00
/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
* SERDES
*/
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1 0xe3000
/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
-
-/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
| DDRCDR_PZ_LOZ \
@@ -205,13 +126,6 @@
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR 0x00040000
-
-/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
@@ -219,22 +133,6 @@
#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */
-/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_4 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512
@@ -248,33 +146,13 @@
* SJA1000 CAN controller on Local Bus
*/
#define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SJA1000_BASE \
- | BR_PS_8 /* 8 bit port size */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
- | OR_GPCM_SCY_5 \
- | OR_GPCM_EHTR_SET)
- /* 0xFFFF8052 */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_SJA1000_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
/*
* CPLD on Local Bus
*/
#define CONFIG_SYS_CPLD_BASE 0xFBFF8000
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_CPLD_BASE \
- | BR_PS_8 /* 8 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB \
- | OR_GPCM_SCY_4 \
- | OR_GPCM_EHTR_SET)
- /* 0xFFFF8042 */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_CPLD_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
/*
* Serial Port
@@ -386,52 +264,6 @@
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
- BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
* Environment Configuration
*/
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 9074be8..d2053cc 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -18,36 +18,10 @@
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_MPC834x 1 /* MPC834x family */
-#define CONFIG_MPC8349 1 /* MPC8349 specific */
/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-/*
- * The default if PCI isn't enabled, or if no PCI clk setting is given
- * is 66MHz; this is what the board defaults to when the PCI slot is
- * physically empty. The board will automatically (i.e w/o jumpers)
- * clock down to 33MHz if you insert a 33MHz PCI card.
- */
-#ifdef CONFIG_PCI_33M
-#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
-#else /* 66M */
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#ifdef CONFIG_PCI_33M
-#define CONFIG_SYS_CLK_FREQ 33000000
-#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
-#else /* 66M */
-#define CONFIG_SYS_CLK_FREQ 66000000
-#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
-#endif
-#endif
-
-#define CONFIG_SYS_IMMR 0xE0000000
-
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00100000
@@ -72,9 +46,7 @@
*/
#undef CONFIG_DDR_32BIT
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#define CONFIG_DDR_2T_TIMING
@@ -122,25 +94,6 @@
#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFF806FF7 */
-
- /* window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
@@ -170,88 +123,8 @@
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-/*
- * Local Bus LCRR and LBCR regs
- * LCRR: DLL bypass, Clock divider is 4
- * External Local Bus rate is
- * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
-#ifdef CONFIG_SYS_LB_SDRAM
-/* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR2, need:
- * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- * port-size = 32-bits = BR2[19:20] = 11
- * no parity checking = BR2[21:22] = 00
- * SDRAM for MSEL = BR2[24:26] = 011
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
- */
-
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
- | BR_PS_32 \
- | BR_MS_SDRAM \
- | BR_V)
- /* 0xF0001861 */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
-
-/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR2, need:
- * 64MB mask for AM, OR2[0:7] = 1111 1100
- * XAM, OR2[17:18] = 11
- * 9 columns OR2[19-21] = 010
- * 13 rows OR2[23-25] = 100
- * EAD set for extra time OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
- */
-
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
- | OR_SDRAM_XAM \
- | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
- | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
- | OR_SDRAM_EAD)
- /* 0xFC006901 */
-
- /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT 0x32000000
- /* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
- | LSDMR_BSMA1516 \
- | LSDMR_RFCR8 \
- | LSDMR_PRETOACT6 \
- | LSDMR_ACTTORW3 \
- | LSDMR_BL8 \
- | LSDMR_WRC3 \
- | LSDMR_CL3)
-
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
-#endif
-
/*
* Serial Port
*/
@@ -309,14 +182,6 @@
#if defined(CONFIG_PCI)
-#define PCI_64BIT
-#define PCI_ONE_PCI1
-#if defined(PCI_64BIT)
-#undef PCI_ALL_PCI1
-#undef PCI_TWO_PCI1
-#undef PCI_ONE_PCI1
-#endif
-
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
@@ -400,185 +265,14 @@
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#if 1 /*528/264*/
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X2 |\
- HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*396/132*/
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X4 |\
- HRCWL_CORE_TO_CSB_3X1)
-#elif 0 /*264/132*/
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X4 |\
- HRCWL_CORE_TO_CSB_2X1)
-#elif 0 /*132/132*/
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X4 |\
- HRCWL_CORE_TO_CSB_1X1)
-#elif 0 /*264/264 */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X4 |\
- HRCWL_CORE_TO_CSB_1X1)
-#endif
-
-#if defined(PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_64_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_32_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#endif
-
/* System IO Config */
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
- | HID0_ENABLE_INSTRUCTION_CACHE)
-
-/* #define CONFIG_SYS_HID0_FINAL (\
- HID0_ENABLE_INSTRUCTION_CACHE |\
- HID0_ENABLE_M_BIT |\
- HID0_ENABLE_ADDRESS_BROADCAST) */
-
-#define CONFIG_SYS_HID2 HID2_HBE
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* PCI @ 0x80000000 */
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT1L (0)
-#define CONFIG_SYS_IBAT1U (0)
-#define CONFIG_SYS_IBAT2L (0)
-#define CONFIG_SYS_IBAT2U (0)
-#endif
-
-#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
#endif
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index e9e264b..d1535b6 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -45,7 +45,6 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
diff --git a/include/configs/strider.h b/include/configs/strider.h
index 972543d..8b942e3 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -12,100 +12,19 @@
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC83xx 1 /* MPC83xx family */
-#define CONFIG_MPC830x 1 /* MPC830x family */
-#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
-#define CONFIG_STRIDER 1 /* STRIDER board specific */
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-/*
- * Hardware Reset Configuration Word
- * if CLKIN is 66.66MHz, then
- * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
- * We choose the A type silicon as default, so the core is 400Mhz.
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_SVCOD_DIV_2 |\
- HRCWL_CSB_TO_CLKIN_4X1 |\
- HRCWL_CORE_TO_CSB_3X1)
-/*
- * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
- * in 8308's HRCWH according to the manual, but original Freescale's
- * code has them and I've expirienced some problems using the board
- * with BDI3000 attached when I've tried to set these bits to zero
- * (UART doesn't work after the 'reset run' command).
- */
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_RL_EXT_LEGACY |\
- HRCWH_TSEC1M_IN_MII |\
- HRCWH_TSEC2M_IN_RGMII |\
- HRCWH_BIG_ENDIAN)
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH (\
- SICRH_ESDHC_A_SD |\
- SICRH_ESDHC_B_SD |\
- SICRH_ESDHC_C_SD |\
- SICRH_GPIO_A_GPIO |\
- SICRH_GPIO_B_GPIO |\
- SICRH_IEEE1588_A_GPIO |\
- SICRH_USB |\
- SICRH_GTM_GPIO |\
- SICRH_IEEE1588_B_GPIO |\
- SICRH_ETSEC2_GPIO |\
- SICRH_GPIOSEL_1 |\
- SICRH_TMROBI_V3P3 |\
- SICRH_TSOBI1_V2P5 |\
- SICRH_TSOBI2_V2P5) /* 0x0037f103 */
-#define CONFIG_SYS_SICRL (\
- SICRL_SPI_PF0 |\
- SICRL_UART_PF0 |\
- SICRL_IRQ_PF0 |\
- SICRL_I2C2_PF0 |\
- SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
* SERDES
*/
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1 0xe3000
/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
-
-/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
| DDRCDR_PZ_LOZ \
@@ -192,13 +111,6 @@
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR 0x00040000
-
-/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
@@ -208,22 +120,6 @@
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
-/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 135
@@ -231,29 +127,6 @@
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-/*
- * FPGA
- */
-#define CONFIG_SYS_FPGA0_BASE 0xE0600000
-#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
-
-/* Window base at FPGA base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
-
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_SCY_5 \
- | OR_GPCM_TRLX_CLEAR \
- | OR_GPCM_EHTR_CLEAR)
-
-#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
#define CONFIG_SYS_FPGA_DONE(k) 0x0010
#define CONFIG_SYS_FPGA_COUNT 1
@@ -547,52 +420,6 @@
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
- BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
* Environment Configuration
*/
diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
index 3e88c90..1705f9c 100644
--- a/include/configs/suvd3.h
+++ b/include/configs/suvd3.h
@@ -20,171 +20,16 @@
* High Level Configuration Options
*/
-/* This needs to be set prior to including km/km83xx-common.h */
-
-#if defined(CONFIG_SUVD3) /* SUVD3 board specific */
#define CONFIG_HOSTNAME "suvd3"
-#define CONFIG_KM_BOARD_NAME "suvd3"
-/* include common defines/options for all 8321 Keymile boards */
-#include "km/km8321-common.h"
-
-#elif defined(CONFIG_KMVECT1) /* VECT1 board specific */
-#define CONFIG_HOSTNAME "kmvect1"
-#define CONFIG_KM_BOARD_NAME "kmvect1"
-/* at end of uboot partition, before env */
-#define CONFIG_SYS_QE_FW_ADDR 0xF00B0000
-/* include common defines/options for all 8309 Keymile boards */
-#include "km/km8309-common.h"
-
-#elif defined(CONFIG_KMTEGR1) /* TEGR1 board specific */
-#define CONFIG_HOSTNAME "kmtegr1"
-#define CONFIG_KM_BOARD_NAME "kmtegr1"
-#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
-#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
-
-#define CONFIG_ENV_ADDR 0xF0100000
-#define CONFIG_ENV_OFFSET 0x100000
-
-#define CONFIG_NAND_ECC_BCH
-#define CONFIG_NAND_KMETER1
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
-
-/* include common defines/options for all 8309 Keymile boards */
-#include "km/km8309-common.h"
-/* must be after the include because KMBEC_FPGA is otherwise undefined */
-#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
-
-#else
-#error Supported boards are: SUVD3, KMVECT1, KMTEGR1
-#endif
-
-#define CONFIG_SYS_APP1_BASE 0xA0000000
-#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
-#define CONFIG_SYS_APP2_BASE 0xB0000000
-#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
-
-/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-/*
- * Init Local Bus Memory Controller:
- *
- * Bank Bus Machine PortSz Size Device
- * ---- --- ------- ------ ----- ------
- * 2 Local UPMA 16 bit 256MB APP1
- * 3 Local GPCM 16 bit 256MB APP2
- *
- */
-
-#if defined(CONFIG_SUVD3) || defined(CONFIG_KMVECT1)
-/*
- * APP1 on the local bus CS2
- */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
-
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \
- BR_PS_16 | \
- BR_MS_UPMA | \
- BR_V)
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
-
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
- BR_PS_16 | \
- BR_V)
+#define CONFIG_KM_BOARD_NAME "suvd3"
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
- OR_GPCM_CSNT | \
- OR_GPCM_ACS_DIV4 | \
- OR_GPCM_SCY_3 | \
- OR_GPCM_TRLX_SET)
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc832x.h"
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
0x0000c000 | \
MxMR_WLFx_2X)
-
-#elif defined(CONFIG_KMTEGR1)
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
- BR_PS_16 | \
- BR_MS_GPCM | \
- BR_V)
-
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
- OR_GPCM_SCY_5 | \
- OR_GPCM_TRLX_CLEAR | \
- OR_GPCM_EHTR_CLEAR)
-
-#endif /* CONFIG_KMTEGR1 */
-
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
-
-/*
- * MMU Setup
- */
-#if defined(CONFIG_SUVD3) || defined(CONFIG_KMVECT1)
-/* APP1: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#elif defined(CONFIG_KMTEGR1)
-#define CONFIG_SYS_IBAT5L (0)
-#define CONFIG_SYS_IBAT5U (0)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#endif /* CONFIG_KMTEGR1 */
-
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-
-/*
- * QE UEC ethernet configuration
- */
-#if defined(CONFIG_KMVECT1)
-#define CONFIG_MV88E6352_SWITCH
-#define CONFIG_KM_MVEXTSW_ADDR 0x10
-
-/* ethernet port connected to simple switch 88e6122 (UEC0) */
-#define CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
-
-#define CONFIG_FIXED_PHY 0xFFFFFFFF
-#define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */
-#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
- {devnum, speed, duplex}
-#define CONFIG_SYS_FIXED_PHY_PORTS \
- CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
-
-#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
-#endif /* CONFIG_KMVECT1 */
-
-#if defined(CONFIG_KMVECT1) || defined(CONFIG_KMTEGR1)
-/* ethernet port connected to piggy (UEC2) */
-#define CONFIG_HAS_ETH1
-#define CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */
-#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
-#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12
-#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR 0
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
-#endif /* CONFIG_KMVECT1 || CONFIG_KMTEGR1 */
-
#endif /* __CONFIG_H */
diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h
new file mode 100644
index 0000000..808538e
--- /dev/null
+++ b/include/configs/tuge1.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ * Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2010-2013
+ * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
+ * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_KM_BOARD_NAME "tuge1"
+#define CONFIG_HOSTNAME "tuge1"
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc832x.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h
index f22d73b..0eb673a 100644
--- a/include/configs/tuxx1.h
+++ b/include/configs/tuxx1.h
@@ -23,174 +23,17 @@
/*
* High Level Configuration Options
*/
-#if defined(CONFIG_KMSUPX5)
-#define CONFIG_KM_BOARD_NAME "kmsupx5"
-#define CONFIG_HOSTNAME "kmsupx5"
-#elif defined(CONFIG_TUGE1)
-#define CONFIG_KM_BOARD_NAME "tuge1"
-#define CONFIG_HOSTNAME "tuge1"
-#elif defined(CONFIG_TUXX1) /* TUXX1 board (tuxa1/tuda1) specific */
#define CONFIG_KM_BOARD_NAME "tuxx1"
#define CONFIG_HOSTNAME "tuxx1"
-#elif defined(CONFIG_KMOPTI2)
-#define CONFIG_KM_BOARD_NAME "kmopti2"
-#define CONFIG_HOSTNAME "kmopti2"
-#elif defined(CONFIG_KMTEPR2)
-#define CONFIG_KM_BOARD_NAME "kmtepr2"
-#define CONFIG_HOSTNAME "kmtepr2"
-#else
-#error ("Board not supported")
-#endif
-/* include common defines/options for all 8321 Keymile boards */
-#include "km/km8321-common.h"
-
-#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */
-#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
-#if defined(CONFIG_TUXX1) || defined(CONFIG_KMOPTI2) || defined(CONFIG_KMTEPR2)
-#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */
-#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
-#endif
-
-/*
- * Init Local Bus Memory Controller:
- * Device on board
- * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2
- * -----------------------------------------------------------------------------
- * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE
- * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit)
- *
- * Device on board (continued)
- * Bank Bus Machine PortSz Size KMTEPR2
- * -----------------------------------------------------------------------------
- * 2 Local GPCM 8 bit 256MB NVRAM
- * 3 Local GPCM 8 bit 256MB TEP2 (16 bit)
- */
-
-#if defined(CONFIG_KMTEPRO2)
-/*
- * Configuration for C2 (NVRAM) on the local bus
- */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \
- BR_PS_8 | \
- BR_MS_GPCM | \
- BR_V)
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
- OR_GPCM_CSNT | \
- OR_GPCM_ACS_DIV2 | \
- OR_GPCM_XACS | \
- OR_GPCM_SCY_2 | \
- OR_GPCM_TRLX_SET | \
- OR_GPCM_EHTR_SET | \
- OR_GPCM_EAD)
-#else
-/*
- * Configuration for C2 on the local bus
- */
-/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
-/* Window size: 256 MB */
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
-
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \
- BR_PS_8 | \
- BR_MS_GPCM | \
- BR_V)
-
-#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
- OR_GPCM_CSNT | \
- OR_GPCM_ACS_DIV4 | \
- OR_GPCM_SCY_2 | \
- OR_GPCM_TRLX_SET | \
- OR_GPCM_EHTR_CLEAR | \
- OR_GPCM_EAD)
-#endif
-
-#if defined(CONFIG_TUXX1)
-/*
- * Configuration for C3 on the local bus
- */
-/* Access window base at PINC3 base */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
-/* Window size: 256 MB */
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
-
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
- BR_PS_8 | \
- BR_MS_GPCM | \
- BR_V)
-
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
- OR_GPCM_CSNT | \
- OR_GPCM_ACS_DIV2 | \
- OR_GPCM_SCY_2 | \
- OR_GPCM_TRLX_SET | \
- OR_GPCM_EHTR_CLEAR)
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc832x.h"
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
0x0000c000 | \
MxMR_WLFx_2X)
-#endif
-
-#if defined(CONFIG_KMOPTI2) || defined(CONFIG_KMTEPR2)
-/*
- * Configuration for C3 on the local bus
- */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
- BR_PS_16 | \
- BR_MS_GPCM | \
- BR_V)
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
- OR_GPCM_SCY_4 | \
- OR_GPCM_TRLX_CLEAR | \
- OR_GPCM_EHTR_CLEAR)
-#endif
-
-/*
- * MMU Setup
- */
-/* APP1: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \
- BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-/* 512M should also include APP2... */
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \
- BATU_BL_256M | \
- BATU_VS | \
- BATU_VP)
-#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \
- BATL_PP_RW | \
- BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#if defined(CONFIG_TUGE1) || defined(CONFIG_KMSUPX5)
-#define CONFIG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#else
-/* APP2: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \
- BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \
- BATU_BL_256M | \
- BATU_VS | \
- BATU_VP)
-#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \
- BATL_PP_RW | \
- BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-#endif
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#endif /* __CONFIG_H */
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 85f678e..66f771d 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -16,8 +16,6 @@
* High Level Configuration Options
*/
#define CONFIG_E300 1
-#define CONFIG_MPC831x 1
-#define CONFIG_MPC8313 1
#define CONFIG_PCI_INDIRECT_BRIDGE 1
#define CONFIG_FSL_ELBC 1
@@ -26,18 +24,9 @@
* On-board devices
*
*/
-#define CONFIG_83XX_CLKIN 32000000 /* in Hz */
-
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-#define CONFIG_SYS_IMMR 0xE0000000
-
#define CONFIG_SYS_MEMTEST_START 0x00001000
#define CONFIG_SYS_MEMTEST_END 0x07000000
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */
-
/*
* Device configurations
*/
@@ -45,9 +34,7 @@
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
/*
* Manually set up DDR parameters, as this board does not
@@ -117,21 +104,6 @@
#define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
-#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV4 \
- | OR_GPCM_SCY_5 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EAD)
- /* 0xfe000c55 */
-
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
-
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */
@@ -157,16 +129,6 @@
#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LCRR_EADC LCRR_EADC_3
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-
-#define CONFIG_SYS_LBC_LBCR 0x00040000
-
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
-/*
* NAND settings
*/
#define CONFIG_SYS_NAND_BASE 0x61000000
@@ -174,58 +136,13 @@
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
-#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
- | BR_PS_8 \
- | BR_DECC_CHK_GEN \
- | BR_MS_FCM \
- | BR_V) /* valid */
- /* 0x61000c21 */
-#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
- | OR_FCM_BCTLD \
- | OR_FCM_CHT \
- | OR_FCM_SCY_2 \
- | OR_FCM_RST \
- | OR_FCM_TRLX)
- /* 0xffff90ac */
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
+/* Still needed for spl_minimal.c */
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
-/* CS2 NvRAM */
-#define CONFIG_SYS_BR2_PRELIM (0x60000000 \
- | BR_PS_8 \
- | BR_V)
- /* 0x60000801 */
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_3 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xfffe0937 */
-/* local bus read write buffer mapping SRAM@0x64000000 */
-#define CONFIG_SYS_BR3_PRELIM (0x62000000 \
- | BR_PS_16 \
- | BR_V)
- /* 0x62001001 */
-
-#define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xfe0009f7 */
/*
* Serial Port
@@ -315,25 +232,6 @@
/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-/* 0x64050000 */
-#define CONFIG_SYS_HRCW_LOW (\
- 0x20000000 /* reserved, must be set */ |\
- HRCWL_DDRCM |\
- HRCWL_CSB_TO_CLKIN_4X1 | \
- HRCWL_CORE_TO_CSB_2_5X1)
-
-/* 0xa0600004 */
-#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
- HRCWH_PCI_ARBITER_ENABLE | \
- HRCWH_CORE_ENABLE | \
- HRCWH_FROM_0X00000100 | \
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT | \
- HRCWH_TSEC1M_IN_MII | \
- HRCWH_BIG_ENDIAN | \
- HRCWH_LALE_EARLY)
-
/* System IO Config */
#define CONFIG_SYS_SICRH (0x01000000 | \
SICRH_ETSEC2_B | \
@@ -353,84 +251,6 @@
SICRL_ETSEC2_A)
/* 0x33fc0003) */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-
-#define CONFIG_SYS_HID2 HID2_HBE
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-#if defined(CONFIG_PCI)
-/* PCI @ 0x80000000 */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT1L (0)
-#define CONFIG_SYS_IBAT1U (0)
-#define CONFIG_SYS_IBAT2L (0)
-#define CONFIG_SYS_IBAT2U (0)
-#endif
-
-/* PCI2 not supported on 8313 */
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* FPGA, SRAM, NAND @ 0x60000000 */
-#define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
#define CONFIG_NETDEV eth0
#define CONFIG_HOSTNAME "ve8313"
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 805f7d3..1c3430d 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -18,42 +18,13 @@
#define __CONFIG_H
/*
- * Top level Makefile configuration choices
- */
-#ifdef CONFIG_CADDY2
-#define VME_CADDY2
-#endif
-
-/*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_MPC834x 1 /* MPC834x family */
-#define CONFIG_MPC8349 1 /* MPC8349 specific */
-#define CONFIG_VME8349 1 /* ESD VME8349 board specific */
/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-#define CONFIG_PCI_66M
-#ifdef CONFIG_PCI_66M
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#else
-#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#ifdef CONFIG_PCI_66M
-#define CONFIG_SYS_CLK_FREQ 66000000
-#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
-#else
-#define CONFIG_SYS_CLK_FREQ 33000000
-#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
-#endif
-#endif
-
-#define CONFIG_SYS_IMMR 0xE0000000
-
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00100000
@@ -80,9 +51,7 @@
*/
#undef CONFIG_DDR_32BIT
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#define CONFIG_DDR_2T_TIMING
@@ -94,59 +63,12 @@
/*
* FLASH on the Local Bus
*/
-#ifdef VME_CADDY2
-#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
- BR_PS_16 | /* 16bit */ \
- BR_MS_GPCM | /* MSEL = GPCM */ \
- BR_V) /* valid */
-
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xffc06ff7 */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB)
-#else
#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
- BR_PS_16 | /* 16bit */ \
- BR_MS_GPCM | /* MSEL = GPCM */ \
- BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xf8006ff7 */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
-#endif
#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
- | BR_PS_32 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0xF0001801 */
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \
- | OR_GPCM_SETA)
- /* 0xfffc0208 */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
+
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
@@ -174,15 +96,6 @@
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
-/*
- * Local Bus LCRR and LBCR regs
- * LCRR: no DLL bypass, Clock divider is 4
- * External Local Bus rate is
- * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
/*
@@ -244,14 +157,6 @@
#if defined(CONFIG_PCI)
-#define PCI_64BIT
-#define PCI_ONE_PCI1
-#if defined(PCI_64BIT)
-#undef PCI_ALL_PCI1
-#undef PCI_TWO_PCI1
-#undef PCI_ONE_PCI1
-#endif
-
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
@@ -341,51 +246,10 @@
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN |\
- HRCWL_VCO_1X2 |\
- HRCWL_CORE_TO_CSB_2X1)
-
-#if defined(PCI_64BIT)
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_64_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_32_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#endif
-
/* System IO Config */
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-
-#define CONFIG_SYS_HID2 HID2_HBE
-
#define CONFIG_SYS_GPIO1_PRELIM
#define CONFIG_SYS_GPIO1_DIR 0x00100000
#define CONFIG_SYS_GPIO1_DAT 0x00100000
@@ -394,84 +258,10 @@
#define CONFIG_SYS_GPIO2_DIR 0x78900000
#define CONFIG_SYS_GPIO2_DAT 0x70100000
-#define CONFIG_HIGH_BATS /* High BATs supported */
-
-/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-
-/* PCI @ 0x80000000 */
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT1L (0)
-#define CONFIG_SYS_IBAT1U (0)
-#define CONFIG_SYS_IBAT2L (0)
-#define CONFIG_SYS_IBAT2U (0)
#endif
-#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
-#endif
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
- BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
- BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#if (CONFIG_SYS_DDR_SIZE == 512)
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
- BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
- BATU_BL_256M | BATU_VS | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#endif
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h
index 2d2a87a..1ef803b 100644
--- a/include/configs/xpedite517x.h
+++ b/include/configs/xpedite517x.h
@@ -17,7 +17,6 @@
#define CONFIG_SYS_FORM_3U_VPX 1
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
#define CONFIG_ALTIVEC 1
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index db4424d..6d38a83 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -7,6 +7,7 @@
#ifndef __GDSYS_FPGA_H
#define __GDSYS_FPGA_H
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
int init_func_fpga(void);
enum {
@@ -33,6 +34,7 @@
&fpga_ptr[ix]->fld, \
offsetof(struct ihs_fpga, fld), \
val)
+#endif
struct ihs_gpio {
u16 read;
@@ -86,89 +88,14 @@
};
#endif
-#ifdef CONFIG_IO
+#if defined(CONFIG_TARGET_HRCON) || defined(CONFIG_STRIDER_CON_DP)
struct ihs_fpga {
u16 reflection_low; /* 0x0000 */
u16 versions; /* 0x0002 */
- u16 fpga_features; /* 0x0004 */
- u16 fpga_version; /* 0x0006 */
- u16 reserved_0[5]; /* 0x0008 */
- u16 quad_serdes_reset; /* 0x0012 */
- u16 reserved_1[8181]; /* 0x0014 */
- u16 reflection_high; /* 0x3ffe */
-};
-#endif
-
-#ifdef CONFIG_IO64
-struct ihs_fpga_channel {
- u16 status_int;
- u16 config_int;
- u16 switch_connect_config;
- u16 tx_destination;
-};
-
-struct ihs_fpga_hicb {
- u16 status_int;
- u16 config_int;
-};
-
-struct ihs_fpga {
- u16 reflection_low; /* 0x0000 */
- u16 versions; /* 0x0002 */
- u16 fpga_features; /* 0x0004 */
- u16 fpga_version; /* 0x0006 */
- u16 reserved_0[5]; /* 0x0008 */
- u16 quad_serdes_reset; /* 0x0012 */
- u16 reserved_1[502]; /* 0x0014 */
- struct ihs_fpga_channel ch[32]; /* 0x0400 */
- struct ihs_fpga_channel hicb_ch[32]; /* 0x0500 */
- u16 reserved_2[7487]; /* 0x0580 */
- u16 reflection_high; /* 0x3ffe */
-};
-#endif
-
-#ifdef CONFIG_IOCON
-struct ihs_fpga {
- u16 reflection_low; /* 0x0000 */
- u16 versions; /* 0x0002 */
u16 fpga_version; /* 0x0004 */
u16 fpga_features; /* 0x0006 */
u16 reserved_0[1]; /* 0x0008 */
u16 top_interrupt; /* 0x000a */
- u16 reserved_1[4]; /* 0x000c */
- struct ihs_gpio gpio; /* 0x0014 */
- u16 mpc3w_control; /* 0x001a */
- u16 reserved_2[2]; /* 0x001c */
- struct ihs_io_ep ep; /* 0x0020 */
- u16 reserved_3[9]; /* 0x002e */
- struct ihs_i2c i2c0; /* 0x0040 */
- u16 reserved_4[10]; /* 0x004c */
- u16 mc_int; /* 0x0060 */
- u16 mc_int_en; /* 0x0062 */
- u16 mc_status; /* 0x0064 */
- u16 mc_control; /* 0x0066 */
- u16 mc_tx_data; /* 0x0068 */
- u16 mc_tx_address; /* 0x006a */
- u16 mc_tx_cmd; /* 0x006c */
- u16 mc_res; /* 0x006e */
- u16 mc_rx_cmd_status; /* 0x0070 */
- u16 mc_rx_data; /* 0x0072 */
- u16 reserved_5[69]; /* 0x0074 */
- u16 reflection_high; /* 0x00fe */
- struct ihs_osd osd0; /* 0x0100 */
- u16 reserved_6[889]; /* 0x010e */
- u16 videomem0[2048]; /* 0x0800 */
-};
-#endif
-
-#if defined(CONFIG_HRCON) || defined(CONFIG_STRIDER_CON_DP)
-struct ihs_fpga {
- u16 reflection_low; /* 0x0000 */
- u16 versions; /* 0x0002 */
- u16 fpga_version; /* 0x0004 */
- u16 fpga_features; /* 0x0006 */
- u16 reserved_0[1]; /* 0x0008 */
- u16 top_interrupt; /* 0x000a */
u16 reserved_1[2]; /* 0x000c */
u16 control; /* 0x0010 */
u16 extended_control; /* 0x0012 */
@@ -270,25 +197,4 @@
};
#endif
-#ifdef CONFIG_DLVISION_10G
-struct ihs_fpga {
- u16 reflection_low; /* 0x0000 */
- u16 versions; /* 0x0002 */
- u16 fpga_version; /* 0x0004 */
- u16 fpga_features; /* 0x0006 */
- u16 reserved_0[10]; /* 0x0008 */
- u16 extended_interrupt; /* 0x001c */
- u16 reserved_1[29]; /* 0x001e */
- u16 mpc3w_control; /* 0x0058 */
- u16 reserved_2[3]; /* 0x005a */
- struct ihs_i2c i2c0; /* 0x0060 */
- u16 reserved_3[2]; /* 0x006c */
- struct ihs_i2c i2c1; /* 0x0070 */
- u16 reserved_4[194]; /* 0x007c */
- struct ihs_osd osd0; /* 0x0200 */
- u16 reserved_5[761]; /* 0x020e */
- u16 videomem0[2048]; /* 0x0800 */
-};
-#endif
-
#endif
diff --git a/include/linux/immap_qe.h b/include/linux/immap_qe.h
index 5180009..022771f 100644
--- a/include/linux/immap_qe.h
+++ b/include/linux/immap_qe.h
@@ -12,11 +12,11 @@
#define __IMMAP_QE_H__
#ifdef CONFIG_MPC83xx
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
#define MAX_QE_RISC 2
#define QE_NUM_OF_SNUM 28
-#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC832X) || defined(CONFIG_ARCH_MPC8309)
#define QE_MURAM_SIZE 0x4000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index a4c5bd3..c2a1853 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -55,7 +55,7 @@
#define SPRIDR_PARTID 0xFFFF0000 /* Part Id */
#define SPRIDR_REVID 0x0000FFFF /* Revision Id */
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
#define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8)
#define REVID_MINOR(spridr) (spridr & 0x000000FF)
#else
@@ -108,7 +108,7 @@
#define SPCR_COREPR 0x00300000
#define SPCR_COREPR_SHIFT (31-11)
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
/* SPCR bits - MPC8349 specific */
/* TSEC1 data priority */
#define SPCR_TSEC1DP 0x00003000
@@ -129,9 +129,9 @@
#define SPCR_TSEC2EP 0x00000003
#define SPCR_TSEC2EP_SHIFT (31-31)
-#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC837x)
-/* SPCR bits - MPC8308, MPC831x and MPC837x specific */
+#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
+/* SPCR bits - MPC8308, MPC831x and MPC837X specific */
/* TSEC data priority */
#define SPCR_TSECDP 0x00003000
#define SPCR_TSECDP_SHIFT (31-19)
@@ -145,7 +145,7 @@
/* SICRL/H - System I/O Configuration Register Low/High
*/
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
/* SICRL bits - MPC8349 specific */
#define SICRL_LDP_A 0x80000000
#define SICRL_USB1 0x40000000
@@ -191,7 +191,7 @@
#define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001
-#elif defined(CONFIG_MPC8360)
+#elif defined(CONFIG_ARCH_MPC8360)
/* SICRL bits - MPC8360 specific */
#define SICRL_LDP_A 0xC0000000
#define SICRL_LCLK_1 0x10000000
@@ -208,7 +208,7 @@
#define SICRH_UC2E1OBI 0x00000002
#define SICRH_UC2E2OBI 0x00000001
-#elif defined(CONFIG_MPC832x)
+#elif defined(CONFIG_ARCH_MPC832X)
/* SICRL bits - MPC832x specific */
#define SICRL_LDP_LCS_A 0x80000000
#define SICRL_IRQ_CKS 0x20000000
@@ -216,7 +216,7 @@
#define SICRL_URT_CTPR 0x06000000
#define SICRL_IRQ_CTPR 0x00C00000
-#elif defined(CONFIG_MPC8313)
+#elif defined(CONFIG_ARCH_MPC8313)
/* SICRL bits - MPC8313 specific */
#define SICRL_LBC 0x30000000
#define SICRL_UART 0x0C000000
@@ -248,7 +248,7 @@
#define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001
-#elif defined(CONFIG_MPC8315)
+#elif defined(CONFIG_ARCH_MPC8315)
/* SICRL bits - MPC8315 specific */
#define SICRL_DMA_CH0 0xc0000000
#define SICRL_DMA_SPI 0x30000000
@@ -283,8 +283,8 @@
#define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001
-#elif defined(CONFIG_MPC837x)
-/* SICRL bits - MPC837x specific */
+#elif defined(CONFIG_ARCH_MPC837X)
+/* SICRL bits - MPC837X specific */
#define SICRL_USB_A 0xC0000000
#define SICRL_USB_B 0x30000000
#define SICRL_USB_B_SD 0x20000000
@@ -314,7 +314,7 @@
#define SICRL_LDP_A 0x00000002
#define SICRL_LDP_B 0x00000001
-/* SICRH bits - MPC837x specific */
+/* SICRH bits - MPC837X specific */
#define SICRH_DDR 0x80000000
#define SICRH_TSEC1_A 0x10000000
#define SICRH_TSEC1_B 0x08000000
@@ -336,7 +336,7 @@
#define SICRH_SPI 0x00000003
#define SICRH_SPI_SD 0x00000001
-#elif defined(CONFIG_MPC8308)
+#elif defined(CONFIG_ARCH_MPC8308)
/* SICRL bits - MPC8308 specific */
#define SICRL_SPI_PF0 (0 << 28)
#define SICRL_SPI_PF1 (1 << 28)
@@ -384,7 +384,7 @@
#define SICRH_TSOBI2_V3P3 (0 << 0)
#define SICRH_TSOBI2_V2P5 (1 << 0)
-#elif defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC8309)
/* SICR_1 */
#define SICR_1_UART1_UART1S (0 << (30-2))
#define SICR_1_UART1_UART1RTS (1 << (30-2))
@@ -593,7 +593,7 @@
#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
#define HRCWL_CORE_TO_CSB_3X1 0x00060000
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC832X)
#define HRCWL_CEVCOD 0x000000C0
#define HRCWL_CEVCOD_SHIFT 6
#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000
@@ -639,7 +639,7 @@
#define HRCWL_CE_TO_PLL_1X30 0x0000001E
#define HRCWL_CE_TO_PLL_1X31 0x0000001F
-#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
+#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315)
#define HRCWL_SVCOD 0x30000000
#define HRCWL_SVCOD_SHIFT 28
#define HRCWL_SVCOD_DIV_2 0x00000000
@@ -647,14 +647,14 @@
#define HRCWL_SVCOD_DIV_8 0x20000000
#define HRCWL_SVCOD_DIV_1 0x30000000
-#elif defined(CONFIG_MPC837x)
+#elif defined(CONFIG_ARCH_MPC837X)
#define HRCWL_SVCOD 0x30000000
#define HRCWL_SVCOD_SHIFT 28
#define HRCWL_SVCOD_DIV_4 0x00000000
#define HRCWL_SVCOD_DIV_8 0x10000000
#define HRCWL_SVCOD_DIV_2 0x20000000
#define HRCWL_SVCOD_DIV_1 0x30000000
-#elif defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC8309)
#define HRCWL_CEVCOD 0x000000C0
#define HRCWL_CEVCOD_SHIFT 6
@@ -720,7 +720,7 @@
#define HRCWH_PCI_HOST_SHIFT 31
#define HRCWH_PCI_AGENT 0x00000000
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
#define HRCWH_32_BIT_PCI 0x00000000
#define HRCWH_64_BIT_PCI 0x40000000
#endif
@@ -731,11 +731,11 @@
#define HRCWH_PCI_ARBITER_DISABLE 0x00000000
#define HRCWH_PCI_ARBITER_ENABLE 0x20000000
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
-#elif defined(CONFIG_MPC8360)
+#elif defined(CONFIG_ARCH_MPC8360)
#define HRCWH_PCICKDRV_DISABLE 0x00000000
#define HRCWH_PCICKDRV_ENABLE 0x10000000
#endif
@@ -755,18 +755,18 @@
#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
#define HRCWH_ROM_LOC_PCI1 0x00100000
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
#define HRCWH_ROM_LOC_PCI2 0x00200000
#endif
-#if defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC837X)
#define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000
#endif
#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
@@ -790,7 +790,7 @@
#define HRCWH_TSEC2M_IN_SGMII 0x00001800
#endif
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
#define HRCWH_TSEC1M_IN_RGMII 0x00000000
#define HRCWH_TSEC1M_IN_RTBI 0x00004000
#define HRCWH_TSEC1M_IN_GMII 0x00008000
@@ -801,7 +801,7 @@
#define HRCWH_TSEC2M_IN_TBI 0x00003000
#endif
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000
#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010
#endif
@@ -818,8 +818,8 @@
/*
* RSR - Reset Status Register
*/
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
- defined(CONFIG_MPC837x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+ defined(CONFIG_ARCH_MPC837X)
#define RSR_RSTSRC 0xF0000000 /* Reset source */
#define RSR_RSTSRC_SHIFT 28
#else
@@ -937,8 +937,8 @@
#define SCCR_PCICM 0x00010000
#define SCCR_PCICM_SHIFT 16
-#if defined(CONFIG_MPC834x)
-/* SCCR bits - MPC834x specific */
+#if defined(CONFIG_ARCH_MPC834X)
+/* SCCR bits - MPC834X specific */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
#define SCCR_TSEC1CM_0 0x00000000
@@ -965,7 +965,7 @@
#define SCCR_USBCM_2 0x00A00000
#define SCCR_USBCM_3 0x00F00000
-#elif defined(CONFIG_MPC8313)
+#elif defined(CONFIG_ARCH_MPC8313)
/* TSEC1 bits are for TSEC2 as well */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
@@ -986,7 +986,7 @@
#define SCCR_USBDRCM_2 0x00200000
#define SCCR_USBDRCM_3 0x00300000
-#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
+#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315)
/* SCCR bits - MPC8315/MPC8308 specific */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
@@ -1032,8 +1032,8 @@
#define SCCR_TDMCM_2 0x00000020
#define SCCR_TDMCM_3 0x00000030
-#elif defined(CONFIG_MPC837x)
-/* SCCR bits - MPC837x specific */
+#elif defined(CONFIG_ARCH_MPC837X)
+/* SCCR bits - MPC837X specific */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
#define SCCR_TSEC1CM_0 0x00000000
@@ -1071,7 +1071,7 @@
#define SCCR_SATACM_1 0x00000055
#define SCCR_SATACM_2 0x000000aa
#define SCCR_SATACM_3 0x000000ff
-#elif defined(CONFIG_MPC8309)
+#elif defined(CONFIG_ARCH_MPC8309)
/* SCCR bits - MPC8309 specific */
#define SCCR_SDHCCM 0x0c000000
#define SCCR_SDHCCM_SHIFT 26
@@ -1117,7 +1117,7 @@
*/
#define CSCONFIG_EN 0x80000000
#define CSCONFIG_AP 0x00800000
-#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X)
#define CSCONFIG_ODT_RD_NEVER 0x00000000
#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
@@ -1126,10 +1126,10 @@
#define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000
#define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000
#define CSCONFIG_ODT_WR_ALL 0x00040000
-#elif defined(CONFIG_MPC832x)
+#elif defined(CONFIG_ARCH_MPC832X)
#define CSCONFIG_ODT_RD_CFG 0x00400000
#define CSCONFIG_ODT_WR_CFG 0x00040000
-#elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x)
+#elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC837X)
#define CSCONFIG_ODT_RD_NEVER 0x00000000
#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
@@ -1239,14 +1239,14 @@
#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
#define SDRAM_CFG_DYN_PWR 0x00200000
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
#define SDRAM_CFG_DBW_MASK 0x00180000
#define SDRAM_CFG_DBW_16 0x00100000
#define SDRAM_CFG_DBW_32 0x00080000
#else
#define SDRAM_CFG_32_BE 0x00080000
#endif
-#if !defined(CONFIG_MPC8308)
+#if !defined(CONFIG_ARCH_MPC8308)
#define SDRAM_CFG_8_BE 0x00040000
#endif
#define SDRAM_CFG_NCAP 0x00020000
diff --git a/include/post.h b/include/post.h
index 08a771e..eb218ac 100644
--- a/include/post.h
+++ b/include/post.h
@@ -21,7 +21,7 @@
#define _POST_WORD_ADDR CONFIG_SYS_POST_WORD_ADDR
#else
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_ARCH_MPC8360)
#include <linux/immap_qe.h>
#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)
diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h
index e4579a5..efb2eec 100644
--- a/include/usb/ehci-ci.h
+++ b/include/usb/ehci-ci.h
@@ -147,7 +147,7 @@
#if defined(CONFIG_MPC83xx)
#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR
-#if defined(CONFIG_MPC834x)
+#if defined(CONFIG_ARCH_MPC834X)
#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR
#else
#define CONFIG_SYS_FSL_USB2_ADDR 0
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index b16bc6a..5ec4ffb 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -733,7 +733,6 @@
CONFIG_HDMI_ENCODER_I2C_ADDR
CONFIG_HETROGENOUS_CLUSTERS
CONFIG_HIDE_LOGO_VERSION
-CONFIG_HIGH_BATS
CONFIG_HIKEY_GPIO
CONFIG_HITACHI_SX14
CONFIG_HOSTNAME
@@ -881,7 +880,6 @@
CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL
CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA
CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP
-CONFIG_HRCON
CONFIG_HRCON_DH
CONFIG_HRCON_FANS
CONFIG_HSMMC2_8BIT
@@ -1220,23 +1218,6 @@
CONFIG_MMC_SUNXI_SLOT
CONFIG_MMU
CONFIG_MONITOR_IS_IN_RAM
-CONFIG_MPC8308
-CONFIG_MPC8309
-CONFIG_MPC830x
-CONFIG_MPC8313
-CONFIG_MPC8313ERDB
-CONFIG_MPC8315
-CONFIG_MPC8315ERDB
-CONFIG_MPC831x
-CONFIG_MPC832XEMDS
-CONFIG_MPC832x
-CONFIG_MPC8349
-CONFIG_MPC8349ITX
-CONFIG_MPC834x
-CONFIG_MPC8360
-CONFIG_MPC837XEMDS
-CONFIG_MPC837XERDB
-CONFIG_MPC837x
CONFIG_MPC83XX_GPIO
CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION
CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN
@@ -1913,7 +1894,6 @@
CONFIG_STATIC_BOARD_REV
CONFIG_STD_DEVICES_SETTINGS
CONFIG_STM32_FLASH
-CONFIG_STRIDER
CONFIG_STRIDER_CON
CONFIG_STRIDER_CON_DP
CONFIG_STRIDER_CPU
@@ -1939,10 +1919,6 @@
CONFIG_SYS_66MHZ
CONFIG_SYS_8313ERDB_BROKEN_PMC
CONFIG_SYS_83XX_DDR_USES_CS0
-CONFIG_SYS_ACR_APARK
-CONFIG_SYS_ACR_PARKM
-CONFIG_SYS_ACR_PIPE_DEP
-CONFIG_SYS_ACR_RPTCNT
CONFIG_SYS_ADDRESS_MAP_A
CONFIG_SYS_ADV7611_I2C
CONFIG_SYS_ALT_BOOT
@@ -1959,10 +1935,6 @@
CONFIG_SYS_AMASK5
CONFIG_SYS_AMASK6
CONFIG_SYS_AMASK7
-CONFIG_SYS_APP1_BASE
-CONFIG_SYS_APP1_SIZE
-CONFIG_SYS_APP2_BASE
-CONFIG_SYS_APP2_SIZE
CONFIG_SYS_ARM_CACHE_WRITETHROUGH
CONFIG_SYS_AT91_CPU_NAME
CONFIG_SYS_AT91_MAIN_CLOCK
@@ -2278,7 +2250,6 @@
CONFIG_SYS_DDRD
CONFIG_SYS_DDRTC
CONFIG_SYS_DDRUA
-CONFIG_SYS_DDR_BASE
CONFIG_SYS_DDR_BLOCK1_SIZE
CONFIG_SYS_DDR_BLOCK2_BASE
CONFIG_SYS_DDR_CDR_1
@@ -2952,9 +2923,6 @@
CONFIG_SYS_GPSR3_VAL
CONFIG_SYS_HALT_BEFOR_RAM_JUMP
CONFIG_SYS_HELP_CMD_WIDTH
-CONFIG_SYS_HID0_FINAL
-CONFIG_SYS_HID0_INIT
-CONFIG_SYS_HID2
CONFIG_SYS_HIGH
CONFIG_SYS_HMI_BASE
CONFIG_SYS_HOSTNAME
@@ -3228,27 +3196,8 @@
CONFIG_SYS_LBC_SDRAM_BASE
CONFIG_SYS_LBC_SDRAM_BASE_PHYS
CONFIG_SYS_LBC_SDRAM_SIZE
-CONFIG_SYS_LBLAWAR0_PRELIM
-CONFIG_SYS_LBLAWAR1_PRELIM
-CONFIG_SYS_LBLAWAR2_PRELIM
-CONFIG_SYS_LBLAWAR3_PRELIM
-CONFIG_SYS_LBLAWAR4_PRELIM
-CONFIG_SYS_LBLAWAR5_PRELIM
-CONFIG_SYS_LBLAWAR6_PRELIM
-CONFIG_SYS_LBLAWAR7_PRELIM
-CONFIG_SYS_LBLAWBAR0_PRELIM
-CONFIG_SYS_LBLAWBAR1_PRELIM
-CONFIG_SYS_LBLAWBAR2_PRELIM
-CONFIG_SYS_LBLAWBAR3_PRELIM
-CONFIG_SYS_LBLAWBAR4_PRELIM
-CONFIG_SYS_LBLAWBAR5_PRELIM
-CONFIG_SYS_LBLAWBAR6_PRELIM
-CONFIG_SYS_LBLAWBAR7_PRELIM
CONFIG_SYS_LB_SDRAM
CONFIG_SYS_LCD_BASE
-CONFIG_SYS_LCRR_CLKDIV
-CONFIG_SYS_LCRR_DBYP
-CONFIG_SYS_LCRR_EADC
CONFIG_SYS_LDB_CLOCK
CONFIG_SYS_LDSCRIPT
CONFIG_SYS_LED_BASE
@@ -4128,7 +4077,6 @@
CONFIG_SYS_SPCR_OPT
CONFIG_SYS_SPCR_TSEC1EP
CONFIG_SYS_SPCR_TSEC2EP
-CONFIG_SYS_SPCR_TSECEP
CONFIG_SYS_SPD_BUS_NUM
CONFIG_SYS_SPI0
CONFIG_SYS_SPI0_NUM_CS