// SPDX-License-Identifier: GPL-2.0+
/*
 * Xilinx CSE NOR board DTS
 *
 * Copyright (C) 2018 Xilinx, Inc.
 */
/dts-v1/;
#include "zynq-7000.dtsi"

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Zynq CSE NOR Board";
	compatible = "xlnx,zynq-cse-nor", "xlnx,zynq-7000";

	aliases {
		serial0 = &dcc;
	};

	memory@fffc0000 {
		device_type = "memory";
		reg = <0xFFFC0000 0x40000>;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	dcc: dcc {
		compatible = "arm,dcc";
		status = "disabled";
		u-boot,dm-pre-reloc;
	};

	amba: amba {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;
		ranges;

		intc: interrupt-controller@f8f01000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0xF8F01000 0x1000>,
			      <0xF8F00100 0x100>;
		};

		slcr: slcr@f8000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
			reg = <0xF8000000 0x1000>;
			ranges;
			clkc: clkc@100 {
				#clock-cells = <1>;
				compatible = "xlnx,ps7-clkc";
				fclk-enable = <0xf>;
				clock-output-names = "armpll", "ddrpll",
						"iopll", "cpu_6or4x",
						"cpu_3or2x", "cpu_2x", "cpu_1x",
						"ddr2x", "ddr3x", "dci",
						"lqspi", "smc", "pcap", "gem0",
						"gem1", "fclk0", "fclk1",
						"fclk2", "fclk3", "can0",
						"can1", "sdio0", "sdio1",
						"uart0", "uart1", "spi0",
						"spi1", "dma", "usb0_aper",
						"usb1_aper", "gem0_aper",
						"gem1_aper", "sdio0_aper",
						"sdio1_aper", "spi0_aper",
						"spi1_aper", "can0_aper",
						"can1_aper", "i2c0_aper",
						"i2c1_aper", "uart0_aper",
						"uart1_aper", "gpio_aper",
						"lqspi_aper", "smc_aper",
						"swdt", "dbg_trc", "dbg_apb";
				reg = <0x100 0x100>;
			};
		};
	};

};

&dcc {
	status = "okay";
};