diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index f3cd4a8..516c14e 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -51,6 +51,9 @@
 #define ARC_AUX_DCCM_BASE	0x18	/* DCCM Base Addr ARCv2 */
 #define ARC_AUX_ICCM_BASE	0x208	/* ICCM Base Addr ARCv2 */
 
+/* CSM auxiliary registers */
+#define ARC_AUX_CSM_ENABLE	0x9A0
+
 /* Timer related auxiliary registers */
 #define ARC_AUX_TIMER0_CNT	0x21	/* Timer 0 count */
 #define ARC_AUX_TIMER0_CTRL	0x22	/* Timer 0 control */
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index b25b133..2cbb59d 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -80,6 +80,7 @@
 	u32_env nvlim;
 	u32_env icache;
 	u32_env dcache;
+	u32_env csm_location;
 	u32_env l2_cache;
 };
 
@@ -132,6 +133,7 @@
 	{ "dcache_ena",	ENV_HEX, true,	0, 1,		&env_common.dcache },
 #if defined(CONFIG_BOARD_HSDK_4XD)
 	{ "l2_cache_ena",	ENV_HEX, true,	0, 1,		&env_common.l2_cache },
+	{ "csm_location",	ENV_HEX, true,	0, NO_CCM,	&env_common.csm_location },
 #endif /* CONFIG_BOARD_HSDK_4XD */
 	{}
 };
@@ -299,6 +301,30 @@
 		slc_disable();
 }
 
+#define CREG_CSM_BASE		(CREG_BASE + 0x210)
+
+static void init_cluster_csm(void)
+{
+	/* ARC HS38 in HSDK SoC doesn't include CSM */
+	if (!is_board_match_config(T_BOARD_HSDK_4XD))
+		return;
+
+	if (env_common.csm_location.val == NO_CCM) {
+		write_aux_reg(ARC_AUX_CSM_ENABLE, 0);
+	} else {
+		/*
+		 * CSM base address is 256kByte aligned but we allow to map
+		 * CSM only to aperture start (256MByte aligned)
+		 * The field in CREG_CSM_BASE is in 17:2 bits itself so we need
+		 * to shift it.
+		 */
+		u32 csm_base = (env_common.csm_location.val * SZ_1K) << 2;
+
+		write_aux_reg(ARC_AUX_CSM_ENABLE, 1);
+		writel(csm_base, (void __iomem *)CREG_CSM_BASE);
+	}
+}
+
 static void init_master_icache(void)
 {
 	if (icache_status()) {
@@ -678,6 +704,7 @@
 	 * cores.
 	 */
 	init_cluster_nvlim();
+	init_cluster_csm();
 	init_cluster_slc();
 }