// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2022 NXP
 */

#include "imx93-u-boot.dtsi"

/ {
	wdt-reboot {
		compatible = "wdt-reboot";
		wdt = <&wdog3>;
		bootph-pre-ram;
		bootph-some-ram;
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};
};

&{/soc@0} {
	bootph-all;
	bootph-pre-ram;
};

&lpi2c2 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <400000>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_lpi2c2>;
	pinctrl-1 = <&pinctrl_lpi2c2>;
	status = "okay";

	pmic@25 {
		compatible = "nxp,pca9451a";
		reg = <0x25>;
		interrupt-parent = <&pcal6524>;
		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;

		regulators {
			buck1: BUCK1 {
				regulator-name = "BUCK1";
				regulator-min-microvolt = <650000>;
				regulator-max-microvolt = <2237500>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
			};

			buck2: BUCK2 {
				regulator-name = "BUCK2";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
			};

			buck4: BUCK4{
				regulator-name = "BUCK4";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck5: BUCK5{
				regulator-name = "BUCK5";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck6: BUCK6 {
				regulator-name = "BUCK6";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1: LDO1 {
				regulator-name = "LDO1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo4: LDO4 {
				regulator-name = "LDO4";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo5: LDO5 {
				regulator-name = "LDO5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};

	pcal6524: gpio@22 {
		compatible = "nxp,pcal6524";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pcal6524>;
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gpio3>;
		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
	};

	adp5585gpio: gpio@34 {
		compatible = "adp5585";
		reg = <0x34>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&aips1 {
	bootph-pre-ram;
	bootph-all;
};

&aips2 {
	bootph-pre-ram;
	bootph-some-ram;
};

&aips3 {
	bootph-pre-ram;
	bootph-some-ram;
};

&iomuxc {
	bootph-pre-ram;
	bootph-some-ram;

	pinctrl_lpi2c2: lpi2c2grp {
		fsl,pins = <
			MX93_PAD_I2C2_SCL__LPI2C2_SCL			0x40000b9e
			MX93_PAD_I2C2_SDA__LPI2C2_SDA			0x40000b9e
		>;
	};

	pinctrl_pcal6524: pcal6524grp {
		fsl,pins = <
			MX93_PAD_CCM_CLKO2__GPIO3_IO27			0x31e
		>;
	};
};

&reg_usdhc2_vmmc {
	u-boot,off-on-delay-us = <20000>;
	bootph-pre-ram;
	bootph-some-ram;
};

&pinctrl_reg_usdhc2_vmmc {
	bootph-pre-ram;
};

&pinctrl_uart1 {
	bootph-pre-ram;
	bootph-some-ram;
};

&pinctrl_usdhc2_gpio {
	bootph-pre-ram;
	bootph-some-ram;
};

&pinctrl_usdhc2 {
	bootph-pre-ram;
	bootph-some-ram;
};

&gpio1 {
	bootph-pre-ram;
	bootph-some-ram;
};

&gpio2 {
	bootph-pre-ram;
	bootph-some-ram;
};

&gpio3 {
	bootph-pre-ram;
	bootph-some-ram;
};

&gpio4 {
	bootph-pre-ram;
	bootph-some-ram;
};

&lpuart1 {
	bootph-pre-ram;
	bootph-some-ram;
};

&usdhc1 {
	bootph-pre-ram;
	bootph-some-ram;
};

&usdhc2 {
	bootph-pre-ram;
	bootph-some-ram;
	fsl,signal-voltage-switch-extra-delay-ms = <8>;
};

&lpi2c2 {
	bootph-pre-ram;
	bootph-some-ram;
};

&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
	bootph-pre-ram;
	bootph-some-ram;
};

&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
	bootph-pre-ram;
	bootph-some-ram;
};

&pinctrl_lpi2c2 {
	bootph-pre-ram;
	bootph-some-ram;
};

&fec {
	phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <15>;
	phy-reset-post-delay = <100>;
};

&ethphy1 {
	reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
	reset-assert-us = <15000>;
	reset-deassert-us = <100000>;
};

&s4muap {
	bootph-pre-ram;
	bootph-some-ram;
	status = "okay";
};

&clk {
	bootph-all;
	bootph-pre-ram;
	/delete-property/ assigned-clocks;
	/delete-property/ assigned-clock-rates;
	/delete-property/ assigned-clock-parents;
};

&osc_32k {
	bootph-all;
	bootph-pre-ram;
};

&osc_24m {
	bootph-all;
	bootph-pre-ram;
};

&clk_ext1 {
	bootph-all;
	bootph-pre-ram;
};