| commit | f91b9b40d3040416db2e90d3e7c390c1129940b3 | [log] [tgz] |
|---|---|---|
| author | David Wu <david.wu@rock-chips.com> | Wed Sep 20 14:38:58 2017 +0800 |
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | Sun Oct 01 00:33:30 2017 +0200 |
| tree | 6bfd8955bddacb21b9769d900a3c7b9d061ad387 | |
| parent | 4771ba647659899480f11146a3a8973edbd525d6 [diff] |
rockchip: clk: Add rk3399 SARADC clock support The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 8-bits width. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>