| commit | f8e7cefe87c1d8176766743e750089cb24adf969 | [log] [tgz] |
|---|---|---|
| author | Padmarao Begari <padmarao.begari@amd.com> | Mon Jan 06 15:21:20 2025 +0530 |
| committer | Michal Simek <michal.simek@amd.com> | Wed Feb 05 16:22:55 2025 +0100 |
| tree | 9a2e56ae72f92441d4b72843dcc111ca3473d8c5 | |
| parent | f227f1bb54ededc4489fa783029c0e9a9f82cbc5 [diff] |
spi: cadence_qspi: Fix OSPI DDR mode alignment issue If the least significant bit of the address is set to one when using the DDR protocol for data transfer then the results are indeterminate for few flash devices. To fix this the least significant bit of the address is set to zero. Signed-off-by: Padmarao Begari <padmarao.begari@amd.com> Link: https://lore.kernel.org/r/20250106095120.800753-1-padmarao.begari@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>