diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h
index a9baacd..d9d8bf9 100644
--- a/include/asm-blackfin/mem_init.h
+++ b/include/asm-blackfin/mem_init.h
@@ -26,7 +26,7 @@
 	CONFIG_MEM_MT48LC64M4A2FB_7E || \
 	CONFIG_MEM_MT48LC16M8A2TG_75 || \
 	CONFIG_MEM_MT48LC8M16A2TG_7E || \
-  CONFIG_MEM_MT48LC8M32B2B5_7  || \
+	CONFIG_MEM_MT48LC8M32B2B5_7  || \
 	CONFIG_MEM_MT48LC32M8A2_75)
 
 	#if ( CONFIG_SCLK_HZ > 119402985 )
@@ -105,43 +105,43 @@
 
 #if (CONFIG_MEM_MT48LC16M16A2TG_75)
 	/*SDRAM INFORMATION: */
-	#define SDRAM_Tref	64       /* Refresh period in milliseconds   */
-	#define SDRAM_NRA	8192     /* Number of row addresses in SDRAM */
+	#define SDRAM_Tref	64	/* Refresh period in milliseconds   */
+	#define SDRAM_NRA	8192	/* Number of row addresses in SDRAM */
 	#define SDRAM_CL	CL_3
 #endif
 
 #if (CONFIG_MEM_MT48LC64M4A2FB_7E)
 	/*SDRAM INFORMATION: */
-	#define SDRAM_Tref	64       /* Refresh period in milliseconds   */
-	#define SDRAM_NRA	8192     /* Number of row addresses in SDRAM */
+	#define SDRAM_Tref	64	/* Refresh period in milliseconds   */
+	#define SDRAM_NRA	8192	/* Number of row addresses in SDRAM */
 	#define SDRAM_CL	CL_2
 #endif
 
 #if (CONFIG_MEM_MT48LC16M8A2TG_75)
-        /*SDRAM INFORMATION: */
-        #define SDRAM_Tref      64       /* Refresh period in milliseconds   */
-        #define SDRAM_NRA       4096     /* Number of row addresses in SDRAM */
-        #define SDRAM_CL        CL_3
+	/*SDRAM INFORMATION: */
+	#define SDRAM_Tref      64	/* Refresh period in milliseconds   */
+	#define SDRAM_NRA       4096	/* Number of row addresses in SDRAM */
+	#define SDRAM_CL        CL_3
 #endif
 
 #if (CONFIG_MEM_MT48LC32M8A2_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64		/* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192	/* Number of row addresses in SDRAM */
+/*SDRAM INFORMATION: */
+#define SDRAM_Tref  64			/* Refresh period in milliseconds   */
+#define SDRAM_NRA   8192		/* Number of row addresses in SDRAM */
 #define SDRAM_CL    CL_3
 #endif
 
 #if (CONFIG_MEM_MT48LC8M16A2TG_7E)
 	/*SDRAM INFORMATION: */
-	#define SDRAM_Tref	64       /* Refresh period in milliseconds   */
-	#define SDRAM_NRA	4096     /* Number of row addresses in SDRAM */
+	#define SDRAM_Tref	64	/* Refresh period in milliseconds   */
+	#define SDRAM_NRA	4096	/* Number of row addresses in SDRAM */
 	#define SDRAM_CL	CL_2
 #endif
 
 #if (CONFIG_MEM_MT48LC8M32B2B5_7)
 	/*SDRAM INFORMATION: */
-	#define SDRAM_Tref	64       /* Refresh period in milliseconds   */
-	#define SDRAM_NRA	4096     /* Number of row addresses in SDRAM */
+	#define SDRAM_Tref	64	/* Refresh period in milliseconds   */
+	#define SDRAM_NRA	4096	/* Number of row addresses in SDRAM */
 	#define SDRAM_CL	CL_3
 #endif