[Blackfin][PATCH] code cleanup
diff --git a/include/asm-blackfin/arch-bf533/anomaly.h b/include/asm-blackfin/arch-bf533/anomaly.h
index 0e5f919..4fe425c 100644
--- a/include/asm-blackfin/arch-bf533/anomaly.h
+++ b/include/asm-blackfin/arch-bf533/anomaly.h
@@ -46,126 +46,126 @@
/* Issues that are common to 0.5, 0.4, and 0.3 silicon */
#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
- slot1 and store of a P register in slot 2 is not
- supported */
+ slot1 and store of a P register in slot 2 is not
+ supported */
#define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on
- every corresponding match */
+ every corresponding match */
#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
- Channel DMA stops */
+ Channel DMA stops */
#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
- registers. */
+ registers. */
#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
- upper bits*/
+ upper bits*/
#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
- syncs */
+ syncs */
#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
- functional */
+ functional */
#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
- state */
+ state */
#define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */
#define ANOMALY_05000272 /* Certain data cache write through modes fail for
- VDDint <=0.9V */
+ VDDint <=0.9V */
#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
- an edge is detected may clear interrupt */
+ an edge is detected may clear interrupt */
#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
- DMA system instability */
+ DMA system instability */
#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
- not restored */
+ not restored */
#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
- control */
+ control */
#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
- killed in a particular stage*/
+ killed in a particular stage*/
#endif
/* These issues only occur on 0.3 or 0.4 BF533 */
#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
- updated at the same time. */
+ updated at the same time. */
#define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data
- Cache Fill can be corrupted after or during
- Instruction DMA if certain core stalls exist */
+ Cache Fill can be corrupted after or during
+ Instruction DMA if certain core stalls exist */
#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
- Purpose TX or RX modes */
+ Purpose TX or RX modes */
#define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by
- preceding memory read */
+ preceding memory read */
#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
- inactive channels in certain conditions */
+ inactive channels in certain conditions */
#define ANOMALY_05000202 /* Possible infinite stall with specific dual dag
- situation */
+ situation */
#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
- data*/
+ data*/
#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
- Differences in certain Conditions */
+ Differences in certain Conditions */
#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
- hardware reset */
+ hardware reset */
#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
- IDLE around a Change of Control causes
- unpredictable results */
+ IDLE around a Change of Control causes
+ unpredictable results */
#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
- shadow of a conditional branch */
+ shadow of a conditional branch */
#define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware
- errors */
+ errors */
#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
- interrupt not functional */
+ interrupt not functional */
#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
- loops may cause the instruction fetch unit to
- malfunction */
+ loops may cause the instruction fetch unit to
+ malfunction */
#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
- the ICPLB Data registers differ */
+ the ICPLB Data registers differ */
#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
#define ANOMALY_05000262 /* Stores to data cache may be lost */
#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
- instruction will cause an infinite stall in the
- second to last instruction in a hardware loop */
+ instruction will cause an infinite stall in the
+ second to last instruction in a hardware loop */
#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
- SPORT external receive and transmit clocks. */
+ SPORT external receive and transmit clocks. */
#define ANOMALY_05000269 /* High I/O activity causes the output voltage of the
- internal voltage regulator (VDDint) to increase. */
+ internal voltage regulator (VDDint) to increase. */
#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
- internal voltage regulator (VDDint) to decrease */
+ internal voltage regulator (VDDint) to decrease */
#endif
/* These issues are only on 0.4 silicon */
#if (defined(CONFIG_BF_REV_0_4))
#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
- (TDM) */
+ (TDM) */
#endif
/* These issues are only on 0.3 silicon */
#if defined(CONFIG_BF_REV_0_3)
#define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with
- External Frame Syncs */
+ External Frame Syncs */
#define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative
- Instruction or Data Fetches, or by Fetches at the
- boundary of reserved memory space */
+ Instruction or Data Fetches, or by Fetches at the
+ boundary of reserved memory space */
#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
- when polarity setting is changed */
+ when polarity setting is changed */
#define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data
- corruption */
+ corruption */
#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
- fix */
+ fix */
#define ANOMALY_05000201 /* Receive frame sync not ignored during active
- frames in sport MCM */
+ frames in sport MCM */
#define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA
- stopping */
+ stopping */
#if defined(CONFIG_BF533)
#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
- allocate cache lines on reads only mode */
+ allocate cache lines on reads only mode */
#endif /* CONFIG_BF533 */
#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
- instructions */
+ instructions */
#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
- Sync Transmit Mode */
+ Sync Transmit Mode */
#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
#endif
diff --git a/include/asm-blackfin/arch-bf533/defBF532.h b/include/asm-blackfin/arch-bf533/defBF532.h
index 312ff2b..25a74e6 100644
--- a/include/asm-blackfin/arch-bf533/defBF532.h
+++ b/include/asm-blackfin/arch-bf533/defBF532.h
@@ -88,7 +88,7 @@
#define UART_LCR 0xFFC0040C /* Line Control Register */
#define UART_MCR 0xFFC00410 /* Modem Control Register */
#define UART_LSR 0xFFC00414 /* Line Status Register */
-/* #define UART_MSR 0xFFC00418 *//* Modem Status Register (UNUSED in ADSP-BF532) */
+/* #define UART_MSR 0xFFC00418 */ /* Modem Status Register (UNUSED in ADSP-BF532) */
#define UART_SCR 0xFFC0041C /* SCR Scratch Register */
#define UART_GCTL 0xFFC00424 /* Global Control Register */
diff --git a/include/asm-blackfin/arch-common/cdef_LPBlackfin.h b/include/asm-blackfin/arch-common/cdef_LPBlackfin.h
index f82ccbe..90b21e5 100644
--- a/include/asm-blackfin/arch-common/cdef_LPBlackfin.h
+++ b/include/asm-blackfin/arch-common/cdef_LPBlackfin.h
@@ -14,14 +14,11 @@
#endif
#include <asm/arch-common/def_LPBlackfin.h>
-// Cache & SRAM Memory
+/* Cache & SRAM Memory */
#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS)
#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR)
-/*
-#define MMR_TIMEOUT 0xFFE00010 // Memory-Mapped Register Timeout Register
-*/
#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0)
#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1)
#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2)
@@ -55,15 +52,8 @@
#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
-/*
-#define DTEST_INDEX 0xFFE00304 // Data Test Index Register
-*/
#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
-/*
-#define DTEST_DATA2 0xFFE00408 // Data Test Data Register
-#define DTEST_DATA3 0xFFE0040C // Data Test Data Register
-*/
#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
#define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR)
@@ -100,13 +90,10 @@
#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
-/*
-#define ITEST_INDEX 0xFFE01304 // Instruction Test Index Register
-*/
#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
-// Event/Interrupt Registers
+/* Event/Interrupt Registers */
#define pEVT0 ((volatile void **)EVT0)
#define pEVT1 ((volatile void **)EVT1)
#define pEVT2 ((volatile void **)EVT2)
@@ -127,24 +114,24 @@
#define pIPEND ((volatile unsigned long *)IPEND)
#define pILAT ((volatile unsigned long *)ILAT)
-// Core Timer Registers
+/* Core Timer Registers */
#define pTCNTL ((volatile unsigned long *)TCNTL)
#define pTPERIOD ((volatile unsigned long *)TPERIOD)
#define pTSCALE ((volatile unsigned long *)TSCALE)
#define pTCOUNT ((volatile unsigned long *)TCOUNT)
-// Debug/MP/Emulation Registers
+/* Debug/MP/Emulation Registers */
#define pDSPID ((volatile unsigned long *)DSPID)
#define pDBGCTL ((volatile unsigned long *)DBGCTL)
#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
#define pEMUDAT ((volatile unsigned long *)EMUDAT)
-// Trace Buffer Registers
+/* Trace Buffer Registers */
#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
#define pTBUF ((volatile void **)TBUF)
-// Watch Point Control Registers
+/* Watch Point Control Registers */
#define pWPIACTL ((volatile unsigned long *)WPIACTL)
#define pWPIA0 ((volatile void **)WPIA0)
#define pWPIA1 ((volatile void **)WPIA1)
@@ -165,13 +152,9 @@
#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
#define pWPSTAT ((volatile unsigned long *)WPSTAT)
-// Performance Monitor Registers
+/* Performance Monitor Registers */
#define pPFCTL ((volatile unsigned long *)PFCTL)
#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
-/*
-#define IPRIO 0xFFE02110 // Core Interrupt Priority Register
-*/
-
#endif /* _CDEF_LPBLACKFIN_H */
diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h
index a9baacd..d9d8bf9 100644
--- a/include/asm-blackfin/mem_init.h
+++ b/include/asm-blackfin/mem_init.h
@@ -26,7 +26,7 @@
CONFIG_MEM_MT48LC64M4A2FB_7E || \
CONFIG_MEM_MT48LC16M8A2TG_75 || \
CONFIG_MEM_MT48LC8M16A2TG_7E || \
- CONFIG_MEM_MT48LC8M32B2B5_7 || \
+ CONFIG_MEM_MT48LC8M32B2B5_7 || \
CONFIG_MEM_MT48LC32M8A2_75)
#if ( CONFIG_SCLK_HZ > 119402985 )
@@ -105,43 +105,43 @@
#if (CONFIG_MEM_MT48LC16M16A2TG_75)
/*SDRAM INFORMATION: */
- #define SDRAM_Tref 64 /* Refresh period in milliseconds */
- #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
+ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
+ #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
#define SDRAM_CL CL_3
#endif
#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
/*SDRAM INFORMATION: */
- #define SDRAM_Tref 64 /* Refresh period in milliseconds */
- #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
+ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
+ #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
#define SDRAM_CL CL_2
#endif
#if (CONFIG_MEM_MT48LC16M8A2TG_75)
- /*SDRAM INFORMATION: */
- #define SDRAM_Tref 64 /* Refresh period in milliseconds */
- #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
- #define SDRAM_CL CL_3
+ /*SDRAM INFORMATION: */
+ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
+ #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
+ #define SDRAM_CL CL_3
#endif
#if (CONFIG_MEM_MT48LC32M8A2_75)
- /*SDRAM INFORMATION: */
-#define SDRAM_Tref 64 /* Refresh period in milliseconds */
-#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
+/*SDRAM INFORMATION: */
+#define SDRAM_Tref 64 /* Refresh period in milliseconds */
+#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
#define SDRAM_CL CL_3
#endif
#if (CONFIG_MEM_MT48LC8M16A2TG_7E)
/*SDRAM INFORMATION: */
- #define SDRAM_Tref 64 /* Refresh period in milliseconds */
- #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
+ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
+ #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
#define SDRAM_CL CL_2
#endif
#if (CONFIG_MEM_MT48LC8M32B2B5_7)
/*SDRAM INFORMATION: */
- #define SDRAM_Tref 64 /* Refresh period in milliseconds */
- #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
+ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
+ #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
#define SDRAM_CL CL_3
#endif