commit f83a65c5f3c7544b97bd76387556e6952cd67d2c
author Aubrey Li <aubrey.adi@gmail.com> Sat Mar 10 23:49:29 2007 +0800
committer Aubrey Li <aubrey.adi@gmail.com> Sat Mar 10 23:49:29 2007 +0800
tree e8f94f4059122b3218cffe1d3bbe577aea6cb6d9
parent 450c23e4c3bbd0e83ae06bd78043c438d2a112a0

[Blackfin][PATCH] code cleanup

cpu/bf533/cache.S

diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S
index d2b34a9..5dcc24f 100644
--- a/cpu/bf533/cache.S
+++ b/cpu/bf533/cache.S
@@ -68,7 +68,7 @@
 	(R7:5) =[SP++];
 	RTS;
 
-/* 
+/*
  * Invalidate the Entire Data cache by
  * clearing DMC[1:0] bits
  */
@@ -80,7 +80,7 @@
 	P0.H = (DMEM_CONTROL >> 16);
 	R7 =[P0];
 
-/* 
+/*
  * Clear the DMC[1:0] bits, All valid bits in the data
  * cache are set to the invalid state
  */
@@ -118,7 +118,7 @@
 	CC = P0 < P1(iu);
 	IF CC JUMP 1b(bp);
 
-/* 
+/*
  * If the data crosses a cache line, then we'll be pointing to
  * the last cache line, but won't have flushed/invalidated it yet, so do
  * one more.