pinctrl: renesas: Minimize R8A779F0 S4 PFC tables
Reduce the PFC tables by ifdeffing out pinmux settings which are
unlikely to be used by U-Boot. This helps reduce the size of the
bootloader in the 10 kiB range. This includes conditional build
of these PFC additions:
- INTC-EX
- MSIOF
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c
index eec5021..2b62913 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779f0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
@@ -654,6 +654,7 @@
SDA5_MARK, SCL5_MARK,
};
+#ifdef CONFIG_PINCTRL_PFC_FULL
/* - INTC-EX ---------------------------------------------------------------- */
static const unsigned int intc_ex_irq0_pins[] = {
/* IRQ0 */
@@ -697,6 +698,7 @@
static const unsigned int intc_ex_irq5_mux[] = {
IRQ5_MARK,
};
+#endif
/* - MMC -------------------------------------------------------------------- */
static const unsigned int mmc_data_pins[] = {
@@ -741,6 +743,7 @@
MMC_DS_MARK,
};
+#ifdef CONFIG_PINCTRL_PFC_FULL
/* - MSIOF0 ----------------------------------------------------------------- */
static const unsigned int msiof0_clk_pins[] = {
/* MSIOF0_SCK */
@@ -916,6 +919,7 @@
static const unsigned int msiof3_rxd_mux[] = {
MSIOF3_RXD_MARK,
};
+#endif
/* - PCIE ------------------------------------------------------------------- */
static const unsigned int pcie0_clkreq_n_pins[] = {
@@ -1308,12 +1312,14 @@
SH_PFC_PIN_GROUP(i2c3),
SH_PFC_PIN_GROUP(i2c4),
SH_PFC_PIN_GROUP(i2c5),
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_PIN_GROUP(intc_ex_irq0),
SH_PFC_PIN_GROUP(intc_ex_irq1),
SH_PFC_PIN_GROUP(intc_ex_irq2),
SH_PFC_PIN_GROUP(intc_ex_irq3),
SH_PFC_PIN_GROUP(intc_ex_irq4),
SH_PFC_PIN_GROUP(intc_ex_irq5),
+#endif
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
BUS_DATA_PIN_GROUP(mmc_data, 8),
@@ -1321,6 +1327,7 @@
SH_PFC_PIN_GROUP(mmc_cd),
SH_PFC_PIN_GROUP(mmc_wp),
SH_PFC_PIN_GROUP(mmc_ds),
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
SH_PFC_PIN_GROUP(msiof0_ss1),
@@ -1345,6 +1352,7 @@
SH_PFC_PIN_GROUP(msiof3_ss2),
SH_PFC_PIN_GROUP(msiof3_txd),
SH_PFC_PIN_GROUP(msiof3_rxd),
+#endif
SH_PFC_PIN_GROUP(pcie0_clkreq_n),
SH_PFC_PIN_GROUP(pcie1_clkreq_n),
SH_PFC_PIN_GROUP(qspi0_ctrl),
@@ -1446,6 +1454,7 @@
"i2c5",
};
+#ifdef CONFIG_PINCTRL_PFC_FULL
static const char * const intc_ex_groups[] = {
"intc_ex_irq0",
"intc_ex_irq1",
@@ -1454,6 +1463,7 @@
"intc_ex_irq4",
"intc_ex_irq5",
};
+#endif
static const char * const mmc_groups[] = {
"mmc_data1",
@@ -1465,6 +1475,7 @@
"mmc_ds",
};
+#ifdef CONFIG_PINCTRL_PFC_FULL
static const char * const msiof0_groups[] = {
"msiof0_clk",
"msiof0_sync",
@@ -1500,6 +1511,7 @@
"msiof3_txd",
"msiof3_rxd",
};
+#endif
static const char * const pcie_groups[] = {
"pcie0_clkreq_n",
@@ -1596,12 +1608,16 @@
SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(i2c4),
SH_PFC_FUNCTION(i2c5),
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_FUNCTION(intc_ex),
+#endif
SH_PFC_FUNCTION(mmc),
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(msiof2),
SH_PFC_FUNCTION(msiof3),
+#endif
SH_PFC_FUNCTION(pcie),
SH_PFC_FUNCTION(qspi0),
SH_PFC_FUNCTION(qspi1),