diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c
index a0f25d1..d6e7a17 100644
--- a/drivers/ddr/altera/sdram_agilex.c
+++ b/drivers/ddr/altera/sdram_agilex.c
@@ -30,7 +30,7 @@
 	u32 i;
 	int ret;
 	phys_size_t hw_size;
-	bd_t bd = {0};
+	struct bd_info bd = {0};
 
 	/* Ensure HMC clock is running */
 	if (poll_hmc_clock_status()) {
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index 91f76e0..2945f1e 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -76,7 +76,7 @@
 	u32 i;
 	int ret;
 	phys_size_t hw_size;
-	bd_t bd = {0};
+	struct bd_info bd = {0};
 
 	/* Enable access to DDR from CPU master */
 	clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG),
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index 491f689..8cb75fe 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -132,7 +132,7 @@
 	}
 }
 
-void sdram_init_ecc_bits(bd_t *bd)
+void sdram_init_ecc_bits(struct bd_info *bd)
 {
 	phys_size_t size, size_init;
 	phys_addr_t start_addr;
@@ -176,7 +176,7 @@
 	       (unsigned int)get_timer(start));
 }
 
-void sdram_size_check(bd_t *bd)
+void sdram_size_check(struct bd_info *bd)
 {
 	phys_size_t total_ram_check = 0;
 	phys_size_t ram_check = 0;
diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h
index 7b25a80..4a830e7 100644
--- a/drivers/ddr/altera/sdram_soc64.h
+++ b/drivers/ddr/altera/sdram_soc64.h
@@ -179,8 +179,8 @@
 int emif_reset(struct altera_sdram_platdata *plat);
 int poll_hmc_clock_status(void);
 void sdram_clear_mem(phys_addr_t addr, phys_size_t size);
-void sdram_init_ecc_bits(bd_t *bd);
-void sdram_size_check(bd_t *bd);
+void sdram_init_ecc_bits(struct bd_info *bd);
+void sdram_size_check(struct bd_info *bd);
 phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat);
 int sdram_mmr_init_full(struct udevice *dev);