commit f7c917616293efc87a8dfa6771d300cc6f087a33
author Igor Opaniuk <igor.opaniuk@foundries.io> Tue Feb 09 13:52:45 2021 +0200
committer Heiko Schocher <hs@denx.de> Sun Feb 21 06:08:00 2021 +0100
tree 153470783919253c3a9bbcbc0e34b38c62f138f1
parent 5f4de78ea32459196650614abde26cf9bd39bb54

dm: i2c: use CONFIG_IS_ENABLED macro for DM_I2C/DM_I2C_GPIO

Use CONFIG_IS_ENABLED() macro, which provides more convenient
way to check $(SPL)DM_I2C/$(SPL)DM_I2C_GPIO configs
for both SPL and U-Boot proper.

CONFIG_IS_ENABLED(DM_I2C) expands to:
- 1 if CONFIG_SPL_BUILD is undefined and CONFIG_DM_I2C is set to 'y',
- 1 if CONFIG_SPL_BUILD is defined and CONFIG_SPL_DM_I2C is set to 'y',
- 0 otherwise.

All occurences were replaced automatically using these bash cmds:
$ find . -type f -exec sed -i
     's/ifndef CONFIG_DM_I2C/if !CONFIG_IS_ENABLED(DM_I2C)/g' {} +
$ find . -type f -exec sed -i
    's/ifdef CONFIG_DM_I2C/if CONFIG_IS_ENABLED(DM_I2C)/g' {} +
$ find . -type f -exec sed -i
    's/defined(CONFIG_DM_I2C)/CONFIG_IS_ENABLED(DM_I2C)/g' {} +
$ find . -type f -exec sed -i
    's/ifndef CONFIG_DM_I2C_GPIO/if !CONFIG_IS_ENABLED(DM_I2C_GPIO)/g' {} +
$ find . -type f -exec sed -i
    's/ifdef CONFIG_DM_I2C_GPIO/if CONFIG_IS_ENABLED(DM_I2C_GPIO)/g' {} +
$ find . -type f -exec sed -i
    's/defined(CONFIG_DM_I2C_GPIO)/CONFIG_IS_ENABLED(DM_I2C_GPIO)/g' {} +

Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

board/freescale/ls1088a/ls1088a.c

diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index 2ba6a39..e76ea01 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -379,7 +379,7 @@
 {
 	int ret;
 
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 #else
 	struct udevice *dev;
@@ -406,7 +406,7 @@
 
 	/* Access to Control/Shared register */
 	reg = 0x0;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 #else
 	struct udevice *dev;
@@ -416,7 +416,7 @@
 #endif
 
 	/* Read device revision and ID */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 #else
 	dm_i2c_read(dev, 1, &reg, 1);
@@ -425,20 +425,20 @@
 
 	/* Enable Broadcast. All writes target all channel register sets */
 	reg = 0x0c;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 #else
 	dm_i2c_write(dev, 0xff, &reg, 1);
 #endif
 
 	/* Reset Channel Registers */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 #else
 	dm_i2c_read(dev, 0, &reg, 1);
 #endif
 	reg |= 0x4;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 #else
 	dm_i2c_write(dev, 0, &reg, 1);
@@ -446,45 +446,45 @@
 
 	/* Set data rate as 10.3125 Gbps */
 	reg = 0x90;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 #else
 	dm_i2c_write(dev, 0x60, &reg, 1);
 #endif
 	reg = 0xb3;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 #else
 	dm_i2c_write(dev, 0x61, &reg, 1);
 #endif
 	reg = 0x90;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 #else
 	dm_i2c_write(dev, 0x62, &reg, 1);
 #endif
 	reg = 0xb3;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 #else
 	dm_i2c_write(dev, 0x63, &reg, 1);
 #endif
 	reg = 0xcd;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 #else
 	dm_i2c_write(dev, 0x64, &reg, 1);
 #endif
 
 	/* Select VCO Divider to full rate (000) */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 #else
 	dm_i2c_read(dev, 0x2F, &reg, 1);
 #endif
 	reg &= 0x0f;
 	reg |= 0x70;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 #else
 	dm_i2c_write(dev, 0x2F, &reg, 1);
@@ -496,7 +496,7 @@
 
 	/* Access to Control/Shared register */
 	reg = 0x0;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 #else
 	i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
@@ -504,7 +504,7 @@
 #endif
 
 	/* Read device revision and ID */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
 #else
 	dm_i2c_read(dev, 1, &reg, 1);
@@ -513,20 +513,20 @@
 
 	/* Enable Broadcast. All writes target all channel register sets */
 	reg = 0x0c;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 #else
 	dm_i2c_write(dev, 0xff, &reg, 1);
 #endif
 
 	/* Reset Channel Registers */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 #else
 	dm_i2c_read(dev, 0, &reg, 1);
 #endif
 	reg |= 0x4;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 #else
 	dm_i2c_write(dev, 0, &reg, 1);
@@ -534,45 +534,45 @@
 
 	/* Set data rate as 10.3125 Gbps */
 	reg = 0x90;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
 #else
 	dm_i2c_write(dev, 0x60, &reg, 1);
 #endif
 	reg = 0xb3;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
 #else
 	dm_i2c_write(dev, 0x61, &reg, 1);
 #endif
 	reg = 0x90;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
 #else
 	dm_i2c_write(dev, 0x62, &reg, 1);
 #endif
 	reg = 0xb3;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
 #else
 	dm_i2c_write(dev, 0x63, &reg, 1);
 #endif
 	reg = 0xcd;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
 #else
 	dm_i2c_write(dev, 0x64, &reg, 1);
 #endif
 
 	/* Select VCO Divider to full rate (000) */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 #else
 	dm_i2c_read(dev, 0x2F, &reg, 1);
 #endif
 	reg &= 0x0f;
 	reg |= 0x70;
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 #else
 	dm_i2c_write(dev, 0x2F, &reg, 1);
@@ -640,7 +640,7 @@
 	u8 chan = PWM_CHANNEL0;
 
 	/* Select the PAGE 0 using PMBus commands PAGE for VDD */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 			PMBUS_CMD_PAGE, 1, &chan, 1);
 #else
@@ -658,7 +658,7 @@
 	}
 
 	/* Read the output voltage using PMBus command READ_VOUT */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
 		       PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
 #else
@@ -679,7 +679,7 @@
 			svdd & 0xFF, (svdd & 0xFF00) >> 8};
 
 	/* Write the desired voltage code to the SVDD regulator */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 			PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
 #else
@@ -720,7 +720,7 @@
 	printf("SVDD changing of RDB\n");
 
 	/* Read the BRDCFG54 via CLPD */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
 		       QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 #else
@@ -740,7 +740,7 @@
 	brdcfg4 = brdcfg4 | 0x08;
 
 	/* Write to the BRDCFG4 */
-#ifndef CONFIG_DM_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
 	ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
 			QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 #else