diff --git a/CHANGELOG b/CHANGELOG
index 3f31d86..3762f21 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -36,7 +36,7 @@
 * Increase malloc arena on TQM5200 board to 256 kB.
   With 64 kb uniform flash sector size the old value of 128 kB was
   too small.
-  
+
 * Fix miiphy global data initialization (problem on 4xx boards when
   no ethaddr is assigned). Initialization moved from
   miiphy_register() to eth_initialize().
diff --git a/board/Marvell/db64360/mv_eth.c b/board/Marvell/db64360/mv_eth.c
index 2dd47bf..3c5dee7 100644
--- a/board/Marvell/db64360/mv_eth.c
+++ b/board/Marvell/db64360/mv_eth.c
@@ -283,7 +283,7 @@
 
 		/* set pointer to memory for stats data structure etc... */
 		port_private = calloc (sizeof (*ethernet_private), 1);
-		ethernet_private->port_private = (void *)port_private; 
+		ethernet_private->port_private = (void *)port_private;
 		if (!port_private) {
 			printf ("%s: %s allocation failure, %s\n",
 				__FUNCTION__, dev->name,
diff --git a/board/Marvell/db64460/mv_eth.c b/board/Marvell/db64460/mv_eth.c
index a50f174..ec5d581 100644
--- a/board/Marvell/db64460/mv_eth.c
+++ b/board/Marvell/db64460/mv_eth.c
@@ -268,7 +268,7 @@
 		dev->recv = (void *) db64460_eth_poll;
 
 		ethernet_private = calloc (sizeof (*ethernet_private), 1);
-		dev->priv = (void *)ethernet_private; 
+		dev->priv = (void *)ethernet_private;
 		if (!ethernet_private) {
 			printf ("%s: %s allocation failure, %s\n",
 				__FUNCTION__, dev->name,
@@ -282,7 +282,7 @@
 
 		/* set pointer to memory for stats data structure etc... */
 		port_private = calloc (sizeof (*ethernet_private), 1);
-		ethernet_private->port_private = (void *)port_private; 
+		ethernet_private->port_private = (void *)port_private;
 		if (!port_private) {
 			printf ("%s: %s allocation failure, %s\n",
 				__FUNCTION__, dev->name,
diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c
index b463f0e..df10c0e 100644
--- a/board/esd/cpci2dp/cpci2dp.c
+++ b/board/esd/cpci2dp/cpci2dp.c
@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -36,11 +36,11 @@
 	cntrl0Reg = mfdcr(cntrl0);
 	mtdcr(cntrl0, cntrl0Reg | 0x00900000);
 
-        /* set output pins to high */
-	out32(GPIO0_OR,  CFG_INTA_FAKE | CFG_EEPROM_WP | CFG_PB_LED);
-        /* INTA# is open drain */
+	/* set output pins to high */
+	out32(GPIO0_OR,	 CFG_INTA_FAKE | CFG_EEPROM_WP | CFG_PB_LED);
+	/* INTA# is open drain */
 	out32(GPIO0_ODR, CFG_INTA_FAKE);
-        /* setup for output */
+	/* setup for output */
 	out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP);
 
 	/*
@@ -55,14 +55,14 @@
 	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
 	 * IRQ 31 (EXT IRQ 6) unused
 	 */
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(uicer, 0x00000000);       /* disable all ints */
-	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
+	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(uicer, 0x00000000);	/* disable all ints */
+	mtdcr(uiccr, 0x00000000);	/* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFF81);	/* set int polarities */
 
-	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uictr, 0x10000000);	/* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
 
 	return 0;
 }
@@ -142,18 +142,17 @@
 
 #if defined(CFG_EEPROM_WREN)
 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
- *         <state>     -1: deliver current state
- *	               0: disable write
+ *	   <state>     -1: deliver current state
+ *		       0: disable write
  *		       1: enable write
- *  Returns:           -1: wrong device address
- *                      0: dis-/en- able done
+ *  Returns:	       -1: wrong device address
+ *			0: dis-/en- able done
  *		     0/1: current state if <state> was -1.
  */
 int eeprom_write_enable (unsigned dev_addr, int state) {
 	if (CFG_I2C_EEPROM_ADDR != dev_addr) {
 		return -1;
-	}
-	else {
+	} else {
 		switch (state) {
 		case 1:
 			/* Enable write access, clear bit GPIO_SINT2. */
@@ -186,19 +185,16 @@
 		state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
 		if (state < 0) {
 			puts ("Query of write access state failed.\n");
-		}
-		else {
+		} else {
 			printf ("Write access for device 0x%0x is %sabled.\n",
 				CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
 			state = 0;
 		}
-	}
-	else {
+	} else {
 		if ('0' == argv[1][0]) {
 			/* Disable write access. */
 			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
-		}
-		else {
+		} else {
 			/* Enable write access. */
 			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
 		}
diff --git a/board/esd/cpci750/mv_eth.c b/board/esd/cpci750/mv_eth.c
index 880528f..be176dc 100644
--- a/board/esd/cpci750/mv_eth.c
+++ b/board/esd/cpci750/mv_eth.c
@@ -284,7 +284,7 @@
 		/* set pointer to memory for stats data structure etc... */
 		port_private =
 			calloc (sizeof (*ethernet_private), 1);
-		ethernet_private->port_private = (void *)port_private; 
+		ethernet_private->port_private = (void *)port_private;
 		if (!port_private) {
 			printf ("%s: %s allocation failure, %s\n",
 				__FUNCTION__, dev->name,
diff --git a/board/evb64260/eth_addrtbl.c b/board/evb64260/eth_addrtbl.c
index 69882f5..e8ef0e3 100644
--- a/board/evb64260/eth_addrtbl.c
+++ b/board/evb64260/eth_addrtbl.c
@@ -57,7 +57,7 @@
 
 		realAddrTableBase[port] =
 			malloc (bytes + 64);
-		tableBase = (unsigned int)realAddrTableBase; 
+		tableBase = (unsigned int)realAddrTableBase;
 
 		if (!tableBase) {
 			printf ("%s: alloc memory failed \n", __FUNCTION__);
diff --git a/board/incaip/flash.c b/board/incaip/flash.c
index 686f2e9..520514d 100644
--- a/board/incaip/flash.c
+++ b/board/incaip/flash.c
@@ -190,7 +190,7 @@
 	int i;
 	uchar *boottype;
 	uchar *bootletter;
-	uchar *fmt;
+	char *fmt;
 	uchar botbootletter[] = "B";
 	uchar topbootletter[] = "T";
 	uchar botboottype[] = "bottom boot sector";
diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c
index eb6eaea..b5d9e00 100644
--- a/board/incaip/incaip.c
+++ b/board/incaip/incaip.c
@@ -68,7 +68,7 @@
 		{
 			*INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) |
 			                           (rows << 4) | cols;
-			size = get_ram_size((ulong *)CFG_SDRAM_BASE,
+			size = get_ram_size((long *)CFG_SDRAM_BASE,
 			                                     max_sdram_size());
 
 			if (size > max_size)
diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S
index fb64ef4..14d738a 100644
--- a/board/incaip/lowlevel_init.S
+++ b/board/incaip/lowlevel_init.S
@@ -66,6 +66,7 @@
 	.globl	ebu_init
 	.ent	ebu_init
 ebu_init:
+__ebu_init:
 
 	li	t1, EBU_MODUL_BASE
 	li	t2, 0xA0000041
@@ -118,6 +119,7 @@
 	.globl	cgu_init
 	.ent	cgu_init
 cgu_init:
+__cgu_init:
 
 	li	t1, CGU_MODUL_BASE
 
@@ -182,6 +184,7 @@
 	.globl	sdram_init
 	.ent	sdram_init
 sdram_init:
+__sdram_init:
 
 	li	t1, MC_MODUL_BASE
 
@@ -281,11 +284,11 @@
 	/* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init()
 	 * modify t0 and a0.
 	 */
-	bal	cgu_init
+	bal	__cgu_init
 	nop
-	bal	ebu_init
+	bal	__ebu_init
 	nop
-	bal	sdram_init
+	bal	__sdram_init
 	nop
 	move	ra, t0
 
diff --git a/board/mpc8260ads/mpc8260ads.c b/board/mpc8260ads/mpc8260ads.c
index 374e979..93550e2 100644
--- a/board/mpc8260ads/mpc8260ads.c
+++ b/board/mpc8260ads/mpc8260ads.c
@@ -251,7 +251,7 @@
 
 	/* Advertise all capabilities */
 	bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_ANAR, 0x01E1);
-	
+
 	/* Do not bypass Rx/Tx (de)scrambler */
 	bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_DCR,  0x0000);
 
diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c
index 8ba66bf..d42a643 100644
--- a/board/prodrive/p3p440/p3p440.c
+++ b/board/prodrive/p3p440/p3p440.c
@@ -72,7 +72,7 @@
 	for (;;) {
 		if (in32(GPIO0_IR) & CFG_EREADY_IO)
 			return;
-        }
+	}
 
 }
 
diff --git a/board/tqm834x/config.mk b/board/tqm834x/config.mk
index 9295e77..f172c4e 100644
--- a/board/tqm834x/config.mk
+++ b/board/tqm834x/config.mk
@@ -21,4 +21,3 @@
 #
 
 TEXT_BASE   =   0x80000000
-
diff --git a/board/tqm834x/pci.c b/board/tqm834x/pci.c
index 590987c..5a23e6c 100644
--- a/board/tqm834x/pci.c
+++ b/board/tqm834x/pci.c
@@ -86,29 +86,29 @@
 	pci_conf = immr->pci_conf;
 
 	hose = &pci1_hose;
-	
+
 	/*
-	 * Configure PCI controller and PCI_CLK_OUTPUT 
+	 * Configure PCI controller and PCI_CLK_OUTPUT
 	 */
 
 	/*
 	 * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
 	 * line actually used for clocking all external PCI devices in TQM83xx.
-	 * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for 
+	 * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
 	 * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7
-	 * are known to hang the board; this issue is under investigation 
+	 * are known to hang the board; this issue is under investigation
 	 * (13 oct 05)
 	 */
 	reg32 = OCCR_PCICOE1;
-#if 0	
+#if 0
 	/* enabling all PCI_CLK_OUTPUT lines HANGS the board... */
 	reg32 = 0xff000000;
-#endif	
+#endif
 	if (clk->spmr & SPMR_CKID) {
 		/* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR
 		 * fields accordingly */
 		reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);
-		
+
 		reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \
 			  | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \
 			  | OCCR_PCICD6 | OCCR_PCICD7);
@@ -138,7 +138,7 @@
 	 * Configure PCI Outbound Translation Windows
 	 */
 
-	/* PCI1 mem space */ 
+	/* PCI1 mem space */
 	pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
 	pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
@@ -152,8 +152,8 @@
 	 * Configure PCI Inbound Translation Windows
 	 */
 
-	/* we need RAM mapped to PCI space for the devices to 
-	 * access main memory */ 
+	/* we need RAM mapped to PCI space for the devices to
+	 * access main memory */
 	pci_ctrl[0].pitar1 = 0x0;
 	pci_ctrl[0].pibar1 = 0x0;
 	pci_ctrl[0].piebar1 = 0x0;
@@ -179,10 +179,10 @@
 	/* System memory space */
 	pci_set_region(hose->regions + 2,
 		       CONFIG_PCI_SYS_MEM_BUS,
-                       CONFIG_PCI_SYS_MEM_PHYS,
-                       CONFIG_PCI_SYS_MEM_SIZE,
-                       PCI_REGION_MEM | PCI_REGION_MEMORY);
-		       
+		       CONFIG_PCI_SYS_MEM_PHYS,
+		       CONFIG_PCI_SYS_MEM_SIZE,
+		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+
 	hose->region_count = 3;
 
 	pci_setup_indirect(hose,
@@ -195,18 +195,18 @@
 	 * Write to Command register
 	 */
 	reg16 = 0xff;
-	pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND, 
+	pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
 					&reg16);
 	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, 
+	pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
 					reg16);
 
 	/*
 	 * Clear non-reserved bits in status register.
 	 */
-	pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS, 
+	pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
 					0xffff);
-	pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER, 
+	pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
 					0x80);
 
 #ifdef CONFIG_PCI_SCAN_SHOW
diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c
index f681dc8..dada673 100644
--- a/board/tqm834x/tqm834x.c
+++ b/board/tqm834x/tqm834x.c
@@ -77,7 +77,7 @@
 	/* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
 		return 0;
-	
+
 	/* detect the number of Flash banks */
 	return detect_num_flash_banks();
 }
@@ -108,7 +108,7 @@
 	set_ddr_config();
 
 	udelay(200);
-	
+
 	/* enable DDR controller */
 	im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
 		SDRAM_CFG_SREN |
@@ -154,7 +154,7 @@
 
 	/* get bus width */
 	w = 32;
-	if (immr->reset.rcwh & RCWH_PCI64) 
+	if (immr->reset.rcwh & RCWH_PCI64)
 		w = 64;
 
 	/* get clock */
@@ -192,7 +192,7 @@
 	ulong total_size;
 
 	tqm834x_num_flash_banks = 2;	/* assume two banks */
-	
+
 	/* Get bank 1 and 2 information */
 	bank1_size = flash_get_size(CFG_FLASH_BASE, 0);
 	debug("Bank1 size: %lu\n", bank1_size);
@@ -318,10 +318,10 @@
 		set_cs_config(cs, 0);
 		return 0;
 	}
-		
+
 	debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
 			conf[detected].row, conf[detected].col, conf[detected].size >> 20, base);
-	
+
 	/* configure cs ro detected params */
 	set_cs_config(cs, CSCONFIG_EN | conf[detected].row |
 			conf[detected].col);
@@ -367,7 +367,7 @@
 	im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |
 		DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
 	SYNC;
-	
+
 	/* timing configuration */
 	im->ddr.timing_cfg_1 =
 		(4 << TIMING_CFG1_PRETOACT_SHIFT) |
@@ -389,7 +389,7 @@
 		SDRAM_CFG_SREN |
 		SDRAM_CFG_SDRAM_TYPE_DDR;
 	SYNC;
-	
+
 	/* Set SDRAM mode */
 	im->ddr.sdram_mode =
 		((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) <<
diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c
index 3bf3c8d..a5c50af 100644
--- a/cpu/mcf52x2/fec.c
+++ b/cpu/mcf52x2/fec.c
@@ -567,4 +567,3 @@
 #endif
 	return 0;
 }
-
diff --git a/cpu/mips/incaip_clock.c b/cpu/mips/incaip_clock.c
index 65ee847..d0515ca 100644
--- a/cpu/mips/incaip_clock.c
+++ b/cpu/mips/incaip_clock.c
@@ -102,7 +102,7 @@
 	extern void ebu_init(long);
 	extern void cgu_init(long);
 	extern void sdram_init(long);
-	uchar tmp[64];
+	char tmp[64];
 	ulong cpuclk;
 
 	if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0) {
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 5964260..1368fc3 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -132,7 +132,7 @@
 
 	/* PCI Host Mode */
 	if (!(im->reset.rcwh & RCWH_PCIHOST)) {
-		/* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH 
+		/* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH
 		 * the im->reset.rcwhr PCI Host Mode is disabled
 		 * FIXME: findout if there is a way to issue some warning */
 		return -2;
@@ -156,7 +156,7 @@
 
 	/* PCI Agent Mode */
 	if (im->reset.rcwh & RCWH_PCIHOST) {
-		/* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH 
+		/* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH
 		 * the im->reset.rcwhr PCI Host Mode is enabled */
 		return -3;
 	}
diff --git a/cpu/mpc8xx/config.mk b/cpu/mpc8xx/config.mk
index 5fa150e..bfa6625 100644
--- a/cpu/mpc8xx/config.mk
+++ b/cpu/mpc8xx/config.mk
@@ -21,6 +21,6 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing 
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
 
 PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -ffixed-r29 -mstring -mcpu=860 -msoft-float
diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c
index 1bdfc16..ebd5f39 100644
--- a/cpu/ppc4xx/spd_sdram.c
+++ b/cpu/ppc4xx/spd_sdram.c
@@ -48,49 +48,49 @@
 /*
  * Set default values
  */
-#ifndef	CFG_I2C_SPEED
-#define	CFG_I2C_SPEED	50000
+#ifndef CFG_I2C_SPEED
+#define CFG_I2C_SPEED	50000
 #endif
 
-#ifndef	CFG_I2C_SLAVE
-#define	CFG_I2C_SLAVE	0xFE
+#ifndef CFG_I2C_SLAVE
+#define CFG_I2C_SLAVE	0xFE
 #endif
 
-#define ONE_BILLION         1000000000
+#define ONE_BILLION	1000000000
 
-#ifndef  CONFIG_440              /* for 405 WALNUT/SYCAMORE/BUBINGA boards */
+#ifndef	 CONFIG_440		/* for 405 WALNUT/SYCAMORE/BUBINGA boards */
 
-#define  SDRAM0_CFG_DCE          0x80000000
-#define  SDRAM0_CFG_SRE          0x40000000
-#define  SDRAM0_CFG_PME          0x20000000
-#define  SDRAM0_CFG_MEMCHK       0x10000000
-#define  SDRAM0_CFG_REGEN        0x08000000
-#define  SDRAM0_CFG_ECCDD        0x00400000
-#define  SDRAM0_CFG_EMDULR       0x00200000
-#define  SDRAM0_CFG_DRW_SHIFT    (31-6)
-#define  SDRAM0_CFG_BRPF_SHIFT   (31-8)
+#define	 SDRAM0_CFG_DCE		0x80000000
+#define	 SDRAM0_CFG_SRE		0x40000000
+#define	 SDRAM0_CFG_PME		0x20000000
+#define	 SDRAM0_CFG_MEMCHK	0x10000000
+#define	 SDRAM0_CFG_REGEN	0x08000000
+#define	 SDRAM0_CFG_ECCDD	0x00400000
+#define	 SDRAM0_CFG_EMDULR	0x00200000
+#define	 SDRAM0_CFG_DRW_SHIFT	(31-6)
+#define	 SDRAM0_CFG_BRPF_SHIFT	(31-8)
 
-#define  SDRAM0_TR_CASL_SHIFT    (31-8)
-#define  SDRAM0_TR_PTA_SHIFT     (31-13)
-#define  SDRAM0_TR_CTP_SHIFT     (31-15)
-#define  SDRAM0_TR_LDF_SHIFT     (31-17)
-#define  SDRAM0_TR_RFTA_SHIFT    (31-29)
-#define  SDRAM0_TR_RCD_SHIFT     (31-31)
+#define	 SDRAM0_TR_CASL_SHIFT	(31-8)
+#define	 SDRAM0_TR_PTA_SHIFT	(31-13)
+#define	 SDRAM0_TR_CTP_SHIFT	(31-15)
+#define	 SDRAM0_TR_LDF_SHIFT	(31-17)
+#define	 SDRAM0_TR_RFTA_SHIFT	(31-29)
+#define	 SDRAM0_TR_RCD_SHIFT	(31-31)
 
-#define  SDRAM0_RTR_SHIFT        (31-15)
-#define  SDRAM0_ECCCFG_SHIFT     (31-11)
+#define	 SDRAM0_RTR_SHIFT	(31-15)
+#define	 SDRAM0_ECCCFG_SHIFT	(31-11)
 
 /* SDRAM0_CFG enable macro  */
 #define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
 
-#define SDRAM0_BXCR_SZ_MASK  0x000e0000
-#define SDRAM0_BXCR_AM_MASK  0x0000e000
+#define SDRAM0_BXCR_SZ_MASK	0x000e0000
+#define SDRAM0_BXCR_AM_MASK	0x0000e000
 
-#define SDRAM0_BXCR_SZ_SHIFT (31-14)
-#define SDRAM0_BXCR_AM_SHIFT (31-18)
+#define SDRAM0_BXCR_SZ_SHIFT	(31-14)
+#define SDRAM0_BXCR_AM_SHIFT	(31-18)
 
-#define SDRAM0_BXCR_SZ(x)  ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
-#define SDRAM0_BXCR_AM(x)  ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
+#define SDRAM0_BXCR_SZ(x)	( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
+#define SDRAM0_BXCR_AM(x)	( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
 
 #ifdef CONFIG_SPDDRAM_SILENT
 # define SPD_ERR(x) do { return 0; } while (0)
@@ -175,7 +175,7 @@
 	 * data from DIMM:
 	 * 27	IN Row Precharge Time ( t RP)
 	 * 29	MIN RAS to CAS Delay ( t RCD)
-	 * 127   Component and Clock Detail ,clk0-clk3, junction temp, CAS
+	 * 127	 Component and Clock Detail ,clk0-clk3, junction temp, CAS
 	 * -------------------------------------------------------------------*/
 
 	/*
@@ -184,18 +184,18 @@
 	 */
 
 	tmp = read_spd(127) & 0x6;
-	if (tmp == 0x02){      	   /* only cas = 2 supported */
+	if (tmp == 0x02) {		/* only cas = 2 supported */
 		min_cas = 2;
-/*     	  t_ck = read_spd(9); */
-/*     	  t_ac = read_spd(10); */
-	} else if (tmp == 0x04) {         /* only cas = 3 supported */
+/*		t_ck = read_spd(9); */
+/*		t_ac = read_spd(10); */
+	} else if (tmp == 0x04) {	/* only cas = 3 supported */
 		min_cas = 3;
-/*     	  t_ck = read_spd(9); */
-/*     	  t_ac = read_spd(10); */
-	} else if (tmp == 0x06) {         /* 2,3 supported, so use 2 */
+/*		t_ck = read_spd(9); */
+/*		t_ac = read_spd(10); */
+	} else if (tmp == 0x06) {	/* 2,3 supported, so use 2 */
 		min_cas = 2;
-/*     	  t_ck = read_spd(23); */
-/*     	  t_ac = read_spd(24); */
+/*		t_ck = read_spd(23); */
+/*		t_ac = read_spd(24); */
 	} else {
 		SPD_ERR("SDRAM - unsupported CAS latency \n");
 	}
@@ -263,7 +263,7 @@
 	}
 	/* convert from nsec to bus cycles */
 	tmp = (tmp * 10) / bus_period_x_10;
-	sdram0_rtr = (tmp & 0x3ff8) <<  SDRAM0_RTR_SHIFT;
+	sdram0_rtr = (tmp & 0x3ff8) <<	SDRAM0_RTR_SHIFT;
 
 	/*------------------------------------------------------------------
 	 * determine the number of banks used
@@ -292,7 +292,7 @@
 	else if (tmp==4)
 		bank_cnt *= 4;
 	else
-		bank_cnt = 8; 		/* 8 is an error code */
+		bank_cnt = 8;		/* 8 is an error code */
 
 	if (bank_cnt > 4)	/* we only have 4 banks to work with */
 		SPD_ERR("SDRAM - unsupported module rows for this width\n");
@@ -323,7 +323,7 @@
 	total_size *= read_spd(5);	/* mult by module rows (dimm sides) */
 
 	/*------------------------------------------------------------------
-	 * map  rows * cols * banks to a mode
+	 * map	rows * cols * banks to a mode
 	 * -------------------------------------------------------------------*/
 
 	switch (row) {
@@ -388,9 +388,9 @@
 	bank_size = total_size / bank_cnt;
 	/* convert bank size to bank size code for ppc4xx
 	   by takeing log2(bank_size) - 22 */
-	tmp = bank_size; 		/* start with tmp = bank_size */
+	tmp = bank_size;		/* start with tmp = bank_size */
 	bank_code = 0;			/* and bank_code = 0 */
-	while (tmp > 1) { 		/* this takes log2 of tmp */
+	while (tmp > 1) {		/* this takes log2 of tmp */
 		bank_code++;		/* and stores result in bank_code */
 		tmp = tmp >> 1;
 	}				/* bank_code is now log2(bank_size) */
@@ -444,7 +444,7 @@
 #endif
 	mtsdram0( mem_sdtr1 , sdram0_tr );
 
-	/* SDRAM have a power on delay,  500 micro should do */
+	/* SDRAM have a power on delay,	 500 micro should do */
 	udelay(500);
 	sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
 	if (ecc_on)
@@ -464,172 +464,172 @@
 		return 0;
 }
 
-#else                             /* CONFIG_440 */
+#else /* CONFIG_440 */
 
 /*-----------------------------------------------------------------------------
   |  Memory Controller Options 0
   +-----------------------------------------------------------------------------*/
-#define SDRAM_CFG0_DCEN           0x80000000  /* SDRAM Controller Enable      */
-#define SDRAM_CFG0_MCHK_MASK      0x30000000  /* Memory data errchecking mask */
-#define SDRAM_CFG0_MCHK_NON       0x00000000  /* No ECC generation            */
-#define SDRAM_CFG0_MCHK_GEN       0x20000000  /* ECC generation               */
-#define SDRAM_CFG0_MCHK_CHK       0x30000000  /* ECC generation and checking  */
-#define SDRAM_CFG0_RDEN           0x08000000  /* Registered DIMM enable       */
-#define SDRAM_CFG0_PMUD           0x04000000  /* Page management unit         */
-#define SDRAM_CFG0_DMWD_MASK      0x02000000  /* DRAM width mask              */
-#define SDRAM_CFG0_DMWD_32        0x00000000  /* 32 bits                      */
-#define SDRAM_CFG0_DMWD_64        0x02000000  /* 64 bits                      */
-#define SDRAM_CFG0_UIOS_MASK      0x00C00000  /* Unused IO State              */
-#define SDRAM_CFG0_PDP            0x00200000  /* Page deallocation policy     */
+#define SDRAM_CFG0_DCEN		0x80000000	/* SDRAM Controller Enable	*/
+#define SDRAM_CFG0_MCHK_MASK	0x30000000	/* Memory data errchecking mask */
+#define SDRAM_CFG0_MCHK_NON	0x00000000	/* No ECC generation		*/
+#define SDRAM_CFG0_MCHK_GEN	0x20000000	/* ECC generation		*/
+#define SDRAM_CFG0_MCHK_CHK	0x30000000	/* ECC generation and checking	*/
+#define SDRAM_CFG0_RDEN		0x08000000	/* Registered DIMM enable	*/
+#define SDRAM_CFG0_PMUD		0x04000000	/* Page management unit		*/
+#define SDRAM_CFG0_DMWD_MASK	0x02000000	/* DRAM width mask		*/
+#define SDRAM_CFG0_DMWD_32	0x00000000	/* 32 bits			*/
+#define SDRAM_CFG0_DMWD_64	0x02000000	/* 64 bits			*/
+#define SDRAM_CFG0_UIOS_MASK	0x00C00000	/* Unused IO State		*/
+#define SDRAM_CFG0_PDP		0x00200000	/* Page deallocation policy	*/
 
 /*-----------------------------------------------------------------------------
   |  Memory Controller Options 1
   +-----------------------------------------------------------------------------*/
-#define SDRAM_CFG1_SRE            0x80000000  /* Self-Refresh Entry           */
-#define SDRAM_CFG1_PMEN           0x40000000  /* Power Management Enable      */
+#define SDRAM_CFG1_SRE		0x80000000	/* Self-Refresh Entry		*/
+#define SDRAM_CFG1_PMEN		0x40000000	/* Power Management Enable	*/
 
 /*-----------------------------------------------------------------------------+
   |  SDRAM DEVPOT Options
   +-----------------------------------------------------------------------------*/
-#define SDRAM_DEVOPT_DLL          0x80000000
-#define SDRAM_DEVOPT_DS           0x40000000
+#define SDRAM_DEVOPT_DLL	0x80000000
+#define SDRAM_DEVOPT_DS		0x40000000
 
 /*-----------------------------------------------------------------------------+
   |  SDRAM MCSTS Options
   +-----------------------------------------------------------------------------*/
-#define SDRAM_MCSTS_MRSC          0x80000000
-#define SDRAM_MCSTS_SRMS          0x40000000
-#define SDRAM_MCSTS_CIS           0x20000000
+#define SDRAM_MCSTS_MRSC	0x80000000
+#define SDRAM_MCSTS_SRMS	0x40000000
+#define SDRAM_MCSTS_CIS		0x20000000
 
 /*-----------------------------------------------------------------------------
   |  SDRAM Refresh Timer Register
   +-----------------------------------------------------------------------------*/
-#define SDRAM_RTR_RINT_MASK       0xFFFF0000
+#define SDRAM_RTR_RINT_MASK	  0xFFFF0000
 #define SDRAM_RTR_RINT_ENCODE(n)  (((n) << 16) & SDRAM_RTR_RINT_MASK)
-#define sdram_HZ_to_ns(hertz)     (1000000000/(hertz))
+#define sdram_HZ_to_ns(hertz)	  (1000000000/(hertz))
 
 /*-----------------------------------------------------------------------------+
   |  SDRAM UABus Base Address Reg
   +-----------------------------------------------------------------------------*/
-#define SDRAM_UABBA_UBBA_MASK     0x0000000F
+#define SDRAM_UABBA_UBBA_MASK	0x0000000F
 
 /*-----------------------------------------------------------------------------+
   |  Memory Bank 0-7 configuration
   +-----------------------------------------------------------------------------*/
-#define SDRAM_BXCR_SDBA_MASK      0xff800000      /* Base address             */
-#define SDRAM_BXCR_SDSZ_MASK      0x000e0000      /* Size                     */
-#define SDRAM_BXCR_SDSZ_8         0x00020000      /*   8M                     */
-#define SDRAM_BXCR_SDSZ_16        0x00040000      /*  16M                     */
-#define SDRAM_BXCR_SDSZ_32        0x00060000      /*  32M                     */
-#define SDRAM_BXCR_SDSZ_64        0x00080000      /*  64M                     */
-#define SDRAM_BXCR_SDSZ_128       0x000a0000      /* 128M                     */
-#define SDRAM_BXCR_SDSZ_256       0x000c0000      /* 256M                     */
-#define SDRAM_BXCR_SDSZ_512       0x000e0000      /* 512M                     */
-#define SDRAM_BXCR_SDAM_MASK      0x0000e000      /* Addressing mode          */
-#define SDRAM_BXCR_SDAM_1         0x00000000      /*   Mode 1                 */
-#define SDRAM_BXCR_SDAM_2         0x00002000      /*   Mode 2                 */
-#define SDRAM_BXCR_SDAM_3         0x00004000      /*   Mode 3                 */
-#define SDRAM_BXCR_SDAM_4         0x00006000      /*   Mode 4                 */
-#define SDRAM_BXCR_SDBE           0x00000001      /* Memory Bank Enable       */
+#define SDRAM_BXCR_SDBA_MASK	0xff800000	  /* Base address	      */
+#define SDRAM_BXCR_SDSZ_MASK	0x000e0000	  /* Size		      */
+#define SDRAM_BXCR_SDSZ_8	0x00020000	  /*   8M		      */
+#define SDRAM_BXCR_SDSZ_16	0x00040000	  /*  16M		      */
+#define SDRAM_BXCR_SDSZ_32	0x00060000	  /*  32M		      */
+#define SDRAM_BXCR_SDSZ_64	0x00080000	  /*  64M		      */
+#define SDRAM_BXCR_SDSZ_128	0x000a0000	  /* 128M		      */
+#define SDRAM_BXCR_SDSZ_256	0x000c0000	  /* 256M		      */
+#define SDRAM_BXCR_SDSZ_512	0x000e0000	  /* 512M		      */
+#define SDRAM_BXCR_SDAM_MASK	0x0000e000	  /* Addressing mode	      */
+#define SDRAM_BXCR_SDAM_1	0x00000000	  /*   Mode 1		      */
+#define SDRAM_BXCR_SDAM_2	0x00002000	  /*   Mode 2		      */
+#define SDRAM_BXCR_SDAM_3	0x00004000	  /*   Mode 3		      */
+#define SDRAM_BXCR_SDAM_4	0x00006000	  /*   Mode 4		      */
+#define SDRAM_BXCR_SDBE		0x00000001	  /* Memory Bank Enable	      */
 
 /*-----------------------------------------------------------------------------+
   |  SDRAM TR0 Options
   +-----------------------------------------------------------------------------*/
-#define SDRAM_TR0_SDWR_MASK       0x80000000
-#define   SDRAM_TR0_SDWR_2_CLK    0x00000000
-#define   SDRAM_TR0_SDWR_3_CLK    0x80000000
-#define SDRAM_TR0_SDWD_MASK       0x40000000
-#define   SDRAM_TR0_SDWD_0_CLK    0x00000000
-#define   SDRAM_TR0_SDWD_1_CLK    0x40000000
-#define SDRAM_TR0_SDCL_MASK       0x01800000
-#define   SDRAM_TR0_SDCL_2_0_CLK  0x00800000
-#define   SDRAM_TR0_SDCL_2_5_CLK  0x01000000
-#define   SDRAM_TR0_SDCL_3_0_CLK  0x01800000
-#define SDRAM_TR0_SDPA_MASK       0x000C0000
-#define   SDRAM_TR0_SDPA_2_CLK    0x00040000
-#define   SDRAM_TR0_SDPA_3_CLK    0x00080000
-#define   SDRAM_TR0_SDPA_4_CLK    0x000C0000
-#define SDRAM_TR0_SDCP_MASK       0x00030000
-#define   SDRAM_TR0_SDCP_2_CLK    0x00000000
-#define   SDRAM_TR0_SDCP_3_CLK    0x00010000
-#define   SDRAM_TR0_SDCP_4_CLK    0x00020000
-#define   SDRAM_TR0_SDCP_5_CLK    0x00030000
-#define SDRAM_TR0_SDLD_MASK       0x0000C000
-#define   SDRAM_TR0_SDLD_1_CLK    0x00000000
-#define   SDRAM_TR0_SDLD_2_CLK    0x00004000
-#define SDRAM_TR0_SDRA_MASK       0x0000001C
-#define   SDRAM_TR0_SDRA_6_CLK    0x00000000
-#define   SDRAM_TR0_SDRA_7_CLK    0x00000004
-#define   SDRAM_TR0_SDRA_8_CLK    0x00000008
-#define   SDRAM_TR0_SDRA_9_CLK    0x0000000C
-#define   SDRAM_TR0_SDRA_10_CLK   0x00000010
-#define   SDRAM_TR0_SDRA_11_CLK   0x00000014
-#define   SDRAM_TR0_SDRA_12_CLK   0x00000018
-#define   SDRAM_TR0_SDRA_13_CLK   0x0000001C
-#define SDRAM_TR0_SDRD_MASK       0x00000003
-#define   SDRAM_TR0_SDRD_2_CLK    0x00000001
-#define   SDRAM_TR0_SDRD_3_CLK    0x00000002
-#define   SDRAM_TR0_SDRD_4_CLK    0x00000003
+#define SDRAM_TR0_SDWR_MASK	0x80000000
+#define	 SDRAM_TR0_SDWR_2_CLK	0x00000000
+#define	 SDRAM_TR0_SDWR_3_CLK	0x80000000
+#define SDRAM_TR0_SDWD_MASK	0x40000000
+#define	 SDRAM_TR0_SDWD_0_CLK	0x00000000
+#define	 SDRAM_TR0_SDWD_1_CLK	0x40000000
+#define SDRAM_TR0_SDCL_MASK	0x01800000
+#define	 SDRAM_TR0_SDCL_2_0_CLK 0x00800000
+#define	 SDRAM_TR0_SDCL_2_5_CLK 0x01000000
+#define	 SDRAM_TR0_SDCL_3_0_CLK 0x01800000
+#define SDRAM_TR0_SDPA_MASK	0x000C0000
+#define	 SDRAM_TR0_SDPA_2_CLK	0x00040000
+#define	 SDRAM_TR0_SDPA_3_CLK	0x00080000
+#define	 SDRAM_TR0_SDPA_4_CLK	0x000C0000
+#define SDRAM_TR0_SDCP_MASK	0x00030000
+#define	 SDRAM_TR0_SDCP_2_CLK	0x00000000
+#define	 SDRAM_TR0_SDCP_3_CLK	0x00010000
+#define	 SDRAM_TR0_SDCP_4_CLK	0x00020000
+#define	 SDRAM_TR0_SDCP_5_CLK	0x00030000
+#define SDRAM_TR0_SDLD_MASK	0x0000C000
+#define	 SDRAM_TR0_SDLD_1_CLK	0x00000000
+#define	 SDRAM_TR0_SDLD_2_CLK	0x00004000
+#define SDRAM_TR0_SDRA_MASK	0x0000001C
+#define	 SDRAM_TR0_SDRA_6_CLK	0x00000000
+#define	 SDRAM_TR0_SDRA_7_CLK	0x00000004
+#define	 SDRAM_TR0_SDRA_8_CLK	0x00000008
+#define	 SDRAM_TR0_SDRA_9_CLK	0x0000000C
+#define	 SDRAM_TR0_SDRA_10_CLK	0x00000010
+#define	 SDRAM_TR0_SDRA_11_CLK	0x00000014
+#define	 SDRAM_TR0_SDRA_12_CLK	0x00000018
+#define	 SDRAM_TR0_SDRA_13_CLK	0x0000001C
+#define SDRAM_TR0_SDRD_MASK	0x00000003
+#define	 SDRAM_TR0_SDRD_2_CLK	0x00000001
+#define	 SDRAM_TR0_SDRD_3_CLK	0x00000002
+#define	 SDRAM_TR0_SDRD_4_CLK	0x00000003
 
 /*-----------------------------------------------------------------------------+
   |  SDRAM TR1 Options
   +-----------------------------------------------------------------------------*/
-#define SDRAM_TR1_RDSS_MASK         0xC0000000
-#define   SDRAM_TR1_RDSS_TR0        0x00000000
-#define   SDRAM_TR1_RDSS_TR1        0x40000000
-#define   SDRAM_TR1_RDSS_TR2        0x80000000
-#define   SDRAM_TR1_RDSS_TR3        0xC0000000
-#define SDRAM_TR1_RDSL_MASK         0x00C00000
-#define   SDRAM_TR1_RDSL_STAGE1     0x00000000
-#define   SDRAM_TR1_RDSL_STAGE2     0x00400000
-#define   SDRAM_TR1_RDSL_STAGE3     0x00800000
-#define SDRAM_TR1_RDCD_MASK         0x00000800
-#define   SDRAM_TR1_RDCD_RCD_0_0    0x00000000
-#define   SDRAM_TR1_RDCD_RCD_1_2    0x00000800
-#define SDRAM_TR1_RDCT_MASK         0x000001FF
-#define   SDRAM_TR1_RDCT_ENCODE(x)  (((x) << 0) & SDRAM_TR1_RDCT_MASK)
-#define   SDRAM_TR1_RDCT_DECODE(x)  (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
-#define   SDRAM_TR1_RDCT_MIN        0x00000000
-#define   SDRAM_TR1_RDCT_MAX        0x000001FF
+#define SDRAM_TR1_RDSS_MASK	0xC0000000
+#define	 SDRAM_TR1_RDSS_TR0	0x00000000
+#define	 SDRAM_TR1_RDSS_TR1	0x40000000
+#define	 SDRAM_TR1_RDSS_TR2	0x80000000
+#define	 SDRAM_TR1_RDSS_TR3	0xC0000000
+#define SDRAM_TR1_RDSL_MASK	0x00C00000
+#define	 SDRAM_TR1_RDSL_STAGE1	0x00000000
+#define	 SDRAM_TR1_RDSL_STAGE2	0x00400000
+#define	 SDRAM_TR1_RDSL_STAGE3	0x00800000
+#define SDRAM_TR1_RDCD_MASK	0x00000800
+#define	 SDRAM_TR1_RDCD_RCD_0_0 0x00000000
+#define	 SDRAM_TR1_RDCD_RCD_1_2 0x00000800
+#define SDRAM_TR1_RDCT_MASK	0x000001FF
+#define	 SDRAM_TR1_RDCT_ENCODE(x)  (((x) << 0) & SDRAM_TR1_RDCT_MASK)
+#define	 SDRAM_TR1_RDCT_DECODE(x)  (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
+#define	 SDRAM_TR1_RDCT_MIN	0x00000000
+#define	 SDRAM_TR1_RDCT_MAX	0x000001FF
 
 /*-----------------------------------------------------------------------------+
   |  SDRAM WDDCTR Options
   +-----------------------------------------------------------------------------*/
-#define SDRAM_WDDCTR_WRCP_MASK       0xC0000000
-#define   SDRAM_WDDCTR_WRCP_0DEG     0x00000000
-#define   SDRAM_WDDCTR_WRCP_90DEG    0x40000000
-#define   SDRAM_WDDCTR_WRCP_180DEG   0x80000000
-#define SDRAM_WDDCTR_DCD_MASK        0x000001FF
+#define SDRAM_WDDCTR_WRCP_MASK	0xC0000000
+#define	 SDRAM_WDDCTR_WRCP_0DEG	  0x00000000
+#define	 SDRAM_WDDCTR_WRCP_90DEG  0x40000000
+#define	 SDRAM_WDDCTR_WRCP_180DEG 0x80000000
+#define SDRAM_WDDCTR_DCD_MASK	0x000001FF
 
 /*-----------------------------------------------------------------------------+
   |  SDRAM CLKTR Options
   +-----------------------------------------------------------------------------*/
-#define SDRAM_CLKTR_CLKP_MASK       0xC0000000
-#define   SDRAM_CLKTR_CLKP_0DEG     0x00000000
-#define   SDRAM_CLKTR_CLKP_90DEG    0x40000000
-#define   SDRAM_CLKTR_CLKP_180DEG   0x80000000
-#define SDRAM_CLKTR_DCDT_MASK       0x000001FF
+#define SDRAM_CLKTR_CLKP_MASK	0xC0000000
+#define	 SDRAM_CLKTR_CLKP_0DEG	  0x00000000
+#define	 SDRAM_CLKTR_CLKP_90DEG	  0x40000000
+#define	 SDRAM_CLKTR_CLKP_180DEG  0x80000000
+#define SDRAM_CLKTR_DCDT_MASK	0x000001FF
 
 /*-----------------------------------------------------------------------------+
   |  SDRAM DLYCAL Options
   +-----------------------------------------------------------------------------*/
-#define SDRAM_DLYCAL_DLCV_MASK      0x000003FC
-#define   SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
-#define   SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
+#define SDRAM_DLYCAL_DLCV_MASK	0x000003FC
+#define	 SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
+#define	 SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
 
 /*-----------------------------------------------------------------------------+
   |  General Definition
   +-----------------------------------------------------------------------------*/
-#define DEFAULT_SPD_ADDR1   0x53
-#define DEFAULT_SPD_ADDR2   0x52
-#define MAXBANKS            4               /* at most 4 dimm banks */
-#define MAX_SPD_BYTES       256
-#define NUMHALFCYCLES       4
-#define NUMMEMTESTS         8
-#define NUMMEMWORDS         8
-#define MAXBXCR             4
-#define TRUE                1
-#define FALSE               0
+#define DEFAULT_SPD_ADDR1	0x53
+#define DEFAULT_SPD_ADDR2	0x52
+#define MAXBANKS		4		/* at most 4 dimm banks */
+#define MAX_SPD_BYTES		256
+#define NUMHALFCYCLES		4
+#define NUMMEMTESTS		8
+#define NUMMEMWORDS		8
+#define MAXBXCR			4
+#define TRUE			1
+#define FALSE			0
 
 const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
 	{0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
@@ -666,37 +666,37 @@
 
 void get_spd_info(unsigned long* dimm_populated,
 		  unsigned char* iic0_dimm_addr,
-		  unsigned long  num_dimm_banks);
+		  unsigned long	 num_dimm_banks);
 
 void check_mem_type
 (unsigned long* dimm_populated,
  unsigned char* iic0_dimm_addr,
- unsigned long  num_dimm_banks);
+ unsigned long	num_dimm_banks);
 
 void check_volt_type
 (unsigned long* dimm_populated,
  unsigned char* iic0_dimm_addr,
- unsigned long  num_dimm_banks);
+ unsigned long	num_dimm_banks);
 
 void program_cfg0(unsigned long* dimm_populated,
 		  unsigned char* iic0_dimm_addr,
-		  unsigned long  num_dimm_banks);
+		  unsigned long	 num_dimm_banks);
 
 void program_cfg1(unsigned long* dimm_populated,
 		  unsigned char* iic0_dimm_addr,
-		  unsigned long  num_dimm_banks);
+		  unsigned long	 num_dimm_banks);
 
 void program_rtr (unsigned long* dimm_populated,
 		  unsigned char* iic0_dimm_addr,
-		  unsigned long  num_dimm_banks);
+		  unsigned long	 num_dimm_banks);
 
 void program_tr0 (unsigned long* dimm_populated,
 		  unsigned char* iic0_dimm_addr,
-		  unsigned long  num_dimm_banks);
+		  unsigned long	 num_dimm_banks);
 
 void program_tr1 (void);
 
-void program_ecc (unsigned long  num_bytes);
+void program_ecc (unsigned long	 num_bytes);
 
 unsigned
 long  program_bxcr(unsigned long* dimm_populated,
@@ -719,7 +719,7 @@
 	unsigned long total_size;
 	unsigned long cfg0;
 	unsigned long mcsts;
-	unsigned long num_dimm_banks;               /* on board dimm banks */
+	unsigned long num_dimm_banks;		    /* on board dimm banks */
 
 	num_dimm_banks = sizeof(iic0_dimm_addr);
 
@@ -841,7 +841,7 @@
 
 void get_spd_info(unsigned long*   dimm_populated,
 		  unsigned char*   iic0_dimm_addr,
-		  unsigned long    num_dimm_banks)
+		  unsigned long	   num_dimm_banks)
 {
 	unsigned long dimm_num;
 	unsigned long dimm_found;
@@ -931,7 +931,7 @@
 
 void program_cfg0(unsigned long* dimm_populated,
 		  unsigned char* iic0_dimm_addr,
-		  unsigned long  num_dimm_banks)
+		  unsigned long	 num_dimm_banks)
 {
 	unsigned long dimm_num;
 	unsigned long cfg0;
@@ -1021,7 +1021,7 @@
 
 void program_cfg1(unsigned long* dimm_populated,
 		  unsigned char* iic0_dimm_addr,
-		  unsigned long  num_dimm_banks)
+		  unsigned long	 num_dimm_banks)
 {
 	unsigned long cfg1;
 	mfsdram(mem_cfg1, cfg1);
@@ -1039,7 +1039,7 @@
 
 void program_rtr (unsigned long* dimm_populated,
 		  unsigned char* iic0_dimm_addr,
-		  unsigned long  num_dimm_banks)
+		  unsigned long	 num_dimm_banks)
 {
 	unsigned long dimm_num;
 	unsigned long bus_period_x_10;
@@ -1100,7 +1100,7 @@
 
 void program_tr0 (unsigned long* dimm_populated,
 		  unsigned char* iic0_dimm_addr,
-		  unsigned long  num_dimm_banks)
+		  unsigned long	 num_dimm_banks)
 {
 	unsigned long dimm_num;
 	unsigned long tr0;
@@ -1159,7 +1159,7 @@
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 		if (dimm_populated[dimm_num] == TRUE) {
 			wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
-			t_rp_ns  = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
+			t_rp_ns	 = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
 			t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
 			t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
 			cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
@@ -1234,7 +1234,7 @@
 	/*
 	 * Program SD_WR and SD_WCSBC fields
 	 */
-	tr0 |= SDRAM_TR0_SDWR_2_CLK;                /* Write Recovery: 2 CLK */
+	tr0 |= SDRAM_TR0_SDWR_2_CLK;		    /* Write Recovery: 2 CLK */
 	switch (wcsbc) {
 	case 0:
 		tr0 |= SDRAM_TR0_SDWD_0_CLK;
@@ -1623,8 +1623,8 @@
 	unsigned long ctrl_bank_num[MAXBANKS];
 	unsigned long bx_cr_num;
 	unsigned long largest_size_index;
-        unsigned long largest_size;
-        unsigned long current_size_index;
+	unsigned long largest_size;
+	unsigned long current_size_index;
 	BANKPARMS bank_parms[MAXBXCR];
 	unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */
 	unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/
@@ -1785,7 +1785,7 @@
 	return(bank_base_addr);
 }
 
-void program_ecc (unsigned long  num_bytes)
+void program_ecc (unsigned long	 num_bytes)
 {
 	unsigned long bank_base_addr;
 	unsigned long current_address;
diff --git a/doc/README.OFT b/doc/README.OFT
index 8f00ebb..dd1c632 100644
--- a/doc/README.OFT
+++ b/doc/README.OFT
@@ -5,7 +5,7 @@
 way to pass bootloader and board setup information is the open
 firmware flat tree.
 
-Please take a look at the following email discussion for some 
+Please take a look at the following email discussion for some
 background.
 
   http://ozlabs.org/pipermail/linuxppc-dev/2005-August/019408.html
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index ba2f4ea..41f44c5 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -95,14 +95,14 @@
  * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
  * banks has to be determined at runtime and stored in a gloabl variable
  * tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only
- * used insted of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and
+ * used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and
  * should be made sufficiently large to accomodate the number of banks that
- * might acutally be detected.  Since most (all?) Flash related functions use
+ * might actually be detected.  Since most (all?) Flash related functions use
  * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is
  * defined as tqm834x_num_flash_banks.
  */
 #define CFG_MAX_FLASH_BANKS_DETECT	2
-#ifndef __ASSEMBLY__ 
+#ifndef __ASSEMBLY__
 extern int tqm834x_num_flash_banks;
 #endif
 #define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks)
diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h
index 981651a..d7d27e5 100644
--- a/include/configs/o2dnt.h
+++ b/include/configs/o2dnt.h
@@ -277,7 +277,7 @@
 #define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
 
 #ifdef CFG_PCISPEED_66
-/* 
+/*
  * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
  */
 #define CFG_BOOTCS_CFG		0x00057801 /* for pci_clk = 66 MHz */
diff --git a/lib_mips/board.c b/lib_mips/board.c
index 5dfdf90..b7d3356 100644
--- a/lib_mips/board.c
+++ b/lib_mips/board.c
@@ -125,7 +125,7 @@
 
 static int init_baudrate (void)
 {
-	uchar tmp[64];	/* long enough for environment variables */
+	char tmp[64];	/* long enough for environment variables */
 	int i = getenv_r ("baudrate", tmp, sizeof (tmp));
 
 	gd->baudrate = (i > 0)
diff --git a/lib_mips/mips_linux.c b/lib_mips/mips_linux.c
index 18eafe1..12e8435 100644
--- a/lib_mips/mips_linux.c
+++ b/lib_mips/mips_linux.c
@@ -94,7 +94,7 @@
 		checksum = ntohl (hdr->ih_hcrc);
 		hdr->ih_hcrc = 0;
 
-		if (crc32 (0, (char *) data, len) != checksum) {
+		if (crc32 (0, (uchar *) data, len) != checksum) {
 			printf ("Bad Header Checksum\n");
 			SHOW_BOOT_PROGRESS (-11);
 			do_reset (cmdtp, flag, argc, argv);
@@ -111,7 +111,7 @@
 			ulong csum = 0;
 
 			printf ("   Verifying Checksum ... ");
-			csum = crc32 (0, (char *) data, len);
+			csum = crc32 (0, (uchar *) data, len);
 			if (csum != ntohl (hdr->ih_dcrc)) {
 				printf ("Bad Data CRC\n");
 				SHOW_BOOT_PROGRESS (-12);
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index f2a4746..f40bb25 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -581,7 +581,6 @@
 	/* NOTREACHED - relocate_code() does not return */
 }
 
-
 /************************************************************************
  *
  * This is the next part if the initialization sequence: we are now
@@ -591,7 +590,6 @@
  *
  ************************************************************************
  */
-
 void board_init_r (gd_t *id, ulong dest_addr)
 {
 	cmd_tbl_t *cmdtp;
@@ -1124,8 +1122,6 @@
 	}
 }
 
-
-
 extern void  dbg(const char *fmt, ...);
 int mdm_init (void)
 {