board: freescale: ls1012aqds: enable network support on ls1012aqds
This patch enables ethernet support for ls1012aqds.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 406194d..4577917 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -25,9 +25,9 @@
#include <fsl_mmdc.h>
#include <spl.h>
#include <netdev.h>
-
#include "../common/qixis.h"
#include "ls1012aqds_qixis.h"
+#include "ls1012aqds_pfe.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -128,11 +128,6 @@
return 0;
}
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
-
int esdhc_status_fixup(void *blob, const char *compat)
{
char esdhc0_path[] = "/soc/esdhc@1560000";
@@ -161,12 +156,102 @@
return 0;
}
+static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
+ char *enet_path, char *mdio_path)
+{
+ do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
+ &prop_val.busid, PFE_PROP_LEN, 1);
+ do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
+ &prop_val.phyid, PFE_PROP_LEN, 1);
+ do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
+ &prop_val.mux_val, PFE_PROP_LEN, 1);
+ do_fixup_by_path(set_blob, enet_path, "phy-mode",
+ prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
+ do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
+ &prop_val.phy_mask, PFE_PROP_LEN, 1);
+ return 0;
+}
+
+static void fdt_fsl_fixup_of_pfe(void *blob)
+{
+ int i = 0;
+ struct pfe_prop_val prop_val;
+ void *l_blob = blob;
+
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ for (i = 0; i < NUM_ETH_NODE; i++) {
+ switch (srds_s1) {
+ case SERDES_1_G_PROTOCOL:
+ if (i == 0) {
+ prop_val.busid = cpu_to_fdt32(
+ ETH_1_1G_BUS_ID);
+ prop_val.phyid = cpu_to_fdt32(
+ ETH_1_1G_PHY_ID);
+ prop_val.mux_val = cpu_to_fdt32(
+ ETH_1_1G_MDIO_MUX);
+ prop_val.phy_mask = cpu_to_fdt32(
+ ETH_1G_MDIO_PHY_MASK);
+ prop_val.phy_mode = "sgmii";
+ pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
+ ETH_1_MDIO);
+ } else {
+ prop_val.busid = cpu_to_fdt32(
+ ETH_2_1G_BUS_ID);
+ prop_val.phyid = cpu_to_fdt32(
+ ETH_2_1G_PHY_ID);
+ prop_val.mux_val = cpu_to_fdt32(
+ ETH_2_1G_MDIO_MUX);
+ prop_val.phy_mask = cpu_to_fdt32(
+ ETH_1G_MDIO_PHY_MASK);
+ prop_val.phy_mode = "rgmii";
+ pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
+ ETH_2_MDIO);
+ }
+ break;
+ case SERDES_2_5_G_PROTOCOL:
+ if (i == 0) {
+ prop_val.busid = cpu_to_fdt32(
+ ETH_1_2_5G_BUS_ID);
+ prop_val.phyid = cpu_to_fdt32(
+ ETH_1_2_5G_PHY_ID);
+ prop_val.mux_val = cpu_to_fdt32(
+ ETH_1_2_5G_MDIO_MUX);
+ prop_val.phy_mask = cpu_to_fdt32(
+ ETH_2_5G_MDIO_PHY_MASK);
+ prop_val.phy_mode = "sgmii-2500";
+ pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
+ ETH_1_MDIO);
+ } else {
+ prop_val.busid = cpu_to_fdt32(
+ ETH_2_2_5G_BUS_ID);
+ prop_val.phyid = cpu_to_fdt32(
+ ETH_2_2_5G_PHY_ID);
+ prop_val.mux_val = cpu_to_fdt32(
+ ETH_2_2_5G_MDIO_MUX);
+ prop_val.phy_mask = cpu_to_fdt32(
+ ETH_2_5G_MDIO_PHY_MASK);
+ prop_val.phy_mode = "sgmii-2500";
+ pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
+ ETH_2_MDIO);
+ }
+ break;
+ default:
+ printf("serdes:[%d]\n", srds_s1);
+ }
+ }
+}
+
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
arch_fixup_fdt(blob);
ft_cpu_setup(blob, bd);
+ fdt_fsl_fixup_of_pfe(blob);
return 0;
}