tree 5c020419fa8e0c2977c1e45c117924a229bafc75
parent 9d2a9fac2c61230a2a31c95a8aee331e91040610
author Masahiro Yamada <yamada.masahiro@socionext.com> 1465376552 +0900
committer Masahiro Yamada <yamada.masahiro@socionext.com> 1465427953 +0900

ARM: uniphier: insert dsb barrier to ensure visibility of store

I noticed secondary CPUs sometimes fail to wake up, and the root
cause is that the sev instruction wakes up slave CPUs before the
preceding the register write is observed by them.

The read-back of the accessed register does not guarantee the order.
In order to ensure the order between the register write and the sev
instruction, a dsb instruction should be executed prior to the sev.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>