diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index fa75cc5..37638a8 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -14,3 +14,4 @@
 obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
 obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
 obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
+obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o
diff --git a/drivers/sysreset/sysreset_ast.c b/drivers/sysreset/sysreset_ast.c
new file mode 100644
index 0000000..a0ab128
--- /dev/null
+++ b/drivers/sysreset/sysreset_ast.c
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+#include <asm/arch/wdt.h>
+#include <linux/err.h>
+
+/* Number of Watchdog Timer ticks before reset */
+#define AST_WDT_RESET_TIMEOUT	10
+#define AST_WDT_FOR_RESET	0
+
+static int ast_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+	struct ast_wdt *wdt = ast_get_wdt(AST_WDT_FOR_RESET);
+	u32 reset_mode = 0;
+
+	if (IS_ERR(wdt))
+		return PTR_ERR(wdt);
+
+	switch (type) {
+	case SYSRESET_WARM:
+		reset_mode = WDT_CTRL_RESET_CPU;
+		break;
+	case SYSRESET_COLD:
+		reset_mode = WDT_CTRL_RESET_CHIP;
+		break;
+	default:
+		return -EPROTONOSUPPORT;
+	}
+
+	/* Clear reset mode bits */
+	clrsetbits_le32(&wdt->ctrl,
+			(WDT_CTRL_RESET_MODE_MASK << WDT_CTRL_RESET_MODE_SHIFT),
+			(reset_mode << WDT_CTRL_RESET_MODE_SHIFT));
+	wdt_start(wdt, AST_WDT_RESET_TIMEOUT);
+
+	return -EINPROGRESS;
+}
+
+static struct sysreset_ops ast_sysreset = {
+	.request	= ast_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_ast) = {
+	.name	= "ast_sysreset",
+	.id	= UCLASS_SYSRESET,
+	.ops	= &ast_sysreset,
+};
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index cb18f12..cd38a6d 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -46,4 +46,16 @@
 	help
 	  Select this to enable an timer for Omap devices.
 
+config AST_TIMER
+	bool "Aspeed ast2400/ast2500 timer support"
+	depends on TIMER
+	default y if ARCH_ASPEED
+	help
+	  Select this to enable timer for Aspeed ast2400/ast2500 devices.
+	  This is a simple sys timer driver, it is compatible with lib/time.c,
+	  but does not support any interrupts. Even though SoC has 8 hardware
+	  counters, they are all treated as a single device by this driver.
+	  This is mostly because they all share several registers which
+	  makes it difficult to completely separate them.
+
 endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index f351fbb..a4b1a48 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -9,3 +9,4 @@
 obj-$(CONFIG_SANDBOX_TIMER)	+= sandbox_timer.o
 obj-$(CONFIG_X86_TSC_TIMER)	+= tsc_timer.o
 obj-$(CONFIG_OMAP_TIMER)	+= omap-timer.o
+obj-$(CONFIG_AST_TIMER)	+= ast_timer.o
diff --git a/drivers/timer/ast_timer.c b/drivers/timer/ast_timer.c
new file mode 100644
index 0000000..d7c5460
--- /dev/null
+++ b/drivers/timer/ast_timer.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2016 Google Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <timer.h>
+#include <asm/io.h>
+#include <asm/arch/timer.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define AST_TICK_TIMER  1
+#define AST_TMC_RELOAD_VAL  0xffffffff
+
+struct ast_timer_priv {
+	struct ast_timer *regs;
+	struct ast_timer_counter *tmc;
+};
+
+static struct ast_timer_counter *ast_get_timer_counter(struct ast_timer *timer,
+						       int n)
+{
+	if (n > 3)
+		return &timer->timers2[n - 4];
+	else
+		return &timer->timers1[n - 1];
+}
+
+static int ast_timer_probe(struct udevice *dev)
+{
+	struct ast_timer_priv *priv = dev_get_priv(dev);
+	struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	writel(AST_TMC_RELOAD_VAL, &priv->tmc->reload_val);
+
+	/*
+	 * Stop the timer. This will also load reload_val into
+	 * the status register.
+	 */
+	clrbits_le32(&priv->regs->ctrl1,
+		     AST_TMC_EN << AST_TMC_CTRL1_SHIFT(AST_TICK_TIMER));
+	/* Start the timer from the fixed 1MHz clock. */
+	setbits_le32(&priv->regs->ctrl1,
+		     (AST_TMC_EN | AST_TMC_1MHZ) <<
+		     AST_TMC_CTRL1_SHIFT(AST_TICK_TIMER));
+
+	uc_priv->clock_rate = AST_TMC_RATE;
+
+	return 0;
+}
+
+static int ast_timer_get_count(struct udevice *dev, u64 *count)
+{
+	struct ast_timer_priv *priv = dev_get_priv(dev);
+
+	*count = AST_TMC_RELOAD_VAL - readl(&priv->tmc->status);
+
+	return 0;
+}
+
+static int ast_timer_ofdata_to_platdata(struct udevice *dev)
+{
+	struct ast_timer_priv *priv = dev_get_priv(dev);
+
+	priv->regs = dev_get_addr_ptr(dev);
+	if (IS_ERR(priv->regs))
+		return PTR_ERR(priv->regs);
+
+	priv->tmc = ast_get_timer_counter(priv->regs, AST_TICK_TIMER);
+
+	return 0;
+}
+
+static const struct timer_ops ast_timer_ops = {
+	.get_count = ast_timer_get_count,
+};
+
+static const struct udevice_id ast_timer_ids[] = {
+	{ .compatible = "aspeed,ast2500-timer" },
+	{ .compatible = "aspeed,ast2400-timer" },
+	{ }
+};
+
+U_BOOT_DRIVER(ast_timer) = {
+	.name = "ast_timer",
+	.id = UCLASS_TIMER,
+	.of_match = ast_timer_ids,
+	.probe = ast_timer_probe,
+	.priv_auto_alloc_size = sizeof(struct ast_timer_priv),
+	.ofdata_to_platdata = ast_timer_ofdata_to_platdata,
+	.ops = &ast_timer_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};