powerpc/85xx: Change timebase divisor to be defined per processor
Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because
different SoCs have different divisor amounts. All the PQ3 parts are
/8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
diff --git a/README b/README
index 157cc9e..2754d1e 100644
--- a/README
+++ b/README
@@ -356,6 +356,13 @@
Define this option if you want to enable the
ICache only when Code runs from RAM.
+- 85xx CPU Options:
+ CONFIG_SYS_FSL_TBCLK_DIV
+
+ Defines the core time base clock divider ratio compared to the
+ system clock. On most PQ3 devices this is 8, on newer QorIQ
+ devices it can be 16 or 32. The ratio varies from SoC to Soc.
+
- Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO